device.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940
  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <rdma/ib_verbs.h>
  36. #include "iw_cxgb4.h"
  37. #define DRV_VERSION "0.1"
  38. MODULE_AUTHOR("Steve Wise");
  39. MODULE_DESCRIPTION("Chelsio T4 RDMA Driver");
  40. MODULE_LICENSE("Dual BSD/GPL");
  41. MODULE_VERSION(DRV_VERSION);
  42. struct uld_ctx {
  43. struct list_head entry;
  44. struct cxgb4_lld_info lldi;
  45. struct c4iw_dev *dev;
  46. };
  47. static LIST_HEAD(uld_ctx_list);
  48. static DEFINE_MUTEX(dev_mutex);
  49. static struct dentry *c4iw_debugfs_root;
  50. struct c4iw_debugfs_data {
  51. struct c4iw_dev *devp;
  52. char *buf;
  53. int bufsize;
  54. int pos;
  55. };
  56. static int count_idrs(int id, void *p, void *data)
  57. {
  58. int *countp = data;
  59. *countp = *countp + 1;
  60. return 0;
  61. }
  62. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  63. loff_t *ppos)
  64. {
  65. struct c4iw_debugfs_data *d = file->private_data;
  66. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  67. }
  68. static int dump_qp(int id, void *p, void *data)
  69. {
  70. struct c4iw_qp *qp = p;
  71. struct c4iw_debugfs_data *qpd = data;
  72. int space;
  73. int cc;
  74. if (id != qp->wq.sq.qid)
  75. return 0;
  76. space = qpd->bufsize - qpd->pos - 1;
  77. if (space == 0)
  78. return 1;
  79. if (qp->ep)
  80. cc = snprintf(qpd->buf + qpd->pos, space,
  81. "qp sq id %u rq id %u state %u onchip %u "
  82. "ep tid %u state %u %pI4:%u->%pI4:%u\n",
  83. qp->wq.sq.qid, qp->wq.rq.qid, (int)qp->attr.state,
  84. qp->wq.sq.flags & T4_SQ_ONCHIP,
  85. qp->ep->hwtid, (int)qp->ep->com.state,
  86. &qp->ep->com.local_addr.sin_addr.s_addr,
  87. ntohs(qp->ep->com.local_addr.sin_port),
  88. &qp->ep->com.remote_addr.sin_addr.s_addr,
  89. ntohs(qp->ep->com.remote_addr.sin_port));
  90. else
  91. cc = snprintf(qpd->buf + qpd->pos, space,
  92. "qp sq id %u rq id %u state %u onchip %u\n",
  93. qp->wq.sq.qid, qp->wq.rq.qid,
  94. (int)qp->attr.state,
  95. qp->wq.sq.flags & T4_SQ_ONCHIP);
  96. if (cc < space)
  97. qpd->pos += cc;
  98. return 0;
  99. }
  100. static int qp_release(struct inode *inode, struct file *file)
  101. {
  102. struct c4iw_debugfs_data *qpd = file->private_data;
  103. if (!qpd) {
  104. printk(KERN_INFO "%s null qpd?\n", __func__);
  105. return 0;
  106. }
  107. kfree(qpd->buf);
  108. kfree(qpd);
  109. return 0;
  110. }
  111. static int qp_open(struct inode *inode, struct file *file)
  112. {
  113. struct c4iw_debugfs_data *qpd;
  114. int ret = 0;
  115. int count = 1;
  116. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  117. if (!qpd) {
  118. ret = -ENOMEM;
  119. goto out;
  120. }
  121. qpd->devp = inode->i_private;
  122. qpd->pos = 0;
  123. spin_lock_irq(&qpd->devp->lock);
  124. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  125. spin_unlock_irq(&qpd->devp->lock);
  126. qpd->bufsize = count * 128;
  127. qpd->buf = kmalloc(qpd->bufsize, GFP_KERNEL);
  128. if (!qpd->buf) {
  129. ret = -ENOMEM;
  130. goto err1;
  131. }
  132. spin_lock_irq(&qpd->devp->lock);
  133. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  134. spin_unlock_irq(&qpd->devp->lock);
  135. qpd->buf[qpd->pos++] = 0;
  136. file->private_data = qpd;
  137. goto out;
  138. err1:
  139. kfree(qpd);
  140. out:
  141. return ret;
  142. }
  143. static const struct file_operations qp_debugfs_fops = {
  144. .owner = THIS_MODULE,
  145. .open = qp_open,
  146. .release = qp_release,
  147. .read = debugfs_read,
  148. .llseek = default_llseek,
  149. };
  150. static int dump_stag(int id, void *p, void *data)
  151. {
  152. struct c4iw_debugfs_data *stagd = data;
  153. int space;
  154. int cc;
  155. space = stagd->bufsize - stagd->pos - 1;
  156. if (space == 0)
  157. return 1;
  158. cc = snprintf(stagd->buf + stagd->pos, space, "0x%x\n", id<<8);
  159. if (cc < space)
  160. stagd->pos += cc;
  161. return 0;
  162. }
  163. static int stag_release(struct inode *inode, struct file *file)
  164. {
  165. struct c4iw_debugfs_data *stagd = file->private_data;
  166. if (!stagd) {
  167. printk(KERN_INFO "%s null stagd?\n", __func__);
  168. return 0;
  169. }
  170. kfree(stagd->buf);
  171. kfree(stagd);
  172. return 0;
  173. }
  174. static int stag_open(struct inode *inode, struct file *file)
  175. {
  176. struct c4iw_debugfs_data *stagd;
  177. int ret = 0;
  178. int count = 1;
  179. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  180. if (!stagd) {
  181. ret = -ENOMEM;
  182. goto out;
  183. }
  184. stagd->devp = inode->i_private;
  185. stagd->pos = 0;
  186. spin_lock_irq(&stagd->devp->lock);
  187. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  188. spin_unlock_irq(&stagd->devp->lock);
  189. stagd->bufsize = count * sizeof("0x12345678\n");
  190. stagd->buf = kmalloc(stagd->bufsize, GFP_KERNEL);
  191. if (!stagd->buf) {
  192. ret = -ENOMEM;
  193. goto err1;
  194. }
  195. spin_lock_irq(&stagd->devp->lock);
  196. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  197. spin_unlock_irq(&stagd->devp->lock);
  198. stagd->buf[stagd->pos++] = 0;
  199. file->private_data = stagd;
  200. goto out;
  201. err1:
  202. kfree(stagd);
  203. out:
  204. return ret;
  205. }
  206. static const struct file_operations stag_debugfs_fops = {
  207. .owner = THIS_MODULE,
  208. .open = stag_open,
  209. .release = stag_release,
  210. .read = debugfs_read,
  211. .llseek = default_llseek,
  212. };
  213. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY"};
  214. static int stats_show(struct seq_file *seq, void *v)
  215. {
  216. struct c4iw_dev *dev = seq->private;
  217. seq_printf(seq, " Object: %10s %10s %10s\n", "Total", "Current", "Max");
  218. seq_printf(seq, " PDID: %10llu %10llu %10llu\n",
  219. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  220. dev->rdev.stats.pd.max);
  221. seq_printf(seq, " QID: %10llu %10llu %10llu\n",
  222. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  223. dev->rdev.stats.qid.max);
  224. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu\n",
  225. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  226. dev->rdev.stats.stag.max);
  227. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu\n",
  228. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  229. dev->rdev.stats.pbl.max);
  230. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu\n",
  231. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  232. dev->rdev.stats.rqt.max);
  233. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu\n",
  234. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  235. dev->rdev.stats.ocqp.max);
  236. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  237. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  238. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  239. seq_printf(seq, " DB State: %s Transitions %llu\n",
  240. db_state_str[dev->db_state],
  241. dev->rdev.stats.db_state_transitions);
  242. return 0;
  243. }
  244. static int stats_open(struct inode *inode, struct file *file)
  245. {
  246. return single_open(file, stats_show, inode->i_private);
  247. }
  248. static ssize_t stats_clear(struct file *file, const char __user *buf,
  249. size_t count, loff_t *pos)
  250. {
  251. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  252. mutex_lock(&dev->rdev.stats.lock);
  253. dev->rdev.stats.pd.max = 0;
  254. dev->rdev.stats.qid.max = 0;
  255. dev->rdev.stats.stag.max = 0;
  256. dev->rdev.stats.pbl.max = 0;
  257. dev->rdev.stats.rqt.max = 0;
  258. dev->rdev.stats.ocqp.max = 0;
  259. dev->rdev.stats.db_full = 0;
  260. dev->rdev.stats.db_empty = 0;
  261. dev->rdev.stats.db_drop = 0;
  262. dev->rdev.stats.db_state_transitions = 0;
  263. mutex_unlock(&dev->rdev.stats.lock);
  264. return count;
  265. }
  266. static const struct file_operations stats_debugfs_fops = {
  267. .owner = THIS_MODULE,
  268. .open = stats_open,
  269. .release = single_release,
  270. .read = seq_read,
  271. .llseek = seq_lseek,
  272. .write = stats_clear,
  273. };
  274. static int setup_debugfs(struct c4iw_dev *devp)
  275. {
  276. struct dentry *de;
  277. if (!devp->debugfs_root)
  278. return -1;
  279. de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
  280. (void *)devp, &qp_debugfs_fops);
  281. if (de && de->d_inode)
  282. de->d_inode->i_size = 4096;
  283. de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
  284. (void *)devp, &stag_debugfs_fops);
  285. if (de && de->d_inode)
  286. de->d_inode->i_size = 4096;
  287. de = debugfs_create_file("stats", S_IWUSR, devp->debugfs_root,
  288. (void *)devp, &stats_debugfs_fops);
  289. if (de && de->d_inode)
  290. de->d_inode->i_size = 4096;
  291. return 0;
  292. }
  293. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  294. struct c4iw_dev_ucontext *uctx)
  295. {
  296. struct list_head *pos, *nxt;
  297. struct c4iw_qid_list *entry;
  298. mutex_lock(&uctx->lock);
  299. list_for_each_safe(pos, nxt, &uctx->qpids) {
  300. entry = list_entry(pos, struct c4iw_qid_list, entry);
  301. list_del_init(&entry->entry);
  302. if (!(entry->qid & rdev->qpmask)) {
  303. c4iw_put_resource(&rdev->resource.qid_fifo, entry->qid,
  304. &rdev->resource.qid_fifo_lock);
  305. mutex_lock(&rdev->stats.lock);
  306. rdev->stats.qid.cur -= rdev->qpmask + 1;
  307. mutex_unlock(&rdev->stats.lock);
  308. }
  309. kfree(entry);
  310. }
  311. list_for_each_safe(pos, nxt, &uctx->qpids) {
  312. entry = list_entry(pos, struct c4iw_qid_list, entry);
  313. list_del_init(&entry->entry);
  314. kfree(entry);
  315. }
  316. mutex_unlock(&uctx->lock);
  317. }
  318. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  319. struct c4iw_dev_ucontext *uctx)
  320. {
  321. INIT_LIST_HEAD(&uctx->qpids);
  322. INIT_LIST_HEAD(&uctx->cqids);
  323. mutex_init(&uctx->lock);
  324. }
  325. /* Caller takes care of locking if needed */
  326. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  327. {
  328. int err;
  329. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  330. /*
  331. * qpshift is the number of bits to shift the qpid left in order
  332. * to get the correct address of the doorbell for that qp.
  333. */
  334. rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
  335. rdev->qpmask = rdev->lldi.udb_density - 1;
  336. rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
  337. rdev->cqmask = rdev->lldi.ucq_density - 1;
  338. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  339. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  340. "qp qid start %u size %u cq qid start %u size %u\n",
  341. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  342. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  343. rdev->lldi.vr->pbl.start,
  344. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  345. rdev->lldi.vr->rq.size,
  346. rdev->lldi.vr->qp.start,
  347. rdev->lldi.vr->qp.size,
  348. rdev->lldi.vr->cq.start,
  349. rdev->lldi.vr->cq.size);
  350. PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
  351. "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
  352. (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
  353. (void *)pci_resource_start(rdev->lldi.pdev, 2),
  354. rdev->lldi.db_reg,
  355. rdev->lldi.gts_reg,
  356. rdev->qpshift, rdev->qpmask,
  357. rdev->cqshift, rdev->cqmask);
  358. if (c4iw_num_stags(rdev) == 0) {
  359. err = -EINVAL;
  360. goto err1;
  361. }
  362. rdev->stats.pd.total = T4_MAX_NUM_PD;
  363. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  364. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  365. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  366. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  367. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  368. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  369. if (err) {
  370. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  371. goto err1;
  372. }
  373. err = c4iw_pblpool_create(rdev);
  374. if (err) {
  375. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  376. goto err2;
  377. }
  378. err = c4iw_rqtpool_create(rdev);
  379. if (err) {
  380. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  381. goto err3;
  382. }
  383. err = c4iw_ocqp_pool_create(rdev);
  384. if (err) {
  385. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  386. goto err4;
  387. }
  388. return 0;
  389. err4:
  390. c4iw_rqtpool_destroy(rdev);
  391. err3:
  392. c4iw_pblpool_destroy(rdev);
  393. err2:
  394. c4iw_destroy_resource(&rdev->resource);
  395. err1:
  396. return err;
  397. }
  398. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  399. {
  400. c4iw_pblpool_destroy(rdev);
  401. c4iw_rqtpool_destroy(rdev);
  402. c4iw_destroy_resource(&rdev->resource);
  403. }
  404. static void c4iw_dealloc(struct uld_ctx *ctx)
  405. {
  406. c4iw_rdev_close(&ctx->dev->rdev);
  407. idr_destroy(&ctx->dev->cqidr);
  408. idr_destroy(&ctx->dev->qpidr);
  409. idr_destroy(&ctx->dev->mmidr);
  410. iounmap(ctx->dev->rdev.oc_mw_kva);
  411. ib_dealloc_device(&ctx->dev->ibdev);
  412. ctx->dev = NULL;
  413. }
  414. static void c4iw_remove(struct uld_ctx *ctx)
  415. {
  416. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  417. c4iw_unregister_device(ctx->dev);
  418. c4iw_dealloc(ctx);
  419. }
  420. static int rdma_supported(const struct cxgb4_lld_info *infop)
  421. {
  422. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  423. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  424. infop->vr->cq.size > 0 && infop->vr->ocq.size > 0;
  425. }
  426. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  427. {
  428. struct c4iw_dev *devp;
  429. int ret;
  430. if (!rdma_supported(infop)) {
  431. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  432. pci_name(infop->pdev));
  433. return ERR_PTR(-ENOSYS);
  434. }
  435. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  436. if (!devp) {
  437. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  438. return ERR_PTR(-ENOMEM);
  439. }
  440. devp->rdev.lldi = *infop;
  441. devp->rdev.oc_mw_pa = pci_resource_start(devp->rdev.lldi.pdev, 2) +
  442. (pci_resource_len(devp->rdev.lldi.pdev, 2) -
  443. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size));
  444. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  445. devp->rdev.lldi.vr->ocq.size);
  446. PDBG(KERN_INFO MOD "ocq memory: "
  447. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  448. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  449. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  450. ret = c4iw_rdev_open(&devp->rdev);
  451. if (ret) {
  452. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  453. ib_dealloc_device(&devp->ibdev);
  454. return ERR_PTR(ret);
  455. }
  456. idr_init(&devp->cqidr);
  457. idr_init(&devp->qpidr);
  458. idr_init(&devp->mmidr);
  459. spin_lock_init(&devp->lock);
  460. mutex_init(&devp->rdev.stats.lock);
  461. mutex_init(&devp->db_mutex);
  462. if (c4iw_debugfs_root) {
  463. devp->debugfs_root = debugfs_create_dir(
  464. pci_name(devp->rdev.lldi.pdev),
  465. c4iw_debugfs_root);
  466. setup_debugfs(devp);
  467. }
  468. return devp;
  469. }
  470. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  471. {
  472. struct uld_ctx *ctx;
  473. static int vers_printed;
  474. int i;
  475. if (!vers_printed++)
  476. printk(KERN_INFO MOD "Chelsio T4 RDMA Driver - version %s\n",
  477. DRV_VERSION);
  478. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  479. if (!ctx) {
  480. ctx = ERR_PTR(-ENOMEM);
  481. goto out;
  482. }
  483. ctx->lldi = *infop;
  484. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  485. __func__, pci_name(ctx->lldi.pdev),
  486. ctx->lldi.nchan, ctx->lldi.nrxq,
  487. ctx->lldi.ntxq, ctx->lldi.nports);
  488. mutex_lock(&dev_mutex);
  489. list_add_tail(&ctx->entry, &uld_ctx_list);
  490. mutex_unlock(&dev_mutex);
  491. for (i = 0; i < ctx->lldi.nrxq; i++)
  492. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  493. out:
  494. return ctx;
  495. }
  496. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  497. const struct pkt_gl *gl)
  498. {
  499. struct uld_ctx *ctx = handle;
  500. struct c4iw_dev *dev = ctx->dev;
  501. struct sk_buff *skb;
  502. const struct cpl_act_establish *rpl;
  503. unsigned int opcode;
  504. if (gl == NULL) {
  505. /* omit RSS and rsp_ctrl at end of descriptor */
  506. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  507. skb = alloc_skb(256, GFP_ATOMIC);
  508. if (!skb)
  509. goto nomem;
  510. __skb_put(skb, len);
  511. skb_copy_to_linear_data(skb, &rsp[1], len);
  512. } else if (gl == CXGB4_MSG_AN) {
  513. const struct rsp_ctrl *rc = (void *)rsp;
  514. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  515. c4iw_ev_handler(dev, qid);
  516. return 0;
  517. } else {
  518. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  519. if (unlikely(!skb))
  520. goto nomem;
  521. }
  522. rpl = cplhdr(skb);
  523. opcode = rpl->ot.opcode;
  524. if (c4iw_handlers[opcode])
  525. c4iw_handlers[opcode](dev, skb);
  526. else
  527. printk(KERN_INFO "%s no handler opcode 0x%x...\n", __func__,
  528. opcode);
  529. return 0;
  530. nomem:
  531. return -1;
  532. }
  533. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  534. {
  535. struct uld_ctx *ctx = handle;
  536. PDBG("%s new_state %u\n", __func__, new_state);
  537. switch (new_state) {
  538. case CXGB4_STATE_UP:
  539. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  540. if (!ctx->dev) {
  541. int ret;
  542. ctx->dev = c4iw_alloc(&ctx->lldi);
  543. if (IS_ERR(ctx->dev)) {
  544. printk(KERN_ERR MOD
  545. "%s: initialization failed: %ld\n",
  546. pci_name(ctx->lldi.pdev),
  547. PTR_ERR(ctx->dev));
  548. ctx->dev = NULL;
  549. break;
  550. }
  551. ret = c4iw_register_device(ctx->dev);
  552. if (ret) {
  553. printk(KERN_ERR MOD
  554. "%s: RDMA registration failed: %d\n",
  555. pci_name(ctx->lldi.pdev), ret);
  556. c4iw_dealloc(ctx);
  557. }
  558. }
  559. break;
  560. case CXGB4_STATE_DOWN:
  561. printk(KERN_INFO MOD "%s: Down\n",
  562. pci_name(ctx->lldi.pdev));
  563. if (ctx->dev)
  564. c4iw_remove(ctx);
  565. break;
  566. case CXGB4_STATE_START_RECOVERY:
  567. printk(KERN_INFO MOD "%s: Fatal Error\n",
  568. pci_name(ctx->lldi.pdev));
  569. if (ctx->dev) {
  570. struct ib_event event;
  571. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  572. memset(&event, 0, sizeof event);
  573. event.event = IB_EVENT_DEVICE_FATAL;
  574. event.device = &ctx->dev->ibdev;
  575. ib_dispatch_event(&event);
  576. c4iw_remove(ctx);
  577. }
  578. break;
  579. case CXGB4_STATE_DETACH:
  580. printk(KERN_INFO MOD "%s: Detach\n",
  581. pci_name(ctx->lldi.pdev));
  582. if (ctx->dev)
  583. c4iw_remove(ctx);
  584. break;
  585. }
  586. return 0;
  587. }
  588. static int disable_qp_db(int id, void *p, void *data)
  589. {
  590. struct c4iw_qp *qp = p;
  591. t4_disable_wq_db(&qp->wq);
  592. return 0;
  593. }
  594. static void stop_queues(struct uld_ctx *ctx)
  595. {
  596. spin_lock_irq(&ctx->dev->lock);
  597. if (ctx->dev->db_state == NORMAL) {
  598. ctx->dev->rdev.stats.db_state_transitions++;
  599. ctx->dev->db_state = FLOW_CONTROL;
  600. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  601. }
  602. spin_unlock_irq(&ctx->dev->lock);
  603. }
  604. static int enable_qp_db(int id, void *p, void *data)
  605. {
  606. struct c4iw_qp *qp = p;
  607. t4_enable_wq_db(&qp->wq);
  608. return 0;
  609. }
  610. static void resume_queues(struct uld_ctx *ctx)
  611. {
  612. spin_lock_irq(&ctx->dev->lock);
  613. if (ctx->dev->qpcnt <= db_fc_threshold &&
  614. ctx->dev->db_state == FLOW_CONTROL) {
  615. ctx->dev->db_state = NORMAL;
  616. ctx->dev->rdev.stats.db_state_transitions++;
  617. idr_for_each(&ctx->dev->qpidr, enable_qp_db, NULL);
  618. }
  619. spin_unlock_irq(&ctx->dev->lock);
  620. }
  621. struct qp_list {
  622. unsigned idx;
  623. struct c4iw_qp **qps;
  624. };
  625. static int add_and_ref_qp(int id, void *p, void *data)
  626. {
  627. struct qp_list *qp_listp = data;
  628. struct c4iw_qp *qp = p;
  629. c4iw_qp_add_ref(&qp->ibqp);
  630. qp_listp->qps[qp_listp->idx++] = qp;
  631. return 0;
  632. }
  633. static int count_qps(int id, void *p, void *data)
  634. {
  635. unsigned *countp = data;
  636. (*countp)++;
  637. return 0;
  638. }
  639. static void deref_qps(struct qp_list qp_list)
  640. {
  641. int idx;
  642. for (idx = 0; idx < qp_list.idx; idx++)
  643. c4iw_qp_rem_ref(&qp_list.qps[idx]->ibqp);
  644. }
  645. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  646. {
  647. int idx;
  648. int ret;
  649. for (idx = 0; idx < qp_list->idx; idx++) {
  650. struct c4iw_qp *qp = qp_list->qps[idx];
  651. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  652. qp->wq.sq.qid,
  653. t4_sq_host_wq_pidx(&qp->wq),
  654. t4_sq_wq_size(&qp->wq));
  655. if (ret) {
  656. printk(KERN_ERR MOD "%s: Fatal error - "
  657. "DB overflow recovery failed - "
  658. "error syncing SQ qid %u\n",
  659. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  660. return;
  661. }
  662. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  663. qp->wq.rq.qid,
  664. t4_rq_host_wq_pidx(&qp->wq),
  665. t4_rq_wq_size(&qp->wq));
  666. if (ret) {
  667. printk(KERN_ERR MOD "%s: Fatal error - "
  668. "DB overflow recovery failed - "
  669. "error syncing RQ qid %u\n",
  670. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  671. return;
  672. }
  673. /* Wait for the dbfifo to drain */
  674. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  675. set_current_state(TASK_UNINTERRUPTIBLE);
  676. schedule_timeout(usecs_to_jiffies(10));
  677. }
  678. }
  679. }
  680. static void recover_queues(struct uld_ctx *ctx)
  681. {
  682. int count = 0;
  683. struct qp_list qp_list;
  684. int ret;
  685. /* lock out kernel db ringers */
  686. mutex_lock(&ctx->dev->db_mutex);
  687. /* put all queues in to recovery mode */
  688. spin_lock_irq(&ctx->dev->lock);
  689. ctx->dev->db_state = RECOVERY;
  690. ctx->dev->rdev.stats.db_state_transitions++;
  691. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  692. spin_unlock_irq(&ctx->dev->lock);
  693. /* slow everybody down */
  694. set_current_state(TASK_UNINTERRUPTIBLE);
  695. schedule_timeout(usecs_to_jiffies(1000));
  696. /* Wait for the dbfifo to completely drain. */
  697. while (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1) > 0) {
  698. set_current_state(TASK_UNINTERRUPTIBLE);
  699. schedule_timeout(usecs_to_jiffies(10));
  700. }
  701. /* flush the SGE contexts */
  702. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  703. if (ret) {
  704. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  705. pci_name(ctx->lldi.pdev));
  706. goto out;
  707. }
  708. /* Count active queues so we can build a list of queues to recover */
  709. spin_lock_irq(&ctx->dev->lock);
  710. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  711. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  712. if (!qp_list.qps) {
  713. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  714. pci_name(ctx->lldi.pdev));
  715. spin_unlock_irq(&ctx->dev->lock);
  716. goto out;
  717. }
  718. qp_list.idx = 0;
  719. /* add and ref each qp so it doesn't get freed */
  720. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  721. spin_unlock_irq(&ctx->dev->lock);
  722. /* now traverse the list in a safe context to recover the db state*/
  723. recover_lost_dbs(ctx, &qp_list);
  724. /* we're almost done! deref the qps and clean up */
  725. deref_qps(qp_list);
  726. kfree(qp_list.qps);
  727. /* Wait for the dbfifo to completely drain again */
  728. while (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1) > 0) {
  729. set_current_state(TASK_UNINTERRUPTIBLE);
  730. schedule_timeout(usecs_to_jiffies(10));
  731. }
  732. /* resume the queues */
  733. spin_lock_irq(&ctx->dev->lock);
  734. if (ctx->dev->qpcnt > db_fc_threshold)
  735. ctx->dev->db_state = FLOW_CONTROL;
  736. else {
  737. ctx->dev->db_state = NORMAL;
  738. idr_for_each(&ctx->dev->qpidr, enable_qp_db, NULL);
  739. }
  740. ctx->dev->rdev.stats.db_state_transitions++;
  741. spin_unlock_irq(&ctx->dev->lock);
  742. out:
  743. /* start up kernel db ringers again */
  744. mutex_unlock(&ctx->dev->db_mutex);
  745. }
  746. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  747. {
  748. struct uld_ctx *ctx = handle;
  749. switch (control) {
  750. case CXGB4_CONTROL_DB_FULL:
  751. stop_queues(ctx);
  752. mutex_lock(&ctx->dev->rdev.stats.lock);
  753. ctx->dev->rdev.stats.db_full++;
  754. mutex_unlock(&ctx->dev->rdev.stats.lock);
  755. break;
  756. case CXGB4_CONTROL_DB_EMPTY:
  757. resume_queues(ctx);
  758. mutex_lock(&ctx->dev->rdev.stats.lock);
  759. ctx->dev->rdev.stats.db_empty++;
  760. mutex_unlock(&ctx->dev->rdev.stats.lock);
  761. break;
  762. case CXGB4_CONTROL_DB_DROP:
  763. recover_queues(ctx);
  764. mutex_lock(&ctx->dev->rdev.stats.lock);
  765. ctx->dev->rdev.stats.db_drop++;
  766. mutex_unlock(&ctx->dev->rdev.stats.lock);
  767. break;
  768. default:
  769. printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
  770. pci_name(ctx->lldi.pdev), control);
  771. break;
  772. }
  773. return 0;
  774. }
  775. static struct cxgb4_uld_info c4iw_uld_info = {
  776. .name = DRV_NAME,
  777. .add = c4iw_uld_add,
  778. .rx_handler = c4iw_uld_rx_handler,
  779. .state_change = c4iw_uld_state_change,
  780. .control = c4iw_uld_control,
  781. };
  782. static int __init c4iw_init_module(void)
  783. {
  784. int err;
  785. err = c4iw_cm_init();
  786. if (err)
  787. return err;
  788. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  789. if (!c4iw_debugfs_root)
  790. printk(KERN_WARNING MOD
  791. "could not create debugfs entry, continuing\n");
  792. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  793. return 0;
  794. }
  795. static void __exit c4iw_exit_module(void)
  796. {
  797. struct uld_ctx *ctx, *tmp;
  798. mutex_lock(&dev_mutex);
  799. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  800. if (ctx->dev)
  801. c4iw_remove(ctx);
  802. kfree(ctx);
  803. }
  804. mutex_unlock(&dev_mutex);
  805. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  806. c4iw_cm_term();
  807. debugfs_remove_recursive(c4iw_debugfs_root);
  808. }
  809. module_init(c4iw_init_module);
  810. module_exit(c4iw_exit_module);