s3c2410_wdt.c 13 KB

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  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@redhat.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. * Changelog:
  26. * 05-Oct-2004 BJD Added semaphore init to stop crashes on open
  27. * Fixed tmr_count / wdt_count confusion
  28. * Added configurable debug
  29. *
  30. * 11-Jan-2005 BJD Fixed divide-by-2 in timeout code
  31. *
  32. * 25-Jan-2005 DA Added suspend/resume support
  33. * Replaced reboot notifier with .shutdown method
  34. *
  35. * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
  36. */
  37. #include <linux/module.h>
  38. #include <linux/moduleparam.h>
  39. #include <linux/types.h>
  40. #include <linux/timer.h>
  41. #include <linux/miscdevice.h>
  42. #include <linux/watchdog.h>
  43. #include <linux/fs.h>
  44. #include <linux/init.h>
  45. #include <linux/platform_device.h>
  46. #include <linux/interrupt.h>
  47. #include <linux/clk.h>
  48. #include <linux/uaccess.h>
  49. #include <linux/io.h>
  50. #include <asm/arch/map.h>
  51. #undef S3C_VA_WATCHDOG
  52. #define S3C_VA_WATCHDOG (0)
  53. #include <asm/plat-s3c/regs-watchdog.h>
  54. #define PFX "s3c2410-wdt: "
  55. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  56. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  57. static int nowayout = WATCHDOG_NOWAYOUT;
  58. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  59. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  60. static int soft_noboot;
  61. static int debug;
  62. module_param(tmr_margin, int, 0);
  63. module_param(tmr_atboot, int, 0);
  64. module_param(nowayout, int, 0);
  65. module_param(soft_noboot, int, 0);
  66. module_param(debug, int, 0);
  67. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
  68. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  69. MODULE_PARM_DESC(tmr_atboot,
  70. "Watchdog is started at boot time if set to 1, default="
  71. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  72. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  73. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  74. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default depends on ONLY_TESTING)");
  75. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
  76. typedef enum close_state {
  77. CLOSE_STATE_NOT,
  78. CLOSE_STATE_ALLOW = 0x4021
  79. } close_state_t;
  80. static unsigned long open_lock;
  81. static struct device *wdt_dev; /* platform device attached to */
  82. static struct resource *wdt_mem;
  83. static struct resource *wdt_irq;
  84. static struct clk *wdt_clock;
  85. static void __iomem *wdt_base;
  86. static unsigned int wdt_count;
  87. static close_state_t allow_close;
  88. static DEFINE_SPINLOCK(wdt_lock);
  89. /* watchdog control routines */
  90. #define DBG(msg...) do { \
  91. if (debug) \
  92. printk(KERN_INFO msg); \
  93. } while (0)
  94. /* functions */
  95. static void s3c2410wdt_keepalive(void)
  96. {
  97. spin_lock(&wdt_lock);
  98. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  99. spin_unlock(&wdt_lock);
  100. }
  101. static void __s3c2410wdt_stop(void)
  102. {
  103. unsigned long wtcon;
  104. spin_lock(&wdt_lock);
  105. wtcon = readl(wdt_base + S3C2410_WTCON);
  106. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  107. writel(wtcon, wdt_base + S3C2410_WTCON);
  108. spin_unlock(&wdt_lock);
  109. }
  110. static void __s3c2410wdt_stop(void)
  111. {
  112. unsigned long wtcon;
  113. wtcon = readl(wdt_base + S3C2410_WTCON);
  114. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  115. writel(wtcon, wdt_base + S3C2410_WTCON);
  116. }
  117. static void s3c2410wdt_stop(void)
  118. {
  119. spin_lock(&wdt_lock);
  120. __s3c2410wdt_stop();
  121. spin_unlock(&wdt_lock);
  122. }
  123. static void s3c2410wdt_start(void)
  124. {
  125. unsigned long wtcon;
  126. spin_lock(&wdt_lock);
  127. __s3c2410wdt_stop();
  128. wtcon = readl(wdt_base + S3C2410_WTCON);
  129. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  130. if (soft_noboot) {
  131. wtcon |= S3C2410_WTCON_INTEN;
  132. wtcon &= ~S3C2410_WTCON_RSTEN;
  133. } else {
  134. wtcon &= ~S3C2410_WTCON_INTEN;
  135. wtcon |= S3C2410_WTCON_RSTEN;
  136. }
  137. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  138. __func__, wdt_count, wtcon);
  139. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  140. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  141. writel(wtcon, wdt_base + S3C2410_WTCON);
  142. spin_unlock(&wdt_lock);
  143. return 0;
  144. }
  145. static int s3c2410wdt_set_heartbeat(int timeout)
  146. {
  147. unsigned int freq = clk_get_rate(wdt_clock);
  148. unsigned int count;
  149. unsigned int divisor = 1;
  150. unsigned long wtcon;
  151. if (timeout < 1)
  152. return -EINVAL;
  153. freq /= 128;
  154. count = timeout * freq;
  155. DBG("%s: count=%d, timeout=%d, freq=%d\n",
  156. __func__, count, timeout, freq);
  157. /* if the count is bigger than the watchdog register,
  158. then work out what we need to do (and if) we can
  159. actually make this value
  160. */
  161. if (count >= 0x10000) {
  162. for (divisor = 1; divisor <= 0x100; divisor++) {
  163. if ((count / divisor) < 0x10000)
  164. break;
  165. }
  166. if ((count / divisor) >= 0x10000) {
  167. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  168. return -EINVAL;
  169. }
  170. }
  171. tmr_margin = timeout;
  172. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  173. __func__, timeout, divisor, count, count/divisor);
  174. count /= divisor;
  175. wdt_count = count;
  176. /* update the pre-scaler */
  177. wtcon = readl(wdt_base + S3C2410_WTCON);
  178. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  179. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  180. writel(count, wdt_base + S3C2410_WTDAT);
  181. writel(wtcon, wdt_base + S3C2410_WTCON);
  182. return 0;
  183. }
  184. /*
  185. * /dev/watchdog handling
  186. */
  187. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  188. {
  189. if (test_and_set_bit(0, &open_lock))
  190. return -EBUSY;
  191. if (nowayout)
  192. __module_get(THIS_MODULE);
  193. allow_close = CLOSE_STATE_NOT;
  194. /* start the timer */
  195. s3c2410wdt_start();
  196. return nonseekable_open(inode, file);
  197. }
  198. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  199. {
  200. /*
  201. * Shut off the timer.
  202. * Lock it in if it's a module and we set nowayout
  203. */
  204. if (allow_close == CLOSE_STATE_ALLOW)
  205. s3c2410wdt_stop();
  206. else {
  207. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  208. s3c2410wdt_keepalive();
  209. }
  210. allow_close = CLOSE_STATE_NOT;
  211. clear_bit(0, &open_lock);
  212. return 0;
  213. }
  214. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  215. size_t len, loff_t *ppos)
  216. {
  217. /*
  218. * Refresh the timer.
  219. */
  220. if (len) {
  221. if (!nowayout) {
  222. size_t i;
  223. /* In case it was set long ago */
  224. allow_close = CLOSE_STATE_NOT;
  225. for (i = 0; i != len; i++) {
  226. char c;
  227. if (get_user(c, data + i))
  228. return -EFAULT;
  229. if (c == 'V')
  230. allow_close = CLOSE_STATE_ALLOW;
  231. }
  232. }
  233. s3c2410wdt_keepalive();
  234. }
  235. return len;
  236. }
  237. #define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE
  238. static const struct watchdog_info s3c2410_wdt_ident = {
  239. .options = OPTIONS,
  240. .firmware_version = 0,
  241. .identity = "S3C2410 Watchdog",
  242. };
  243. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  244. unsigned long arg)
  245. {
  246. void __user *argp = (void __user *)arg;
  247. int __user *p = argp;
  248. int new_margin;
  249. switch (cmd) {
  250. default:
  251. return -ENOTTY;
  252. case WDIOC_GETSUPPORT:
  253. return copy_to_user(argp, &s3c2410_wdt_ident,
  254. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  255. case WDIOC_GETSTATUS:
  256. case WDIOC_GETBOOTSTATUS:
  257. return put_user(0, p);
  258. case WDIOC_KEEPALIVE:
  259. s3c2410wdt_keepalive();
  260. return 0;
  261. case WDIOC_SETTIMEOUT:
  262. if (get_user(new_margin, p))
  263. return -EFAULT;
  264. if (s3c2410wdt_set_heartbeat(new_margin))
  265. return -EINVAL;
  266. s3c2410wdt_keepalive();
  267. return put_user(tmr_margin, p);
  268. case WDIOC_GETTIMEOUT:
  269. return put_user(tmr_margin, p);
  270. }
  271. }
  272. /* kernel interface */
  273. static const struct file_operations s3c2410wdt_fops = {
  274. .owner = THIS_MODULE,
  275. .llseek = no_llseek,
  276. .write = s3c2410wdt_write,
  277. .unlocked_ioctl = s3c2410wdt_ioctl,
  278. .open = s3c2410wdt_open,
  279. .release = s3c2410wdt_release,
  280. };
  281. static struct miscdevice s3c2410wdt_miscdev = {
  282. .minor = WATCHDOG_MINOR,
  283. .name = "watchdog",
  284. .fops = &s3c2410wdt_fops,
  285. };
  286. /* interrupt handler code */
  287. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  288. {
  289. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  290. s3c2410wdt_keepalive();
  291. return IRQ_HANDLED;
  292. }
  293. /* device interface */
  294. static int s3c2410wdt_probe(struct platform_device *pdev)
  295. {
  296. struct resource *res;
  297. struct device *dev;
  298. unsigned int wtcon;
  299. int started = 0;
  300. int ret;
  301. int size;
  302. DBG("%s: probe=%p\n", __func__, pdev);
  303. dev = &pdev->dev;
  304. wdt_dev = &pdev->dev;
  305. /* get the memory region for the watchdog timer */
  306. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  307. if (res == NULL) {
  308. dev_err(dev, "no memory resource specified\n");
  309. return -ENOENT;
  310. }
  311. size = (res->end-res->start)+1;
  312. wdt_mem = request_mem_region(res->start, size, pdev->name);
  313. if (wdt_mem == NULL) {
  314. dev_err(dev, "failed to get memory region\n");
  315. ret = -ENOENT;
  316. goto err_req;
  317. }
  318. wdt_base = ioremap(res->start, size);
  319. if (wdt_base == 0) {
  320. dev_err(dev, "failed to ioremap() region\n");
  321. ret = -EINVAL;
  322. goto err_req;
  323. }
  324. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  325. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  326. if (wdt_irq == NULL) {
  327. dev_err(dev, "no irq resource specified\n");
  328. ret = -ENOENT;
  329. goto err_map;
  330. }
  331. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  332. if (ret != 0) {
  333. dev_err(dev, "failed to install irq (%d)\n", ret);
  334. goto err_map;
  335. }
  336. wdt_clock = clk_get(&pdev->dev, "watchdog");
  337. if (IS_ERR(wdt_clock)) {
  338. dev_err(dev, "failed to find watchdog clock source\n");
  339. ret = PTR_ERR(wdt_clock);
  340. goto err_irq;
  341. }
  342. clk_enable(wdt_clock);
  343. /* see if we can actually set the requested timer margin, and if
  344. * not, try the default value */
  345. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  346. started = s3c2410wdt_set_heartbeat(
  347. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  348. if (started == 0)
  349. dev_info(dev,
  350. "tmr_margin value out of range, default %d used\n",
  351. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  352. else
  353. dev_info(dev, "default timer value is out of range, cannot start\n");
  354. }
  355. ret = misc_register(&s3c2410wdt_miscdev);
  356. if (ret) {
  357. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  358. WATCHDOG_MINOR, ret);
  359. goto err_clk;
  360. }
  361. if (tmr_atboot && started == 0) {
  362. dev_info(dev, "starting watchdog timer\n");
  363. s3c2410wdt_start();
  364. } else if (!tmr_atboot) {
  365. /* if we're not enabling the watchdog, then ensure it is
  366. * disabled if it has been left running from the bootloader
  367. * or other source */
  368. s3c2410wdt_stop();
  369. }
  370. /* print out a statement of readiness */
  371. wtcon = readl(wdt_base + S3C2410_WTCON);
  372. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  373. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  374. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  375. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  376. return 0;
  377. err_clk:
  378. clk_disable(wdt_clock);
  379. clk_put(wdt_clock);
  380. err_irq:
  381. free_irq(wdt_irq->start, pdev);
  382. err_map:
  383. iounmap(wdt_base);
  384. err_req:
  385. release_resource(wdt_mem);
  386. kfree(wdt_mem);
  387. return ret;
  388. }
  389. static int s3c2410wdt_remove(struct platform_device *dev)
  390. {
  391. release_resource(wdt_mem);
  392. kfree(wdt_mem);
  393. wdt_mem = NULL;
  394. free_irq(wdt_irq->start, dev);
  395. wdt_irq = NULL;
  396. clk_disable(wdt_clock);
  397. clk_put(wdt_clock);
  398. wdt_clock = NULL;
  399. iounmap(wdt_base);
  400. misc_deregister(&s3c2410wdt_miscdev);
  401. return 0;
  402. }
  403. static void s3c2410wdt_shutdown(struct platform_device *dev)
  404. {
  405. s3c2410wdt_stop();
  406. }
  407. #ifdef CONFIG_PM
  408. static unsigned long wtcon_save;
  409. static unsigned long wtdat_save;
  410. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  411. {
  412. /* Save watchdog state, and turn it off. */
  413. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  414. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  415. /* Note that WTCNT doesn't need to be saved. */
  416. s3c2410wdt_stop();
  417. return 0;
  418. }
  419. static int s3c2410wdt_resume(struct platform_device *dev)
  420. {
  421. /* Restore watchdog state. */
  422. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  423. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  424. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  425. printk(KERN_INFO PFX "watchdog %sabled\n",
  426. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  427. return 0;
  428. }
  429. #else
  430. #define s3c2410wdt_suspend NULL
  431. #define s3c2410wdt_resume NULL
  432. #endif /* CONFIG_PM */
  433. static struct platform_driver s3c2410wdt_driver = {
  434. .probe = s3c2410wdt_probe,
  435. .remove = s3c2410wdt_remove,
  436. .shutdown = s3c2410wdt_shutdown,
  437. .suspend = s3c2410wdt_suspend,
  438. .resume = s3c2410wdt_resume,
  439. .driver = {
  440. .owner = THIS_MODULE,
  441. .name = "s3c2410-wdt",
  442. },
  443. };
  444. static char banner[] __initdata =
  445. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  446. static int __init watchdog_init(void)
  447. {
  448. printk(banner);
  449. return platform_driver_register(&s3c2410wdt_driver);
  450. }
  451. static void __exit watchdog_exit(void)
  452. {
  453. platform_driver_unregister(&s3c2410wdt_driver);
  454. }
  455. module_init(watchdog_init);
  456. module_exit(watchdog_exit);
  457. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  458. "Dimitry Andric <dimitry.andric@tomtom.com>");
  459. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  460. MODULE_LICENSE("GPL");
  461. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  462. MODULE_ALIAS("platform:s3c2410-wdt");