iwl3945-base.c 232 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  95. * DMA services
  96. *
  97. * Theory of operation
  98. *
  99. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  100. * of buffer descriptors, each of which points to one or more data buffers for
  101. * the device to read from or fill. Driver and device exchange status of each
  102. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  103. * entries in each circular buffer, to protect against confusing empty and full
  104. * queue states.
  105. *
  106. * The device reads or writes the data in the queues via the device's several
  107. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  108. *
  109. * For Tx queue, there are low mark and high mark limits. If, after queuing
  110. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  111. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  112. * Tx queue resumed.
  113. *
  114. * The 3945 operates with six queues: One receive queue, one transmit queue
  115. * (#4) for sending commands to the device firmware, and four transmit queues
  116. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  117. ***************************************************/
  118. int iwl3945_queue_space(const struct iwl3945_queue *q)
  119. {
  120. int s = q->read_ptr - q->write_ptr;
  121. if (q->read_ptr > q->write_ptr)
  122. s -= q->n_bd;
  123. if (s <= 0)
  124. s += q->n_window;
  125. /* keep some reserve to not confuse empty and full situations */
  126. s -= 2;
  127. if (s < 0)
  128. s = 0;
  129. return s;
  130. }
  131. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  132. {
  133. return q->write_ptr > q->read_ptr ?
  134. (i >= q->read_ptr && i < q->write_ptr) :
  135. !(i < q->read_ptr && i >= q->write_ptr);
  136. }
  137. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  138. {
  139. /* This is for scan command, the big buffer at end of command array */
  140. if (is_huge)
  141. return q->n_window; /* must be power of 2 */
  142. /* Otherwise, use normal size buffers */
  143. return index & (q->n_window - 1);
  144. }
  145. /**
  146. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  147. */
  148. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  149. int count, int slots_num, u32 id)
  150. {
  151. q->n_bd = count;
  152. q->n_window = slots_num;
  153. q->id = id;
  154. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  155. * and iwl_queue_dec_wrap are broken. */
  156. BUG_ON(!is_power_of_2(count));
  157. /* slots_num must be power-of-two size, otherwise
  158. * get_cmd_index is broken. */
  159. BUG_ON(!is_power_of_2(slots_num));
  160. q->low_mark = q->n_window / 4;
  161. if (q->low_mark < 4)
  162. q->low_mark = 4;
  163. q->high_mark = q->n_window / 8;
  164. if (q->high_mark < 2)
  165. q->high_mark = 2;
  166. q->write_ptr = q->read_ptr = 0;
  167. return 0;
  168. }
  169. /**
  170. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  171. */
  172. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  173. struct iwl3945_tx_queue *txq, u32 id)
  174. {
  175. struct pci_dev *dev = priv->pci_dev;
  176. /* Driver private data, only for Tx (not command) queues,
  177. * not shared with device. */
  178. if (id != IWL_CMD_QUEUE_NUM) {
  179. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  180. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  181. if (!txq->txb) {
  182. IWL_ERROR("kmalloc for auxiliary BD "
  183. "structures failed\n");
  184. goto error;
  185. }
  186. } else
  187. txq->txb = NULL;
  188. /* Circular buffer of transmit frame descriptors (TFDs),
  189. * shared with device */
  190. txq->bd = pci_alloc_consistent(dev,
  191. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  192. &txq->q.dma_addr);
  193. if (!txq->bd) {
  194. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  195. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  196. goto error;
  197. }
  198. txq->q.id = id;
  199. return 0;
  200. error:
  201. kfree(txq->txb);
  202. txq->txb = NULL;
  203. return -ENOMEM;
  204. }
  205. /**
  206. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  207. */
  208. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  209. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  210. {
  211. struct pci_dev *dev = priv->pci_dev;
  212. int len;
  213. int rc = 0;
  214. /*
  215. * Alloc buffer array for commands (Tx or other types of commands).
  216. * For the command queue (#4), allocate command space + one big
  217. * command for scan, since scan command is very huge; the system will
  218. * not have two scans at the same time, so only one is needed.
  219. * For data Tx queues (all other queues), no super-size command
  220. * space is needed.
  221. */
  222. len = sizeof(struct iwl3945_cmd) * slots_num;
  223. if (txq_id == IWL_CMD_QUEUE_NUM)
  224. len += IWL_MAX_SCAN_SIZE;
  225. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  226. if (!txq->cmd)
  227. return -ENOMEM;
  228. /* Alloc driver data array and TFD circular buffer */
  229. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  230. if (rc) {
  231. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  232. return -ENOMEM;
  233. }
  234. txq->need_update = 0;
  235. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  236. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  237. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  238. /* Initialize queue high/low-water, head/tail indexes */
  239. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  240. /* Tell device where to find queue, enable DMA channel. */
  241. iwl3945_hw_tx_queue_init(priv, txq);
  242. return 0;
  243. }
  244. /**
  245. * iwl3945_tx_queue_free - Deallocate DMA queue.
  246. * @txq: Transmit queue to deallocate.
  247. *
  248. * Empty queue by removing and destroying all BD's.
  249. * Free all buffers.
  250. * 0-fill, but do not free "txq" descriptor structure.
  251. */
  252. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  253. {
  254. struct iwl3945_queue *q = &txq->q;
  255. struct pci_dev *dev = priv->pci_dev;
  256. int len;
  257. if (q->n_bd == 0)
  258. return;
  259. /* first, empty all BD's */
  260. for (; q->write_ptr != q->read_ptr;
  261. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  262. iwl3945_hw_txq_free_tfd(priv, txq);
  263. len = sizeof(struct iwl3945_cmd) * q->n_window;
  264. if (q->id == IWL_CMD_QUEUE_NUM)
  265. len += IWL_MAX_SCAN_SIZE;
  266. /* De-alloc array of command/tx buffers */
  267. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  268. /* De-alloc circular buffer of TFDs */
  269. if (txq->q.n_bd)
  270. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  271. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  272. /* De-alloc array of per-TFD driver data */
  273. kfree(txq->txb);
  274. txq->txb = NULL;
  275. /* 0-fill queue descriptor structure */
  276. memset(txq, 0, sizeof(*txq));
  277. }
  278. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  279. /*************** STATION TABLE MANAGEMENT ****
  280. * mac80211 should be examined to determine if sta_info is duplicating
  281. * the functionality provided here
  282. */
  283. /**************************************************************/
  284. #if 0 /* temporary disable till we add real remove station */
  285. /**
  286. * iwl3945_remove_station - Remove driver's knowledge of station.
  287. *
  288. * NOTE: This does not remove station from device's station table.
  289. */
  290. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  291. {
  292. int index = IWL_INVALID_STATION;
  293. int i;
  294. unsigned long flags;
  295. spin_lock_irqsave(&priv->sta_lock, flags);
  296. if (is_ap)
  297. index = IWL_AP_ID;
  298. else if (is_broadcast_ether_addr(addr))
  299. index = priv->hw_setting.bcast_sta_id;
  300. else
  301. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  302. if (priv->stations[i].used &&
  303. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  304. addr)) {
  305. index = i;
  306. break;
  307. }
  308. if (unlikely(index == IWL_INVALID_STATION))
  309. goto out;
  310. if (priv->stations[index].used) {
  311. priv->stations[index].used = 0;
  312. priv->num_stations--;
  313. }
  314. BUG_ON(priv->num_stations < 0);
  315. out:
  316. spin_unlock_irqrestore(&priv->sta_lock, flags);
  317. return 0;
  318. }
  319. #endif
  320. /**
  321. * iwl3945_clear_stations_table - Clear the driver's station table
  322. *
  323. * NOTE: This does not clear or otherwise alter the device's station table.
  324. */
  325. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  326. {
  327. unsigned long flags;
  328. spin_lock_irqsave(&priv->sta_lock, flags);
  329. priv->num_stations = 0;
  330. memset(priv->stations, 0, sizeof(priv->stations));
  331. spin_unlock_irqrestore(&priv->sta_lock, flags);
  332. }
  333. /**
  334. * iwl3945_add_station - Add station to station tables in driver and device
  335. */
  336. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  337. {
  338. int i;
  339. int index = IWL_INVALID_STATION;
  340. struct iwl3945_station_entry *station;
  341. unsigned long flags_spin;
  342. u8 rate;
  343. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  344. if (is_ap)
  345. index = IWL_AP_ID;
  346. else if (is_broadcast_ether_addr(addr))
  347. index = priv->hw_setting.bcast_sta_id;
  348. else
  349. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  350. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  351. addr)) {
  352. index = i;
  353. break;
  354. }
  355. if (!priv->stations[i].used &&
  356. index == IWL_INVALID_STATION)
  357. index = i;
  358. }
  359. /* These two conditions has the same outcome but keep them separate
  360. since they have different meaning */
  361. if (unlikely(index == IWL_INVALID_STATION)) {
  362. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  363. return index;
  364. }
  365. if (priv->stations[index].used &&
  366. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  367. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  368. return index;
  369. }
  370. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  371. station = &priv->stations[index];
  372. station->used = 1;
  373. priv->num_stations++;
  374. /* Set up the REPLY_ADD_STA command to send to device */
  375. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  376. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  377. station->sta.mode = 0;
  378. station->sta.sta.sta_id = index;
  379. station->sta.station_flags = 0;
  380. if (priv->band == IEEE80211_BAND_5GHZ)
  381. rate = IWL_RATE_6M_PLCP;
  382. else
  383. rate = IWL_RATE_1M_PLCP;
  384. /* Turn on both antennas for the station... */
  385. station->sta.rate_n_flags =
  386. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  387. station->current_rate.rate_n_flags =
  388. le16_to_cpu(station->sta.rate_n_flags);
  389. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  390. /* Add station to device's station table */
  391. iwl3945_send_add_station(priv, &station->sta, flags);
  392. return index;
  393. }
  394. /*************** DRIVER STATUS FUNCTIONS *****/
  395. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  396. {
  397. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  398. * set but EXIT_PENDING is not */
  399. return test_bit(STATUS_READY, &priv->status) &&
  400. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  401. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  402. }
  403. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  404. {
  405. return test_bit(STATUS_ALIVE, &priv->status);
  406. }
  407. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  408. {
  409. return test_bit(STATUS_INIT, &priv->status);
  410. }
  411. static inline int iwl3945_is_rfkill_sw(struct iwl3945_priv *priv)
  412. {
  413. return test_bit(STATUS_RF_KILL_SW, &priv->status);
  414. }
  415. static inline int iwl3945_is_rfkill_hw(struct iwl3945_priv *priv)
  416. {
  417. return test_bit(STATUS_RF_KILL_HW, &priv->status);
  418. }
  419. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  420. {
  421. return iwl3945_is_rfkill_hw(priv) ||
  422. iwl3945_is_rfkill_sw(priv);
  423. }
  424. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  425. {
  426. if (iwl3945_is_rfkill(priv))
  427. return 0;
  428. return iwl3945_is_ready(priv);
  429. }
  430. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  431. #define IWL_CMD(x) case x : return #x
  432. static const char *get_cmd_string(u8 cmd)
  433. {
  434. switch (cmd) {
  435. IWL_CMD(REPLY_ALIVE);
  436. IWL_CMD(REPLY_ERROR);
  437. IWL_CMD(REPLY_RXON);
  438. IWL_CMD(REPLY_RXON_ASSOC);
  439. IWL_CMD(REPLY_QOS_PARAM);
  440. IWL_CMD(REPLY_RXON_TIMING);
  441. IWL_CMD(REPLY_ADD_STA);
  442. IWL_CMD(REPLY_REMOVE_STA);
  443. IWL_CMD(REPLY_REMOVE_ALL_STA);
  444. IWL_CMD(REPLY_3945_RX);
  445. IWL_CMD(REPLY_TX);
  446. IWL_CMD(REPLY_RATE_SCALE);
  447. IWL_CMD(REPLY_LEDS_CMD);
  448. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  449. IWL_CMD(RADAR_NOTIFICATION);
  450. IWL_CMD(REPLY_QUIET_CMD);
  451. IWL_CMD(REPLY_CHANNEL_SWITCH);
  452. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  453. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  454. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  455. IWL_CMD(POWER_TABLE_CMD);
  456. IWL_CMD(PM_SLEEP_NOTIFICATION);
  457. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  458. IWL_CMD(REPLY_SCAN_CMD);
  459. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  460. IWL_CMD(SCAN_START_NOTIFICATION);
  461. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  462. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  463. IWL_CMD(BEACON_NOTIFICATION);
  464. IWL_CMD(REPLY_TX_BEACON);
  465. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  466. IWL_CMD(QUIET_NOTIFICATION);
  467. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  468. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  469. IWL_CMD(REPLY_BT_CONFIG);
  470. IWL_CMD(REPLY_STATISTICS_CMD);
  471. IWL_CMD(STATISTICS_NOTIFICATION);
  472. IWL_CMD(REPLY_CARD_STATE_CMD);
  473. IWL_CMD(CARD_STATE_NOTIFICATION);
  474. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  475. default:
  476. return "UNKNOWN";
  477. }
  478. }
  479. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  480. /**
  481. * iwl3945_enqueue_hcmd - enqueue a uCode command
  482. * @priv: device private data point
  483. * @cmd: a point to the ucode command structure
  484. *
  485. * The function returns < 0 values to indicate the operation is
  486. * failed. On success, it turns the index (> 0) of command in the
  487. * command queue.
  488. */
  489. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  490. {
  491. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  492. struct iwl3945_queue *q = &txq->q;
  493. struct iwl3945_tfd_frame *tfd;
  494. u32 *control_flags;
  495. struct iwl3945_cmd *out_cmd;
  496. u32 idx;
  497. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  498. dma_addr_t phys_addr;
  499. int pad;
  500. u16 count;
  501. int ret;
  502. unsigned long flags;
  503. /* If any of the command structures end up being larger than
  504. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  505. * we will need to increase the size of the TFD entries */
  506. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  507. !(cmd->meta.flags & CMD_SIZE_HUGE));
  508. if (iwl3945_is_rfkill(priv)) {
  509. IWL_DEBUG_INFO("Not sending command - RF KILL");
  510. return -EIO;
  511. }
  512. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  513. IWL_ERROR("No space for Tx\n");
  514. return -ENOSPC;
  515. }
  516. spin_lock_irqsave(&priv->hcmd_lock, flags);
  517. tfd = &txq->bd[q->write_ptr];
  518. memset(tfd, 0, sizeof(*tfd));
  519. control_flags = (u32 *) tfd;
  520. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  521. out_cmd = &txq->cmd[idx];
  522. out_cmd->hdr.cmd = cmd->id;
  523. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  524. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  525. /* At this point, the out_cmd now has all of the incoming cmd
  526. * information */
  527. out_cmd->hdr.flags = 0;
  528. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  529. INDEX_TO_SEQ(q->write_ptr));
  530. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  531. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  532. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  533. offsetof(struct iwl3945_cmd, hdr);
  534. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  535. pad = U32_PAD(cmd->len);
  536. count = TFD_CTL_COUNT_GET(*control_flags);
  537. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  538. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  539. "%d bytes at %d[%d]:%d\n",
  540. get_cmd_string(out_cmd->hdr.cmd),
  541. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  542. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  543. txq->need_update = 1;
  544. /* Increment and update queue's write index */
  545. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  546. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  547. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  548. return ret ? ret : idx;
  549. }
  550. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  551. {
  552. int ret;
  553. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  554. /* An asynchronous command can not expect an SKB to be set. */
  555. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  556. /* An asynchronous command MUST have a callback. */
  557. BUG_ON(!cmd->meta.u.callback);
  558. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  559. return -EBUSY;
  560. ret = iwl3945_enqueue_hcmd(priv, cmd);
  561. if (ret < 0) {
  562. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  563. get_cmd_string(cmd->id), ret);
  564. return ret;
  565. }
  566. return 0;
  567. }
  568. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  569. {
  570. int cmd_idx;
  571. int ret;
  572. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  573. /* A synchronous command can not have a callback set. */
  574. BUG_ON(cmd->meta.u.callback != NULL);
  575. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  576. IWL_ERROR("Error sending %s: Already sending a host command\n",
  577. get_cmd_string(cmd->id));
  578. ret = -EBUSY;
  579. goto out;
  580. }
  581. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  582. if (cmd->meta.flags & CMD_WANT_SKB)
  583. cmd->meta.source = &cmd->meta;
  584. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  585. if (cmd_idx < 0) {
  586. ret = cmd_idx;
  587. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  588. get_cmd_string(cmd->id), ret);
  589. goto out;
  590. }
  591. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  592. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  593. HOST_COMPLETE_TIMEOUT);
  594. if (!ret) {
  595. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  596. IWL_ERROR("Error sending %s: time out after %dms.\n",
  597. get_cmd_string(cmd->id),
  598. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  599. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  600. ret = -ETIMEDOUT;
  601. goto cancel;
  602. }
  603. }
  604. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  605. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  606. get_cmd_string(cmd->id));
  607. ret = -ECANCELED;
  608. goto fail;
  609. }
  610. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  611. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  612. get_cmd_string(cmd->id));
  613. ret = -EIO;
  614. goto fail;
  615. }
  616. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  617. IWL_ERROR("Error: Response NULL in '%s'\n",
  618. get_cmd_string(cmd->id));
  619. ret = -EIO;
  620. goto out;
  621. }
  622. ret = 0;
  623. goto out;
  624. cancel:
  625. if (cmd->meta.flags & CMD_WANT_SKB) {
  626. struct iwl3945_cmd *qcmd;
  627. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  628. * TX cmd queue. Otherwise in case the cmd comes
  629. * in later, it will possibly set an invalid
  630. * address (cmd->meta.source). */
  631. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  632. qcmd->meta.flags &= ~CMD_WANT_SKB;
  633. }
  634. fail:
  635. if (cmd->meta.u.skb) {
  636. dev_kfree_skb_any(cmd->meta.u.skb);
  637. cmd->meta.u.skb = NULL;
  638. }
  639. out:
  640. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  641. return ret;
  642. }
  643. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  644. {
  645. if (cmd->meta.flags & CMD_ASYNC)
  646. return iwl3945_send_cmd_async(priv, cmd);
  647. return iwl3945_send_cmd_sync(priv, cmd);
  648. }
  649. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  650. {
  651. struct iwl3945_host_cmd cmd = {
  652. .id = id,
  653. .len = len,
  654. .data = data,
  655. };
  656. return iwl3945_send_cmd_sync(priv, &cmd);
  657. }
  658. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  659. {
  660. struct iwl3945_host_cmd cmd = {
  661. .id = id,
  662. .len = sizeof(val),
  663. .data = &val,
  664. };
  665. return iwl3945_send_cmd_sync(priv, &cmd);
  666. }
  667. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  668. {
  669. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  670. }
  671. /**
  672. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  673. * @band: 2.4 or 5 GHz band
  674. * @channel: Any channel valid for the requested band
  675. * In addition to setting the staging RXON, priv->band is also set.
  676. *
  677. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  678. * in the staging RXON flag structure based on the band
  679. */
  680. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  681. enum ieee80211_band band,
  682. u16 channel)
  683. {
  684. if (!iwl3945_get_channel_info(priv, band, channel)) {
  685. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  686. channel, band);
  687. return -EINVAL;
  688. }
  689. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  690. (priv->band == band))
  691. return 0;
  692. priv->staging_rxon.channel = cpu_to_le16(channel);
  693. if (band == IEEE80211_BAND_5GHZ)
  694. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  695. else
  696. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  697. priv->band = band;
  698. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  699. return 0;
  700. }
  701. /**
  702. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  703. *
  704. * NOTE: This is really only useful during development and can eventually
  705. * be #ifdef'd out once the driver is stable and folks aren't actively
  706. * making changes
  707. */
  708. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  709. {
  710. int error = 0;
  711. int counter = 1;
  712. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  713. error |= le32_to_cpu(rxon->flags &
  714. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  715. RXON_FLG_RADAR_DETECT_MSK));
  716. if (error)
  717. IWL_WARNING("check 24G fields %d | %d\n",
  718. counter++, error);
  719. } else {
  720. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  721. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  722. if (error)
  723. IWL_WARNING("check 52 fields %d | %d\n",
  724. counter++, error);
  725. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  726. if (error)
  727. IWL_WARNING("check 52 CCK %d | %d\n",
  728. counter++, error);
  729. }
  730. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  731. if (error)
  732. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  733. /* make sure basic rates 6Mbps and 1Mbps are supported */
  734. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  735. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  736. if (error)
  737. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  738. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  739. if (error)
  740. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  741. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  742. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  743. if (error)
  744. IWL_WARNING("check CCK and short slot %d | %d\n",
  745. counter++, error);
  746. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  747. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  748. if (error)
  749. IWL_WARNING("check CCK & auto detect %d | %d\n",
  750. counter++, error);
  751. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  752. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  753. if (error)
  754. IWL_WARNING("check TGG and auto detect %d | %d\n",
  755. counter++, error);
  756. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  757. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  758. RXON_FLG_ANT_A_MSK)) == 0);
  759. if (error)
  760. IWL_WARNING("check antenna %d %d\n", counter++, error);
  761. if (error)
  762. IWL_WARNING("Tuning to channel %d\n",
  763. le16_to_cpu(rxon->channel));
  764. if (error) {
  765. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  766. return -1;
  767. }
  768. return 0;
  769. }
  770. /**
  771. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  772. * @priv: staging_rxon is compared to active_rxon
  773. *
  774. * If the RXON structure is changing enough to require a new tune,
  775. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  776. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  777. */
  778. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  779. {
  780. /* These items are only settable from the full RXON command */
  781. if (!(iwl3945_is_associated(priv)) ||
  782. compare_ether_addr(priv->staging_rxon.bssid_addr,
  783. priv->active_rxon.bssid_addr) ||
  784. compare_ether_addr(priv->staging_rxon.node_addr,
  785. priv->active_rxon.node_addr) ||
  786. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  787. priv->active_rxon.wlap_bssid_addr) ||
  788. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  789. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  790. (priv->staging_rxon.air_propagation !=
  791. priv->active_rxon.air_propagation) ||
  792. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  793. return 1;
  794. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  795. * be updated with the RXON_ASSOC command -- however only some
  796. * flag transitions are allowed using RXON_ASSOC */
  797. /* Check if we are not switching bands */
  798. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  799. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  800. return 1;
  801. /* Check if we are switching association toggle */
  802. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  803. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  804. return 1;
  805. return 0;
  806. }
  807. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  808. {
  809. int rc = 0;
  810. struct iwl3945_rx_packet *res = NULL;
  811. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  812. struct iwl3945_host_cmd cmd = {
  813. .id = REPLY_RXON_ASSOC,
  814. .len = sizeof(rxon_assoc),
  815. .meta.flags = CMD_WANT_SKB,
  816. .data = &rxon_assoc,
  817. };
  818. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  819. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  820. if ((rxon1->flags == rxon2->flags) &&
  821. (rxon1->filter_flags == rxon2->filter_flags) &&
  822. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  823. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  824. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  825. return 0;
  826. }
  827. rxon_assoc.flags = priv->staging_rxon.flags;
  828. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  829. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  830. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  831. rxon_assoc.reserved = 0;
  832. rc = iwl3945_send_cmd_sync(priv, &cmd);
  833. if (rc)
  834. return rc;
  835. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  836. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  837. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  838. rc = -EIO;
  839. }
  840. priv->alloc_rxb_skb--;
  841. dev_kfree_skb_any(cmd.meta.u.skb);
  842. return rc;
  843. }
  844. /**
  845. * iwl3945_commit_rxon - commit staging_rxon to hardware
  846. *
  847. * The RXON command in staging_rxon is committed to the hardware and
  848. * the active_rxon structure is updated with the new data. This
  849. * function correctly transitions out of the RXON_ASSOC_MSK state if
  850. * a HW tune is required based on the RXON structure changes.
  851. */
  852. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  853. {
  854. /* cast away the const for active_rxon in this function */
  855. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  856. int rc = 0;
  857. if (!iwl3945_is_alive(priv))
  858. return -1;
  859. /* always get timestamp with Rx frame */
  860. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  861. /* select antenna */
  862. priv->staging_rxon.flags &=
  863. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  864. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  865. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  866. if (rc) {
  867. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  868. return -EINVAL;
  869. }
  870. /* If we don't need to send a full RXON, we can use
  871. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  872. * and other flags for the current radio configuration. */
  873. if (!iwl3945_full_rxon_required(priv)) {
  874. rc = iwl3945_send_rxon_assoc(priv);
  875. if (rc) {
  876. IWL_ERROR("Error setting RXON_ASSOC "
  877. "configuration (%d).\n", rc);
  878. return rc;
  879. }
  880. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  881. return 0;
  882. }
  883. /* If we are currently associated and the new config requires
  884. * an RXON_ASSOC and the new config wants the associated mask enabled,
  885. * we must clear the associated from the active configuration
  886. * before we apply the new config */
  887. if (iwl3945_is_associated(priv) &&
  888. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  889. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  890. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  891. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  892. sizeof(struct iwl3945_rxon_cmd),
  893. &priv->active_rxon);
  894. /* If the mask clearing failed then we set
  895. * active_rxon back to what it was previously */
  896. if (rc) {
  897. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  898. IWL_ERROR("Error clearing ASSOC_MSK on current "
  899. "configuration (%d).\n", rc);
  900. return rc;
  901. }
  902. }
  903. IWL_DEBUG_INFO("Sending RXON\n"
  904. "* with%s RXON_FILTER_ASSOC_MSK\n"
  905. "* channel = %d\n"
  906. "* bssid = %pM\n",
  907. ((priv->staging_rxon.filter_flags &
  908. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  909. le16_to_cpu(priv->staging_rxon.channel),
  910. priv->staging_rxon.bssid_addr);
  911. /* Apply the new configuration */
  912. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  913. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  914. if (rc) {
  915. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  916. return rc;
  917. }
  918. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  919. iwl3945_clear_stations_table(priv);
  920. /* If we issue a new RXON command which required a tune then we must
  921. * send a new TXPOWER command or we won't be able to Tx any frames */
  922. rc = iwl3945_hw_reg_send_txpower(priv);
  923. if (rc) {
  924. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  925. return rc;
  926. }
  927. /* Add the broadcast address so we can send broadcast frames */
  928. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  929. IWL_INVALID_STATION) {
  930. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  931. return -EIO;
  932. }
  933. /* If we have set the ASSOC_MSK and we are in BSS mode then
  934. * add the IWL_AP_ID to the station rate table */
  935. if (iwl3945_is_associated(priv) &&
  936. (priv->iw_mode == NL80211_IFTYPE_STATION))
  937. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  938. == IWL_INVALID_STATION) {
  939. IWL_ERROR("Error adding AP address for transmit.\n");
  940. return -EIO;
  941. }
  942. /* Init the hardware's rate fallback order based on the band */
  943. rc = iwl3945_init_hw_rate_table(priv);
  944. if (rc) {
  945. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  946. return -EIO;
  947. }
  948. return 0;
  949. }
  950. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  951. {
  952. struct iwl3945_bt_cmd bt_cmd = {
  953. .flags = 3,
  954. .lead_time = 0xAA,
  955. .max_kill = 1,
  956. .kill_ack_mask = 0,
  957. .kill_cts_mask = 0,
  958. };
  959. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  960. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  961. }
  962. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  963. {
  964. int rc = 0;
  965. struct iwl3945_rx_packet *res;
  966. struct iwl3945_host_cmd cmd = {
  967. .id = REPLY_SCAN_ABORT_CMD,
  968. .meta.flags = CMD_WANT_SKB,
  969. };
  970. /* If there isn't a scan actively going on in the hardware
  971. * then we are in between scan bands and not actually
  972. * actively scanning, so don't send the abort command */
  973. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  974. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  975. return 0;
  976. }
  977. rc = iwl3945_send_cmd_sync(priv, &cmd);
  978. if (rc) {
  979. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  980. return rc;
  981. }
  982. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  983. if (res->u.status != CAN_ABORT_STATUS) {
  984. /* The scan abort will return 1 for success or
  985. * 2 for "failure". A failure condition can be
  986. * due to simply not being in an active scan which
  987. * can occur if we send the scan abort before we
  988. * the microcode has notified us that a scan is
  989. * completed. */
  990. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  991. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  992. clear_bit(STATUS_SCAN_HW, &priv->status);
  993. }
  994. dev_kfree_skb_any(cmd.meta.u.skb);
  995. return rc;
  996. }
  997. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  998. struct iwl3945_cmd *cmd,
  999. struct sk_buff *skb)
  1000. {
  1001. return 1;
  1002. }
  1003. /*
  1004. * CARD_STATE_CMD
  1005. *
  1006. * Use: Sets the device's internal card state to enable, disable, or halt
  1007. *
  1008. * When in the 'enable' state the card operates as normal.
  1009. * When in the 'disable' state, the card enters into a low power mode.
  1010. * When in the 'halt' state, the card is shut down and must be fully
  1011. * restarted to come back on.
  1012. */
  1013. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1014. {
  1015. struct iwl3945_host_cmd cmd = {
  1016. .id = REPLY_CARD_STATE_CMD,
  1017. .len = sizeof(u32),
  1018. .data = &flags,
  1019. .meta.flags = meta_flag,
  1020. };
  1021. if (meta_flag & CMD_ASYNC)
  1022. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1023. return iwl3945_send_cmd(priv, &cmd);
  1024. }
  1025. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1026. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1027. {
  1028. struct iwl3945_rx_packet *res = NULL;
  1029. if (!skb) {
  1030. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1031. return 1;
  1032. }
  1033. res = (struct iwl3945_rx_packet *)skb->data;
  1034. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1035. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1036. res->hdr.flags);
  1037. return 1;
  1038. }
  1039. switch (res->u.add_sta.status) {
  1040. case ADD_STA_SUCCESS_MSK:
  1041. break;
  1042. default:
  1043. break;
  1044. }
  1045. /* We didn't cache the SKB; let the caller free it */
  1046. return 1;
  1047. }
  1048. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1049. struct iwl3945_addsta_cmd *sta, u8 flags)
  1050. {
  1051. struct iwl3945_rx_packet *res = NULL;
  1052. int rc = 0;
  1053. struct iwl3945_host_cmd cmd = {
  1054. .id = REPLY_ADD_STA,
  1055. .len = sizeof(struct iwl3945_addsta_cmd),
  1056. .meta.flags = flags,
  1057. .data = sta,
  1058. };
  1059. if (flags & CMD_ASYNC)
  1060. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1061. else
  1062. cmd.meta.flags |= CMD_WANT_SKB;
  1063. rc = iwl3945_send_cmd(priv, &cmd);
  1064. if (rc || (flags & CMD_ASYNC))
  1065. return rc;
  1066. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1067. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1068. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1069. res->hdr.flags);
  1070. rc = -EIO;
  1071. }
  1072. if (rc == 0) {
  1073. switch (res->u.add_sta.status) {
  1074. case ADD_STA_SUCCESS_MSK:
  1075. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1076. break;
  1077. default:
  1078. rc = -EIO;
  1079. IWL_WARNING("REPLY_ADD_STA failed\n");
  1080. break;
  1081. }
  1082. }
  1083. priv->alloc_rxb_skb--;
  1084. dev_kfree_skb_any(cmd.meta.u.skb);
  1085. return rc;
  1086. }
  1087. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1088. struct ieee80211_key_conf *keyconf,
  1089. u8 sta_id)
  1090. {
  1091. unsigned long flags;
  1092. __le16 key_flags = 0;
  1093. switch (keyconf->alg) {
  1094. case ALG_CCMP:
  1095. key_flags |= STA_KEY_FLG_CCMP;
  1096. key_flags |= cpu_to_le16(
  1097. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1098. key_flags &= ~STA_KEY_FLG_INVALID;
  1099. break;
  1100. case ALG_TKIP:
  1101. case ALG_WEP:
  1102. default:
  1103. return -EINVAL;
  1104. }
  1105. spin_lock_irqsave(&priv->sta_lock, flags);
  1106. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1107. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1108. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1109. keyconf->keylen);
  1110. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1111. keyconf->keylen);
  1112. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1113. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1114. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1115. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1116. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1117. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1118. return 0;
  1119. }
  1120. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1121. {
  1122. unsigned long flags;
  1123. spin_lock_irqsave(&priv->sta_lock, flags);
  1124. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1125. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1126. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1127. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1128. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1129. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1130. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1131. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1132. return 0;
  1133. }
  1134. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1135. {
  1136. struct list_head *element;
  1137. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1138. priv->frames_count);
  1139. while (!list_empty(&priv->free_frames)) {
  1140. element = priv->free_frames.next;
  1141. list_del(element);
  1142. kfree(list_entry(element, struct iwl3945_frame, list));
  1143. priv->frames_count--;
  1144. }
  1145. if (priv->frames_count) {
  1146. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1147. priv->frames_count);
  1148. priv->frames_count = 0;
  1149. }
  1150. }
  1151. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1152. {
  1153. struct iwl3945_frame *frame;
  1154. struct list_head *element;
  1155. if (list_empty(&priv->free_frames)) {
  1156. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1157. if (!frame) {
  1158. IWL_ERROR("Could not allocate frame!\n");
  1159. return NULL;
  1160. }
  1161. priv->frames_count++;
  1162. return frame;
  1163. }
  1164. element = priv->free_frames.next;
  1165. list_del(element);
  1166. return list_entry(element, struct iwl3945_frame, list);
  1167. }
  1168. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1169. {
  1170. memset(frame, 0, sizeof(*frame));
  1171. list_add(&frame->list, &priv->free_frames);
  1172. }
  1173. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1174. struct ieee80211_hdr *hdr,
  1175. const u8 *dest, int left)
  1176. {
  1177. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1178. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1179. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1180. return 0;
  1181. if (priv->ibss_beacon->len > left)
  1182. return 0;
  1183. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1184. return priv->ibss_beacon->len;
  1185. }
  1186. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1187. {
  1188. u8 i;
  1189. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1190. i = iwl3945_rates[i].next_ieee) {
  1191. if (rate_mask & (1 << i))
  1192. return iwl3945_rates[i].plcp;
  1193. }
  1194. return IWL_RATE_INVALID;
  1195. }
  1196. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1197. {
  1198. struct iwl3945_frame *frame;
  1199. unsigned int frame_size;
  1200. int rc;
  1201. u8 rate;
  1202. frame = iwl3945_get_free_frame(priv);
  1203. if (!frame) {
  1204. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1205. "command.\n");
  1206. return -ENOMEM;
  1207. }
  1208. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1209. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1210. 0xFF0);
  1211. if (rate == IWL_INVALID_RATE)
  1212. rate = IWL_RATE_6M_PLCP;
  1213. } else {
  1214. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1215. if (rate == IWL_INVALID_RATE)
  1216. rate = IWL_RATE_1M_PLCP;
  1217. }
  1218. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1219. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1220. &frame->u.cmd[0]);
  1221. iwl3945_free_frame(priv, frame);
  1222. return rc;
  1223. }
  1224. /******************************************************************************
  1225. *
  1226. * EEPROM related functions
  1227. *
  1228. ******************************************************************************/
  1229. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1230. {
  1231. memcpy(mac, priv->eeprom.mac_address, 6);
  1232. }
  1233. /*
  1234. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1235. * embedded controller) as EEPROM reader; each read is a series of pulses
  1236. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1237. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1238. * simply claims ownership, which should be safe when this function is called
  1239. * (i.e. before loading uCode!).
  1240. */
  1241. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1242. {
  1243. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1244. return 0;
  1245. }
  1246. /**
  1247. * iwl3945_eeprom_init - read EEPROM contents
  1248. *
  1249. * Load the EEPROM contents from adapter into priv->eeprom
  1250. *
  1251. * NOTE: This routine uses the non-debug IO access functions.
  1252. */
  1253. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1254. {
  1255. u16 *e = (u16 *)&priv->eeprom;
  1256. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1257. u32 r;
  1258. int sz = sizeof(priv->eeprom);
  1259. int rc;
  1260. int i;
  1261. u16 addr;
  1262. /* The EEPROM structure has several padding buffers within it
  1263. * and when adding new EEPROM maps is subject to programmer errors
  1264. * which may be very difficult to identify without explicitly
  1265. * checking the resulting size of the eeprom map. */
  1266. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1267. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1268. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1269. return -ENOENT;
  1270. }
  1271. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1272. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1273. if (rc < 0) {
  1274. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1275. return -ENOENT;
  1276. }
  1277. /* eeprom is an array of 16bit values */
  1278. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1279. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1280. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1281. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1282. i += IWL_EEPROM_ACCESS_DELAY) {
  1283. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1284. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1285. break;
  1286. udelay(IWL_EEPROM_ACCESS_DELAY);
  1287. }
  1288. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1289. IWL_ERROR("Time out reading EEPROM[%d]\n", addr);
  1290. return -ETIMEDOUT;
  1291. }
  1292. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1293. }
  1294. return 0;
  1295. }
  1296. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1297. {
  1298. if (priv->hw_setting.shared_virt)
  1299. pci_free_consistent(priv->pci_dev,
  1300. sizeof(struct iwl3945_shared),
  1301. priv->hw_setting.shared_virt,
  1302. priv->hw_setting.shared_phys);
  1303. }
  1304. /**
  1305. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1306. *
  1307. * return : set the bit for each supported rate insert in ie
  1308. */
  1309. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1310. u16 basic_rate, int *left)
  1311. {
  1312. u16 ret_rates = 0, bit;
  1313. int i;
  1314. u8 *cnt = ie;
  1315. u8 *rates = ie + 1;
  1316. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1317. if (bit & supported_rate) {
  1318. ret_rates |= bit;
  1319. rates[*cnt] = iwl3945_rates[i].ieee |
  1320. ((bit & basic_rate) ? 0x80 : 0x00);
  1321. (*cnt)++;
  1322. (*left)--;
  1323. if ((*left <= 0) ||
  1324. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1325. break;
  1326. }
  1327. }
  1328. return ret_rates;
  1329. }
  1330. /**
  1331. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1332. */
  1333. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1334. struct ieee80211_mgmt *frame,
  1335. int left)
  1336. {
  1337. int len = 0;
  1338. u8 *pos = NULL;
  1339. u16 active_rates, ret_rates, cck_rates;
  1340. /* Make sure there is enough space for the probe request,
  1341. * two mandatory IEs and the data */
  1342. left -= 24;
  1343. if (left < 0)
  1344. return 0;
  1345. len += 24;
  1346. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1347. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1348. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1349. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1350. frame->seq_ctrl = 0;
  1351. /* fill in our indirect SSID IE */
  1352. /* ...next IE... */
  1353. left -= 2;
  1354. if (left < 0)
  1355. return 0;
  1356. len += 2;
  1357. pos = &(frame->u.probe_req.variable[0]);
  1358. *pos++ = WLAN_EID_SSID;
  1359. *pos++ = 0;
  1360. /* fill in supported rate */
  1361. /* ...next IE... */
  1362. left -= 2;
  1363. if (left < 0)
  1364. return 0;
  1365. /* ... fill it in... */
  1366. *pos++ = WLAN_EID_SUPP_RATES;
  1367. *pos = 0;
  1368. priv->active_rate = priv->rates_mask;
  1369. active_rates = priv->active_rate;
  1370. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1371. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1372. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1373. priv->active_rate_basic, &left);
  1374. active_rates &= ~ret_rates;
  1375. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1376. priv->active_rate_basic, &left);
  1377. active_rates &= ~ret_rates;
  1378. len += 2 + *pos;
  1379. pos += (*pos) + 1;
  1380. if (active_rates == 0)
  1381. goto fill_end;
  1382. /* fill in supported extended rate */
  1383. /* ...next IE... */
  1384. left -= 2;
  1385. if (left < 0)
  1386. return 0;
  1387. /* ... fill it in... */
  1388. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1389. *pos = 0;
  1390. iwl3945_supported_rate_to_ie(pos, active_rates,
  1391. priv->active_rate_basic, &left);
  1392. if (*pos > 0)
  1393. len += 2 + *pos;
  1394. fill_end:
  1395. return (u16)len;
  1396. }
  1397. /*
  1398. * QoS support
  1399. */
  1400. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1401. struct iwl3945_qosparam_cmd *qos)
  1402. {
  1403. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1404. sizeof(struct iwl3945_qosparam_cmd), qos);
  1405. }
  1406. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1407. {
  1408. u16 cw_min = 15;
  1409. u16 cw_max = 1023;
  1410. u8 aifs = 2;
  1411. u8 is_legacy = 0;
  1412. unsigned long flags;
  1413. int i;
  1414. spin_lock_irqsave(&priv->lock, flags);
  1415. priv->qos_data.qos_active = 0;
  1416. if (priv->iw_mode == NL80211_IFTYPE_ADHOC) {
  1417. if (priv->qos_data.qos_enable)
  1418. priv->qos_data.qos_active = 1;
  1419. if (!(priv->active_rate & 0xfff0)) {
  1420. cw_min = 31;
  1421. is_legacy = 1;
  1422. }
  1423. } else if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1424. if (priv->qos_data.qos_enable)
  1425. priv->qos_data.qos_active = 1;
  1426. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1427. cw_min = 31;
  1428. is_legacy = 1;
  1429. }
  1430. if (priv->qos_data.qos_active)
  1431. aifs = 3;
  1432. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1433. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1434. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1435. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1436. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1437. if (priv->qos_data.qos_active) {
  1438. i = 1;
  1439. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1440. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1441. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1442. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1443. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1444. i = 2;
  1445. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1446. cpu_to_le16((cw_min + 1) / 2 - 1);
  1447. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1448. cpu_to_le16(cw_max);
  1449. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1450. if (is_legacy)
  1451. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1452. cpu_to_le16(6016);
  1453. else
  1454. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1455. cpu_to_le16(3008);
  1456. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1457. i = 3;
  1458. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1459. cpu_to_le16((cw_min + 1) / 4 - 1);
  1460. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1461. cpu_to_le16((cw_max + 1) / 2 - 1);
  1462. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1463. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1464. if (is_legacy)
  1465. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1466. cpu_to_le16(3264);
  1467. else
  1468. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1469. cpu_to_le16(1504);
  1470. } else {
  1471. for (i = 1; i < 4; i++) {
  1472. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1473. cpu_to_le16(cw_min);
  1474. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1475. cpu_to_le16(cw_max);
  1476. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1477. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1478. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1479. }
  1480. }
  1481. IWL_DEBUG_QOS("set QoS to default \n");
  1482. spin_unlock_irqrestore(&priv->lock, flags);
  1483. }
  1484. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1485. {
  1486. unsigned long flags;
  1487. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1488. return;
  1489. if (!priv->qos_data.qos_enable)
  1490. return;
  1491. spin_lock_irqsave(&priv->lock, flags);
  1492. priv->qos_data.def_qos_parm.qos_flags = 0;
  1493. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1494. !priv->qos_data.qos_cap.q_AP.txop_request)
  1495. priv->qos_data.def_qos_parm.qos_flags |=
  1496. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1497. if (priv->qos_data.qos_active)
  1498. priv->qos_data.def_qos_parm.qos_flags |=
  1499. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1500. spin_unlock_irqrestore(&priv->lock, flags);
  1501. if (force || iwl3945_is_associated(priv)) {
  1502. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1503. priv->qos_data.qos_active);
  1504. iwl3945_send_qos_params_command(priv,
  1505. &(priv->qos_data.def_qos_parm));
  1506. }
  1507. }
  1508. /*
  1509. * Power management (not Tx power!) functions
  1510. */
  1511. #define MSEC_TO_USEC 1024
  1512. #define NOSLP __constant_cpu_to_le32(0)
  1513. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1514. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1515. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1516. __constant_cpu_to_le32(X1), \
  1517. __constant_cpu_to_le32(X2), \
  1518. __constant_cpu_to_le32(X3), \
  1519. __constant_cpu_to_le32(X4)}
  1520. /* default power management (not Tx power) table values */
  1521. /* for TIM 0-10 */
  1522. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1523. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1524. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1525. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1526. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1527. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1528. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1529. };
  1530. /* for TIM > 10 */
  1531. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1532. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1533. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1534. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1535. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1536. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1537. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1538. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1539. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1540. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1541. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1542. };
  1543. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1544. {
  1545. int rc = 0, i;
  1546. struct iwl3945_power_mgr *pow_data;
  1547. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1548. u16 pci_pm;
  1549. IWL_DEBUG_POWER("Initialize power \n");
  1550. pow_data = &(priv->power_data);
  1551. memset(pow_data, 0, sizeof(*pow_data));
  1552. pow_data->active_index = IWL_POWER_RANGE_0;
  1553. pow_data->dtim_val = 0xffff;
  1554. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1555. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1556. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1557. if (rc != 0)
  1558. return 0;
  1559. else {
  1560. struct iwl3945_powertable_cmd *cmd;
  1561. IWL_DEBUG_POWER("adjust power command flags\n");
  1562. for (i = 0; i < IWL_POWER_AC; i++) {
  1563. cmd = &pow_data->pwr_range_0[i].cmd;
  1564. if (pci_pm & 0x1)
  1565. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1566. else
  1567. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1568. }
  1569. }
  1570. return rc;
  1571. }
  1572. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1573. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1574. {
  1575. int rc = 0, i;
  1576. u8 skip;
  1577. u32 max_sleep = 0;
  1578. struct iwl3945_power_vec_entry *range;
  1579. u8 period = 0;
  1580. struct iwl3945_power_mgr *pow_data;
  1581. if (mode > IWL_POWER_INDEX_5) {
  1582. IWL_DEBUG_POWER("Error invalid power mode \n");
  1583. return -1;
  1584. }
  1585. pow_data = &(priv->power_data);
  1586. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1587. range = &pow_data->pwr_range_0[0];
  1588. else
  1589. range = &pow_data->pwr_range_1[1];
  1590. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1591. #ifdef IWL_MAC80211_DISABLE
  1592. if (priv->assoc_network != NULL) {
  1593. unsigned long flags;
  1594. period = priv->assoc_network->tim.tim_period;
  1595. }
  1596. #endif /*IWL_MAC80211_DISABLE */
  1597. skip = range[mode].no_dtim;
  1598. if (period == 0) {
  1599. period = 1;
  1600. skip = 0;
  1601. }
  1602. if (skip == 0) {
  1603. max_sleep = period;
  1604. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1605. } else {
  1606. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1607. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1608. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1609. }
  1610. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1611. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1612. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1613. }
  1614. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1615. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1616. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1617. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1618. le32_to_cpu(cmd->sleep_interval[0]),
  1619. le32_to_cpu(cmd->sleep_interval[1]),
  1620. le32_to_cpu(cmd->sleep_interval[2]),
  1621. le32_to_cpu(cmd->sleep_interval[3]),
  1622. le32_to_cpu(cmd->sleep_interval[4]));
  1623. return rc;
  1624. }
  1625. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1626. {
  1627. u32 uninitialized_var(final_mode);
  1628. int rc;
  1629. struct iwl3945_powertable_cmd cmd;
  1630. /* If on battery, set to 3,
  1631. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1632. * else user level */
  1633. switch (mode) {
  1634. case IWL_POWER_BATTERY:
  1635. final_mode = IWL_POWER_INDEX_3;
  1636. break;
  1637. case IWL_POWER_AC:
  1638. final_mode = IWL_POWER_MODE_CAM;
  1639. break;
  1640. default:
  1641. final_mode = mode;
  1642. break;
  1643. }
  1644. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1645. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1646. if (final_mode == IWL_POWER_MODE_CAM)
  1647. clear_bit(STATUS_POWER_PMI, &priv->status);
  1648. else
  1649. set_bit(STATUS_POWER_PMI, &priv->status);
  1650. return rc;
  1651. }
  1652. /**
  1653. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1654. *
  1655. * NOTE: priv->mutex is not required before calling this function
  1656. */
  1657. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1658. {
  1659. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1660. clear_bit(STATUS_SCANNING, &priv->status);
  1661. return 0;
  1662. }
  1663. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1664. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1665. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1666. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1667. queue_work(priv->workqueue, &priv->abort_scan);
  1668. } else
  1669. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1670. return test_bit(STATUS_SCANNING, &priv->status);
  1671. }
  1672. return 0;
  1673. }
  1674. /**
  1675. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1676. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1677. *
  1678. * NOTE: priv->mutex must be held before calling this function
  1679. */
  1680. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1681. {
  1682. unsigned long now = jiffies;
  1683. int ret;
  1684. ret = iwl3945_scan_cancel(priv);
  1685. if (ret && ms) {
  1686. mutex_unlock(&priv->mutex);
  1687. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1688. test_bit(STATUS_SCANNING, &priv->status))
  1689. msleep(1);
  1690. mutex_lock(&priv->mutex);
  1691. return test_bit(STATUS_SCANNING, &priv->status);
  1692. }
  1693. return ret;
  1694. }
  1695. #define MAX_UCODE_BEACON_INTERVAL 1024
  1696. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1697. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1698. {
  1699. u16 new_val = 0;
  1700. u16 beacon_factor = 0;
  1701. beacon_factor =
  1702. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1703. / MAX_UCODE_BEACON_INTERVAL;
  1704. new_val = beacon_val / beacon_factor;
  1705. return cpu_to_le16(new_val);
  1706. }
  1707. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1708. {
  1709. u64 interval_tm_unit;
  1710. u64 tsf, result;
  1711. unsigned long flags;
  1712. struct ieee80211_conf *conf = NULL;
  1713. u16 beacon_int = 0;
  1714. conf = ieee80211_get_hw_conf(priv->hw);
  1715. spin_lock_irqsave(&priv->lock, flags);
  1716. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1717. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1718. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1719. tsf = priv->timestamp1;
  1720. tsf = ((tsf << 32) | priv->timestamp0);
  1721. beacon_int = priv->beacon_int;
  1722. spin_unlock_irqrestore(&priv->lock, flags);
  1723. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1724. if (beacon_int == 0) {
  1725. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1726. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1727. } else {
  1728. priv->rxon_timing.beacon_interval =
  1729. cpu_to_le16(beacon_int);
  1730. priv->rxon_timing.beacon_interval =
  1731. iwl3945_adjust_beacon_interval(
  1732. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1733. }
  1734. priv->rxon_timing.atim_window = 0;
  1735. } else {
  1736. priv->rxon_timing.beacon_interval =
  1737. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1738. /* TODO: we need to get atim_window from upper stack
  1739. * for now we set to 0 */
  1740. priv->rxon_timing.atim_window = 0;
  1741. }
  1742. interval_tm_unit =
  1743. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1744. result = do_div(tsf, interval_tm_unit);
  1745. priv->rxon_timing.beacon_init_val =
  1746. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1747. IWL_DEBUG_ASSOC
  1748. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1749. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1750. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1751. le16_to_cpu(priv->rxon_timing.atim_window));
  1752. }
  1753. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1754. {
  1755. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1756. IWL_ERROR("APs don't scan.\n");
  1757. return 0;
  1758. }
  1759. if (!iwl3945_is_ready_rf(priv)) {
  1760. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1761. return -EIO;
  1762. }
  1763. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1764. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1765. return -EAGAIN;
  1766. }
  1767. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1768. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1769. "Queuing.\n");
  1770. return -EAGAIN;
  1771. }
  1772. IWL_DEBUG_INFO("Starting scan...\n");
  1773. if (priv->cfg->sku & IWL_SKU_G)
  1774. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1775. if (priv->cfg->sku & IWL_SKU_A)
  1776. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1777. set_bit(STATUS_SCANNING, &priv->status);
  1778. priv->scan_start = jiffies;
  1779. priv->scan_pass_start = priv->scan_start;
  1780. queue_work(priv->workqueue, &priv->request_scan);
  1781. return 0;
  1782. }
  1783. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1784. {
  1785. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1786. if (hw_decrypt)
  1787. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1788. else
  1789. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1790. return 0;
  1791. }
  1792. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1793. enum ieee80211_band band)
  1794. {
  1795. if (band == IEEE80211_BAND_5GHZ) {
  1796. priv->staging_rxon.flags &=
  1797. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1798. | RXON_FLG_CCK_MSK);
  1799. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1800. } else {
  1801. /* Copied from iwl3945_bg_post_associate() */
  1802. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1803. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1804. else
  1805. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1806. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1807. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1808. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1809. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1810. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1811. }
  1812. }
  1813. /*
  1814. * initialize rxon structure with default values from eeprom
  1815. */
  1816. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1817. {
  1818. const struct iwl3945_channel_info *ch_info;
  1819. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1820. switch (priv->iw_mode) {
  1821. case NL80211_IFTYPE_AP:
  1822. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1823. break;
  1824. case NL80211_IFTYPE_STATION:
  1825. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1826. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1827. break;
  1828. case NL80211_IFTYPE_ADHOC:
  1829. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1830. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1831. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1832. RXON_FILTER_ACCEPT_GRP_MSK;
  1833. break;
  1834. case NL80211_IFTYPE_MONITOR:
  1835. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1836. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1837. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1838. break;
  1839. default:
  1840. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1841. break;
  1842. }
  1843. #if 0
  1844. /* TODO: Figure out when short_preamble would be set and cache from
  1845. * that */
  1846. if (!hw_to_local(priv->hw)->short_preamble)
  1847. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1848. else
  1849. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1850. #endif
  1851. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1852. le16_to_cpu(priv->active_rxon.channel));
  1853. if (!ch_info)
  1854. ch_info = &priv->channel_info[0];
  1855. /*
  1856. * in some case A channels are all non IBSS
  1857. * in this case force B/G channel
  1858. */
  1859. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1860. !(is_channel_ibss(ch_info)))
  1861. ch_info = &priv->channel_info[0];
  1862. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1863. if (is_channel_a_band(ch_info))
  1864. priv->band = IEEE80211_BAND_5GHZ;
  1865. else
  1866. priv->band = IEEE80211_BAND_2GHZ;
  1867. iwl3945_set_flags_for_phymode(priv, priv->band);
  1868. priv->staging_rxon.ofdm_basic_rates =
  1869. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1870. priv->staging_rxon.cck_basic_rates =
  1871. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1872. }
  1873. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1874. {
  1875. if (mode == NL80211_IFTYPE_ADHOC) {
  1876. const struct iwl3945_channel_info *ch_info;
  1877. ch_info = iwl3945_get_channel_info(priv,
  1878. priv->band,
  1879. le16_to_cpu(priv->staging_rxon.channel));
  1880. if (!ch_info || !is_channel_ibss(ch_info)) {
  1881. IWL_ERROR("channel %d not IBSS channel\n",
  1882. le16_to_cpu(priv->staging_rxon.channel));
  1883. return -EINVAL;
  1884. }
  1885. }
  1886. priv->iw_mode = mode;
  1887. iwl3945_connection_init_rx_config(priv);
  1888. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1889. iwl3945_clear_stations_table(priv);
  1890. /* don't commit rxon if rf-kill is on*/
  1891. if (!iwl3945_is_ready_rf(priv))
  1892. return -EAGAIN;
  1893. cancel_delayed_work(&priv->scan_check);
  1894. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1895. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1896. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1897. return -EAGAIN;
  1898. }
  1899. iwl3945_commit_rxon(priv);
  1900. return 0;
  1901. }
  1902. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1903. struct ieee80211_tx_info *info,
  1904. struct iwl3945_cmd *cmd,
  1905. struct sk_buff *skb_frag,
  1906. int last_frag)
  1907. {
  1908. struct iwl3945_hw_key *keyinfo =
  1909. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1910. switch (keyinfo->alg) {
  1911. case ALG_CCMP:
  1912. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1913. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1914. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1915. break;
  1916. case ALG_TKIP:
  1917. #if 0
  1918. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  1919. if (last_frag)
  1920. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  1921. 8);
  1922. else
  1923. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  1924. #endif
  1925. break;
  1926. case ALG_WEP:
  1927. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  1928. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1929. if (keyinfo->keylen == 13)
  1930. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  1931. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  1932. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1933. "with key %d\n", info->control.hw_key->hw_key_idx);
  1934. break;
  1935. default:
  1936. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  1937. break;
  1938. }
  1939. }
  1940. /*
  1941. * handle build REPLY_TX command notification.
  1942. */
  1943. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  1944. struct iwl3945_cmd *cmd,
  1945. struct ieee80211_tx_info *info,
  1946. struct ieee80211_hdr *hdr,
  1947. int is_unicast, u8 std_id)
  1948. {
  1949. __le16 fc = hdr->frame_control;
  1950. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  1951. u8 rc_flags = info->control.rates[0].flags;
  1952. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1953. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1954. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1955. if (ieee80211_is_mgmt(fc))
  1956. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1957. if (ieee80211_is_probe_resp(fc) &&
  1958. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1959. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1960. } else {
  1961. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1962. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1963. }
  1964. cmd->cmd.tx.sta_id = std_id;
  1965. if (ieee80211_has_morefrags(fc))
  1966. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1967. if (ieee80211_is_data_qos(fc)) {
  1968. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1969. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  1970. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1971. } else {
  1972. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1973. }
  1974. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1975. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1976. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1977. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1978. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1979. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1980. }
  1981. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1982. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1983. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1984. if (ieee80211_is_mgmt(fc)) {
  1985. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1986. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  1987. else
  1988. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  1989. } else {
  1990. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  1991. #ifdef CONFIG_IWL3945_LEDS
  1992. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1993. #endif
  1994. }
  1995. cmd->cmd.tx.driver_txop = 0;
  1996. cmd->cmd.tx.tx_flags = tx_flags;
  1997. cmd->cmd.tx.next_frame_len = 0;
  1998. }
  1999. /**
  2000. * iwl3945_get_sta_id - Find station's index within station table
  2001. */
  2002. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2003. {
  2004. int sta_id;
  2005. u16 fc = le16_to_cpu(hdr->frame_control);
  2006. /* If this frame is broadcast or management, use broadcast station id */
  2007. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2008. is_multicast_ether_addr(hdr->addr1))
  2009. return priv->hw_setting.bcast_sta_id;
  2010. switch (priv->iw_mode) {
  2011. /* If we are a client station in a BSS network, use the special
  2012. * AP station entry (that's the only station we communicate with) */
  2013. case NL80211_IFTYPE_STATION:
  2014. return IWL_AP_ID;
  2015. /* If we are an AP, then find the station, or use BCAST */
  2016. case NL80211_IFTYPE_AP:
  2017. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2018. if (sta_id != IWL_INVALID_STATION)
  2019. return sta_id;
  2020. return priv->hw_setting.bcast_sta_id;
  2021. /* If this frame is going out to an IBSS network, find the station,
  2022. * or create a new station table entry */
  2023. case NL80211_IFTYPE_ADHOC: {
  2024. /* Create new station table entry */
  2025. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2026. if (sta_id != IWL_INVALID_STATION)
  2027. return sta_id;
  2028. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2029. if (sta_id != IWL_INVALID_STATION)
  2030. return sta_id;
  2031. IWL_DEBUG_DROP("Station %pM not in station map. "
  2032. "Defaulting to broadcast...\n",
  2033. hdr->addr1);
  2034. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2035. return priv->hw_setting.bcast_sta_id;
  2036. }
  2037. /* If we are in monitor mode, use BCAST. This is required for
  2038. * packet injection. */
  2039. case NL80211_IFTYPE_MONITOR:
  2040. return priv->hw_setting.bcast_sta_id;
  2041. default:
  2042. IWL_WARNING("Unknown mode of operation: %d\n", priv->iw_mode);
  2043. return priv->hw_setting.bcast_sta_id;
  2044. }
  2045. }
  2046. /*
  2047. * start REPLY_TX command process
  2048. */
  2049. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2050. {
  2051. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2052. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2053. struct iwl3945_tfd_frame *tfd;
  2054. u32 *control_flags;
  2055. int txq_id = skb_get_queue_mapping(skb);
  2056. struct iwl3945_tx_queue *txq = NULL;
  2057. struct iwl3945_queue *q = NULL;
  2058. dma_addr_t phys_addr;
  2059. dma_addr_t txcmd_phys;
  2060. struct iwl3945_cmd *out_cmd = NULL;
  2061. u16 len, idx, len_org, hdr_len;
  2062. u8 id;
  2063. u8 unicast;
  2064. u8 sta_id;
  2065. u8 tid = 0;
  2066. u16 seq_number = 0;
  2067. __le16 fc;
  2068. u8 wait_write_ptr = 0;
  2069. u8 *qc = NULL;
  2070. unsigned long flags;
  2071. int rc;
  2072. spin_lock_irqsave(&priv->lock, flags);
  2073. if (iwl3945_is_rfkill(priv)) {
  2074. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2075. goto drop_unlock;
  2076. }
  2077. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2078. IWL_ERROR("ERROR: No TX rate available.\n");
  2079. goto drop_unlock;
  2080. }
  2081. unicast = !is_multicast_ether_addr(hdr->addr1);
  2082. id = 0;
  2083. fc = hdr->frame_control;
  2084. #ifdef CONFIG_IWL3945_DEBUG
  2085. if (ieee80211_is_auth(fc))
  2086. IWL_DEBUG_TX("Sending AUTH frame\n");
  2087. else if (ieee80211_is_assoc_req(fc))
  2088. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2089. else if (ieee80211_is_reassoc_req(fc))
  2090. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2091. #endif
  2092. /* drop all data frame if we are not associated */
  2093. if (ieee80211_is_data(fc) &&
  2094. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  2095. (!iwl3945_is_associated(priv) ||
  2096. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  2097. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2098. goto drop_unlock;
  2099. }
  2100. spin_unlock_irqrestore(&priv->lock, flags);
  2101. hdr_len = ieee80211_hdrlen(fc);
  2102. /* Find (or create) index into station table for destination station */
  2103. sta_id = iwl3945_get_sta_id(priv, hdr);
  2104. if (sta_id == IWL_INVALID_STATION) {
  2105. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  2106. hdr->addr1);
  2107. goto drop;
  2108. }
  2109. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2110. if (ieee80211_is_data_qos(fc)) {
  2111. qc = ieee80211_get_qos_ctl(hdr);
  2112. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  2113. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2114. IEEE80211_SCTL_SEQ;
  2115. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2116. (hdr->seq_ctrl &
  2117. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2118. seq_number += 0x10;
  2119. }
  2120. /* Descriptor for chosen Tx queue */
  2121. txq = &priv->txq[txq_id];
  2122. q = &txq->q;
  2123. spin_lock_irqsave(&priv->lock, flags);
  2124. /* Set up first empty TFD within this queue's circular TFD buffer */
  2125. tfd = &txq->bd[q->write_ptr];
  2126. memset(tfd, 0, sizeof(*tfd));
  2127. control_flags = (u32 *) tfd;
  2128. idx = get_cmd_index(q, q->write_ptr, 0);
  2129. /* Set up driver data for this TFD */
  2130. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2131. txq->txb[q->write_ptr].skb[0] = skb;
  2132. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2133. out_cmd = &txq->cmd[idx];
  2134. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2135. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2136. /*
  2137. * Set up the Tx-command (not MAC!) header.
  2138. * Store the chosen Tx queue and TFD index within the sequence field;
  2139. * after Tx, uCode's Tx response will return this value so driver can
  2140. * locate the frame within the tx queue and do post-tx processing.
  2141. */
  2142. out_cmd->hdr.cmd = REPLY_TX;
  2143. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2144. INDEX_TO_SEQ(q->write_ptr)));
  2145. /* Copy MAC header from skb into command buffer */
  2146. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2147. /*
  2148. * Use the first empty entry in this queue's command buffer array
  2149. * to contain the Tx command and MAC header concatenated together
  2150. * (payload data will be in another buffer).
  2151. * Size of this varies, due to varying MAC header length.
  2152. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2153. * of the MAC header (device reads on dword boundaries).
  2154. * We'll tell device about this padding later.
  2155. */
  2156. len = priv->hw_setting.tx_cmd_len +
  2157. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2158. len_org = len;
  2159. len = (len + 3) & ~3;
  2160. if (len_org != len)
  2161. len_org = 1;
  2162. else
  2163. len_org = 0;
  2164. /* Physical address of this Tx command's header (not MAC header!),
  2165. * within command buffer array. */
  2166. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2167. offsetof(struct iwl3945_cmd, hdr);
  2168. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2169. * first entry */
  2170. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2171. if (info->control.hw_key)
  2172. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2173. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2174. * if any (802.11 null frames have no payload). */
  2175. len = skb->len - hdr_len;
  2176. if (len) {
  2177. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2178. len, PCI_DMA_TODEVICE);
  2179. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2180. }
  2181. if (!len)
  2182. /* If there is no payload, then we use only one Tx buffer */
  2183. *control_flags = TFD_CTL_COUNT_SET(1);
  2184. else
  2185. /* Else use 2 buffers.
  2186. * Tell 3945 about any padding after MAC header */
  2187. *control_flags = TFD_CTL_COUNT_SET(2) |
  2188. TFD_CTL_PAD_SET(U32_PAD(len));
  2189. /* Total # bytes to be transmitted */
  2190. len = (u16)skb->len;
  2191. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2192. /* TODO need this for burst mode later on */
  2193. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2194. /* set is_hcca to 0; it probably will never be implemented */
  2195. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2196. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2197. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2198. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2199. txq->need_update = 1;
  2200. if (qc)
  2201. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2202. } else {
  2203. wait_write_ptr = 1;
  2204. txq->need_update = 0;
  2205. }
  2206. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2207. sizeof(out_cmd->cmd.tx));
  2208. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2209. ieee80211_hdrlen(fc));
  2210. /* Tell device the write index *just past* this latest filled TFD */
  2211. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2212. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2213. spin_unlock_irqrestore(&priv->lock, flags);
  2214. if (rc)
  2215. return rc;
  2216. if ((iwl3945_queue_space(q) < q->high_mark)
  2217. && priv->mac80211_registered) {
  2218. if (wait_write_ptr) {
  2219. spin_lock_irqsave(&priv->lock, flags);
  2220. txq->need_update = 1;
  2221. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2222. spin_unlock_irqrestore(&priv->lock, flags);
  2223. }
  2224. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2225. }
  2226. return 0;
  2227. drop_unlock:
  2228. spin_unlock_irqrestore(&priv->lock, flags);
  2229. drop:
  2230. return -1;
  2231. }
  2232. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2233. {
  2234. const struct ieee80211_supported_band *sband = NULL;
  2235. struct ieee80211_rate *rate;
  2236. int i;
  2237. sband = iwl3945_get_band(priv, priv->band);
  2238. if (!sband) {
  2239. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2240. return;
  2241. }
  2242. priv->active_rate = 0;
  2243. priv->active_rate_basic = 0;
  2244. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2245. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2246. for (i = 0; i < sband->n_bitrates; i++) {
  2247. rate = &sband->bitrates[i];
  2248. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2249. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2250. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2251. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2252. priv->active_rate |= (1 << rate->hw_value);
  2253. }
  2254. }
  2255. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2256. priv->active_rate, priv->active_rate_basic);
  2257. /*
  2258. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2259. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2260. * OFDM
  2261. */
  2262. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2263. priv->staging_rxon.cck_basic_rates =
  2264. ((priv->active_rate_basic &
  2265. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2266. else
  2267. priv->staging_rxon.cck_basic_rates =
  2268. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2269. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2270. priv->staging_rxon.ofdm_basic_rates =
  2271. ((priv->active_rate_basic &
  2272. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2273. IWL_FIRST_OFDM_RATE) & 0xFF;
  2274. else
  2275. priv->staging_rxon.ofdm_basic_rates =
  2276. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2277. }
  2278. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2279. {
  2280. unsigned long flags;
  2281. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2282. return;
  2283. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2284. disable_radio ? "OFF" : "ON");
  2285. if (disable_radio) {
  2286. iwl3945_scan_cancel(priv);
  2287. /* FIXME: This is a workaround for AP */
  2288. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2289. spin_lock_irqsave(&priv->lock, flags);
  2290. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2291. CSR_UCODE_SW_BIT_RFKILL);
  2292. spin_unlock_irqrestore(&priv->lock, flags);
  2293. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2294. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2295. }
  2296. return;
  2297. }
  2298. spin_lock_irqsave(&priv->lock, flags);
  2299. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2300. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2301. spin_unlock_irqrestore(&priv->lock, flags);
  2302. /* wake up ucode */
  2303. msleep(10);
  2304. spin_lock_irqsave(&priv->lock, flags);
  2305. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2306. if (!iwl3945_grab_nic_access(priv))
  2307. iwl3945_release_nic_access(priv);
  2308. spin_unlock_irqrestore(&priv->lock, flags);
  2309. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2310. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2311. "disabled by HW switch\n");
  2312. return;
  2313. }
  2314. if (priv->is_open)
  2315. queue_work(priv->workqueue, &priv->restart);
  2316. return;
  2317. }
  2318. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2319. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2320. {
  2321. u16 fc =
  2322. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2323. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2324. return;
  2325. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2326. return;
  2327. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2328. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2329. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2330. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2331. RX_RES_STATUS_BAD_ICV_MIC)
  2332. stats->flag |= RX_FLAG_MMIC_ERROR;
  2333. case RX_RES_STATUS_SEC_TYPE_WEP:
  2334. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2335. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2336. RX_RES_STATUS_DECRYPT_OK) {
  2337. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2338. stats->flag |= RX_FLAG_DECRYPTED;
  2339. }
  2340. break;
  2341. default:
  2342. break;
  2343. }
  2344. }
  2345. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2346. #include "iwl-spectrum.h"
  2347. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2348. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2349. #define TIME_UNIT 1024
  2350. /*
  2351. * extended beacon time format
  2352. * time in usec will be changed into a 32-bit value in 8:24 format
  2353. * the high 1 byte is the beacon counts
  2354. * the lower 3 bytes is the time in usec within one beacon interval
  2355. */
  2356. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2357. {
  2358. u32 quot;
  2359. u32 rem;
  2360. u32 interval = beacon_interval * 1024;
  2361. if (!interval || !usec)
  2362. return 0;
  2363. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2364. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2365. return (quot << 24) + rem;
  2366. }
  2367. /* base is usually what we get from ucode with each received frame,
  2368. * the same as HW timer counter counting down
  2369. */
  2370. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2371. {
  2372. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2373. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2374. u32 interval = beacon_interval * TIME_UNIT;
  2375. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2376. (addon & BEACON_TIME_MASK_HIGH);
  2377. if (base_low > addon_low)
  2378. res += base_low - addon_low;
  2379. else if (base_low < addon_low) {
  2380. res += interval + base_low - addon_low;
  2381. res += (1 << 24);
  2382. } else
  2383. res += (1 << 24);
  2384. return cpu_to_le32(res);
  2385. }
  2386. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2387. struct ieee80211_measurement_params *params,
  2388. u8 type)
  2389. {
  2390. struct iwl3945_spectrum_cmd spectrum;
  2391. struct iwl3945_rx_packet *res;
  2392. struct iwl3945_host_cmd cmd = {
  2393. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2394. .data = (void *)&spectrum,
  2395. .meta.flags = CMD_WANT_SKB,
  2396. };
  2397. u32 add_time = le64_to_cpu(params->start_time);
  2398. int rc;
  2399. int spectrum_resp_status;
  2400. int duration = le16_to_cpu(params->duration);
  2401. if (iwl3945_is_associated(priv))
  2402. add_time =
  2403. iwl3945_usecs_to_beacons(
  2404. le64_to_cpu(params->start_time) - priv->last_tsf,
  2405. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2406. memset(&spectrum, 0, sizeof(spectrum));
  2407. spectrum.channel_count = cpu_to_le16(1);
  2408. spectrum.flags =
  2409. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2410. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2411. cmd.len = sizeof(spectrum);
  2412. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2413. if (iwl3945_is_associated(priv))
  2414. spectrum.start_time =
  2415. iwl3945_add_beacon_time(priv->last_beacon_time,
  2416. add_time,
  2417. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2418. else
  2419. spectrum.start_time = 0;
  2420. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2421. spectrum.channels[0].channel = params->channel;
  2422. spectrum.channels[0].type = type;
  2423. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2424. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2425. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2426. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2427. if (rc)
  2428. return rc;
  2429. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2430. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2431. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2432. rc = -EIO;
  2433. }
  2434. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2435. switch (spectrum_resp_status) {
  2436. case 0: /* Command will be handled */
  2437. if (res->u.spectrum.id != 0xff) {
  2438. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2439. res->u.spectrum.id);
  2440. priv->measurement_status &= ~MEASUREMENT_READY;
  2441. }
  2442. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2443. rc = 0;
  2444. break;
  2445. case 1: /* Command will not be handled */
  2446. rc = -EAGAIN;
  2447. break;
  2448. }
  2449. dev_kfree_skb_any(cmd.meta.u.skb);
  2450. return rc;
  2451. }
  2452. #endif
  2453. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2454. struct iwl3945_rx_mem_buffer *rxb)
  2455. {
  2456. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2457. struct iwl3945_alive_resp *palive;
  2458. struct delayed_work *pwork;
  2459. palive = &pkt->u.alive_frame;
  2460. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2461. "0x%01X 0x%01X\n",
  2462. palive->is_valid, palive->ver_type,
  2463. palive->ver_subtype);
  2464. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2465. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2466. memcpy(&priv->card_alive_init,
  2467. &pkt->u.alive_frame,
  2468. sizeof(struct iwl3945_init_alive_resp));
  2469. pwork = &priv->init_alive_start;
  2470. } else {
  2471. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2472. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2473. sizeof(struct iwl3945_alive_resp));
  2474. pwork = &priv->alive_start;
  2475. iwl3945_disable_events(priv);
  2476. }
  2477. /* We delay the ALIVE response by 5ms to
  2478. * give the HW RF Kill time to activate... */
  2479. if (palive->is_valid == UCODE_VALID_OK)
  2480. queue_delayed_work(priv->workqueue, pwork,
  2481. msecs_to_jiffies(5));
  2482. else
  2483. IWL_WARNING("uCode did not respond OK.\n");
  2484. }
  2485. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2486. struct iwl3945_rx_mem_buffer *rxb)
  2487. {
  2488. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2489. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2490. return;
  2491. }
  2492. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2493. struct iwl3945_rx_mem_buffer *rxb)
  2494. {
  2495. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2496. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2497. "seq 0x%04X ser 0x%08X\n",
  2498. le32_to_cpu(pkt->u.err_resp.error_type),
  2499. get_cmd_string(pkt->u.err_resp.cmd_id),
  2500. pkt->u.err_resp.cmd_id,
  2501. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2502. le32_to_cpu(pkt->u.err_resp.error_info));
  2503. }
  2504. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2505. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2506. {
  2507. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2508. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2509. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2510. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2511. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2512. rxon->channel = csa->channel;
  2513. priv->staging_rxon.channel = csa->channel;
  2514. }
  2515. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2516. struct iwl3945_rx_mem_buffer *rxb)
  2517. {
  2518. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2519. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2520. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2521. if (!report->state) {
  2522. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2523. "Spectrum Measure Notification: Start\n");
  2524. return;
  2525. }
  2526. memcpy(&priv->measure_report, report, sizeof(*report));
  2527. priv->measurement_status |= MEASUREMENT_READY;
  2528. #endif
  2529. }
  2530. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2531. struct iwl3945_rx_mem_buffer *rxb)
  2532. {
  2533. #ifdef CONFIG_IWL3945_DEBUG
  2534. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2535. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2536. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2537. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2538. #endif
  2539. }
  2540. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2541. struct iwl3945_rx_mem_buffer *rxb)
  2542. {
  2543. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2544. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2545. "notification for %s:\n",
  2546. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2547. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2548. }
  2549. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2550. {
  2551. struct iwl3945_priv *priv =
  2552. container_of(work, struct iwl3945_priv, beacon_update);
  2553. struct sk_buff *beacon;
  2554. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2555. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2556. if (!beacon) {
  2557. IWL_ERROR("update beacon failed\n");
  2558. return;
  2559. }
  2560. mutex_lock(&priv->mutex);
  2561. /* new beacon skb is allocated every time; dispose previous.*/
  2562. if (priv->ibss_beacon)
  2563. dev_kfree_skb(priv->ibss_beacon);
  2564. priv->ibss_beacon = beacon;
  2565. mutex_unlock(&priv->mutex);
  2566. iwl3945_send_beacon_cmd(priv);
  2567. }
  2568. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2569. struct iwl3945_rx_mem_buffer *rxb)
  2570. {
  2571. #ifdef CONFIG_IWL3945_DEBUG
  2572. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2573. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2574. u8 rate = beacon->beacon_notify_hdr.rate;
  2575. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2576. "tsf %d %d rate %d\n",
  2577. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2578. beacon->beacon_notify_hdr.failure_frame,
  2579. le32_to_cpu(beacon->ibss_mgr_status),
  2580. le32_to_cpu(beacon->high_tsf),
  2581. le32_to_cpu(beacon->low_tsf), rate);
  2582. #endif
  2583. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2584. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2585. queue_work(priv->workqueue, &priv->beacon_update);
  2586. }
  2587. /* Service response to REPLY_SCAN_CMD (0x80) */
  2588. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2589. struct iwl3945_rx_mem_buffer *rxb)
  2590. {
  2591. #ifdef CONFIG_IWL3945_DEBUG
  2592. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2593. struct iwl3945_scanreq_notification *notif =
  2594. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2595. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2596. #endif
  2597. }
  2598. /* Service SCAN_START_NOTIFICATION (0x82) */
  2599. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2600. struct iwl3945_rx_mem_buffer *rxb)
  2601. {
  2602. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2603. struct iwl3945_scanstart_notification *notif =
  2604. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2605. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2606. IWL_DEBUG_SCAN("Scan start: "
  2607. "%d [802.11%s] "
  2608. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2609. notif->channel,
  2610. notif->band ? "bg" : "a",
  2611. notif->tsf_high,
  2612. notif->tsf_low, notif->status, notif->beacon_timer);
  2613. }
  2614. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2615. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2616. struct iwl3945_rx_mem_buffer *rxb)
  2617. {
  2618. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2619. struct iwl3945_scanresults_notification *notif =
  2620. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2621. IWL_DEBUG_SCAN("Scan ch.res: "
  2622. "%d [802.11%s] "
  2623. "(TSF: 0x%08X:%08X) - %d "
  2624. "elapsed=%lu usec (%dms since last)\n",
  2625. notif->channel,
  2626. notif->band ? "bg" : "a",
  2627. le32_to_cpu(notif->tsf_high),
  2628. le32_to_cpu(notif->tsf_low),
  2629. le32_to_cpu(notif->statistics[0]),
  2630. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2631. jiffies_to_msecs(elapsed_jiffies
  2632. (priv->last_scan_jiffies, jiffies)));
  2633. priv->last_scan_jiffies = jiffies;
  2634. priv->next_scan_jiffies = 0;
  2635. }
  2636. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2637. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2638. struct iwl3945_rx_mem_buffer *rxb)
  2639. {
  2640. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2641. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2642. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2643. scan_notif->scanned_channels,
  2644. scan_notif->tsf_low,
  2645. scan_notif->tsf_high, scan_notif->status);
  2646. /* The HW is no longer scanning */
  2647. clear_bit(STATUS_SCAN_HW, &priv->status);
  2648. /* The scan completion notification came in, so kill that timer... */
  2649. cancel_delayed_work(&priv->scan_check);
  2650. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2651. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2652. "2.4" : "5.2",
  2653. jiffies_to_msecs(elapsed_jiffies
  2654. (priv->scan_pass_start, jiffies)));
  2655. /* Remove this scanned band from the list of pending
  2656. * bands to scan, band G precedes A in order of scanning
  2657. * as seen in iwl3945_bg_request_scan */
  2658. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2659. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2660. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2661. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2662. /* If a request to abort was given, or the scan did not succeed
  2663. * then we reset the scan state machine and terminate,
  2664. * re-queuing another scan if one has been requested */
  2665. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2666. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2667. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2668. } else {
  2669. /* If there are more bands on this scan pass reschedule */
  2670. if (priv->scan_bands > 0)
  2671. goto reschedule;
  2672. }
  2673. priv->last_scan_jiffies = jiffies;
  2674. priv->next_scan_jiffies = 0;
  2675. IWL_DEBUG_INFO("Setting scan to off\n");
  2676. clear_bit(STATUS_SCANNING, &priv->status);
  2677. IWL_DEBUG_INFO("Scan took %dms\n",
  2678. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2679. queue_work(priv->workqueue, &priv->scan_completed);
  2680. return;
  2681. reschedule:
  2682. priv->scan_pass_start = jiffies;
  2683. queue_work(priv->workqueue, &priv->request_scan);
  2684. }
  2685. /* Handle notification from uCode that card's power state is changing
  2686. * due to software, hardware, or critical temperature RFKILL */
  2687. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2688. struct iwl3945_rx_mem_buffer *rxb)
  2689. {
  2690. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2691. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2692. unsigned long status = priv->status;
  2693. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2694. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2695. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2696. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2697. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2698. if (flags & HW_CARD_DISABLED)
  2699. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2700. else
  2701. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2702. if (flags & SW_CARD_DISABLED)
  2703. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2704. else
  2705. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2706. iwl3945_scan_cancel(priv);
  2707. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2708. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2709. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2710. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2711. queue_work(priv->workqueue, &priv->rf_kill);
  2712. else
  2713. wake_up_interruptible(&priv->wait_command_queue);
  2714. }
  2715. /**
  2716. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2717. *
  2718. * Setup the RX handlers for each of the reply types sent from the uCode
  2719. * to the host.
  2720. *
  2721. * This function chains into the hardware specific files for them to setup
  2722. * any hardware specific handlers as well.
  2723. */
  2724. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2725. {
  2726. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2727. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2728. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2729. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2730. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2731. iwl3945_rx_spectrum_measure_notif;
  2732. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2733. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2734. iwl3945_rx_pm_debug_statistics_notif;
  2735. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2736. /*
  2737. * The same handler is used for both the REPLY to a discrete
  2738. * statistics request from the host as well as for the periodic
  2739. * statistics notifications (after received beacons) from the uCode.
  2740. */
  2741. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2742. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2743. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2744. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2745. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2746. iwl3945_rx_scan_results_notif;
  2747. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2748. iwl3945_rx_scan_complete_notif;
  2749. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2750. /* Set up hardware specific Rx handlers */
  2751. iwl3945_hw_rx_handler_setup(priv);
  2752. }
  2753. /**
  2754. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2755. * When FW advances 'R' index, all entries between old and new 'R' index
  2756. * need to be reclaimed.
  2757. */
  2758. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2759. int txq_id, int index)
  2760. {
  2761. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2762. struct iwl3945_queue *q = &txq->q;
  2763. int nfreed = 0;
  2764. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2765. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2766. "is out of range [0-%d] %d %d.\n", txq_id,
  2767. index, q->n_bd, q->write_ptr, q->read_ptr);
  2768. return;
  2769. }
  2770. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2771. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2772. if (nfreed > 1) {
  2773. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2774. q->write_ptr, q->read_ptr);
  2775. queue_work(priv->workqueue, &priv->restart);
  2776. break;
  2777. }
  2778. nfreed++;
  2779. }
  2780. }
  2781. /**
  2782. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2783. * @rxb: Rx buffer to reclaim
  2784. *
  2785. * If an Rx buffer has an async callback associated with it the callback
  2786. * will be executed. The attached skb (if present) will only be freed
  2787. * if the callback returns 1
  2788. */
  2789. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2790. struct iwl3945_rx_mem_buffer *rxb)
  2791. {
  2792. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2793. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2794. int txq_id = SEQ_TO_QUEUE(sequence);
  2795. int index = SEQ_TO_INDEX(sequence);
  2796. int huge = sequence & SEQ_HUGE_FRAME;
  2797. int cmd_index;
  2798. struct iwl3945_cmd *cmd;
  2799. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2800. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2801. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2802. /* Input error checking is done when commands are added to queue. */
  2803. if (cmd->meta.flags & CMD_WANT_SKB) {
  2804. cmd->meta.source->u.skb = rxb->skb;
  2805. rxb->skb = NULL;
  2806. } else if (cmd->meta.u.callback &&
  2807. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2808. rxb->skb = NULL;
  2809. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2810. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2811. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2812. wake_up_interruptible(&priv->wait_command_queue);
  2813. }
  2814. }
  2815. /************************** RX-FUNCTIONS ****************************/
  2816. /*
  2817. * Rx theory of operation
  2818. *
  2819. * The host allocates 32 DMA target addresses and passes the host address
  2820. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2821. * 0 to 31
  2822. *
  2823. * Rx Queue Indexes
  2824. * The host/firmware share two index registers for managing the Rx buffers.
  2825. *
  2826. * The READ index maps to the first position that the firmware may be writing
  2827. * to -- the driver can read up to (but not including) this position and get
  2828. * good data.
  2829. * The READ index is managed by the firmware once the card is enabled.
  2830. *
  2831. * The WRITE index maps to the last position the driver has read from -- the
  2832. * position preceding WRITE is the last slot the firmware can place a packet.
  2833. *
  2834. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2835. * WRITE = READ.
  2836. *
  2837. * During initialization, the host sets up the READ queue position to the first
  2838. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2839. *
  2840. * When the firmware places a packet in a buffer, it will advance the READ index
  2841. * and fire the RX interrupt. The driver can then query the READ index and
  2842. * process as many packets as possible, moving the WRITE index forward as it
  2843. * resets the Rx queue buffers with new memory.
  2844. *
  2845. * The management in the driver is as follows:
  2846. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2847. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2848. * to replenish the iwl->rxq->rx_free.
  2849. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2850. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2851. * 'processed' and 'read' driver indexes as well)
  2852. * + A received packet is processed and handed to the kernel network stack,
  2853. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2854. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2855. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2856. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2857. * were enough free buffers and RX_STALLED is set it is cleared.
  2858. *
  2859. *
  2860. * Driver sequence:
  2861. *
  2862. * iwl3945_rx_queue_alloc() Allocates rx_free
  2863. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2864. * iwl3945_rx_queue_restock
  2865. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2866. * queue, updates firmware pointers, and updates
  2867. * the WRITE index. If insufficient rx_free buffers
  2868. * are available, schedules iwl3945_rx_replenish
  2869. *
  2870. * -- enable interrupts --
  2871. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  2872. * READ INDEX, detaching the SKB from the pool.
  2873. * Moves the packet buffer from queue to rx_used.
  2874. * Calls iwl3945_rx_queue_restock to refill any empty
  2875. * slots.
  2876. * ...
  2877. *
  2878. */
  2879. /**
  2880. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2881. */
  2882. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  2883. {
  2884. int s = q->read - q->write;
  2885. if (s <= 0)
  2886. s += RX_QUEUE_SIZE;
  2887. /* keep some buffer to not confuse full and empty queue */
  2888. s -= 2;
  2889. if (s < 0)
  2890. s = 0;
  2891. return s;
  2892. }
  2893. /**
  2894. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2895. */
  2896. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  2897. {
  2898. u32 reg = 0;
  2899. int rc = 0;
  2900. unsigned long flags;
  2901. spin_lock_irqsave(&q->lock, flags);
  2902. if (q->need_update == 0)
  2903. goto exit_unlock;
  2904. /* If power-saving is in use, make sure device is awake */
  2905. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2906. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2907. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2908. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  2909. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2910. goto exit_unlock;
  2911. }
  2912. rc = iwl3945_grab_nic_access(priv);
  2913. if (rc)
  2914. goto exit_unlock;
  2915. /* Device expects a multiple of 8 */
  2916. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  2917. q->write & ~0x7);
  2918. iwl3945_release_nic_access(priv);
  2919. /* Else device is assumed to be awake */
  2920. } else
  2921. /* Device expects a multiple of 8 */
  2922. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2923. q->need_update = 0;
  2924. exit_unlock:
  2925. spin_unlock_irqrestore(&q->lock, flags);
  2926. return rc;
  2927. }
  2928. /**
  2929. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2930. */
  2931. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  2932. dma_addr_t dma_addr)
  2933. {
  2934. return cpu_to_le32((u32)dma_addr);
  2935. }
  2936. /**
  2937. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2938. *
  2939. * If there are slots in the RX queue that need to be restocked,
  2940. * and we have free pre-allocated buffers, fill the ranks as much
  2941. * as we can, pulling from rx_free.
  2942. *
  2943. * This moves the 'write' index forward to catch up with 'processed', and
  2944. * also updates the memory address in the firmware to reference the new
  2945. * target buffer.
  2946. */
  2947. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  2948. {
  2949. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2950. struct list_head *element;
  2951. struct iwl3945_rx_mem_buffer *rxb;
  2952. unsigned long flags;
  2953. int write, rc;
  2954. spin_lock_irqsave(&rxq->lock, flags);
  2955. write = rxq->write & ~0x7;
  2956. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2957. /* Get next free Rx buffer, remove from free list */
  2958. element = rxq->rx_free.next;
  2959. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  2960. list_del(element);
  2961. /* Point to Rx buffer via next RBD in circular buffer */
  2962. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  2963. rxq->queue[rxq->write] = rxb;
  2964. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2965. rxq->free_count--;
  2966. }
  2967. spin_unlock_irqrestore(&rxq->lock, flags);
  2968. /* If the pre-allocated buffer pool is dropping low, schedule to
  2969. * refill it */
  2970. if (rxq->free_count <= RX_LOW_WATERMARK)
  2971. queue_work(priv->workqueue, &priv->rx_replenish);
  2972. /* If we've added more space for the firmware to place data, tell it.
  2973. * Increment device's write pointer in multiples of 8. */
  2974. if ((write != (rxq->write & ~0x7))
  2975. || (abs(rxq->write - rxq->read) > 7)) {
  2976. spin_lock_irqsave(&rxq->lock, flags);
  2977. rxq->need_update = 1;
  2978. spin_unlock_irqrestore(&rxq->lock, flags);
  2979. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2980. if (rc)
  2981. return rc;
  2982. }
  2983. return 0;
  2984. }
  2985. /**
  2986. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2987. *
  2988. * When moving to rx_free an SKB is allocated for the slot.
  2989. *
  2990. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2991. * This is called as a scheduled work item (except for during initialization)
  2992. */
  2993. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  2994. {
  2995. struct iwl3945_rx_queue *rxq = &priv->rxq;
  2996. struct list_head *element;
  2997. struct iwl3945_rx_mem_buffer *rxb;
  2998. unsigned long flags;
  2999. spin_lock_irqsave(&rxq->lock, flags);
  3000. while (!list_empty(&rxq->rx_used)) {
  3001. element = rxq->rx_used.next;
  3002. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3003. /* Alloc a new receive buffer */
  3004. rxb->skb =
  3005. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3006. if (!rxb->skb) {
  3007. if (net_ratelimit())
  3008. printk(KERN_CRIT DRV_NAME
  3009. ": Can not allocate SKB buffers\n");
  3010. /* We don't reschedule replenish work here -- we will
  3011. * call the restock method and if it still needs
  3012. * more buffers it will schedule replenish */
  3013. break;
  3014. }
  3015. /* If radiotap head is required, reserve some headroom here.
  3016. * The physical head count is a variable rx_stats->phy_count.
  3017. * We reserve 4 bytes here. Plus these extra bytes, the
  3018. * headroom of the physical head should be enough for the
  3019. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3020. */
  3021. skb_reserve(rxb->skb, 4);
  3022. priv->alloc_rxb_skb++;
  3023. list_del(element);
  3024. /* Get physical address of RB/SKB */
  3025. rxb->dma_addr =
  3026. pci_map_single(priv->pci_dev, rxb->skb->data,
  3027. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3028. list_add_tail(&rxb->list, &rxq->rx_free);
  3029. rxq->free_count++;
  3030. }
  3031. spin_unlock_irqrestore(&rxq->lock, flags);
  3032. }
  3033. /*
  3034. * this should be called while priv->lock is locked
  3035. */
  3036. static void __iwl3945_rx_replenish(void *data)
  3037. {
  3038. struct iwl3945_priv *priv = data;
  3039. iwl3945_rx_allocate(priv);
  3040. iwl3945_rx_queue_restock(priv);
  3041. }
  3042. void iwl3945_rx_replenish(void *data)
  3043. {
  3044. struct iwl3945_priv *priv = data;
  3045. unsigned long flags;
  3046. iwl3945_rx_allocate(priv);
  3047. spin_lock_irqsave(&priv->lock, flags);
  3048. iwl3945_rx_queue_restock(priv);
  3049. spin_unlock_irqrestore(&priv->lock, flags);
  3050. }
  3051. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3052. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3053. * This free routine walks the list of POOL entries and if SKB is set to
  3054. * non NULL it is unmapped and freed
  3055. */
  3056. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3057. {
  3058. int i;
  3059. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3060. if (rxq->pool[i].skb != NULL) {
  3061. pci_unmap_single(priv->pci_dev,
  3062. rxq->pool[i].dma_addr,
  3063. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3064. dev_kfree_skb(rxq->pool[i].skb);
  3065. }
  3066. }
  3067. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3068. rxq->dma_addr);
  3069. rxq->bd = NULL;
  3070. }
  3071. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3072. {
  3073. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3074. struct pci_dev *dev = priv->pci_dev;
  3075. int i;
  3076. spin_lock_init(&rxq->lock);
  3077. INIT_LIST_HEAD(&rxq->rx_free);
  3078. INIT_LIST_HEAD(&rxq->rx_used);
  3079. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3080. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3081. if (!rxq->bd)
  3082. return -ENOMEM;
  3083. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3084. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3085. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3086. /* Set us so that we have processed and used all buffers, but have
  3087. * not restocked the Rx queue with fresh buffers */
  3088. rxq->read = rxq->write = 0;
  3089. rxq->free_count = 0;
  3090. rxq->need_update = 0;
  3091. return 0;
  3092. }
  3093. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3094. {
  3095. unsigned long flags;
  3096. int i;
  3097. spin_lock_irqsave(&rxq->lock, flags);
  3098. INIT_LIST_HEAD(&rxq->rx_free);
  3099. INIT_LIST_HEAD(&rxq->rx_used);
  3100. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3101. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3102. /* In the reset function, these buffers may have been allocated
  3103. * to an SKB, so we need to unmap and free potential storage */
  3104. if (rxq->pool[i].skb != NULL) {
  3105. pci_unmap_single(priv->pci_dev,
  3106. rxq->pool[i].dma_addr,
  3107. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3108. priv->alloc_rxb_skb--;
  3109. dev_kfree_skb(rxq->pool[i].skb);
  3110. rxq->pool[i].skb = NULL;
  3111. }
  3112. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3113. }
  3114. /* Set us so that we have processed and used all buffers, but have
  3115. * not restocked the Rx queue with fresh buffers */
  3116. rxq->read = rxq->write = 0;
  3117. rxq->free_count = 0;
  3118. spin_unlock_irqrestore(&rxq->lock, flags);
  3119. }
  3120. /* Convert linear signal-to-noise ratio into dB */
  3121. static u8 ratio2dB[100] = {
  3122. /* 0 1 2 3 4 5 6 7 8 9 */
  3123. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3124. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3125. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3126. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3127. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3128. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3129. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3130. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3131. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3132. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3133. };
  3134. /* Calculates a relative dB value from a ratio of linear
  3135. * (i.e. not dB) signal levels.
  3136. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3137. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3138. {
  3139. /* 1000:1 or higher just report as 60 dB */
  3140. if (sig_ratio >= 1000)
  3141. return 60;
  3142. /* 100:1 or higher, divide by 10 and use table,
  3143. * add 20 dB to make up for divide by 10 */
  3144. if (sig_ratio >= 100)
  3145. return 20 + (int)ratio2dB[sig_ratio/10];
  3146. /* We shouldn't see this */
  3147. if (sig_ratio < 1)
  3148. return 0;
  3149. /* Use table for ratios 1:1 - 99:1 */
  3150. return (int)ratio2dB[sig_ratio];
  3151. }
  3152. #define PERFECT_RSSI (-20) /* dBm */
  3153. #define WORST_RSSI (-95) /* dBm */
  3154. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3155. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3156. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3157. * about formulas used below. */
  3158. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3159. {
  3160. int sig_qual;
  3161. int degradation = PERFECT_RSSI - rssi_dbm;
  3162. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3163. * as indicator; formula is (signal dbm - noise dbm).
  3164. * SNR at or above 40 is a great signal (100%).
  3165. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3166. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3167. if (noise_dbm) {
  3168. if (rssi_dbm - noise_dbm >= 40)
  3169. return 100;
  3170. else if (rssi_dbm < noise_dbm)
  3171. return 0;
  3172. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3173. /* Else use just the signal level.
  3174. * This formula is a least squares fit of data points collected and
  3175. * compared with a reference system that had a percentage (%) display
  3176. * for signal quality. */
  3177. } else
  3178. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3179. (15 * RSSI_RANGE + 62 * degradation)) /
  3180. (RSSI_RANGE * RSSI_RANGE);
  3181. if (sig_qual > 100)
  3182. sig_qual = 100;
  3183. else if (sig_qual < 1)
  3184. sig_qual = 0;
  3185. return sig_qual;
  3186. }
  3187. /**
  3188. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3189. *
  3190. * Uses the priv->rx_handlers callback function array to invoke
  3191. * the appropriate handlers, including command responses,
  3192. * frame-received notifications, and other notifications.
  3193. */
  3194. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3195. {
  3196. struct iwl3945_rx_mem_buffer *rxb;
  3197. struct iwl3945_rx_packet *pkt;
  3198. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3199. u32 r, i;
  3200. int reclaim;
  3201. unsigned long flags;
  3202. u8 fill_rx = 0;
  3203. u32 count = 8;
  3204. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3205. * buffer that the driver may process (last buffer filled by ucode). */
  3206. r = iwl3945_hw_get_rx_read(priv);
  3207. i = rxq->read;
  3208. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3209. fill_rx = 1;
  3210. /* Rx interrupt, but nothing sent from uCode */
  3211. if (i == r)
  3212. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3213. while (i != r) {
  3214. rxb = rxq->queue[i];
  3215. /* If an RXB doesn't have a Rx queue slot associated with it,
  3216. * then a bug has been introduced in the queue refilling
  3217. * routines -- catch it here */
  3218. BUG_ON(rxb == NULL);
  3219. rxq->queue[i] = NULL;
  3220. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3221. IWL_RX_BUF_SIZE,
  3222. PCI_DMA_FROMDEVICE);
  3223. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3224. /* Reclaim a command buffer only if this packet is a response
  3225. * to a (driver-originated) command.
  3226. * If the packet (e.g. Rx frame) originated from uCode,
  3227. * there is no command buffer to reclaim.
  3228. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3229. * but apparently a few don't get set; catch them here. */
  3230. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3231. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3232. (pkt->hdr.cmd != REPLY_TX);
  3233. /* Based on type of command response or notification,
  3234. * handle those that need handling via function in
  3235. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3236. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3237. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3238. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3239. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3240. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3241. } else {
  3242. /* No handling needed */
  3243. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3244. "r %d i %d No handler needed for %s, 0x%02x\n",
  3245. r, i, get_cmd_string(pkt->hdr.cmd),
  3246. pkt->hdr.cmd);
  3247. }
  3248. if (reclaim) {
  3249. /* Invoke any callbacks, transfer the skb to caller, and
  3250. * fire off the (possibly) blocking iwl3945_send_cmd()
  3251. * as we reclaim the driver command queue */
  3252. if (rxb && rxb->skb)
  3253. iwl3945_tx_cmd_complete(priv, rxb);
  3254. else
  3255. IWL_WARNING("Claim null rxb?\n");
  3256. }
  3257. /* For now we just don't re-use anything. We can tweak this
  3258. * later to try and re-use notification packets and SKBs that
  3259. * fail to Rx correctly */
  3260. if (rxb->skb != NULL) {
  3261. priv->alloc_rxb_skb--;
  3262. dev_kfree_skb_any(rxb->skb);
  3263. rxb->skb = NULL;
  3264. }
  3265. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3266. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3267. spin_lock_irqsave(&rxq->lock, flags);
  3268. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3269. spin_unlock_irqrestore(&rxq->lock, flags);
  3270. i = (i + 1) & RX_QUEUE_MASK;
  3271. /* If there are a lot of unused frames,
  3272. * restock the Rx queue so ucode won't assert. */
  3273. if (fill_rx) {
  3274. count++;
  3275. if (count >= 8) {
  3276. priv->rxq.read = i;
  3277. __iwl3945_rx_replenish(priv);
  3278. count = 0;
  3279. }
  3280. }
  3281. }
  3282. /* Backtrack one entry */
  3283. priv->rxq.read = i;
  3284. iwl3945_rx_queue_restock(priv);
  3285. }
  3286. /**
  3287. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3288. */
  3289. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3290. struct iwl3945_tx_queue *txq)
  3291. {
  3292. u32 reg = 0;
  3293. int rc = 0;
  3294. int txq_id = txq->q.id;
  3295. if (txq->need_update == 0)
  3296. return rc;
  3297. /* if we're trying to save power */
  3298. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3299. /* wake up nic if it's powered down ...
  3300. * uCode will wake up, and interrupt us again, so next
  3301. * time we'll skip this part. */
  3302. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3303. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3304. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3305. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3306. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3307. return rc;
  3308. }
  3309. /* restore this queue's parameters in nic hardware. */
  3310. rc = iwl3945_grab_nic_access(priv);
  3311. if (rc)
  3312. return rc;
  3313. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3314. txq->q.write_ptr | (txq_id << 8));
  3315. iwl3945_release_nic_access(priv);
  3316. /* else not in power-save mode, uCode will never sleep when we're
  3317. * trying to tx (during RFKILL, we're not trying to tx). */
  3318. } else
  3319. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3320. txq->q.write_ptr | (txq_id << 8));
  3321. txq->need_update = 0;
  3322. return rc;
  3323. }
  3324. #ifdef CONFIG_IWL3945_DEBUG
  3325. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3326. {
  3327. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3328. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3329. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3330. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3331. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3332. le32_to_cpu(rxon->filter_flags));
  3333. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3334. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3335. rxon->ofdm_basic_rates);
  3336. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3337. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3338. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3339. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3340. }
  3341. #endif
  3342. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3343. {
  3344. IWL_DEBUG_ISR("Enabling interrupts\n");
  3345. set_bit(STATUS_INT_ENABLED, &priv->status);
  3346. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3347. }
  3348. /* call this function to flush any scheduled tasklet */
  3349. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3350. {
  3351. /* wait to make sure we flush pending tasklet*/
  3352. synchronize_irq(priv->pci_dev->irq);
  3353. tasklet_kill(&priv->irq_tasklet);
  3354. }
  3355. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3356. {
  3357. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3358. /* disable interrupts from uCode/NIC to host */
  3359. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3360. /* acknowledge/clear/reset any interrupts still pending
  3361. * from uCode or flow handler (Rx/Tx DMA) */
  3362. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3363. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3364. IWL_DEBUG_ISR("Disabled interrupts\n");
  3365. }
  3366. static const char *desc_lookup(int i)
  3367. {
  3368. switch (i) {
  3369. case 1:
  3370. return "FAIL";
  3371. case 2:
  3372. return "BAD_PARAM";
  3373. case 3:
  3374. return "BAD_CHECKSUM";
  3375. case 4:
  3376. return "NMI_INTERRUPT";
  3377. case 5:
  3378. return "SYSASSERT";
  3379. case 6:
  3380. return "FATAL_ERROR";
  3381. }
  3382. return "UNKNOWN";
  3383. }
  3384. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3385. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3386. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3387. {
  3388. u32 i;
  3389. u32 desc, time, count, base, data1;
  3390. u32 blink1, blink2, ilink1, ilink2;
  3391. int rc;
  3392. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3393. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3394. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3395. return;
  3396. }
  3397. rc = iwl3945_grab_nic_access(priv);
  3398. if (rc) {
  3399. IWL_WARNING("Can not read from adapter at this time.\n");
  3400. return;
  3401. }
  3402. count = iwl3945_read_targ_mem(priv, base);
  3403. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3404. IWL_ERROR("Start IWL Error Log Dump:\n");
  3405. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3406. }
  3407. IWL_ERROR("Desc Time asrtPC blink2 "
  3408. "ilink1 nmiPC Line\n");
  3409. for (i = ERROR_START_OFFSET;
  3410. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3411. i += ERROR_ELEM_SIZE) {
  3412. desc = iwl3945_read_targ_mem(priv, base + i);
  3413. time =
  3414. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3415. blink1 =
  3416. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3417. blink2 =
  3418. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3419. ilink1 =
  3420. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3421. ilink2 =
  3422. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3423. data1 =
  3424. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3425. IWL_ERROR
  3426. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3427. desc_lookup(desc), desc, time, blink1, blink2,
  3428. ilink1, ilink2, data1);
  3429. }
  3430. iwl3945_release_nic_access(priv);
  3431. }
  3432. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3433. /**
  3434. * iwl3945_print_event_log - Dump error event log to syslog
  3435. *
  3436. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3437. */
  3438. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3439. u32 num_events, u32 mode)
  3440. {
  3441. u32 i;
  3442. u32 base; /* SRAM byte address of event log header */
  3443. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3444. u32 ptr; /* SRAM byte address of log data */
  3445. u32 ev, time, data; /* event log data */
  3446. if (num_events == 0)
  3447. return;
  3448. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3449. if (mode == 0)
  3450. event_size = 2 * sizeof(u32);
  3451. else
  3452. event_size = 3 * sizeof(u32);
  3453. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3454. /* "time" is actually "data" for mode 0 (no timestamp).
  3455. * place event id # at far right for easier visual parsing. */
  3456. for (i = 0; i < num_events; i++) {
  3457. ev = iwl3945_read_targ_mem(priv, ptr);
  3458. ptr += sizeof(u32);
  3459. time = iwl3945_read_targ_mem(priv, ptr);
  3460. ptr += sizeof(u32);
  3461. if (mode == 0)
  3462. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3463. else {
  3464. data = iwl3945_read_targ_mem(priv, ptr);
  3465. ptr += sizeof(u32);
  3466. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3467. }
  3468. }
  3469. }
  3470. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3471. {
  3472. int rc;
  3473. u32 base; /* SRAM byte address of event log header */
  3474. u32 capacity; /* event log capacity in # entries */
  3475. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3476. u32 num_wraps; /* # times uCode wrapped to top of log */
  3477. u32 next_entry; /* index of next entry to be written by uCode */
  3478. u32 size; /* # entries that we'll print */
  3479. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3480. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3481. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3482. return;
  3483. }
  3484. rc = iwl3945_grab_nic_access(priv);
  3485. if (rc) {
  3486. IWL_WARNING("Can not read from adapter at this time.\n");
  3487. return;
  3488. }
  3489. /* event log header */
  3490. capacity = iwl3945_read_targ_mem(priv, base);
  3491. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3492. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3493. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3494. size = num_wraps ? capacity : next_entry;
  3495. /* bail out if nothing in log */
  3496. if (size == 0) {
  3497. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3498. iwl3945_release_nic_access(priv);
  3499. return;
  3500. }
  3501. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3502. size, num_wraps);
  3503. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3504. * i.e the next one that uCode would fill. */
  3505. if (num_wraps)
  3506. iwl3945_print_event_log(priv, next_entry,
  3507. capacity - next_entry, mode);
  3508. /* (then/else) start at top of log */
  3509. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3510. iwl3945_release_nic_access(priv);
  3511. }
  3512. /**
  3513. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3514. */
  3515. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3516. {
  3517. /* Set the FW error flag -- cleared on iwl3945_down */
  3518. set_bit(STATUS_FW_ERROR, &priv->status);
  3519. /* Cancel currently queued command. */
  3520. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3521. #ifdef CONFIG_IWL3945_DEBUG
  3522. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3523. iwl3945_dump_nic_error_log(priv);
  3524. iwl3945_dump_nic_event_log(priv);
  3525. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3526. }
  3527. #endif
  3528. wake_up_interruptible(&priv->wait_command_queue);
  3529. /* Keep the restart process from trying to send host
  3530. * commands by clearing the INIT status bit */
  3531. clear_bit(STATUS_READY, &priv->status);
  3532. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3533. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3534. "Restarting adapter due to uCode error.\n");
  3535. if (iwl3945_is_associated(priv)) {
  3536. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3537. sizeof(priv->recovery_rxon));
  3538. priv->error_recovering = 1;
  3539. }
  3540. queue_work(priv->workqueue, &priv->restart);
  3541. }
  3542. }
  3543. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3544. {
  3545. unsigned long flags;
  3546. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3547. sizeof(priv->staging_rxon));
  3548. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3549. iwl3945_commit_rxon(priv);
  3550. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3551. spin_lock_irqsave(&priv->lock, flags);
  3552. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3553. priv->error_recovering = 0;
  3554. spin_unlock_irqrestore(&priv->lock, flags);
  3555. }
  3556. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3557. {
  3558. u32 inta, handled = 0;
  3559. u32 inta_fh;
  3560. unsigned long flags;
  3561. #ifdef CONFIG_IWL3945_DEBUG
  3562. u32 inta_mask;
  3563. #endif
  3564. spin_lock_irqsave(&priv->lock, flags);
  3565. /* Ack/clear/reset pending uCode interrupts.
  3566. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3567. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3568. inta = iwl3945_read32(priv, CSR_INT);
  3569. iwl3945_write32(priv, CSR_INT, inta);
  3570. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3571. * Any new interrupts that happen after this, either while we're
  3572. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3573. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3574. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3575. #ifdef CONFIG_IWL3945_DEBUG
  3576. if (iwl3945_debug_level & IWL_DL_ISR) {
  3577. /* just for debug */
  3578. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3579. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3580. inta, inta_mask, inta_fh);
  3581. }
  3582. #endif
  3583. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3584. * atomic, make sure that inta covers all the interrupts that
  3585. * we've discovered, even if FH interrupt came in just after
  3586. * reading CSR_INT. */
  3587. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3588. inta |= CSR_INT_BIT_FH_RX;
  3589. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3590. inta |= CSR_INT_BIT_FH_TX;
  3591. /* Now service all interrupt bits discovered above. */
  3592. if (inta & CSR_INT_BIT_HW_ERR) {
  3593. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3594. /* Tell the device to stop sending interrupts */
  3595. iwl3945_disable_interrupts(priv);
  3596. iwl3945_irq_handle_error(priv);
  3597. handled |= CSR_INT_BIT_HW_ERR;
  3598. spin_unlock_irqrestore(&priv->lock, flags);
  3599. return;
  3600. }
  3601. #ifdef CONFIG_IWL3945_DEBUG
  3602. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3603. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3604. if (inta & CSR_INT_BIT_SCD)
  3605. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3606. "the frame/frames.\n");
  3607. /* Alive notification via Rx interrupt will do the real work */
  3608. if (inta & CSR_INT_BIT_ALIVE)
  3609. IWL_DEBUG_ISR("Alive interrupt\n");
  3610. }
  3611. #endif
  3612. /* Safely ignore these bits for debug checks below */
  3613. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3614. /* HW RF KILL switch toggled (4965 only) */
  3615. if (inta & CSR_INT_BIT_RF_KILL) {
  3616. int hw_rf_kill = 0;
  3617. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3618. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3619. hw_rf_kill = 1;
  3620. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3621. "RF_KILL bit toggled to %s.\n",
  3622. hw_rf_kill ? "disable radio":"enable radio");
  3623. /* Queue restart only if RF_KILL switch was set to "kill"
  3624. * when we loaded driver, and is now set to "enable".
  3625. * After we're Alive, RF_KILL gets handled by
  3626. * iwl3945_rx_card_state_notif() */
  3627. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3628. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3629. queue_work(priv->workqueue, &priv->restart);
  3630. }
  3631. handled |= CSR_INT_BIT_RF_KILL;
  3632. }
  3633. /* Chip got too hot and stopped itself (4965 only) */
  3634. if (inta & CSR_INT_BIT_CT_KILL) {
  3635. IWL_ERROR("Microcode CT kill error detected.\n");
  3636. handled |= CSR_INT_BIT_CT_KILL;
  3637. }
  3638. /* Error detected by uCode */
  3639. if (inta & CSR_INT_BIT_SW_ERR) {
  3640. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3641. inta);
  3642. iwl3945_irq_handle_error(priv);
  3643. handled |= CSR_INT_BIT_SW_ERR;
  3644. }
  3645. /* uCode wakes up after power-down sleep */
  3646. if (inta & CSR_INT_BIT_WAKEUP) {
  3647. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3648. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3649. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3650. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3651. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3652. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3653. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3654. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3655. handled |= CSR_INT_BIT_WAKEUP;
  3656. }
  3657. /* All uCode command responses, including Tx command responses,
  3658. * Rx "responses" (frame-received notification), and other
  3659. * notifications from uCode come through here*/
  3660. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3661. iwl3945_rx_handle(priv);
  3662. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3663. }
  3664. if (inta & CSR_INT_BIT_FH_TX) {
  3665. IWL_DEBUG_ISR("Tx interrupt\n");
  3666. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3667. if (!iwl3945_grab_nic_access(priv)) {
  3668. iwl3945_write_direct32(priv,
  3669. FH_TCSR_CREDIT
  3670. (ALM_FH_SRVC_CHNL), 0x0);
  3671. iwl3945_release_nic_access(priv);
  3672. }
  3673. handled |= CSR_INT_BIT_FH_TX;
  3674. }
  3675. if (inta & ~handled)
  3676. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3677. if (inta & ~CSR_INI_SET_MASK) {
  3678. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3679. inta & ~CSR_INI_SET_MASK);
  3680. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3681. }
  3682. /* Re-enable all interrupts */
  3683. /* only Re-enable if disabled by irq */
  3684. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3685. iwl3945_enable_interrupts(priv);
  3686. #ifdef CONFIG_IWL3945_DEBUG
  3687. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3688. inta = iwl3945_read32(priv, CSR_INT);
  3689. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3690. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3691. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3692. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3693. }
  3694. #endif
  3695. spin_unlock_irqrestore(&priv->lock, flags);
  3696. }
  3697. static irqreturn_t iwl3945_isr(int irq, void *data)
  3698. {
  3699. struct iwl3945_priv *priv = data;
  3700. u32 inta, inta_mask;
  3701. u32 inta_fh;
  3702. if (!priv)
  3703. return IRQ_NONE;
  3704. spin_lock(&priv->lock);
  3705. /* Disable (but don't clear!) interrupts here to avoid
  3706. * back-to-back ISRs and sporadic interrupts from our NIC.
  3707. * If we have something to service, the tasklet will re-enable ints.
  3708. * If we *don't* have something, we'll re-enable before leaving here. */
  3709. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3710. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3711. /* Discover which interrupts are active/pending */
  3712. inta = iwl3945_read32(priv, CSR_INT);
  3713. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3714. /* Ignore interrupt if there's nothing in NIC to service.
  3715. * This may be due to IRQ shared with another device,
  3716. * or due to sporadic interrupts thrown from our NIC. */
  3717. if (!inta && !inta_fh) {
  3718. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3719. goto none;
  3720. }
  3721. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3722. /* Hardware disappeared */
  3723. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3724. goto unplugged;
  3725. }
  3726. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3727. inta, inta_mask, inta_fh);
  3728. inta &= ~CSR_INT_BIT_SCD;
  3729. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3730. if (likely(inta || inta_fh))
  3731. tasklet_schedule(&priv->irq_tasklet);
  3732. unplugged:
  3733. spin_unlock(&priv->lock);
  3734. return IRQ_HANDLED;
  3735. none:
  3736. /* re-enable interrupts here since we don't have anything to service. */
  3737. /* only Re-enable if disabled by irq */
  3738. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3739. iwl3945_enable_interrupts(priv);
  3740. spin_unlock(&priv->lock);
  3741. return IRQ_NONE;
  3742. }
  3743. /************************** EEPROM BANDS ****************************
  3744. *
  3745. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3746. * EEPROM contents to the specific channel number supported for each
  3747. * band.
  3748. *
  3749. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3750. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3751. * The specific geography and calibration information for that channel
  3752. * is contained in the eeprom map itself.
  3753. *
  3754. * During init, we copy the eeprom information and channel map
  3755. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3756. *
  3757. * channel_map_24/52 provides the index in the channel_info array for a
  3758. * given channel. We have to have two separate maps as there is channel
  3759. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3760. * band_2
  3761. *
  3762. * A value of 0xff stored in the channel_map indicates that the channel
  3763. * is not supported by the hardware at all.
  3764. *
  3765. * A value of 0xfe in the channel_map indicates that the channel is not
  3766. * valid for Tx with the current hardware. This means that
  3767. * while the system can tune and receive on a given channel, it may not
  3768. * be able to associate or transmit any frames on that
  3769. * channel. There is no corresponding channel information for that
  3770. * entry.
  3771. *
  3772. *********************************************************************/
  3773. /* 2.4 GHz */
  3774. static const u8 iwl3945_eeprom_band_1[14] = {
  3775. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3776. };
  3777. /* 5.2 GHz bands */
  3778. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3779. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3780. };
  3781. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3782. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3783. };
  3784. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3785. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3786. };
  3787. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3788. 145, 149, 153, 157, 161, 165
  3789. };
  3790. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3791. int *eeprom_ch_count,
  3792. const struct iwl3945_eeprom_channel
  3793. **eeprom_ch_info,
  3794. const u8 **eeprom_ch_index)
  3795. {
  3796. switch (band) {
  3797. case 1: /* 2.4GHz band */
  3798. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3799. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3800. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3801. break;
  3802. case 2: /* 4.9GHz band */
  3803. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3804. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3805. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3806. break;
  3807. case 3: /* 5.2GHz band */
  3808. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3809. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3810. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3811. break;
  3812. case 4: /* 5.5GHz band */
  3813. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3814. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3815. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3816. break;
  3817. case 5: /* 5.7GHz band */
  3818. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3819. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3820. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3821. break;
  3822. default:
  3823. BUG();
  3824. return;
  3825. }
  3826. }
  3827. /**
  3828. * iwl3945_get_channel_info - Find driver's private channel info
  3829. *
  3830. * Based on band and channel number.
  3831. */
  3832. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3833. enum ieee80211_band band, u16 channel)
  3834. {
  3835. int i;
  3836. switch (band) {
  3837. case IEEE80211_BAND_5GHZ:
  3838. for (i = 14; i < priv->channel_count; i++) {
  3839. if (priv->channel_info[i].channel == channel)
  3840. return &priv->channel_info[i];
  3841. }
  3842. break;
  3843. case IEEE80211_BAND_2GHZ:
  3844. if (channel >= 1 && channel <= 14)
  3845. return &priv->channel_info[channel - 1];
  3846. break;
  3847. case IEEE80211_NUM_BANDS:
  3848. WARN_ON(1);
  3849. }
  3850. return NULL;
  3851. }
  3852. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3853. ? # x " " : "")
  3854. /**
  3855. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3856. */
  3857. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  3858. {
  3859. int eeprom_ch_count = 0;
  3860. const u8 *eeprom_ch_index = NULL;
  3861. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  3862. int band, ch;
  3863. struct iwl3945_channel_info *ch_info;
  3864. if (priv->channel_count) {
  3865. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3866. return 0;
  3867. }
  3868. if (priv->eeprom.version < 0x2f) {
  3869. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  3870. priv->eeprom.version);
  3871. return -EINVAL;
  3872. }
  3873. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3874. priv->channel_count =
  3875. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3876. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3877. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3878. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3879. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3880. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3881. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  3882. priv->channel_count, GFP_KERNEL);
  3883. if (!priv->channel_info) {
  3884. IWL_ERROR("Could not allocate channel_info\n");
  3885. priv->channel_count = 0;
  3886. return -ENOMEM;
  3887. }
  3888. ch_info = priv->channel_info;
  3889. /* Loop through the 5 EEPROM bands adding them in order to the
  3890. * channel map we maintain (that contains additional information than
  3891. * what just in the EEPROM) */
  3892. for (band = 1; band <= 5; band++) {
  3893. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3894. &eeprom_ch_info, &eeprom_ch_index);
  3895. /* Loop through each band adding each of the channels */
  3896. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3897. ch_info->channel = eeprom_ch_index[ch];
  3898. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3899. IEEE80211_BAND_5GHZ;
  3900. /* permanently store EEPROM's channel regulatory flags
  3901. * and max power in channel info database. */
  3902. ch_info->eeprom = eeprom_ch_info[ch];
  3903. /* Copy the run-time flags so they are there even on
  3904. * invalid channels */
  3905. ch_info->flags = eeprom_ch_info[ch].flags;
  3906. if (!(is_channel_valid(ch_info))) {
  3907. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3908. "No traffic\n",
  3909. ch_info->channel,
  3910. ch_info->flags,
  3911. is_channel_a_band(ch_info) ?
  3912. "5.2" : "2.4");
  3913. ch_info++;
  3914. continue;
  3915. }
  3916. /* Initialize regulatory-based run-time data */
  3917. ch_info->max_power_avg = ch_info->curr_txpow =
  3918. eeprom_ch_info[ch].max_power_avg;
  3919. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3920. ch_info->min_power = 0;
  3921. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3922. " %ddBm): Ad-Hoc %ssupported\n",
  3923. ch_info->channel,
  3924. is_channel_a_band(ch_info) ?
  3925. "5.2" : "2.4",
  3926. CHECK_AND_PRINT(VALID),
  3927. CHECK_AND_PRINT(IBSS),
  3928. CHECK_AND_PRINT(ACTIVE),
  3929. CHECK_AND_PRINT(RADAR),
  3930. CHECK_AND_PRINT(WIDE),
  3931. CHECK_AND_PRINT(DFS),
  3932. eeprom_ch_info[ch].flags,
  3933. eeprom_ch_info[ch].max_power_avg,
  3934. ((eeprom_ch_info[ch].
  3935. flags & EEPROM_CHANNEL_IBSS)
  3936. && !(eeprom_ch_info[ch].
  3937. flags & EEPROM_CHANNEL_RADAR))
  3938. ? "" : "not ");
  3939. /* Set the user_txpower_limit to the highest power
  3940. * supported by any channel */
  3941. if (eeprom_ch_info[ch].max_power_avg >
  3942. priv->user_txpower_limit)
  3943. priv->user_txpower_limit =
  3944. eeprom_ch_info[ch].max_power_avg;
  3945. ch_info++;
  3946. }
  3947. }
  3948. /* Set up txpower settings in driver for all channels */
  3949. if (iwl3945_txpower_set_from_eeprom(priv))
  3950. return -EIO;
  3951. return 0;
  3952. }
  3953. /*
  3954. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3955. */
  3956. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  3957. {
  3958. kfree(priv->channel_info);
  3959. priv->channel_count = 0;
  3960. }
  3961. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3962. * sending probe req. This should be set long enough to hear probe responses
  3963. * from more than one AP. */
  3964. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3965. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3966. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3967. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3968. /* For faster active scanning, scan will move to the next channel if fewer than
  3969. * PLCP_QUIET_THRESH packets are heard on this channel within
  3970. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3971. * time if it's a quiet channel (nothing responded to our probe, and there's
  3972. * no other traffic).
  3973. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3974. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3975. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3976. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3977. * Must be set longer than active dwell time.
  3978. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3979. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3980. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3981. #define IWL_PASSIVE_DWELL_BASE (100)
  3982. #define IWL_CHANNEL_TUNE_TIME 5
  3983. #define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
  3984. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  3985. enum ieee80211_band band,
  3986. u8 n_probes)
  3987. {
  3988. if (band == IEEE80211_BAND_5GHZ)
  3989. return IWL_ACTIVE_DWELL_TIME_52 +
  3990. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3991. else
  3992. return IWL_ACTIVE_DWELL_TIME_24 +
  3993. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3994. }
  3995. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  3996. enum ieee80211_band band)
  3997. {
  3998. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3999. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4000. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4001. if (iwl3945_is_associated(priv)) {
  4002. /* If we're associated, we clamp the maximum passive
  4003. * dwell time to be 98% of the beacon interval (minus
  4004. * 2 * channel tune time) */
  4005. passive = priv->beacon_int;
  4006. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4007. passive = IWL_PASSIVE_DWELL_BASE;
  4008. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4009. }
  4010. return passive;
  4011. }
  4012. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4013. enum ieee80211_band band,
  4014. u8 is_active, u8 n_probes,
  4015. struct iwl3945_scan_channel *scan_ch)
  4016. {
  4017. const struct ieee80211_channel *channels = NULL;
  4018. const struct ieee80211_supported_band *sband;
  4019. const struct iwl3945_channel_info *ch_info;
  4020. u16 passive_dwell = 0;
  4021. u16 active_dwell = 0;
  4022. int added, i;
  4023. sband = iwl3945_get_band(priv, band);
  4024. if (!sband)
  4025. return 0;
  4026. channels = sband->channels;
  4027. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  4028. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4029. if (passive_dwell <= active_dwell)
  4030. passive_dwell = active_dwell + 1;
  4031. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4032. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4033. continue;
  4034. scan_ch->channel = channels[i].hw_value;
  4035. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4036. if (!is_channel_valid(ch_info)) {
  4037. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4038. scan_ch->channel);
  4039. continue;
  4040. }
  4041. if (!is_active || is_channel_passive(ch_info) ||
  4042. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4043. scan_ch->type = 0; /* passive */
  4044. else
  4045. scan_ch->type = 1; /* active */
  4046. if ((scan_ch->type & 1) && n_probes)
  4047. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  4048. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4049. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4050. /* Set txpower levels to defaults */
  4051. scan_ch->tpc.dsp_atten = 110;
  4052. /* scan_pwr_info->tpc.dsp_atten; */
  4053. /*scan_pwr_info->tpc.tx_gain; */
  4054. if (band == IEEE80211_BAND_5GHZ)
  4055. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4056. else {
  4057. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4058. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4059. * power level:
  4060. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4061. */
  4062. }
  4063. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4064. scan_ch->channel,
  4065. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4066. (scan_ch->type & 1) ?
  4067. active_dwell : passive_dwell);
  4068. scan_ch++;
  4069. added++;
  4070. }
  4071. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4072. return added;
  4073. }
  4074. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4075. struct ieee80211_rate *rates)
  4076. {
  4077. int i;
  4078. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4079. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4080. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4081. rates[i].hw_value_short = i;
  4082. rates[i].flags = 0;
  4083. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4084. /*
  4085. * If CCK != 1M then set short preamble rate flag.
  4086. */
  4087. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4088. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4089. }
  4090. }
  4091. }
  4092. /**
  4093. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4094. */
  4095. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4096. {
  4097. struct iwl3945_channel_info *ch;
  4098. struct ieee80211_supported_band *sband;
  4099. struct ieee80211_channel *channels;
  4100. struct ieee80211_channel *geo_ch;
  4101. struct ieee80211_rate *rates;
  4102. int i = 0;
  4103. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4104. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4105. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4106. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4107. return 0;
  4108. }
  4109. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4110. priv->channel_count, GFP_KERNEL);
  4111. if (!channels)
  4112. return -ENOMEM;
  4113. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4114. GFP_KERNEL);
  4115. if (!rates) {
  4116. kfree(channels);
  4117. return -ENOMEM;
  4118. }
  4119. /* 5.2GHz channels start after the 2.4GHz channels */
  4120. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4121. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4122. /* just OFDM */
  4123. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4124. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4125. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4126. sband->channels = channels;
  4127. /* OFDM & CCK */
  4128. sband->bitrates = rates;
  4129. sband->n_bitrates = IWL_RATE_COUNT;
  4130. priv->ieee_channels = channels;
  4131. priv->ieee_rates = rates;
  4132. iwl3945_init_hw_rates(priv, rates);
  4133. for (i = 0; i < priv->channel_count; i++) {
  4134. ch = &priv->channel_info[i];
  4135. /* FIXME: might be removed if scan is OK*/
  4136. if (!is_channel_valid(ch))
  4137. continue;
  4138. if (is_channel_a_band(ch))
  4139. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4140. else
  4141. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4142. geo_ch = &sband->channels[sband->n_channels++];
  4143. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4144. geo_ch->max_power = ch->max_power_avg;
  4145. geo_ch->max_antenna_gain = 0xff;
  4146. geo_ch->hw_value = ch->channel;
  4147. if (is_channel_valid(ch)) {
  4148. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4149. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4150. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4151. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4152. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4153. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4154. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4155. priv->max_channel_txpower_limit =
  4156. ch->max_power_avg;
  4157. } else {
  4158. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4159. }
  4160. /* Save flags for reg domain usage */
  4161. geo_ch->orig_flags = geo_ch->flags;
  4162. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4163. ch->channel, geo_ch->center_freq,
  4164. is_channel_a_band(ch) ? "5.2" : "2.4",
  4165. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4166. "restricted" : "valid",
  4167. geo_ch->flags);
  4168. }
  4169. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4170. priv->cfg->sku & IWL_SKU_A) {
  4171. printk(KERN_INFO DRV_NAME
  4172. ": Incorrectly detected BG card as ABG. Please send "
  4173. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4174. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4175. priv->cfg->sku &= ~IWL_SKU_A;
  4176. }
  4177. printk(KERN_INFO DRV_NAME
  4178. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4179. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4180. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4181. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4182. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4183. &priv->bands[IEEE80211_BAND_2GHZ];
  4184. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4185. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4186. &priv->bands[IEEE80211_BAND_5GHZ];
  4187. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4188. return 0;
  4189. }
  4190. /*
  4191. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4192. */
  4193. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4194. {
  4195. kfree(priv->ieee_channels);
  4196. kfree(priv->ieee_rates);
  4197. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4198. }
  4199. /******************************************************************************
  4200. *
  4201. * uCode download functions
  4202. *
  4203. ******************************************************************************/
  4204. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4205. {
  4206. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4207. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4208. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4209. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4210. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4211. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4212. }
  4213. /**
  4214. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4215. * looking at all data.
  4216. */
  4217. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4218. {
  4219. u32 val;
  4220. u32 save_len = len;
  4221. int rc = 0;
  4222. u32 errcnt;
  4223. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4224. rc = iwl3945_grab_nic_access(priv);
  4225. if (rc)
  4226. return rc;
  4227. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4228. errcnt = 0;
  4229. for (; len > 0; len -= sizeof(u32), image++) {
  4230. /* read data comes through single port, auto-incr addr */
  4231. /* NOTE: Use the debugless read so we don't flood kernel log
  4232. * if IWL_DL_IO is set */
  4233. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4234. if (val != le32_to_cpu(*image)) {
  4235. IWL_ERROR("uCode INST section is invalid at "
  4236. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4237. save_len - len, val, le32_to_cpu(*image));
  4238. rc = -EIO;
  4239. errcnt++;
  4240. if (errcnt >= 20)
  4241. break;
  4242. }
  4243. }
  4244. iwl3945_release_nic_access(priv);
  4245. if (!errcnt)
  4246. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4247. return rc;
  4248. }
  4249. /**
  4250. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4251. * using sample data 100 bytes apart. If these sample points are good,
  4252. * it's a pretty good bet that everything between them is good, too.
  4253. */
  4254. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4255. {
  4256. u32 val;
  4257. int rc = 0;
  4258. u32 errcnt = 0;
  4259. u32 i;
  4260. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4261. rc = iwl3945_grab_nic_access(priv);
  4262. if (rc)
  4263. return rc;
  4264. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4265. /* read data comes through single port, auto-incr addr */
  4266. /* NOTE: Use the debugless read so we don't flood kernel log
  4267. * if IWL_DL_IO is set */
  4268. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4269. i + RTC_INST_LOWER_BOUND);
  4270. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4271. if (val != le32_to_cpu(*image)) {
  4272. #if 0 /* Enable this if you want to see details */
  4273. IWL_ERROR("uCode INST section is invalid at "
  4274. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4275. i, val, *image);
  4276. #endif
  4277. rc = -EIO;
  4278. errcnt++;
  4279. if (errcnt >= 3)
  4280. break;
  4281. }
  4282. }
  4283. iwl3945_release_nic_access(priv);
  4284. return rc;
  4285. }
  4286. /**
  4287. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4288. * and verify its contents
  4289. */
  4290. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4291. {
  4292. __le32 *image;
  4293. u32 len;
  4294. int rc = 0;
  4295. /* Try bootstrap */
  4296. image = (__le32 *)priv->ucode_boot.v_addr;
  4297. len = priv->ucode_boot.len;
  4298. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4299. if (rc == 0) {
  4300. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4301. return 0;
  4302. }
  4303. /* Try initialize */
  4304. image = (__le32 *)priv->ucode_init.v_addr;
  4305. len = priv->ucode_init.len;
  4306. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4307. if (rc == 0) {
  4308. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4309. return 0;
  4310. }
  4311. /* Try runtime/protocol */
  4312. image = (__le32 *)priv->ucode_code.v_addr;
  4313. len = priv->ucode_code.len;
  4314. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4315. if (rc == 0) {
  4316. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4317. return 0;
  4318. }
  4319. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4320. /* Since nothing seems to match, show first several data entries in
  4321. * instruction SRAM, so maybe visual inspection will give a clue.
  4322. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4323. image = (__le32 *)priv->ucode_boot.v_addr;
  4324. len = priv->ucode_boot.len;
  4325. rc = iwl3945_verify_inst_full(priv, image, len);
  4326. return rc;
  4327. }
  4328. /* check contents of special bootstrap uCode SRAM */
  4329. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4330. {
  4331. __le32 *image = priv->ucode_boot.v_addr;
  4332. u32 len = priv->ucode_boot.len;
  4333. u32 reg;
  4334. u32 val;
  4335. IWL_DEBUG_INFO("Begin verify bsm\n");
  4336. /* verify BSM SRAM contents */
  4337. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4338. for (reg = BSM_SRAM_LOWER_BOUND;
  4339. reg < BSM_SRAM_LOWER_BOUND + len;
  4340. reg += sizeof(u32), image++) {
  4341. val = iwl3945_read_prph(priv, reg);
  4342. if (val != le32_to_cpu(*image)) {
  4343. IWL_ERROR("BSM uCode verification failed at "
  4344. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4345. BSM_SRAM_LOWER_BOUND,
  4346. reg - BSM_SRAM_LOWER_BOUND, len,
  4347. val, le32_to_cpu(*image));
  4348. return -EIO;
  4349. }
  4350. }
  4351. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4352. return 0;
  4353. }
  4354. /**
  4355. * iwl3945_load_bsm - Load bootstrap instructions
  4356. *
  4357. * BSM operation:
  4358. *
  4359. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4360. * in special SRAM that does not power down during RFKILL. When powering back
  4361. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4362. * the bootstrap program into the on-board processor, and starts it.
  4363. *
  4364. * The bootstrap program loads (via DMA) instructions and data for a new
  4365. * program from host DRAM locations indicated by the host driver in the
  4366. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4367. * automatically.
  4368. *
  4369. * When initializing the NIC, the host driver points the BSM to the
  4370. * "initialize" uCode image. This uCode sets up some internal data, then
  4371. * notifies host via "initialize alive" that it is complete.
  4372. *
  4373. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4374. * normal runtime uCode instructions and a backup uCode data cache buffer
  4375. * (filled initially with starting data values for the on-board processor),
  4376. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4377. * which begins normal operation.
  4378. *
  4379. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4380. * the backup data cache in DRAM before SRAM is powered down.
  4381. *
  4382. * When powering back up, the BSM loads the bootstrap program. This reloads
  4383. * the runtime uCode instructions and the backup data cache into SRAM,
  4384. * and re-launches the runtime uCode from where it left off.
  4385. */
  4386. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4387. {
  4388. __le32 *image = priv->ucode_boot.v_addr;
  4389. u32 len = priv->ucode_boot.len;
  4390. dma_addr_t pinst;
  4391. dma_addr_t pdata;
  4392. u32 inst_len;
  4393. u32 data_len;
  4394. int rc;
  4395. int i;
  4396. u32 done;
  4397. u32 reg_offset;
  4398. IWL_DEBUG_INFO("Begin load bsm\n");
  4399. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4400. if (len > IWL_MAX_BSM_SIZE)
  4401. return -EINVAL;
  4402. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4403. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4404. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4405. * after the "initialize" uCode has run, to point to
  4406. * runtime/protocol instructions and backup data cache. */
  4407. pinst = priv->ucode_init.p_addr;
  4408. pdata = priv->ucode_init_data.p_addr;
  4409. inst_len = priv->ucode_init.len;
  4410. data_len = priv->ucode_init_data.len;
  4411. rc = iwl3945_grab_nic_access(priv);
  4412. if (rc)
  4413. return rc;
  4414. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4415. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4416. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4417. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4418. /* Fill BSM memory with bootstrap instructions */
  4419. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4420. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4421. reg_offset += sizeof(u32), image++)
  4422. _iwl3945_write_prph(priv, reg_offset,
  4423. le32_to_cpu(*image));
  4424. rc = iwl3945_verify_bsm(priv);
  4425. if (rc) {
  4426. iwl3945_release_nic_access(priv);
  4427. return rc;
  4428. }
  4429. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4430. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4431. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4432. RTC_INST_LOWER_BOUND);
  4433. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4434. /* Load bootstrap code into instruction SRAM now,
  4435. * to prepare to load "initialize" uCode */
  4436. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4437. BSM_WR_CTRL_REG_BIT_START);
  4438. /* Wait for load of bootstrap uCode to finish */
  4439. for (i = 0; i < 100; i++) {
  4440. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4441. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4442. break;
  4443. udelay(10);
  4444. }
  4445. if (i < 100)
  4446. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4447. else {
  4448. IWL_ERROR("BSM write did not complete!\n");
  4449. return -EIO;
  4450. }
  4451. /* Enable future boot loads whenever power management unit triggers it
  4452. * (e.g. when powering back up after power-save shutdown) */
  4453. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4454. BSM_WR_CTRL_REG_BIT_START_EN);
  4455. iwl3945_release_nic_access(priv);
  4456. return 0;
  4457. }
  4458. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4459. {
  4460. /* Remove all resets to allow NIC to operate */
  4461. iwl3945_write32(priv, CSR_RESET, 0);
  4462. }
  4463. /**
  4464. * iwl3945_read_ucode - Read uCode images from disk file.
  4465. *
  4466. * Copy into buffers for card to fetch via bus-mastering
  4467. */
  4468. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4469. {
  4470. struct iwl3945_ucode *ucode;
  4471. int ret = 0;
  4472. const struct firmware *ucode_raw;
  4473. /* firmware file name contains uCode/driver compatibility version */
  4474. const char *name = priv->cfg->fw_name;
  4475. u8 *src;
  4476. size_t len;
  4477. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4478. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4479. * request_firmware() is synchronous, file is in memory on return. */
  4480. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4481. if (ret < 0) {
  4482. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4483. name, ret);
  4484. goto error;
  4485. }
  4486. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4487. name, ucode_raw->size);
  4488. /* Make sure that we got at least our header! */
  4489. if (ucode_raw->size < sizeof(*ucode)) {
  4490. IWL_ERROR("File size way too small!\n");
  4491. ret = -EINVAL;
  4492. goto err_release;
  4493. }
  4494. /* Data from ucode file: header followed by uCode images */
  4495. ucode = (void *)ucode_raw->data;
  4496. ver = le32_to_cpu(ucode->ver);
  4497. inst_size = le32_to_cpu(ucode->inst_size);
  4498. data_size = le32_to_cpu(ucode->data_size);
  4499. init_size = le32_to_cpu(ucode->init_size);
  4500. init_data_size = le32_to_cpu(ucode->init_data_size);
  4501. boot_size = le32_to_cpu(ucode->boot_size);
  4502. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4503. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4504. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4505. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4506. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4507. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4508. /* Verify size of file vs. image size info in file's header */
  4509. if (ucode_raw->size < sizeof(*ucode) +
  4510. inst_size + data_size + init_size +
  4511. init_data_size + boot_size) {
  4512. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4513. (int)ucode_raw->size);
  4514. ret = -EINVAL;
  4515. goto err_release;
  4516. }
  4517. /* Verify that uCode images will fit in card's SRAM */
  4518. if (inst_size > IWL_MAX_INST_SIZE) {
  4519. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4520. inst_size);
  4521. ret = -EINVAL;
  4522. goto err_release;
  4523. }
  4524. if (data_size > IWL_MAX_DATA_SIZE) {
  4525. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4526. data_size);
  4527. ret = -EINVAL;
  4528. goto err_release;
  4529. }
  4530. if (init_size > IWL_MAX_INST_SIZE) {
  4531. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4532. init_size);
  4533. ret = -EINVAL;
  4534. goto err_release;
  4535. }
  4536. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4537. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4538. init_data_size);
  4539. ret = -EINVAL;
  4540. goto err_release;
  4541. }
  4542. if (boot_size > IWL_MAX_BSM_SIZE) {
  4543. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4544. boot_size);
  4545. ret = -EINVAL;
  4546. goto err_release;
  4547. }
  4548. /* Allocate ucode buffers for card's bus-master loading ... */
  4549. /* Runtime instructions and 2 copies of data:
  4550. * 1) unmodified from disk
  4551. * 2) backup cache for save/restore during power-downs */
  4552. priv->ucode_code.len = inst_size;
  4553. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4554. priv->ucode_data.len = data_size;
  4555. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4556. priv->ucode_data_backup.len = data_size;
  4557. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4558. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4559. !priv->ucode_data_backup.v_addr)
  4560. goto err_pci_alloc;
  4561. /* Initialization instructions and data */
  4562. if (init_size && init_data_size) {
  4563. priv->ucode_init.len = init_size;
  4564. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4565. priv->ucode_init_data.len = init_data_size;
  4566. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4567. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4568. goto err_pci_alloc;
  4569. }
  4570. /* Bootstrap (instructions only, no data) */
  4571. if (boot_size) {
  4572. priv->ucode_boot.len = boot_size;
  4573. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4574. if (!priv->ucode_boot.v_addr)
  4575. goto err_pci_alloc;
  4576. }
  4577. /* Copy images into buffers for card's bus-master reads ... */
  4578. /* Runtime instructions (first block of data in file) */
  4579. src = &ucode->data[0];
  4580. len = priv->ucode_code.len;
  4581. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4582. memcpy(priv->ucode_code.v_addr, src, len);
  4583. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4584. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4585. /* Runtime data (2nd block)
  4586. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4587. src = &ucode->data[inst_size];
  4588. len = priv->ucode_data.len;
  4589. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4590. memcpy(priv->ucode_data.v_addr, src, len);
  4591. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4592. /* Initialization instructions (3rd block) */
  4593. if (init_size) {
  4594. src = &ucode->data[inst_size + data_size];
  4595. len = priv->ucode_init.len;
  4596. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4597. len);
  4598. memcpy(priv->ucode_init.v_addr, src, len);
  4599. }
  4600. /* Initialization data (4th block) */
  4601. if (init_data_size) {
  4602. src = &ucode->data[inst_size + data_size + init_size];
  4603. len = priv->ucode_init_data.len;
  4604. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4605. (int)len);
  4606. memcpy(priv->ucode_init_data.v_addr, src, len);
  4607. }
  4608. /* Bootstrap instructions (5th block) */
  4609. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4610. len = priv->ucode_boot.len;
  4611. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4612. (int)len);
  4613. memcpy(priv->ucode_boot.v_addr, src, len);
  4614. /* We have our copies now, allow OS release its copies */
  4615. release_firmware(ucode_raw);
  4616. return 0;
  4617. err_pci_alloc:
  4618. IWL_ERROR("failed to allocate pci memory\n");
  4619. ret = -ENOMEM;
  4620. iwl3945_dealloc_ucode_pci(priv);
  4621. err_release:
  4622. release_firmware(ucode_raw);
  4623. error:
  4624. return ret;
  4625. }
  4626. /**
  4627. * iwl3945_set_ucode_ptrs - Set uCode address location
  4628. *
  4629. * Tell initialization uCode where to find runtime uCode.
  4630. *
  4631. * BSM registers initially contain pointers to initialization uCode.
  4632. * We need to replace them to load runtime uCode inst and data,
  4633. * and to save runtime data when powering down.
  4634. */
  4635. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4636. {
  4637. dma_addr_t pinst;
  4638. dma_addr_t pdata;
  4639. int rc = 0;
  4640. unsigned long flags;
  4641. /* bits 31:0 for 3945 */
  4642. pinst = priv->ucode_code.p_addr;
  4643. pdata = priv->ucode_data_backup.p_addr;
  4644. spin_lock_irqsave(&priv->lock, flags);
  4645. rc = iwl3945_grab_nic_access(priv);
  4646. if (rc) {
  4647. spin_unlock_irqrestore(&priv->lock, flags);
  4648. return rc;
  4649. }
  4650. /* Tell bootstrap uCode where to find image to load */
  4651. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4652. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4653. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4654. priv->ucode_data.len);
  4655. /* Inst byte count must be last to set up, bit 31 signals uCode
  4656. * that all new ptr/size info is in place */
  4657. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4658. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4659. iwl3945_release_nic_access(priv);
  4660. spin_unlock_irqrestore(&priv->lock, flags);
  4661. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4662. return rc;
  4663. }
  4664. /**
  4665. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4666. *
  4667. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4668. *
  4669. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4670. */
  4671. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4672. {
  4673. /* Check alive response for "valid" sign from uCode */
  4674. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4675. /* We had an error bringing up the hardware, so take it
  4676. * all the way back down so we can try again */
  4677. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4678. goto restart;
  4679. }
  4680. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4681. * This is a paranoid check, because we would not have gotten the
  4682. * "initialize" alive if code weren't properly loaded. */
  4683. if (iwl3945_verify_ucode(priv)) {
  4684. /* Runtime instruction load was bad;
  4685. * take it all the way back down so we can try again */
  4686. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4687. goto restart;
  4688. }
  4689. /* Send pointers to protocol/runtime uCode image ... init code will
  4690. * load and launch runtime uCode, which will send us another "Alive"
  4691. * notification. */
  4692. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4693. if (iwl3945_set_ucode_ptrs(priv)) {
  4694. /* Runtime instruction load won't happen;
  4695. * take it all the way back down so we can try again */
  4696. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4697. goto restart;
  4698. }
  4699. return;
  4700. restart:
  4701. queue_work(priv->workqueue, &priv->restart);
  4702. }
  4703. /**
  4704. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4705. * from protocol/runtime uCode (initialization uCode's
  4706. * Alive gets handled by iwl3945_init_alive_start()).
  4707. */
  4708. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4709. {
  4710. int rc = 0;
  4711. int thermal_spin = 0;
  4712. u32 rfkill;
  4713. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4714. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4715. /* We had an error bringing up the hardware, so take it
  4716. * all the way back down so we can try again */
  4717. IWL_DEBUG_INFO("Alive failed.\n");
  4718. goto restart;
  4719. }
  4720. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4721. * This is a paranoid check, because we would not have gotten the
  4722. * "runtime" alive if code weren't properly loaded. */
  4723. if (iwl3945_verify_ucode(priv)) {
  4724. /* Runtime instruction load was bad;
  4725. * take it all the way back down so we can try again */
  4726. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4727. goto restart;
  4728. }
  4729. iwl3945_clear_stations_table(priv);
  4730. rc = iwl3945_grab_nic_access(priv);
  4731. if (rc) {
  4732. IWL_WARNING("Can not read RFKILL status from adapter\n");
  4733. return;
  4734. }
  4735. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4736. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4737. iwl3945_release_nic_access(priv);
  4738. if (rfkill & 0x1) {
  4739. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4740. /* if RFKILL is not on, then wait for thermal
  4741. * sensor in adapter to kick in */
  4742. while (iwl3945_hw_get_temperature(priv) == 0) {
  4743. thermal_spin++;
  4744. udelay(10);
  4745. }
  4746. if (thermal_spin)
  4747. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4748. thermal_spin * 10);
  4749. } else
  4750. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4751. /* After the ALIVE response, we can send commands to 3945 uCode */
  4752. set_bit(STATUS_ALIVE, &priv->status);
  4753. /* Clear out the uCode error bit if it is set */
  4754. clear_bit(STATUS_FW_ERROR, &priv->status);
  4755. if (iwl3945_is_rfkill(priv))
  4756. return;
  4757. ieee80211_wake_queues(priv->hw);
  4758. priv->active_rate = priv->rates_mask;
  4759. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4760. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4761. if (iwl3945_is_associated(priv)) {
  4762. struct iwl3945_rxon_cmd *active_rxon =
  4763. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4764. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4765. sizeof(priv->staging_rxon));
  4766. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4767. } else {
  4768. /* Initialize our rx_config data */
  4769. iwl3945_connection_init_rx_config(priv);
  4770. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4771. }
  4772. /* Configure Bluetooth device coexistence support */
  4773. iwl3945_send_bt_config(priv);
  4774. /* Configure the adapter for unassociated operation */
  4775. iwl3945_commit_rxon(priv);
  4776. iwl3945_reg_txpower_periodic(priv);
  4777. iwl3945_led_register(priv);
  4778. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4779. set_bit(STATUS_READY, &priv->status);
  4780. wake_up_interruptible(&priv->wait_command_queue);
  4781. if (priv->error_recovering)
  4782. iwl3945_error_recovery(priv);
  4783. return;
  4784. restart:
  4785. queue_work(priv->workqueue, &priv->restart);
  4786. }
  4787. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4788. static void __iwl3945_down(struct iwl3945_priv *priv)
  4789. {
  4790. unsigned long flags;
  4791. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4792. struct ieee80211_conf *conf = NULL;
  4793. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4794. conf = ieee80211_get_hw_conf(priv->hw);
  4795. if (!exit_pending)
  4796. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4797. iwl3945_led_unregister(priv);
  4798. iwl3945_clear_stations_table(priv);
  4799. /* Unblock any waiting calls */
  4800. wake_up_interruptible_all(&priv->wait_command_queue);
  4801. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4802. * exiting the module */
  4803. if (!exit_pending)
  4804. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4805. /* stop and reset the on-board processor */
  4806. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4807. /* tell the device to stop sending interrupts */
  4808. spin_lock_irqsave(&priv->lock, flags);
  4809. iwl3945_disable_interrupts(priv);
  4810. spin_unlock_irqrestore(&priv->lock, flags);
  4811. iwl_synchronize_irq(priv);
  4812. if (priv->mac80211_registered)
  4813. ieee80211_stop_queues(priv->hw);
  4814. /* If we have not previously called iwl3945_init() then
  4815. * clear all bits but the RF Kill and SUSPEND bits and return */
  4816. if (!iwl3945_is_init(priv)) {
  4817. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4818. STATUS_RF_KILL_HW |
  4819. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4820. STATUS_RF_KILL_SW |
  4821. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4822. STATUS_GEO_CONFIGURED |
  4823. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4824. STATUS_IN_SUSPEND |
  4825. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4826. STATUS_EXIT_PENDING;
  4827. goto exit;
  4828. }
  4829. /* ...otherwise clear out all the status bits but the RF Kill and
  4830. * SUSPEND bits and continue taking the NIC down. */
  4831. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4832. STATUS_RF_KILL_HW |
  4833. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4834. STATUS_RF_KILL_SW |
  4835. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4836. STATUS_GEO_CONFIGURED |
  4837. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4838. STATUS_IN_SUSPEND |
  4839. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4840. STATUS_FW_ERROR |
  4841. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4842. STATUS_EXIT_PENDING;
  4843. spin_lock_irqsave(&priv->lock, flags);
  4844. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4845. spin_unlock_irqrestore(&priv->lock, flags);
  4846. iwl3945_hw_txq_ctx_stop(priv);
  4847. iwl3945_hw_rxq_stop(priv);
  4848. spin_lock_irqsave(&priv->lock, flags);
  4849. if (!iwl3945_grab_nic_access(priv)) {
  4850. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4851. APMG_CLK_VAL_DMA_CLK_RQT);
  4852. iwl3945_release_nic_access(priv);
  4853. }
  4854. spin_unlock_irqrestore(&priv->lock, flags);
  4855. udelay(5);
  4856. iwl3945_hw_nic_stop_master(priv);
  4857. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4858. iwl3945_hw_nic_reset(priv);
  4859. exit:
  4860. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  4861. if (priv->ibss_beacon)
  4862. dev_kfree_skb(priv->ibss_beacon);
  4863. priv->ibss_beacon = NULL;
  4864. /* clear out any free frames */
  4865. iwl3945_clear_free_frames(priv);
  4866. }
  4867. static void iwl3945_down(struct iwl3945_priv *priv)
  4868. {
  4869. mutex_lock(&priv->mutex);
  4870. __iwl3945_down(priv);
  4871. mutex_unlock(&priv->mutex);
  4872. iwl3945_cancel_deferred_work(priv);
  4873. }
  4874. #define MAX_HW_RESTARTS 5
  4875. static int __iwl3945_up(struct iwl3945_priv *priv)
  4876. {
  4877. int rc, i;
  4878. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4879. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  4880. return -EIO;
  4881. }
  4882. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4883. IWL_WARNING("Radio disabled by SW RF kill (module "
  4884. "parameter)\n");
  4885. return -ENODEV;
  4886. }
  4887. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4888. IWL_ERROR("ucode not available for device bring up\n");
  4889. return -EIO;
  4890. }
  4891. /* If platform's RF_KILL switch is NOT set to KILL */
  4892. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  4893. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4894. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4895. else {
  4896. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4897. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4898. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  4899. return -ENODEV;
  4900. }
  4901. }
  4902. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4903. rc = iwl3945_hw_nic_init(priv);
  4904. if (rc) {
  4905. IWL_ERROR("Unable to int nic\n");
  4906. return rc;
  4907. }
  4908. /* make sure rfkill handshake bits are cleared */
  4909. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4910. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4911. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4912. /* clear (again), then enable host interrupts */
  4913. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  4914. iwl3945_enable_interrupts(priv);
  4915. /* really make sure rfkill handshake bits are cleared */
  4916. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4917. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4918. /* Copy original ucode data image from disk into backup cache.
  4919. * This will be used to initialize the on-board processor's
  4920. * data SRAM for a clean start when the runtime program first loads. */
  4921. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4922. priv->ucode_data.len);
  4923. /* We return success when we resume from suspend and rf_kill is on. */
  4924. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4925. return 0;
  4926. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4927. iwl3945_clear_stations_table(priv);
  4928. /* load bootstrap state machine,
  4929. * load bootstrap program into processor's memory,
  4930. * prepare to load the "initialize" uCode */
  4931. rc = iwl3945_load_bsm(priv);
  4932. if (rc) {
  4933. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  4934. continue;
  4935. }
  4936. /* start card; "initialize" will load runtime ucode */
  4937. iwl3945_nic_start(priv);
  4938. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4939. return 0;
  4940. }
  4941. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4942. __iwl3945_down(priv);
  4943. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4944. /* tried to restart and config the device for as long as our
  4945. * patience could withstand */
  4946. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  4947. return -EIO;
  4948. }
  4949. /*****************************************************************************
  4950. *
  4951. * Workqueue callbacks
  4952. *
  4953. *****************************************************************************/
  4954. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4955. {
  4956. struct iwl3945_priv *priv =
  4957. container_of(data, struct iwl3945_priv, init_alive_start.work);
  4958. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4959. return;
  4960. mutex_lock(&priv->mutex);
  4961. iwl3945_init_alive_start(priv);
  4962. mutex_unlock(&priv->mutex);
  4963. }
  4964. static void iwl3945_bg_alive_start(struct work_struct *data)
  4965. {
  4966. struct iwl3945_priv *priv =
  4967. container_of(data, struct iwl3945_priv, alive_start.work);
  4968. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4969. return;
  4970. mutex_lock(&priv->mutex);
  4971. iwl3945_alive_start(priv);
  4972. mutex_unlock(&priv->mutex);
  4973. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  4974. }
  4975. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4976. {
  4977. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  4978. wake_up_interruptible(&priv->wait_command_queue);
  4979. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4980. return;
  4981. mutex_lock(&priv->mutex);
  4982. if (!iwl3945_is_rfkill(priv)) {
  4983. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4984. "HW and/or SW RF Kill no longer active, restarting "
  4985. "device\n");
  4986. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4987. queue_work(priv->workqueue, &priv->restart);
  4988. } else {
  4989. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4990. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4991. "disabled by SW switch\n");
  4992. else
  4993. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  4994. "Kill switch must be turned off for "
  4995. "wireless networking to work.\n");
  4996. }
  4997. mutex_unlock(&priv->mutex);
  4998. iwl3945_rfkill_set_hw_state(priv);
  4999. }
  5000. static void iwl3945_bg_set_monitor(struct work_struct *work)
  5001. {
  5002. struct iwl3945_priv *priv = container_of(work,
  5003. struct iwl3945_priv, set_monitor);
  5004. IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
  5005. mutex_lock(&priv->mutex);
  5006. if (!iwl3945_is_ready(priv))
  5007. IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
  5008. else
  5009. if (iwl3945_set_mode(priv, NL80211_IFTYPE_MONITOR) != 0)
  5010. IWL_ERROR("iwl3945_set_mode() failed\n");
  5011. mutex_unlock(&priv->mutex);
  5012. }
  5013. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5014. static void iwl3945_bg_scan_check(struct work_struct *data)
  5015. {
  5016. struct iwl3945_priv *priv =
  5017. container_of(data, struct iwl3945_priv, scan_check.work);
  5018. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5019. return;
  5020. mutex_lock(&priv->mutex);
  5021. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5022. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5023. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5024. "Scan completion watchdog resetting adapter (%dms)\n",
  5025. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5026. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5027. iwl3945_send_scan_abort(priv);
  5028. }
  5029. mutex_unlock(&priv->mutex);
  5030. }
  5031. static void iwl3945_bg_request_scan(struct work_struct *data)
  5032. {
  5033. struct iwl3945_priv *priv =
  5034. container_of(data, struct iwl3945_priv, request_scan);
  5035. struct iwl3945_host_cmd cmd = {
  5036. .id = REPLY_SCAN_CMD,
  5037. .len = sizeof(struct iwl3945_scan_cmd),
  5038. .meta.flags = CMD_SIZE_HUGE,
  5039. };
  5040. int rc = 0;
  5041. struct iwl3945_scan_cmd *scan;
  5042. struct ieee80211_conf *conf = NULL;
  5043. u8 n_probes = 2;
  5044. enum ieee80211_band band;
  5045. DECLARE_SSID_BUF(ssid);
  5046. conf = ieee80211_get_hw_conf(priv->hw);
  5047. mutex_lock(&priv->mutex);
  5048. if (!iwl3945_is_ready(priv)) {
  5049. IWL_WARNING("request scan called when driver not ready.\n");
  5050. goto done;
  5051. }
  5052. /* Make sure the scan wasn't canceled before this queued work
  5053. * was given the chance to run... */
  5054. if (!test_bit(STATUS_SCANNING, &priv->status))
  5055. goto done;
  5056. /* This should never be called or scheduled if there is currently
  5057. * a scan active in the hardware. */
  5058. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5059. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5060. "Ignoring second request.\n");
  5061. rc = -EIO;
  5062. goto done;
  5063. }
  5064. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5065. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5066. goto done;
  5067. }
  5068. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5069. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5070. goto done;
  5071. }
  5072. if (iwl3945_is_rfkill(priv)) {
  5073. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5074. goto done;
  5075. }
  5076. if (!test_bit(STATUS_READY, &priv->status)) {
  5077. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5078. goto done;
  5079. }
  5080. if (!priv->scan_bands) {
  5081. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5082. goto done;
  5083. }
  5084. if (!priv->scan) {
  5085. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5086. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5087. if (!priv->scan) {
  5088. rc = -ENOMEM;
  5089. goto done;
  5090. }
  5091. }
  5092. scan = priv->scan;
  5093. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5094. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5095. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5096. if (iwl3945_is_associated(priv)) {
  5097. u16 interval = 0;
  5098. u32 extra;
  5099. u32 suspend_time = 100;
  5100. u32 scan_suspend_time = 100;
  5101. unsigned long flags;
  5102. IWL_DEBUG_INFO("Scanning while associated...\n");
  5103. spin_lock_irqsave(&priv->lock, flags);
  5104. interval = priv->beacon_int;
  5105. spin_unlock_irqrestore(&priv->lock, flags);
  5106. scan->suspend_time = 0;
  5107. scan->max_out_time = cpu_to_le32(200 * 1024);
  5108. if (!interval)
  5109. interval = suspend_time;
  5110. /*
  5111. * suspend time format:
  5112. * 0-19: beacon interval in usec (time before exec.)
  5113. * 20-23: 0
  5114. * 24-31: number of beacons (suspend between channels)
  5115. */
  5116. extra = (suspend_time / interval) << 24;
  5117. scan_suspend_time = 0xFF0FFFFF &
  5118. (extra | ((suspend_time % interval) * 1024));
  5119. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5120. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5121. scan_suspend_time, interval);
  5122. }
  5123. /* We should add the ability for user to lock to PASSIVE ONLY */
  5124. if (priv->one_direct_scan) {
  5125. IWL_DEBUG_SCAN
  5126. ("Kicking off one direct scan for '%s'\n",
  5127. print_ssid(ssid, priv->direct_ssid,
  5128. priv->direct_ssid_len));
  5129. scan->direct_scan[0].id = WLAN_EID_SSID;
  5130. scan->direct_scan[0].len = priv->direct_ssid_len;
  5131. memcpy(scan->direct_scan[0].ssid,
  5132. priv->direct_ssid, priv->direct_ssid_len);
  5133. n_probes++;
  5134. } else
  5135. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5136. /* We don't build a direct scan probe request; the uCode will do
  5137. * that based on the direct_mask added to each channel entry */
  5138. scan->tx_cmd.len = cpu_to_le16(
  5139. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5140. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  5141. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5142. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5143. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5144. /* flags + rate selection */
  5145. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5146. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5147. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5148. scan->good_CRC_th = 0;
  5149. band = IEEE80211_BAND_2GHZ;
  5150. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5151. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5152. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5153. band = IEEE80211_BAND_5GHZ;
  5154. } else {
  5155. IWL_WARNING("Invalid scan band count\n");
  5156. goto done;
  5157. }
  5158. /* select Rx antennas */
  5159. scan->flags |= iwl3945_get_antenna_flags(priv);
  5160. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  5161. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5162. scan->channel_count =
  5163. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  5164. n_probes,
  5165. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5166. if (scan->channel_count == 0) {
  5167. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  5168. goto done;
  5169. }
  5170. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5171. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5172. cmd.data = scan;
  5173. scan->len = cpu_to_le16(cmd.len);
  5174. set_bit(STATUS_SCAN_HW, &priv->status);
  5175. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5176. if (rc)
  5177. goto done;
  5178. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5179. IWL_SCAN_CHECK_WATCHDOG);
  5180. mutex_unlock(&priv->mutex);
  5181. return;
  5182. done:
  5183. /* can not perform scan make sure we clear scanning
  5184. * bits from status so next scan request can be performed.
  5185. * if we dont clear scanning status bit here all next scan
  5186. * will fail
  5187. */
  5188. clear_bit(STATUS_SCAN_HW, &priv->status);
  5189. clear_bit(STATUS_SCANNING, &priv->status);
  5190. /* inform mac80211 scan aborted */
  5191. queue_work(priv->workqueue, &priv->scan_completed);
  5192. mutex_unlock(&priv->mutex);
  5193. }
  5194. static void iwl3945_bg_up(struct work_struct *data)
  5195. {
  5196. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5197. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5198. return;
  5199. mutex_lock(&priv->mutex);
  5200. __iwl3945_up(priv);
  5201. mutex_unlock(&priv->mutex);
  5202. iwl3945_rfkill_set_hw_state(priv);
  5203. }
  5204. static void iwl3945_bg_restart(struct work_struct *data)
  5205. {
  5206. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5207. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5208. return;
  5209. iwl3945_down(priv);
  5210. queue_work(priv->workqueue, &priv->up);
  5211. }
  5212. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5213. {
  5214. struct iwl3945_priv *priv =
  5215. container_of(data, struct iwl3945_priv, rx_replenish);
  5216. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5217. return;
  5218. mutex_lock(&priv->mutex);
  5219. iwl3945_rx_replenish(priv);
  5220. mutex_unlock(&priv->mutex);
  5221. }
  5222. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5223. static void iwl3945_post_associate(struct iwl3945_priv *priv)
  5224. {
  5225. int rc = 0;
  5226. struct ieee80211_conf *conf = NULL;
  5227. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5228. IWL_ERROR("%s Should not be called in AP mode\n", __func__);
  5229. return;
  5230. }
  5231. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  5232. priv->assoc_id, priv->active_rxon.bssid_addr);
  5233. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5234. return;
  5235. if (!priv->vif || !priv->is_open)
  5236. return;
  5237. iwl3945_scan_cancel_timeout(priv, 200);
  5238. conf = ieee80211_get_hw_conf(priv->hw);
  5239. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5240. iwl3945_commit_rxon(priv);
  5241. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5242. iwl3945_setup_rxon_timing(priv);
  5243. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5244. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5245. if (rc)
  5246. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5247. "Attempting to continue.\n");
  5248. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5249. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5250. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5251. priv->assoc_id, priv->beacon_int);
  5252. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5253. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5254. else
  5255. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5256. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5257. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5258. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5259. else
  5260. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5261. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5262. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5263. }
  5264. iwl3945_commit_rxon(priv);
  5265. switch (priv->iw_mode) {
  5266. case NL80211_IFTYPE_STATION:
  5267. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5268. break;
  5269. case NL80211_IFTYPE_ADHOC:
  5270. /* clear out the station table */
  5271. iwl3945_clear_stations_table(priv);
  5272. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5273. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5274. iwl3945_sync_sta(priv, IWL_STA_ID,
  5275. (priv->band == IEEE80211_BAND_5GHZ) ?
  5276. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5277. CMD_ASYNC);
  5278. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5279. iwl3945_send_beacon_cmd(priv);
  5280. break;
  5281. default:
  5282. IWL_ERROR("%s Should not be called in %d mode\n",
  5283. __func__, priv->iw_mode);
  5284. break;
  5285. }
  5286. iwl3945_activate_qos(priv, 0);
  5287. /* we have just associated, don't start scan too early */
  5288. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5289. }
  5290. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5291. {
  5292. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5293. if (!iwl3945_is_ready(priv))
  5294. return;
  5295. mutex_lock(&priv->mutex);
  5296. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5297. iwl3945_send_scan_abort(priv);
  5298. mutex_unlock(&priv->mutex);
  5299. }
  5300. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  5301. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5302. {
  5303. struct iwl3945_priv *priv =
  5304. container_of(work, struct iwl3945_priv, scan_completed);
  5305. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5306. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5307. return;
  5308. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5309. iwl3945_mac_config(priv->hw, 0);
  5310. ieee80211_scan_completed(priv->hw);
  5311. /* Since setting the TXPOWER may have been deferred while
  5312. * performing the scan, fire one off */
  5313. mutex_lock(&priv->mutex);
  5314. iwl3945_hw_reg_send_txpower(priv);
  5315. mutex_unlock(&priv->mutex);
  5316. }
  5317. /*****************************************************************************
  5318. *
  5319. * mac80211 entry point functions
  5320. *
  5321. *****************************************************************************/
  5322. #define UCODE_READY_TIMEOUT (2 * HZ)
  5323. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5324. {
  5325. struct iwl3945_priv *priv = hw->priv;
  5326. int ret;
  5327. IWL_DEBUG_MAC80211("enter\n");
  5328. if (pci_enable_device(priv->pci_dev)) {
  5329. IWL_ERROR("Fail to pci_enable_device\n");
  5330. return -ENODEV;
  5331. }
  5332. pci_restore_state(priv->pci_dev);
  5333. pci_enable_msi(priv->pci_dev);
  5334. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5335. DRV_NAME, priv);
  5336. if (ret) {
  5337. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5338. goto out_disable_msi;
  5339. }
  5340. /* we should be verifying the device is ready to be opened */
  5341. mutex_lock(&priv->mutex);
  5342. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5343. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5344. * ucode filename and max sizes are card-specific. */
  5345. if (!priv->ucode_code.len) {
  5346. ret = iwl3945_read_ucode(priv);
  5347. if (ret) {
  5348. IWL_ERROR("Could not read microcode: %d\n", ret);
  5349. mutex_unlock(&priv->mutex);
  5350. goto out_release_irq;
  5351. }
  5352. }
  5353. ret = __iwl3945_up(priv);
  5354. mutex_unlock(&priv->mutex);
  5355. iwl3945_rfkill_set_hw_state(priv);
  5356. if (ret)
  5357. goto out_release_irq;
  5358. IWL_DEBUG_INFO("Start UP work.\n");
  5359. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5360. return 0;
  5361. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5362. * mac80211 will not be run successfully. */
  5363. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5364. test_bit(STATUS_READY, &priv->status),
  5365. UCODE_READY_TIMEOUT);
  5366. if (!ret) {
  5367. if (!test_bit(STATUS_READY, &priv->status)) {
  5368. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5369. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5370. ret = -ETIMEDOUT;
  5371. goto out_release_irq;
  5372. }
  5373. }
  5374. priv->is_open = 1;
  5375. IWL_DEBUG_MAC80211("leave\n");
  5376. return 0;
  5377. out_release_irq:
  5378. free_irq(priv->pci_dev->irq, priv);
  5379. out_disable_msi:
  5380. pci_disable_msi(priv->pci_dev);
  5381. pci_disable_device(priv->pci_dev);
  5382. priv->is_open = 0;
  5383. IWL_DEBUG_MAC80211("leave - failed\n");
  5384. return ret;
  5385. }
  5386. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5387. {
  5388. struct iwl3945_priv *priv = hw->priv;
  5389. IWL_DEBUG_MAC80211("enter\n");
  5390. if (!priv->is_open) {
  5391. IWL_DEBUG_MAC80211("leave - skip\n");
  5392. return;
  5393. }
  5394. priv->is_open = 0;
  5395. if (iwl3945_is_ready_rf(priv)) {
  5396. /* stop mac, cancel any scan request and clear
  5397. * RXON_FILTER_ASSOC_MSK BIT
  5398. */
  5399. mutex_lock(&priv->mutex);
  5400. iwl3945_scan_cancel_timeout(priv, 100);
  5401. mutex_unlock(&priv->mutex);
  5402. }
  5403. iwl3945_down(priv);
  5404. flush_workqueue(priv->workqueue);
  5405. free_irq(priv->pci_dev->irq, priv);
  5406. pci_disable_msi(priv->pci_dev);
  5407. pci_save_state(priv->pci_dev);
  5408. pci_disable_device(priv->pci_dev);
  5409. IWL_DEBUG_MAC80211("leave\n");
  5410. }
  5411. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5412. {
  5413. struct iwl3945_priv *priv = hw->priv;
  5414. IWL_DEBUG_MAC80211("enter\n");
  5415. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5416. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5417. if (iwl3945_tx_skb(priv, skb))
  5418. dev_kfree_skb_any(skb);
  5419. IWL_DEBUG_MAC80211("leave\n");
  5420. return 0;
  5421. }
  5422. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5423. struct ieee80211_if_init_conf *conf)
  5424. {
  5425. struct iwl3945_priv *priv = hw->priv;
  5426. unsigned long flags;
  5427. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5428. if (priv->vif) {
  5429. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5430. return -EOPNOTSUPP;
  5431. }
  5432. spin_lock_irqsave(&priv->lock, flags);
  5433. priv->vif = conf->vif;
  5434. spin_unlock_irqrestore(&priv->lock, flags);
  5435. mutex_lock(&priv->mutex);
  5436. if (conf->mac_addr) {
  5437. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5438. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5439. }
  5440. if (iwl3945_is_ready(priv))
  5441. iwl3945_set_mode(priv, conf->type);
  5442. mutex_unlock(&priv->mutex);
  5443. IWL_DEBUG_MAC80211("leave\n");
  5444. return 0;
  5445. }
  5446. /**
  5447. * iwl3945_mac_config - mac80211 config callback
  5448. *
  5449. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5450. * be set inappropriately and the driver currently sets the hardware up to
  5451. * use it whenever needed.
  5452. */
  5453. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5454. {
  5455. struct iwl3945_priv *priv = hw->priv;
  5456. const struct iwl3945_channel_info *ch_info;
  5457. struct ieee80211_conf *conf = &hw->conf;
  5458. unsigned long flags;
  5459. int ret = 0;
  5460. mutex_lock(&priv->mutex);
  5461. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5462. if (!iwl3945_is_ready(priv)) {
  5463. IWL_DEBUG_MAC80211("leave - not ready\n");
  5464. ret = -EIO;
  5465. goto out;
  5466. }
  5467. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5468. test_bit(STATUS_SCANNING, &priv->status))) {
  5469. IWL_DEBUG_MAC80211("leave - scanning\n");
  5470. set_bit(STATUS_CONF_PENDING, &priv->status);
  5471. mutex_unlock(&priv->mutex);
  5472. return 0;
  5473. }
  5474. spin_lock_irqsave(&priv->lock, flags);
  5475. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5476. conf->channel->hw_value);
  5477. if (!is_channel_valid(ch_info)) {
  5478. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5479. conf->channel->hw_value, conf->channel->band);
  5480. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5481. spin_unlock_irqrestore(&priv->lock, flags);
  5482. ret = -EINVAL;
  5483. goto out;
  5484. }
  5485. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5486. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5487. /* The list of supported rates and rate mask can be different
  5488. * for each phymode; since the phymode may have changed, reset
  5489. * the rate mask to what mac80211 lists */
  5490. iwl3945_set_rate(priv);
  5491. spin_unlock_irqrestore(&priv->lock, flags);
  5492. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5493. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5494. iwl3945_hw_channel_switch(priv, conf->channel);
  5495. goto out;
  5496. }
  5497. #endif
  5498. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5499. if (!conf->radio_enabled) {
  5500. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5501. goto out;
  5502. }
  5503. if (iwl3945_is_rfkill(priv)) {
  5504. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5505. ret = -EIO;
  5506. goto out;
  5507. }
  5508. iwl3945_set_rate(priv);
  5509. if (memcmp(&priv->active_rxon,
  5510. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5511. iwl3945_commit_rxon(priv);
  5512. else
  5513. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5514. IWL_DEBUG_MAC80211("leave\n");
  5515. out:
  5516. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5517. mutex_unlock(&priv->mutex);
  5518. return ret;
  5519. }
  5520. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5521. {
  5522. int rc = 0;
  5523. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5524. return;
  5525. /* The following should be done only at AP bring up */
  5526. if (!(iwl3945_is_associated(priv))) {
  5527. /* RXON - unassoc (to set timing command) */
  5528. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5529. iwl3945_commit_rxon(priv);
  5530. /* RXON Timing */
  5531. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5532. iwl3945_setup_rxon_timing(priv);
  5533. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5534. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5535. if (rc)
  5536. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5537. "Attempting to continue.\n");
  5538. /* FIXME: what should be the assoc_id for AP? */
  5539. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5540. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5541. priv->staging_rxon.flags |=
  5542. RXON_FLG_SHORT_PREAMBLE_MSK;
  5543. else
  5544. priv->staging_rxon.flags &=
  5545. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5546. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5547. if (priv->assoc_capability &
  5548. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5549. priv->staging_rxon.flags |=
  5550. RXON_FLG_SHORT_SLOT_MSK;
  5551. else
  5552. priv->staging_rxon.flags &=
  5553. ~RXON_FLG_SHORT_SLOT_MSK;
  5554. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5555. priv->staging_rxon.flags &=
  5556. ~RXON_FLG_SHORT_SLOT_MSK;
  5557. }
  5558. /* restore RXON assoc */
  5559. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5560. iwl3945_commit_rxon(priv);
  5561. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5562. }
  5563. iwl3945_send_beacon_cmd(priv);
  5564. /* FIXME - we need to add code here to detect a totally new
  5565. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5566. * clear sta table, add BCAST sta... */
  5567. }
  5568. /* temporary */
  5569. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb);
  5570. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5571. struct ieee80211_vif *vif,
  5572. struct ieee80211_if_conf *conf)
  5573. {
  5574. struct iwl3945_priv *priv = hw->priv;
  5575. int rc;
  5576. if (conf == NULL)
  5577. return -EIO;
  5578. if (priv->vif != vif) {
  5579. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5580. return 0;
  5581. }
  5582. /* handle this temporarily here */
  5583. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5584. conf->changed & IEEE80211_IFCC_BEACON) {
  5585. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5586. if (!beacon)
  5587. return -ENOMEM;
  5588. rc = iwl3945_mac_beacon_update(hw, beacon);
  5589. if (rc)
  5590. return rc;
  5591. }
  5592. /* XXX: this MUST use conf->mac_addr */
  5593. if (!iwl3945_is_alive(priv))
  5594. return -EAGAIN;
  5595. mutex_lock(&priv->mutex);
  5596. if (conf->bssid)
  5597. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5598. /*
  5599. * very dubious code was here; the probe filtering flag is never set:
  5600. *
  5601. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5602. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5603. */
  5604. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5605. if (!conf->bssid) {
  5606. conf->bssid = priv->mac_addr;
  5607. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5608. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5609. conf->bssid);
  5610. }
  5611. if (priv->ibss_beacon)
  5612. dev_kfree_skb(priv->ibss_beacon);
  5613. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5614. }
  5615. if (iwl3945_is_rfkill(priv))
  5616. goto done;
  5617. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5618. !is_multicast_ether_addr(conf->bssid)) {
  5619. /* If there is currently a HW scan going on in the background
  5620. * then we need to cancel it else the RXON below will fail. */
  5621. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5622. IWL_WARNING("Aborted scan still in progress "
  5623. "after 100ms\n");
  5624. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5625. mutex_unlock(&priv->mutex);
  5626. return -EAGAIN;
  5627. }
  5628. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5629. /* TODO: Audit driver for usage of these members and see
  5630. * if mac80211 deprecates them (priv->bssid looks like it
  5631. * shouldn't be there, but I haven't scanned the IBSS code
  5632. * to verify) - jpk */
  5633. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5634. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5635. iwl3945_config_ap(priv);
  5636. else {
  5637. rc = iwl3945_commit_rxon(priv);
  5638. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5639. iwl3945_add_station(priv,
  5640. priv->active_rxon.bssid_addr, 1, 0);
  5641. }
  5642. } else {
  5643. iwl3945_scan_cancel_timeout(priv, 100);
  5644. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5645. iwl3945_commit_rxon(priv);
  5646. }
  5647. done:
  5648. IWL_DEBUG_MAC80211("leave\n");
  5649. mutex_unlock(&priv->mutex);
  5650. return 0;
  5651. }
  5652. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5653. unsigned int changed_flags,
  5654. unsigned int *total_flags,
  5655. int mc_count, struct dev_addr_list *mc_list)
  5656. {
  5657. struct iwl3945_priv *priv = hw->priv;
  5658. if (changed_flags & (*total_flags) & FIF_OTHER_BSS) {
  5659. IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
  5660. NL80211_IFTYPE_MONITOR,
  5661. changed_flags, *total_flags);
  5662. /* queue work 'cuz mac80211 is holding a lock which
  5663. * prevents us from issuing (synchronous) f/w cmds */
  5664. queue_work(priv->workqueue, &priv->set_monitor);
  5665. }
  5666. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI |
  5667. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5668. }
  5669. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5670. struct ieee80211_if_init_conf *conf)
  5671. {
  5672. struct iwl3945_priv *priv = hw->priv;
  5673. IWL_DEBUG_MAC80211("enter\n");
  5674. mutex_lock(&priv->mutex);
  5675. if (iwl3945_is_ready_rf(priv)) {
  5676. iwl3945_scan_cancel_timeout(priv, 100);
  5677. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5678. iwl3945_commit_rxon(priv);
  5679. }
  5680. if (priv->vif == conf->vif) {
  5681. priv->vif = NULL;
  5682. memset(priv->bssid, 0, ETH_ALEN);
  5683. }
  5684. mutex_unlock(&priv->mutex);
  5685. IWL_DEBUG_MAC80211("leave\n");
  5686. }
  5687. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5688. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5689. struct ieee80211_vif *vif,
  5690. struct ieee80211_bss_conf *bss_conf,
  5691. u32 changes)
  5692. {
  5693. struct iwl3945_priv *priv = hw->priv;
  5694. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5695. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5696. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5697. bss_conf->use_short_preamble);
  5698. if (bss_conf->use_short_preamble)
  5699. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5700. else
  5701. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5702. }
  5703. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5704. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5705. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5706. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5707. else
  5708. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5709. }
  5710. if (changes & BSS_CHANGED_ASSOC) {
  5711. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5712. /* This should never happen as this function should
  5713. * never be called from interrupt context. */
  5714. if (WARN_ON_ONCE(in_interrupt()))
  5715. return;
  5716. if (bss_conf->assoc) {
  5717. priv->assoc_id = bss_conf->aid;
  5718. priv->beacon_int = bss_conf->beacon_int;
  5719. priv->timestamp0 = bss_conf->timestamp & 0xFFFFFFFF;
  5720. priv->timestamp1 = (bss_conf->timestamp >> 32) &
  5721. 0xFFFFFFFF;
  5722. priv->assoc_capability = bss_conf->assoc_capability;
  5723. priv->next_scan_jiffies = jiffies +
  5724. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5725. mutex_lock(&priv->mutex);
  5726. iwl3945_post_associate(priv);
  5727. mutex_unlock(&priv->mutex);
  5728. } else {
  5729. priv->assoc_id = 0;
  5730. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5731. }
  5732. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5733. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5734. iwl3945_send_rxon_assoc(priv);
  5735. }
  5736. }
  5737. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5738. {
  5739. int rc = 0;
  5740. unsigned long flags;
  5741. struct iwl3945_priv *priv = hw->priv;
  5742. DECLARE_SSID_BUF(ssid_buf);
  5743. IWL_DEBUG_MAC80211("enter\n");
  5744. mutex_lock(&priv->mutex);
  5745. spin_lock_irqsave(&priv->lock, flags);
  5746. if (!iwl3945_is_ready_rf(priv)) {
  5747. rc = -EIO;
  5748. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5749. goto out_unlock;
  5750. }
  5751. if (priv->iw_mode == NL80211_IFTYPE_AP) { /* APs don't scan */
  5752. rc = -EIO;
  5753. IWL_ERROR("ERROR: APs don't scan\n");
  5754. goto out_unlock;
  5755. }
  5756. /* we don't schedule scan within next_scan_jiffies period */
  5757. if (priv->next_scan_jiffies &&
  5758. time_after(priv->next_scan_jiffies, jiffies)) {
  5759. rc = -EAGAIN;
  5760. goto out_unlock;
  5761. }
  5762. /* if we just finished scan ask for delay for a broadcast scan */
  5763. if ((len == 0) && priv->last_scan_jiffies &&
  5764. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5765. jiffies)) {
  5766. rc = -EAGAIN;
  5767. goto out_unlock;
  5768. }
  5769. if (len) {
  5770. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5771. print_ssid(ssid_buf, ssid, len), (int)len);
  5772. priv->one_direct_scan = 1;
  5773. priv->direct_ssid_len = (u8)
  5774. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5775. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5776. } else
  5777. priv->one_direct_scan = 0;
  5778. rc = iwl3945_scan_initiate(priv);
  5779. IWL_DEBUG_MAC80211("leave\n");
  5780. out_unlock:
  5781. spin_unlock_irqrestore(&priv->lock, flags);
  5782. mutex_unlock(&priv->mutex);
  5783. return rc;
  5784. }
  5785. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5786. const u8 *local_addr, const u8 *addr,
  5787. struct ieee80211_key_conf *key)
  5788. {
  5789. struct iwl3945_priv *priv = hw->priv;
  5790. int rc = 0;
  5791. u8 sta_id;
  5792. IWL_DEBUG_MAC80211("enter\n");
  5793. if (!iwl3945_param_hwcrypto) {
  5794. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5795. return -EOPNOTSUPP;
  5796. }
  5797. if (is_zero_ether_addr(addr))
  5798. /* only support pairwise keys */
  5799. return -EOPNOTSUPP;
  5800. sta_id = iwl3945_hw_find_station(priv, addr);
  5801. if (sta_id == IWL_INVALID_STATION) {
  5802. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5803. addr);
  5804. return -EINVAL;
  5805. }
  5806. mutex_lock(&priv->mutex);
  5807. iwl3945_scan_cancel_timeout(priv, 100);
  5808. switch (cmd) {
  5809. case SET_KEY:
  5810. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5811. if (!rc) {
  5812. iwl3945_set_rxon_hwcrypto(priv, 1);
  5813. iwl3945_commit_rxon(priv);
  5814. key->hw_key_idx = sta_id;
  5815. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5816. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5817. }
  5818. break;
  5819. case DISABLE_KEY:
  5820. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5821. if (!rc) {
  5822. iwl3945_set_rxon_hwcrypto(priv, 0);
  5823. iwl3945_commit_rxon(priv);
  5824. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5825. }
  5826. break;
  5827. default:
  5828. rc = -EINVAL;
  5829. }
  5830. IWL_DEBUG_MAC80211("leave\n");
  5831. mutex_unlock(&priv->mutex);
  5832. return rc;
  5833. }
  5834. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5835. const struct ieee80211_tx_queue_params *params)
  5836. {
  5837. struct iwl3945_priv *priv = hw->priv;
  5838. unsigned long flags;
  5839. int q;
  5840. IWL_DEBUG_MAC80211("enter\n");
  5841. if (!iwl3945_is_ready_rf(priv)) {
  5842. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5843. return -EIO;
  5844. }
  5845. if (queue >= AC_NUM) {
  5846. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5847. return 0;
  5848. }
  5849. if (!priv->qos_data.qos_enable) {
  5850. priv->qos_data.qos_active = 0;
  5851. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5852. return 0;
  5853. }
  5854. q = AC_NUM - 1 - queue;
  5855. spin_lock_irqsave(&priv->lock, flags);
  5856. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5857. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5858. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5859. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5860. cpu_to_le16((params->txop * 32));
  5861. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5862. priv->qos_data.qos_active = 1;
  5863. spin_unlock_irqrestore(&priv->lock, flags);
  5864. mutex_lock(&priv->mutex);
  5865. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5866. iwl3945_activate_qos(priv, 1);
  5867. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5868. iwl3945_activate_qos(priv, 0);
  5869. mutex_unlock(&priv->mutex);
  5870. IWL_DEBUG_MAC80211("leave\n");
  5871. return 0;
  5872. }
  5873. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5874. struct ieee80211_tx_queue_stats *stats)
  5875. {
  5876. struct iwl3945_priv *priv = hw->priv;
  5877. int i, avail;
  5878. struct iwl3945_tx_queue *txq;
  5879. struct iwl3945_queue *q;
  5880. unsigned long flags;
  5881. IWL_DEBUG_MAC80211("enter\n");
  5882. if (!iwl3945_is_ready_rf(priv)) {
  5883. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5884. return -EIO;
  5885. }
  5886. spin_lock_irqsave(&priv->lock, flags);
  5887. for (i = 0; i < AC_NUM; i++) {
  5888. txq = &priv->txq[i];
  5889. q = &txq->q;
  5890. avail = iwl3945_queue_space(q);
  5891. stats[i].len = q->n_window - avail;
  5892. stats[i].limit = q->n_window - q->high_mark;
  5893. stats[i].count = q->n_window;
  5894. }
  5895. spin_unlock_irqrestore(&priv->lock, flags);
  5896. IWL_DEBUG_MAC80211("leave\n");
  5897. return 0;
  5898. }
  5899. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  5900. struct ieee80211_low_level_stats *stats)
  5901. {
  5902. IWL_DEBUG_MAC80211("enter\n");
  5903. IWL_DEBUG_MAC80211("leave\n");
  5904. return 0;
  5905. }
  5906. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5907. {
  5908. struct iwl3945_priv *priv = hw->priv;
  5909. unsigned long flags;
  5910. mutex_lock(&priv->mutex);
  5911. IWL_DEBUG_MAC80211("enter\n");
  5912. iwl3945_reset_qos(priv);
  5913. spin_lock_irqsave(&priv->lock, flags);
  5914. priv->assoc_id = 0;
  5915. priv->assoc_capability = 0;
  5916. priv->call_post_assoc_from_beacon = 0;
  5917. /* new association get rid of ibss beacon skb */
  5918. if (priv->ibss_beacon)
  5919. dev_kfree_skb(priv->ibss_beacon);
  5920. priv->ibss_beacon = NULL;
  5921. priv->beacon_int = priv->hw->conf.beacon_int;
  5922. priv->timestamp1 = 0;
  5923. priv->timestamp0 = 0;
  5924. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5925. priv->beacon_int = 0;
  5926. spin_unlock_irqrestore(&priv->lock, flags);
  5927. if (!iwl3945_is_ready_rf(priv)) {
  5928. IWL_DEBUG_MAC80211("leave - not ready\n");
  5929. mutex_unlock(&priv->mutex);
  5930. return;
  5931. }
  5932. /* we are restarting association process
  5933. * clear RXON_FILTER_ASSOC_MSK bit
  5934. */
  5935. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5936. iwl3945_scan_cancel_timeout(priv, 100);
  5937. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5938. iwl3945_commit_rxon(priv);
  5939. }
  5940. /* Per mac80211.h: This is only used in IBSS mode... */
  5941. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5942. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5943. mutex_unlock(&priv->mutex);
  5944. return;
  5945. }
  5946. iwl3945_set_rate(priv);
  5947. mutex_unlock(&priv->mutex);
  5948. IWL_DEBUG_MAC80211("leave\n");
  5949. }
  5950. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5951. {
  5952. struct iwl3945_priv *priv = hw->priv;
  5953. unsigned long flags;
  5954. mutex_lock(&priv->mutex);
  5955. IWL_DEBUG_MAC80211("enter\n");
  5956. if (!iwl3945_is_ready_rf(priv)) {
  5957. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5958. mutex_unlock(&priv->mutex);
  5959. return -EIO;
  5960. }
  5961. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5962. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5963. mutex_unlock(&priv->mutex);
  5964. return -EIO;
  5965. }
  5966. spin_lock_irqsave(&priv->lock, flags);
  5967. if (priv->ibss_beacon)
  5968. dev_kfree_skb(priv->ibss_beacon);
  5969. priv->ibss_beacon = skb;
  5970. priv->assoc_id = 0;
  5971. IWL_DEBUG_MAC80211("leave\n");
  5972. spin_unlock_irqrestore(&priv->lock, flags);
  5973. iwl3945_reset_qos(priv);
  5974. iwl3945_post_associate(priv);
  5975. mutex_unlock(&priv->mutex);
  5976. return 0;
  5977. }
  5978. /*****************************************************************************
  5979. *
  5980. * sysfs attributes
  5981. *
  5982. *****************************************************************************/
  5983. #ifdef CONFIG_IWL3945_DEBUG
  5984. /*
  5985. * The following adds a new attribute to the sysfs representation
  5986. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5987. * used for controlling the debug level.
  5988. *
  5989. * See the level definitions in iwl for details.
  5990. */
  5991. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  5992. {
  5993. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  5994. }
  5995. static ssize_t store_debug_level(struct device_driver *d,
  5996. const char *buf, size_t count)
  5997. {
  5998. char *p = (char *)buf;
  5999. u32 val;
  6000. val = simple_strtoul(p, &p, 0);
  6001. if (p == buf)
  6002. printk(KERN_INFO DRV_NAME
  6003. ": %s is not in hex or decimal form.\n", buf);
  6004. else
  6005. iwl3945_debug_level = val;
  6006. return strnlen(buf, count);
  6007. }
  6008. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6009. show_debug_level, store_debug_level);
  6010. #endif /* CONFIG_IWL3945_DEBUG */
  6011. static ssize_t show_temperature(struct device *d,
  6012. struct device_attribute *attr, char *buf)
  6013. {
  6014. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6015. if (!iwl3945_is_alive(priv))
  6016. return -EAGAIN;
  6017. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6018. }
  6019. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6020. static ssize_t show_tx_power(struct device *d,
  6021. struct device_attribute *attr, char *buf)
  6022. {
  6023. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6024. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6025. }
  6026. static ssize_t store_tx_power(struct device *d,
  6027. struct device_attribute *attr,
  6028. const char *buf, size_t count)
  6029. {
  6030. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6031. char *p = (char *)buf;
  6032. u32 val;
  6033. val = simple_strtoul(p, &p, 10);
  6034. if (p == buf)
  6035. printk(KERN_INFO DRV_NAME
  6036. ": %s is not in decimal form.\n", buf);
  6037. else
  6038. iwl3945_hw_reg_set_txpower(priv, val);
  6039. return count;
  6040. }
  6041. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6042. static ssize_t show_flags(struct device *d,
  6043. struct device_attribute *attr, char *buf)
  6044. {
  6045. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6046. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6047. }
  6048. static ssize_t store_flags(struct device *d,
  6049. struct device_attribute *attr,
  6050. const char *buf, size_t count)
  6051. {
  6052. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6053. u32 flags = simple_strtoul(buf, NULL, 0);
  6054. mutex_lock(&priv->mutex);
  6055. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6056. /* Cancel any currently running scans... */
  6057. if (iwl3945_scan_cancel_timeout(priv, 100))
  6058. IWL_WARNING("Could not cancel scan.\n");
  6059. else {
  6060. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6061. flags);
  6062. priv->staging_rxon.flags = cpu_to_le32(flags);
  6063. iwl3945_commit_rxon(priv);
  6064. }
  6065. }
  6066. mutex_unlock(&priv->mutex);
  6067. return count;
  6068. }
  6069. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6070. static ssize_t show_filter_flags(struct device *d,
  6071. struct device_attribute *attr, char *buf)
  6072. {
  6073. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6074. return sprintf(buf, "0x%04X\n",
  6075. le32_to_cpu(priv->active_rxon.filter_flags));
  6076. }
  6077. static ssize_t store_filter_flags(struct device *d,
  6078. struct device_attribute *attr,
  6079. const char *buf, size_t count)
  6080. {
  6081. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6082. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6083. mutex_lock(&priv->mutex);
  6084. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6085. /* Cancel any currently running scans... */
  6086. if (iwl3945_scan_cancel_timeout(priv, 100))
  6087. IWL_WARNING("Could not cancel scan.\n");
  6088. else {
  6089. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6090. "0x%04X\n", filter_flags);
  6091. priv->staging_rxon.filter_flags =
  6092. cpu_to_le32(filter_flags);
  6093. iwl3945_commit_rxon(priv);
  6094. }
  6095. }
  6096. mutex_unlock(&priv->mutex);
  6097. return count;
  6098. }
  6099. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6100. store_filter_flags);
  6101. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6102. static ssize_t show_measurement(struct device *d,
  6103. struct device_attribute *attr, char *buf)
  6104. {
  6105. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6106. struct iwl3945_spectrum_notification measure_report;
  6107. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6108. u8 *data = (u8 *)&measure_report;
  6109. unsigned long flags;
  6110. spin_lock_irqsave(&priv->lock, flags);
  6111. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6112. spin_unlock_irqrestore(&priv->lock, flags);
  6113. return 0;
  6114. }
  6115. memcpy(&measure_report, &priv->measure_report, size);
  6116. priv->measurement_status = 0;
  6117. spin_unlock_irqrestore(&priv->lock, flags);
  6118. while (size && (PAGE_SIZE - len)) {
  6119. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6120. PAGE_SIZE - len, 1);
  6121. len = strlen(buf);
  6122. if (PAGE_SIZE - len)
  6123. buf[len++] = '\n';
  6124. ofs += 16;
  6125. size -= min(size, 16U);
  6126. }
  6127. return len;
  6128. }
  6129. static ssize_t store_measurement(struct device *d,
  6130. struct device_attribute *attr,
  6131. const char *buf, size_t count)
  6132. {
  6133. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6134. struct ieee80211_measurement_params params = {
  6135. .channel = le16_to_cpu(priv->active_rxon.channel),
  6136. .start_time = cpu_to_le64(priv->last_tsf),
  6137. .duration = cpu_to_le16(1),
  6138. };
  6139. u8 type = IWL_MEASURE_BASIC;
  6140. u8 buffer[32];
  6141. u8 channel;
  6142. if (count) {
  6143. char *p = buffer;
  6144. strncpy(buffer, buf, min(sizeof(buffer), count));
  6145. channel = simple_strtoul(p, NULL, 0);
  6146. if (channel)
  6147. params.channel = channel;
  6148. p = buffer;
  6149. while (*p && *p != ' ')
  6150. p++;
  6151. if (*p)
  6152. type = simple_strtoul(p + 1, NULL, 0);
  6153. }
  6154. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6155. "channel %d (for '%s')\n", type, params.channel, buf);
  6156. iwl3945_get_measurement(priv, &params, type);
  6157. return count;
  6158. }
  6159. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6160. show_measurement, store_measurement);
  6161. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6162. static ssize_t store_retry_rate(struct device *d,
  6163. struct device_attribute *attr,
  6164. const char *buf, size_t count)
  6165. {
  6166. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6167. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6168. if (priv->retry_rate <= 0)
  6169. priv->retry_rate = 1;
  6170. return count;
  6171. }
  6172. static ssize_t show_retry_rate(struct device *d,
  6173. struct device_attribute *attr, char *buf)
  6174. {
  6175. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6176. return sprintf(buf, "%d", priv->retry_rate);
  6177. }
  6178. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6179. store_retry_rate);
  6180. static ssize_t store_power_level(struct device *d,
  6181. struct device_attribute *attr,
  6182. const char *buf, size_t count)
  6183. {
  6184. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6185. int rc;
  6186. int mode;
  6187. mode = simple_strtoul(buf, NULL, 0);
  6188. mutex_lock(&priv->mutex);
  6189. if (!iwl3945_is_ready(priv)) {
  6190. rc = -EAGAIN;
  6191. goto out;
  6192. }
  6193. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6194. mode = IWL_POWER_AC;
  6195. else
  6196. mode |= IWL_POWER_ENABLED;
  6197. if (mode != priv->power_mode) {
  6198. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6199. if (rc) {
  6200. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6201. goto out;
  6202. }
  6203. priv->power_mode = mode;
  6204. }
  6205. rc = count;
  6206. out:
  6207. mutex_unlock(&priv->mutex);
  6208. return rc;
  6209. }
  6210. #define MAX_WX_STRING 80
  6211. /* Values are in microsecond */
  6212. static const s32 timeout_duration[] = {
  6213. 350000,
  6214. 250000,
  6215. 75000,
  6216. 37000,
  6217. 25000,
  6218. };
  6219. static const s32 period_duration[] = {
  6220. 400000,
  6221. 700000,
  6222. 1000000,
  6223. 1000000,
  6224. 1000000
  6225. };
  6226. static ssize_t show_power_level(struct device *d,
  6227. struct device_attribute *attr, char *buf)
  6228. {
  6229. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6230. int level = IWL_POWER_LEVEL(priv->power_mode);
  6231. char *p = buf;
  6232. p += sprintf(p, "%d ", level);
  6233. switch (level) {
  6234. case IWL_POWER_MODE_CAM:
  6235. case IWL_POWER_AC:
  6236. p += sprintf(p, "(AC)");
  6237. break;
  6238. case IWL_POWER_BATTERY:
  6239. p += sprintf(p, "(BATTERY)");
  6240. break;
  6241. default:
  6242. p += sprintf(p,
  6243. "(Timeout %dms, Period %dms)",
  6244. timeout_duration[level - 1] / 1000,
  6245. period_duration[level - 1] / 1000);
  6246. }
  6247. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6248. p += sprintf(p, " OFF\n");
  6249. else
  6250. p += sprintf(p, " \n");
  6251. return p - buf + 1;
  6252. }
  6253. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6254. store_power_level);
  6255. static ssize_t show_channels(struct device *d,
  6256. struct device_attribute *attr, char *buf)
  6257. {
  6258. /* all this shit doesn't belong into sysfs anyway */
  6259. return 0;
  6260. }
  6261. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6262. static ssize_t show_statistics(struct device *d,
  6263. struct device_attribute *attr, char *buf)
  6264. {
  6265. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6266. u32 size = sizeof(struct iwl3945_notif_statistics);
  6267. u32 len = 0, ofs = 0;
  6268. u8 *data = (u8 *)&priv->statistics;
  6269. int rc = 0;
  6270. if (!iwl3945_is_alive(priv))
  6271. return -EAGAIN;
  6272. mutex_lock(&priv->mutex);
  6273. rc = iwl3945_send_statistics_request(priv);
  6274. mutex_unlock(&priv->mutex);
  6275. if (rc) {
  6276. len = sprintf(buf,
  6277. "Error sending statistics request: 0x%08X\n", rc);
  6278. return len;
  6279. }
  6280. while (size && (PAGE_SIZE - len)) {
  6281. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6282. PAGE_SIZE - len, 1);
  6283. len = strlen(buf);
  6284. if (PAGE_SIZE - len)
  6285. buf[len++] = '\n';
  6286. ofs += 16;
  6287. size -= min(size, 16U);
  6288. }
  6289. return len;
  6290. }
  6291. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6292. static ssize_t show_antenna(struct device *d,
  6293. struct device_attribute *attr, char *buf)
  6294. {
  6295. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6296. if (!iwl3945_is_alive(priv))
  6297. return -EAGAIN;
  6298. return sprintf(buf, "%d\n", priv->antenna);
  6299. }
  6300. static ssize_t store_antenna(struct device *d,
  6301. struct device_attribute *attr,
  6302. const char *buf, size_t count)
  6303. {
  6304. int ant;
  6305. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6306. if (count == 0)
  6307. return 0;
  6308. if (sscanf(buf, "%1i", &ant) != 1) {
  6309. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6310. return count;
  6311. }
  6312. if ((ant >= 0) && (ant <= 2)) {
  6313. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6314. priv->antenna = (enum iwl3945_antenna)ant;
  6315. } else
  6316. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6317. return count;
  6318. }
  6319. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6320. static ssize_t show_status(struct device *d,
  6321. struct device_attribute *attr, char *buf)
  6322. {
  6323. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6324. if (!iwl3945_is_alive(priv))
  6325. return -EAGAIN;
  6326. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6327. }
  6328. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6329. static ssize_t dump_error_log(struct device *d,
  6330. struct device_attribute *attr,
  6331. const char *buf, size_t count)
  6332. {
  6333. char *p = (char *)buf;
  6334. if (p[0] == '1')
  6335. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6336. return strnlen(buf, count);
  6337. }
  6338. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6339. static ssize_t dump_event_log(struct device *d,
  6340. struct device_attribute *attr,
  6341. const char *buf, size_t count)
  6342. {
  6343. char *p = (char *)buf;
  6344. if (p[0] == '1')
  6345. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6346. return strnlen(buf, count);
  6347. }
  6348. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6349. /*****************************************************************************
  6350. *
  6351. * driver setup and tear down
  6352. *
  6353. *****************************************************************************/
  6354. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6355. {
  6356. priv->workqueue = create_workqueue(DRV_NAME);
  6357. init_waitqueue_head(&priv->wait_command_queue);
  6358. INIT_WORK(&priv->up, iwl3945_bg_up);
  6359. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6360. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6361. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6362. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6363. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6364. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6365. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6366. INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
  6367. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6368. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6369. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6370. iwl3945_hw_setup_deferred_work(priv);
  6371. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6372. iwl3945_irq_tasklet, (unsigned long)priv);
  6373. }
  6374. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6375. {
  6376. iwl3945_hw_cancel_deferred_work(priv);
  6377. cancel_delayed_work_sync(&priv->init_alive_start);
  6378. cancel_delayed_work(&priv->scan_check);
  6379. cancel_delayed_work(&priv->alive_start);
  6380. cancel_work_sync(&priv->beacon_update);
  6381. }
  6382. static struct attribute *iwl3945_sysfs_entries[] = {
  6383. &dev_attr_antenna.attr,
  6384. &dev_attr_channels.attr,
  6385. &dev_attr_dump_errors.attr,
  6386. &dev_attr_dump_events.attr,
  6387. &dev_attr_flags.attr,
  6388. &dev_attr_filter_flags.attr,
  6389. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6390. &dev_attr_measurement.attr,
  6391. #endif
  6392. &dev_attr_power_level.attr,
  6393. &dev_attr_retry_rate.attr,
  6394. &dev_attr_statistics.attr,
  6395. &dev_attr_status.attr,
  6396. &dev_attr_temperature.attr,
  6397. &dev_attr_tx_power.attr,
  6398. NULL
  6399. };
  6400. static struct attribute_group iwl3945_attribute_group = {
  6401. .name = NULL, /* put in device directory */
  6402. .attrs = iwl3945_sysfs_entries,
  6403. };
  6404. static struct ieee80211_ops iwl3945_hw_ops = {
  6405. .tx = iwl3945_mac_tx,
  6406. .start = iwl3945_mac_start,
  6407. .stop = iwl3945_mac_stop,
  6408. .add_interface = iwl3945_mac_add_interface,
  6409. .remove_interface = iwl3945_mac_remove_interface,
  6410. .config = iwl3945_mac_config,
  6411. .config_interface = iwl3945_mac_config_interface,
  6412. .configure_filter = iwl3945_configure_filter,
  6413. .set_key = iwl3945_mac_set_key,
  6414. .get_stats = iwl3945_mac_get_stats,
  6415. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6416. .conf_tx = iwl3945_mac_conf_tx,
  6417. .reset_tsf = iwl3945_mac_reset_tsf,
  6418. .bss_info_changed = iwl3945_bss_info_changed,
  6419. .hw_scan = iwl3945_mac_hw_scan
  6420. };
  6421. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6422. {
  6423. int err = 0;
  6424. struct iwl3945_priv *priv;
  6425. struct ieee80211_hw *hw;
  6426. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6427. unsigned long flags;
  6428. /* Disabling hardware scan means that mac80211 will perform scans
  6429. * "the hard way", rather than using device's scan. */
  6430. if (iwl3945_param_disable_hw_scan) {
  6431. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6432. iwl3945_hw_ops.hw_scan = NULL;
  6433. }
  6434. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6435. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6436. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6437. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6438. err = -EINVAL;
  6439. goto out;
  6440. }
  6441. /* mac80211 allocates memory for this device instance, including
  6442. * space for this driver's private structure */
  6443. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6444. if (hw == NULL) {
  6445. IWL_ERROR("Can not allocate network device\n");
  6446. err = -ENOMEM;
  6447. goto out;
  6448. }
  6449. SET_IEEE80211_DEV(hw, &pdev->dev);
  6450. hw->rate_control_algorithm = "iwl-3945-rs";
  6451. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6452. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6453. priv = hw->priv;
  6454. priv->hw = hw;
  6455. priv->pci_dev = pdev;
  6456. priv->cfg = cfg;
  6457. /* Select antenna (may be helpful if only one antenna is connected) */
  6458. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6459. #ifdef CONFIG_IWL3945_DEBUG
  6460. iwl3945_debug_level = iwl3945_param_debug;
  6461. atomic_set(&priv->restrict_refcnt, 0);
  6462. #endif
  6463. priv->retry_rate = 1;
  6464. priv->ibss_beacon = NULL;
  6465. /* Tell mac80211 our characteristics */
  6466. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6467. IEEE80211_HW_NOISE_DBM;
  6468. hw->wiphy->interface_modes =
  6469. BIT(NL80211_IFTYPE_AP) |
  6470. BIT(NL80211_IFTYPE_STATION) |
  6471. BIT(NL80211_IFTYPE_ADHOC);
  6472. /* 4 EDCA QOS priorities */
  6473. hw->queues = 4;
  6474. spin_lock_init(&priv->lock);
  6475. spin_lock_init(&priv->power_data.lock);
  6476. spin_lock_init(&priv->sta_lock);
  6477. spin_lock_init(&priv->hcmd_lock);
  6478. INIT_LIST_HEAD(&priv->free_frames);
  6479. mutex_init(&priv->mutex);
  6480. if (pci_enable_device(pdev)) {
  6481. err = -ENODEV;
  6482. goto out_ieee80211_free_hw;
  6483. }
  6484. pci_set_master(pdev);
  6485. /* Clear the driver's (not device's) station table */
  6486. iwl3945_clear_stations_table(priv);
  6487. priv->data_retry_limit = -1;
  6488. priv->ieee_channels = NULL;
  6489. priv->ieee_rates = NULL;
  6490. priv->band = IEEE80211_BAND_2GHZ;
  6491. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6492. if (!err)
  6493. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6494. if (err) {
  6495. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6496. goto out_pci_disable_device;
  6497. }
  6498. pci_set_drvdata(pdev, priv);
  6499. err = pci_request_regions(pdev, DRV_NAME);
  6500. if (err)
  6501. goto out_pci_disable_device;
  6502. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6503. * PCI Tx retries from interfering with C3 CPU state */
  6504. pci_write_config_byte(pdev, 0x41, 0x00);
  6505. priv->hw_base = pci_iomap(pdev, 0, 0);
  6506. if (!priv->hw_base) {
  6507. err = -ENODEV;
  6508. goto out_pci_release_regions;
  6509. }
  6510. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6511. (unsigned long long) pci_resource_len(pdev, 0));
  6512. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6513. /* Initialize module parameter values here */
  6514. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6515. if (iwl3945_param_disable) {
  6516. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6517. IWL_DEBUG_INFO("Radio disabled.\n");
  6518. }
  6519. priv->iw_mode = NL80211_IFTYPE_STATION;
  6520. printk(KERN_INFO DRV_NAME
  6521. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6522. /* Device-specific setup */
  6523. if (iwl3945_hw_set_hw_setting(priv)) {
  6524. IWL_ERROR("failed to set hw settings\n");
  6525. goto out_iounmap;
  6526. }
  6527. if (iwl3945_param_qos_enable)
  6528. priv->qos_data.qos_enable = 1;
  6529. iwl3945_reset_qos(priv);
  6530. priv->qos_data.qos_active = 0;
  6531. priv->qos_data.qos_cap.val = 0;
  6532. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6533. iwl3945_setup_deferred_work(priv);
  6534. iwl3945_setup_rx_handlers(priv);
  6535. priv->rates_mask = IWL_RATES_MASK;
  6536. /* If power management is turned on, default to AC mode */
  6537. priv->power_mode = IWL_POWER_AC;
  6538. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6539. spin_lock_irqsave(&priv->lock, flags);
  6540. iwl3945_disable_interrupts(priv);
  6541. spin_unlock_irqrestore(&priv->lock, flags);
  6542. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6543. if (err) {
  6544. IWL_ERROR("failed to create sysfs device attributes\n");
  6545. goto out_release_irq;
  6546. }
  6547. /* nic init */
  6548. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6549. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6550. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6551. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6552. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6553. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6554. if (err < 0) {
  6555. IWL_DEBUG_INFO("Failed to init the card\n");
  6556. goto out_remove_sysfs;
  6557. }
  6558. /* Read the EEPROM */
  6559. err = iwl3945_eeprom_init(priv);
  6560. if (err) {
  6561. IWL_ERROR("Unable to init EEPROM\n");
  6562. goto out_remove_sysfs;
  6563. }
  6564. /* MAC Address location in EEPROM same for 3945/4965 */
  6565. get_eeprom_mac(priv, priv->mac_addr);
  6566. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6567. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6568. err = iwl3945_init_channel_map(priv);
  6569. if (err) {
  6570. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6571. goto out_remove_sysfs;
  6572. }
  6573. err = iwl3945_init_geos(priv);
  6574. if (err) {
  6575. IWL_ERROR("initializing geos failed: %d\n", err);
  6576. goto out_free_channel_map;
  6577. }
  6578. err = ieee80211_register_hw(priv->hw);
  6579. if (err) {
  6580. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6581. goto out_free_geos;
  6582. }
  6583. priv->hw->conf.beacon_int = 100;
  6584. priv->mac80211_registered = 1;
  6585. pci_save_state(pdev);
  6586. pci_disable_device(pdev);
  6587. err = iwl3945_rfkill_init(priv);
  6588. if (err)
  6589. IWL_ERROR("Unable to initialize RFKILL system. "
  6590. "Ignoring error: %d\n", err);
  6591. return 0;
  6592. out_free_geos:
  6593. iwl3945_free_geos(priv);
  6594. out_free_channel_map:
  6595. iwl3945_free_channel_map(priv);
  6596. out_remove_sysfs:
  6597. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6598. out_release_irq:
  6599. destroy_workqueue(priv->workqueue);
  6600. priv->workqueue = NULL;
  6601. iwl3945_unset_hw_setting(priv);
  6602. out_iounmap:
  6603. pci_iounmap(pdev, priv->hw_base);
  6604. out_pci_release_regions:
  6605. pci_release_regions(pdev);
  6606. out_pci_disable_device:
  6607. pci_disable_device(pdev);
  6608. pci_set_drvdata(pdev, NULL);
  6609. out_ieee80211_free_hw:
  6610. ieee80211_free_hw(priv->hw);
  6611. out:
  6612. return err;
  6613. }
  6614. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6615. {
  6616. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6617. unsigned long flags;
  6618. if (!priv)
  6619. return;
  6620. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6621. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6622. iwl3945_down(priv);
  6623. /* make sure we flush any pending irq or
  6624. * tasklet for the driver
  6625. */
  6626. spin_lock_irqsave(&priv->lock, flags);
  6627. iwl3945_disable_interrupts(priv);
  6628. spin_unlock_irqrestore(&priv->lock, flags);
  6629. iwl_synchronize_irq(priv);
  6630. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6631. iwl3945_rfkill_unregister(priv);
  6632. iwl3945_dealloc_ucode_pci(priv);
  6633. if (priv->rxq.bd)
  6634. iwl3945_rx_queue_free(priv, &priv->rxq);
  6635. iwl3945_hw_txq_ctx_free(priv);
  6636. iwl3945_unset_hw_setting(priv);
  6637. iwl3945_clear_stations_table(priv);
  6638. if (priv->mac80211_registered)
  6639. ieee80211_unregister_hw(priv->hw);
  6640. /*netif_stop_queue(dev); */
  6641. flush_workqueue(priv->workqueue);
  6642. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6643. * priv->workqueue... so we can't take down the workqueue
  6644. * until now... */
  6645. destroy_workqueue(priv->workqueue);
  6646. priv->workqueue = NULL;
  6647. pci_iounmap(pdev, priv->hw_base);
  6648. pci_release_regions(pdev);
  6649. pci_disable_device(pdev);
  6650. pci_set_drvdata(pdev, NULL);
  6651. iwl3945_free_channel_map(priv);
  6652. iwl3945_free_geos(priv);
  6653. kfree(priv->scan);
  6654. if (priv->ibss_beacon)
  6655. dev_kfree_skb(priv->ibss_beacon);
  6656. ieee80211_free_hw(priv->hw);
  6657. }
  6658. #ifdef CONFIG_PM
  6659. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6660. {
  6661. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6662. if (priv->is_open) {
  6663. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6664. iwl3945_mac_stop(priv->hw);
  6665. priv->is_open = 1;
  6666. }
  6667. pci_set_power_state(pdev, PCI_D3hot);
  6668. return 0;
  6669. }
  6670. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6671. {
  6672. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6673. pci_set_power_state(pdev, PCI_D0);
  6674. if (priv->is_open)
  6675. iwl3945_mac_start(priv->hw);
  6676. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6677. return 0;
  6678. }
  6679. #endif /* CONFIG_PM */
  6680. /*************** RFKILL FUNCTIONS **********/
  6681. #ifdef CONFIG_IWL3945_RFKILL
  6682. /* software rf-kill from user */
  6683. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6684. {
  6685. struct iwl3945_priv *priv = data;
  6686. int err = 0;
  6687. if (!priv->rfkill)
  6688. return 0;
  6689. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6690. return 0;
  6691. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6692. mutex_lock(&priv->mutex);
  6693. switch (state) {
  6694. case RFKILL_STATE_UNBLOCKED:
  6695. if (iwl3945_is_rfkill_hw(priv)) {
  6696. err = -EBUSY;
  6697. goto out_unlock;
  6698. }
  6699. iwl3945_radio_kill_sw(priv, 0);
  6700. break;
  6701. case RFKILL_STATE_SOFT_BLOCKED:
  6702. iwl3945_radio_kill_sw(priv, 1);
  6703. break;
  6704. default:
  6705. IWL_WARNING("we received unexpected RFKILL state %d\n", state);
  6706. break;
  6707. }
  6708. out_unlock:
  6709. mutex_unlock(&priv->mutex);
  6710. return err;
  6711. }
  6712. int iwl3945_rfkill_init(struct iwl3945_priv *priv)
  6713. {
  6714. struct device *device = wiphy_dev(priv->hw->wiphy);
  6715. int ret = 0;
  6716. BUG_ON(device == NULL);
  6717. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6718. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6719. if (!priv->rfkill) {
  6720. IWL_ERROR("Unable to allocate rfkill device.\n");
  6721. ret = -ENOMEM;
  6722. goto error;
  6723. }
  6724. priv->rfkill->name = priv->cfg->name;
  6725. priv->rfkill->data = priv;
  6726. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6727. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6728. priv->rfkill->user_claim_unsupported = 1;
  6729. priv->rfkill->dev.class->suspend = NULL;
  6730. priv->rfkill->dev.class->resume = NULL;
  6731. ret = rfkill_register(priv->rfkill);
  6732. if (ret) {
  6733. IWL_ERROR("Unable to register rfkill: %d\n", ret);
  6734. goto freed_rfkill;
  6735. }
  6736. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6737. return ret;
  6738. freed_rfkill:
  6739. if (priv->rfkill != NULL)
  6740. rfkill_free(priv->rfkill);
  6741. priv->rfkill = NULL;
  6742. error:
  6743. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6744. return ret;
  6745. }
  6746. void iwl3945_rfkill_unregister(struct iwl3945_priv *priv)
  6747. {
  6748. if (priv->rfkill)
  6749. rfkill_unregister(priv->rfkill);
  6750. priv->rfkill = NULL;
  6751. }
  6752. /* set rf-kill to the right state. */
  6753. void iwl3945_rfkill_set_hw_state(struct iwl3945_priv *priv)
  6754. {
  6755. if (!priv->rfkill)
  6756. return;
  6757. if (iwl3945_is_rfkill_hw(priv)) {
  6758. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6759. return;
  6760. }
  6761. if (!iwl3945_is_rfkill_sw(priv))
  6762. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6763. else
  6764. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6765. }
  6766. #endif
  6767. /*****************************************************************************
  6768. *
  6769. * driver and module entry point
  6770. *
  6771. *****************************************************************************/
  6772. static struct pci_driver iwl3945_driver = {
  6773. .name = DRV_NAME,
  6774. .id_table = iwl3945_hw_card_ids,
  6775. .probe = iwl3945_pci_probe,
  6776. .remove = __devexit_p(iwl3945_pci_remove),
  6777. #ifdef CONFIG_PM
  6778. .suspend = iwl3945_pci_suspend,
  6779. .resume = iwl3945_pci_resume,
  6780. #endif
  6781. };
  6782. static int __init iwl3945_init(void)
  6783. {
  6784. int ret;
  6785. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6786. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6787. ret = iwl3945_rate_control_register();
  6788. if (ret) {
  6789. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6790. return ret;
  6791. }
  6792. ret = pci_register_driver(&iwl3945_driver);
  6793. if (ret) {
  6794. IWL_ERROR("Unable to initialize PCI module\n");
  6795. goto error_register;
  6796. }
  6797. #ifdef CONFIG_IWL3945_DEBUG
  6798. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6799. if (ret) {
  6800. IWL_ERROR("Unable to create driver sysfs file\n");
  6801. goto error_debug;
  6802. }
  6803. #endif
  6804. return ret;
  6805. #ifdef CONFIG_IWL3945_DEBUG
  6806. error_debug:
  6807. pci_unregister_driver(&iwl3945_driver);
  6808. #endif
  6809. error_register:
  6810. iwl3945_rate_control_unregister();
  6811. return ret;
  6812. }
  6813. static void __exit iwl3945_exit(void)
  6814. {
  6815. #ifdef CONFIG_IWL3945_DEBUG
  6816. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6817. #endif
  6818. pci_unregister_driver(&iwl3945_driver);
  6819. iwl3945_rate_control_unregister();
  6820. }
  6821. MODULE_FIRMWARE("iwlwifi-3945" IWL3945_UCODE_API ".ucode");
  6822. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6823. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6824. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6825. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6826. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6827. MODULE_PARM_DESC(hwcrypto,
  6828. "using hardware crypto engine (default 0 [software])\n");
  6829. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6830. MODULE_PARM_DESC(debug, "debug output mask");
  6831. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6832. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6833. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6834. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6835. /* QoS */
  6836. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6837. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6838. module_exit(iwl3945_exit);
  6839. module_init(iwl3945_init);