Kconfig 29 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. def_bool n
  8. config FPU
  9. def_bool n
  10. config RWSEM_GENERIC_SPINLOCK
  11. def_bool y
  12. config RWSEM_XCHGADD_ALGORITHM
  13. def_bool n
  14. config BLACKFIN
  15. def_bool y
  16. select HAVE_FUNCTION_GRAPH_TRACER
  17. select HAVE_FUNCTION_TRACER
  18. select HAVE_IDE
  19. select HAVE_KERNEL_GZIP
  20. select HAVE_KERNEL_BZIP2
  21. select HAVE_KERNEL_LZMA
  22. select HAVE_OPROFILE
  23. select ARCH_WANT_OPTIONAL_GPIOLIB
  24. config GENERIC_BUG
  25. def_bool y
  26. depends on BUG
  27. config ZONE_DMA
  28. def_bool y
  29. config GENERIC_FIND_NEXT_BIT
  30. def_bool y
  31. config GENERIC_HWEIGHT
  32. def_bool y
  33. config GENERIC_HARDIRQS
  34. def_bool y
  35. config GENERIC_IRQ_PROBE
  36. def_bool y
  37. config GENERIC_GPIO
  38. def_bool y
  39. config FORCE_MAX_ZONEORDER
  40. int
  41. default "14"
  42. config GENERIC_CALIBRATE_DELAY
  43. def_bool y
  44. config LOCKDEP_SUPPORT
  45. def_bool y
  46. config STACKTRACE_SUPPORT
  47. def_bool y
  48. config TRACE_IRQFLAGS_SUPPORT
  49. def_bool y
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. source "kernel/Kconfig.freezer"
  53. menu "Blackfin Processor Options"
  54. comment "Processor and Board Settings"
  55. choice
  56. prompt "CPU"
  57. default BF533
  58. config BF512
  59. bool "BF512"
  60. help
  61. BF512 Processor Support.
  62. config BF514
  63. bool "BF514"
  64. help
  65. BF514 Processor Support.
  66. config BF516
  67. bool "BF516"
  68. help
  69. BF516 Processor Support.
  70. config BF518
  71. bool "BF518"
  72. help
  73. BF518 Processor Support.
  74. config BF522
  75. bool "BF522"
  76. help
  77. BF522 Processor Support.
  78. config BF523
  79. bool "BF523"
  80. help
  81. BF523 Processor Support.
  82. config BF524
  83. bool "BF524"
  84. help
  85. BF524 Processor Support.
  86. config BF525
  87. bool "BF525"
  88. help
  89. BF525 Processor Support.
  90. config BF526
  91. bool "BF526"
  92. help
  93. BF526 Processor Support.
  94. config BF527
  95. bool "BF527"
  96. help
  97. BF527 Processor Support.
  98. config BF531
  99. bool "BF531"
  100. help
  101. BF531 Processor Support.
  102. config BF532
  103. bool "BF532"
  104. help
  105. BF532 Processor Support.
  106. config BF533
  107. bool "BF533"
  108. help
  109. BF533 Processor Support.
  110. config BF534
  111. bool "BF534"
  112. help
  113. BF534 Processor Support.
  114. config BF536
  115. bool "BF536"
  116. help
  117. BF536 Processor Support.
  118. config BF537
  119. bool "BF537"
  120. help
  121. BF537 Processor Support.
  122. config BF538
  123. bool "BF538"
  124. help
  125. BF538 Processor Support.
  126. config BF539
  127. bool "BF539"
  128. help
  129. BF539 Processor Support.
  130. config BF542
  131. bool "BF542"
  132. help
  133. BF542 Processor Support.
  134. config BF542M
  135. bool "BF542m"
  136. help
  137. BF542 Processor Support.
  138. config BF544
  139. bool "BF544"
  140. help
  141. BF544 Processor Support.
  142. config BF544M
  143. bool "BF544m"
  144. help
  145. BF544 Processor Support.
  146. config BF547
  147. bool "BF547"
  148. help
  149. BF547 Processor Support.
  150. config BF547M
  151. bool "BF547m"
  152. help
  153. BF547 Processor Support.
  154. config BF548
  155. bool "BF548"
  156. help
  157. BF548 Processor Support.
  158. config BF548M
  159. bool "BF548m"
  160. help
  161. BF548 Processor Support.
  162. config BF549
  163. bool "BF549"
  164. help
  165. BF549 Processor Support.
  166. config BF549M
  167. bool "BF549m"
  168. help
  169. BF549 Processor Support.
  170. config BF561
  171. bool "BF561"
  172. help
  173. BF561 Processor Support.
  174. endchoice
  175. config SMP
  176. depends on BF561
  177. select GENERIC_TIME
  178. bool "Symmetric multi-processing support"
  179. ---help---
  180. This enables support for systems with more than one CPU,
  181. like the dual core BF561. If you have a system with only one
  182. CPU, say N. If you have a system with more than one CPU, say Y.
  183. If you don't know what to do here, say N.
  184. config NR_CPUS
  185. int
  186. depends on SMP
  187. default 2 if BF561
  188. config IRQ_PER_CPU
  189. bool
  190. depends on SMP
  191. default y
  192. config BF_REV_MIN
  193. int
  194. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  195. default 2 if (BF537 || BF536 || BF534)
  196. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  197. default 4 if (BF538 || BF539)
  198. config BF_REV_MAX
  199. int
  200. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  201. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  202. default 5 if (BF561 || BF538 || BF539)
  203. default 6 if (BF533 || BF532 || BF531)
  204. choice
  205. prompt "Silicon Rev"
  206. default BF_REV_0_0 if (BF51x || BF52x)
  207. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  208. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  209. config BF_REV_0_0
  210. bool "0.0"
  211. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  212. config BF_REV_0_1
  213. bool "0.1"
  214. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  215. config BF_REV_0_2
  216. bool "0.2"
  217. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  218. config BF_REV_0_3
  219. bool "0.3"
  220. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  221. config BF_REV_0_4
  222. bool "0.4"
  223. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  224. config BF_REV_0_5
  225. bool "0.5"
  226. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  227. config BF_REV_0_6
  228. bool "0.6"
  229. depends on (BF533 || BF532 || BF531)
  230. config BF_REV_ANY
  231. bool "any"
  232. config BF_REV_NONE
  233. bool "none"
  234. endchoice
  235. config BF51x
  236. bool
  237. depends on (BF512 || BF514 || BF516 || BF518)
  238. default y
  239. config BF52x
  240. bool
  241. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  242. default y
  243. config BF53x
  244. bool
  245. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  246. default y
  247. config BF54xM
  248. bool
  249. depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
  250. default y
  251. config BF54x
  252. bool
  253. depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
  254. default y
  255. config MEM_GENERIC_BOARD
  256. bool
  257. depends on GENERIC_BOARD
  258. default y
  259. config MEM_MT48LC64M4A2FB_7E
  260. bool
  261. depends on (BFIN533_STAMP)
  262. default y
  263. config MEM_MT48LC16M16A2TG_75
  264. bool
  265. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  266. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  267. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  268. default y
  269. config MEM_MT48LC32M8A2_75
  270. bool
  271. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  272. default y
  273. config MEM_MT48LC8M32B2B5_7
  274. bool
  275. depends on (BFIN561_BLUETECHNIX_CM)
  276. default y
  277. config MEM_MT48LC32M16A2TG_75
  278. bool
  279. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
  280. default y
  281. config MEM_MT48LC32M8A2_75
  282. bool
  283. depends on (BFIN518F_EZBRD)
  284. default y
  285. source "arch/blackfin/mach-bf518/Kconfig"
  286. source "arch/blackfin/mach-bf527/Kconfig"
  287. source "arch/blackfin/mach-bf533/Kconfig"
  288. source "arch/blackfin/mach-bf561/Kconfig"
  289. source "arch/blackfin/mach-bf537/Kconfig"
  290. source "arch/blackfin/mach-bf538/Kconfig"
  291. source "arch/blackfin/mach-bf548/Kconfig"
  292. menu "Board customizations"
  293. config CMDLINE_BOOL
  294. bool "Default bootloader kernel arguments"
  295. config CMDLINE
  296. string "Initial kernel command string"
  297. depends on CMDLINE_BOOL
  298. default "console=ttyBF0,57600"
  299. help
  300. If you don't have a boot loader capable of passing a command line string
  301. to the kernel, you may specify one here. As a minimum, you should specify
  302. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  303. config BOOT_LOAD
  304. hex "Kernel load address for booting"
  305. default "0x1000"
  306. range 0x1000 0x20000000
  307. help
  308. This option allows you to set the load address of the kernel.
  309. This can be useful if you are on a board which has a small amount
  310. of memory or you wish to reserve some memory at the beginning of
  311. the address space.
  312. Note that you need to keep this value above 4k (0x1000) as this
  313. memory region is used to capture NULL pointer references as well
  314. as some core kernel functions.
  315. config ROM_BASE
  316. hex "Kernel ROM Base"
  317. depends on ROMKERNEL
  318. default "0x20040000"
  319. range 0x20000000 0x20400000 if !(BF54x || BF561)
  320. range 0x20000000 0x30000000 if (BF54x || BF561)
  321. help
  322. comment "Clock/PLL Setup"
  323. config CLKIN_HZ
  324. int "Frequency of the crystal on the board in Hz"
  325. default "10000000" if BFIN532_IP0X
  326. default "11059200" if BFIN533_STAMP
  327. default "24576000" if PNAV10
  328. default "25000000" # most people use this
  329. default "27000000" if BFIN533_EZKIT
  330. default "30000000" if BFIN561_EZKIT
  331. help
  332. The frequency of CLKIN crystal oscillator on the board in Hz.
  333. Warning: This value should match the crystal on the board. Otherwise,
  334. peripherals won't work properly.
  335. config BFIN_KERNEL_CLOCK
  336. bool "Re-program Clocks while Kernel boots?"
  337. default n
  338. help
  339. This option decides if kernel clocks are re-programed from the
  340. bootloader settings. If the clocks are not set, the SDRAM settings
  341. are also not changed, and the Bootloader does 100% of the hardware
  342. configuration.
  343. config PLL_BYPASS
  344. bool "Bypass PLL"
  345. depends on BFIN_KERNEL_CLOCK
  346. default n
  347. config CLKIN_HALF
  348. bool "Half Clock In"
  349. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  350. default n
  351. help
  352. If this is set the clock will be divided by 2, before it goes to the PLL.
  353. config VCO_MULT
  354. int "VCO Multiplier"
  355. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  356. range 1 64
  357. default "22" if BFIN533_EZKIT
  358. default "45" if BFIN533_STAMP
  359. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  360. default "22" if BFIN533_BLUETECHNIX_CM
  361. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  362. default "20" if BFIN561_EZKIT
  363. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  364. help
  365. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  366. PLL Frequency = (Crystal Frequency) * (this setting)
  367. choice
  368. prompt "Core Clock Divider"
  369. depends on BFIN_KERNEL_CLOCK
  370. default CCLK_DIV_1
  371. help
  372. This sets the frequency of the core. It can be 1, 2, 4 or 8
  373. Core Frequency = (PLL frequency) / (this setting)
  374. config CCLK_DIV_1
  375. bool "1"
  376. config CCLK_DIV_2
  377. bool "2"
  378. config CCLK_DIV_4
  379. bool "4"
  380. config CCLK_DIV_8
  381. bool "8"
  382. endchoice
  383. config SCLK_DIV
  384. int "System Clock Divider"
  385. depends on BFIN_KERNEL_CLOCK
  386. range 1 15
  387. default 5
  388. help
  389. This sets the frequency of the system clock (including SDRAM or DDR).
  390. This can be between 1 and 15
  391. System Clock = (PLL frequency) / (this setting)
  392. choice
  393. prompt "DDR SDRAM Chip Type"
  394. depends on BFIN_KERNEL_CLOCK
  395. depends on BF54x
  396. default MEM_MT46V32M16_5B
  397. config MEM_MT46V32M16_6T
  398. bool "MT46V32M16_6T"
  399. config MEM_MT46V32M16_5B
  400. bool "MT46V32M16_5B"
  401. endchoice
  402. choice
  403. prompt "DDR/SDRAM Timing"
  404. depends on BFIN_KERNEL_CLOCK
  405. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  406. help
  407. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  408. The calculated SDRAM timing parameters may not be 100%
  409. accurate - This option is therefore marked experimental.
  410. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  411. bool "Calculate Timings (EXPERIMENTAL)"
  412. depends on EXPERIMENTAL
  413. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  414. bool "Provide accurate Timings based on target SCLK"
  415. help
  416. Please consult the Blackfin Hardware Reference Manuals as well
  417. as the memory device datasheet.
  418. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  419. endchoice
  420. menu "Memory Init Control"
  421. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  422. config MEM_DDRCTL0
  423. depends on BF54x
  424. hex "DDRCTL0"
  425. default 0x0
  426. config MEM_DDRCTL1
  427. depends on BF54x
  428. hex "DDRCTL1"
  429. default 0x0
  430. config MEM_DDRCTL2
  431. depends on BF54x
  432. hex "DDRCTL2"
  433. default 0x0
  434. config MEM_EBIU_DDRQUE
  435. depends on BF54x
  436. hex "DDRQUE"
  437. default 0x0
  438. config MEM_SDRRC
  439. depends on !BF54x
  440. hex "SDRRC"
  441. default 0x0
  442. config MEM_SDGCTL
  443. depends on !BF54x
  444. hex "SDGCTL"
  445. default 0x0
  446. endmenu
  447. #
  448. # Max & Min Speeds for various Chips
  449. #
  450. config MAX_VCO_HZ
  451. int
  452. default 400000000 if BF512
  453. default 400000000 if BF514
  454. default 400000000 if BF516
  455. default 400000000 if BF518
  456. default 600000000 if BF522
  457. default 400000000 if BF523
  458. default 400000000 if BF524
  459. default 600000000 if BF525
  460. default 400000000 if BF526
  461. default 600000000 if BF527
  462. default 400000000 if BF531
  463. default 400000000 if BF532
  464. default 750000000 if BF533
  465. default 500000000 if BF534
  466. default 400000000 if BF536
  467. default 600000000 if BF537
  468. default 533333333 if BF538
  469. default 533333333 if BF539
  470. default 600000000 if BF542
  471. default 533333333 if BF544
  472. default 600000000 if BF547
  473. default 600000000 if BF548
  474. default 533333333 if BF549
  475. default 600000000 if BF561
  476. config MIN_VCO_HZ
  477. int
  478. default 50000000
  479. config MAX_SCLK_HZ
  480. int
  481. default 133333333
  482. config MIN_SCLK_HZ
  483. int
  484. default 27000000
  485. comment "Kernel Timer/Scheduler"
  486. source kernel/Kconfig.hz
  487. config GENERIC_TIME
  488. bool "Generic time"
  489. default y
  490. config GENERIC_CLOCKEVENTS
  491. bool "Generic clock events"
  492. depends on GENERIC_TIME
  493. default y
  494. choice
  495. prompt "Kernel Tick Source"
  496. depends on GENERIC_CLOCKEVENTS
  497. default TICKSOURCE_CORETMR
  498. config TICKSOURCE_GPTMR0
  499. bool "Gptimer0 (SCLK domain)"
  500. select BFIN_GPTIMERS
  501. config TICKSOURCE_CORETMR
  502. bool "Core timer (CCLK domain)"
  503. endchoice
  504. config CYCLES_CLOCKSOURCE
  505. bool "Use 'CYCLES' as a clocksource"
  506. depends on GENERIC_CLOCKEVENTS
  507. depends on !BFIN_SCRATCH_REG_CYCLES
  508. depends on !SMP
  509. help
  510. If you say Y here, you will enable support for using the 'cycles'
  511. registers as a clock source. Doing so means you will be unable to
  512. safely write to the 'cycles' register during runtime. You will
  513. still be able to read it (such as for performance monitoring), but
  514. writing the registers will most likely crash the kernel.
  515. config GPTMR0_CLOCKSOURCE
  516. bool "Use GPTimer0 as a clocksource (higher rating)"
  517. depends on GENERIC_CLOCKEVENTS
  518. depends on !TICKSOURCE_GPTMR0
  519. source kernel/time/Kconfig
  520. comment "Misc"
  521. choice
  522. prompt "Blackfin Exception Scratch Register"
  523. default BFIN_SCRATCH_REG_RETN
  524. help
  525. Select the resource to reserve for the Exception handler:
  526. - RETN: Non-Maskable Interrupt (NMI)
  527. - RETE: Exception Return (JTAG/ICE)
  528. - CYCLES: Performance counter
  529. If you are unsure, please select "RETN".
  530. config BFIN_SCRATCH_REG_RETN
  531. bool "RETN"
  532. help
  533. Use the RETN register in the Blackfin exception handler
  534. as a stack scratch register. This means you cannot
  535. safely use NMI on the Blackfin while running Linux, but
  536. you can debug the system with a JTAG ICE and use the
  537. CYCLES performance registers.
  538. If you are unsure, please select "RETN".
  539. config BFIN_SCRATCH_REG_RETE
  540. bool "RETE"
  541. help
  542. Use the RETE register in the Blackfin exception handler
  543. as a stack scratch register. This means you cannot
  544. safely use a JTAG ICE while debugging a Blackfin board,
  545. but you can safely use the CYCLES performance registers
  546. and the NMI.
  547. If you are unsure, please select "RETN".
  548. config BFIN_SCRATCH_REG_CYCLES
  549. bool "CYCLES"
  550. help
  551. Use the CYCLES register in the Blackfin exception handler
  552. as a stack scratch register. This means you cannot
  553. safely use the CYCLES performance registers on a Blackfin
  554. board at anytime, but you can debug the system with a JTAG
  555. ICE and use the NMI.
  556. If you are unsure, please select "RETN".
  557. endchoice
  558. endmenu
  559. menu "Blackfin Kernel Optimizations"
  560. depends on !SMP
  561. comment "Memory Optimizations"
  562. config I_ENTRY_L1
  563. bool "Locate interrupt entry code in L1 Memory"
  564. default y
  565. help
  566. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  567. into L1 instruction memory. (less latency)
  568. config EXCPT_IRQ_SYSC_L1
  569. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  570. default y
  571. help
  572. If enabled, the entire ASM lowlevel exception and interrupt entry code
  573. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  574. (less latency)
  575. config DO_IRQ_L1
  576. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  577. default y
  578. help
  579. If enabled, the frequently called do_irq dispatcher function is linked
  580. into L1 instruction memory. (less latency)
  581. config CORE_TIMER_IRQ_L1
  582. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  583. default y
  584. help
  585. If enabled, the frequently called timer_interrupt() function is linked
  586. into L1 instruction memory. (less latency)
  587. config IDLE_L1
  588. bool "Locate frequently idle function in L1 Memory"
  589. default y
  590. help
  591. If enabled, the frequently called idle function is linked
  592. into L1 instruction memory. (less latency)
  593. config SCHEDULE_L1
  594. bool "Locate kernel schedule function in L1 Memory"
  595. default y
  596. help
  597. If enabled, the frequently called kernel schedule is linked
  598. into L1 instruction memory. (less latency)
  599. config ARITHMETIC_OPS_L1
  600. bool "Locate kernel owned arithmetic functions in L1 Memory"
  601. default y
  602. help
  603. If enabled, arithmetic functions are linked
  604. into L1 instruction memory. (less latency)
  605. config ACCESS_OK_L1
  606. bool "Locate access_ok function in L1 Memory"
  607. default y
  608. help
  609. If enabled, the access_ok function is linked
  610. into L1 instruction memory. (less latency)
  611. config MEMSET_L1
  612. bool "Locate memset function in L1 Memory"
  613. default y
  614. help
  615. If enabled, the memset function is linked
  616. into L1 instruction memory. (less latency)
  617. config MEMCPY_L1
  618. bool "Locate memcpy function in L1 Memory"
  619. default y
  620. help
  621. If enabled, the memcpy function is linked
  622. into L1 instruction memory. (less latency)
  623. config SYS_BFIN_SPINLOCK_L1
  624. bool "Locate sys_bfin_spinlock function in L1 Memory"
  625. default y
  626. help
  627. If enabled, sys_bfin_spinlock function is linked
  628. into L1 instruction memory. (less latency)
  629. config IP_CHECKSUM_L1
  630. bool "Locate IP Checksum function in L1 Memory"
  631. default n
  632. help
  633. If enabled, the IP Checksum function is linked
  634. into L1 instruction memory. (less latency)
  635. config CACHELINE_ALIGNED_L1
  636. bool "Locate cacheline_aligned data to L1 Data Memory"
  637. default y if !BF54x
  638. default n if BF54x
  639. depends on !BF531
  640. help
  641. If enabled, cacheline_aligned data is linked
  642. into L1 data memory. (less latency)
  643. config SYSCALL_TAB_L1
  644. bool "Locate Syscall Table L1 Data Memory"
  645. default n
  646. depends on !BF531
  647. help
  648. If enabled, the Syscall LUT is linked
  649. into L1 data memory. (less latency)
  650. config CPLB_SWITCH_TAB_L1
  651. bool "Locate CPLB Switch Tables L1 Data Memory"
  652. default n
  653. depends on !BF531
  654. help
  655. If enabled, the CPLB Switch Tables are linked
  656. into L1 data memory. (less latency)
  657. config APP_STACK_L1
  658. bool "Support locating application stack in L1 Scratch Memory"
  659. default y
  660. help
  661. If enabled the application stack can be located in L1
  662. scratch memory (less latency).
  663. Currently only works with FLAT binaries.
  664. config EXCEPTION_L1_SCRATCH
  665. bool "Locate exception stack in L1 Scratch Memory"
  666. default n
  667. depends on !APP_STACK_L1
  668. help
  669. Whenever an exception occurs, use the L1 Scratch memory for
  670. stack storage. You cannot place the stacks of FLAT binaries
  671. in L1 when using this option.
  672. If you don't use L1 Scratch, then you should say Y here.
  673. comment "Speed Optimizations"
  674. config BFIN_INS_LOWOVERHEAD
  675. bool "ins[bwl] low overhead, higher interrupt latency"
  676. default y
  677. help
  678. Reads on the Blackfin are speculative. In Blackfin terms, this means
  679. they can be interrupted at any time (even after they have been issued
  680. on to the external bus), and re-issued after the interrupt occurs.
  681. For memory - this is not a big deal, since memory does not change if
  682. it sees a read.
  683. If a FIFO is sitting on the end of the read, it will see two reads,
  684. when the core only sees one since the FIFO receives both the read
  685. which is cancelled (and not delivered to the core) and the one which
  686. is re-issued (which is delivered to the core).
  687. To solve this, interrupts are turned off before reads occur to
  688. I/O space. This option controls which the overhead/latency of
  689. controlling interrupts during this time
  690. "n" turns interrupts off every read
  691. (higher overhead, but lower interrupt latency)
  692. "y" turns interrupts off every loop
  693. (low overhead, but longer interrupt latency)
  694. default behavior is to leave this set to on (type "Y"). If you are experiencing
  695. interrupt latency issues, it is safe and OK to turn this off.
  696. endmenu
  697. choice
  698. prompt "Kernel executes from"
  699. help
  700. Choose the memory type that the kernel will be running in.
  701. config RAMKERNEL
  702. bool "RAM"
  703. help
  704. The kernel will be resident in RAM when running.
  705. config ROMKERNEL
  706. bool "ROM"
  707. help
  708. The kernel will be resident in FLASH/ROM when running.
  709. endchoice
  710. source "mm/Kconfig"
  711. config BFIN_GPTIMERS
  712. tristate "Enable Blackfin General Purpose Timers API"
  713. default n
  714. help
  715. Enable support for the General Purpose Timers API. If you
  716. are unsure, say N.
  717. To compile this driver as a module, choose M here: the module
  718. will be called gptimers.
  719. choice
  720. prompt "Uncached DMA region"
  721. default DMA_UNCACHED_1M
  722. config DMA_UNCACHED_4M
  723. bool "Enable 4M DMA region"
  724. config DMA_UNCACHED_2M
  725. bool "Enable 2M DMA region"
  726. config DMA_UNCACHED_1M
  727. bool "Enable 1M DMA region"
  728. config DMA_UNCACHED_NONE
  729. bool "Disable DMA region"
  730. endchoice
  731. comment "Cache Support"
  732. config BFIN_ICACHE
  733. bool "Enable ICACHE"
  734. default y
  735. config BFIN_ICACHE_LOCK
  736. bool "Enable Instruction Cache Locking"
  737. depends on BFIN_ICACHE
  738. default n
  739. config BFIN_EXTMEM_ICACHEABLE
  740. bool "Enable ICACHE for external memory"
  741. depends on BFIN_ICACHE
  742. default y
  743. config BFIN_L2_ICACHEABLE
  744. bool "Enable ICACHE for L2 SRAM"
  745. depends on BFIN_ICACHE
  746. depends on BF54x || BF561
  747. default n
  748. config BFIN_DCACHE
  749. bool "Enable DCACHE"
  750. default y
  751. config BFIN_DCACHE_BANKA
  752. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  753. depends on BFIN_DCACHE && !BF531
  754. default n
  755. config BFIN_EXTMEM_DCACHEABLE
  756. bool "Enable DCACHE for external memory"
  757. depends on BFIN_DCACHE
  758. default y
  759. choice
  760. prompt "External memory DCACHE policy"
  761. depends on BFIN_EXTMEM_DCACHEABLE
  762. default BFIN_EXTMEM_WRITEBACK if !SMP
  763. default BFIN_EXTMEM_WRITETHROUGH if SMP
  764. config BFIN_EXTMEM_WRITEBACK
  765. bool "Write back"
  766. depends on !SMP
  767. help
  768. Write Back Policy:
  769. Cached data will be written back to SDRAM only when needed.
  770. This can give a nice increase in performance, but beware of
  771. broken drivers that do not properly invalidate/flush their
  772. cache.
  773. Write Through Policy:
  774. Cached data will always be written back to SDRAM when the
  775. cache is updated. This is a completely safe setting, but
  776. performance is worse than Write Back.
  777. If you are unsure of the options and you want to be safe,
  778. then go with Write Through.
  779. config BFIN_EXTMEM_WRITETHROUGH
  780. bool "Write through"
  781. help
  782. Write Back Policy:
  783. Cached data will be written back to SDRAM only when needed.
  784. This can give a nice increase in performance, but beware of
  785. broken drivers that do not properly invalidate/flush their
  786. cache.
  787. Write Through Policy:
  788. Cached data will always be written back to SDRAM when the
  789. cache is updated. This is a completely safe setting, but
  790. performance is worse than Write Back.
  791. If you are unsure of the options and you want to be safe,
  792. then go with Write Through.
  793. endchoice
  794. config BFIN_L2_DCACHEABLE
  795. bool "Enable DCACHE for L2 SRAM"
  796. depends on BFIN_DCACHE
  797. depends on BF54x || BF561
  798. default n
  799. choice
  800. prompt "L2 SRAM DCACHE policy"
  801. depends on BFIN_L2_DCACHEABLE
  802. default BFIN_L2_WRITEBACK
  803. config BFIN_L2_WRITEBACK
  804. bool "Write back"
  805. depends on !SMP
  806. config BFIN_L2_WRITETHROUGH
  807. bool "Write through"
  808. depends on !SMP
  809. endchoice
  810. comment "Memory Protection Unit"
  811. config MPU
  812. bool "Enable the memory protection unit (EXPERIMENTAL)"
  813. default n
  814. help
  815. Use the processor's MPU to protect applications from accessing
  816. memory they do not own. This comes at a performance penalty
  817. and is recommended only for debugging.
  818. comment "Asynchronous Memory Configuration"
  819. menu "EBIU_AMGCTL Global Control"
  820. config C_AMCKEN
  821. bool "Enable CLKOUT"
  822. default y
  823. config C_CDPRIO
  824. bool "DMA has priority over core for ext. accesses"
  825. default n
  826. config C_B0PEN
  827. depends on BF561
  828. bool "Bank 0 16 bit packing enable"
  829. default y
  830. config C_B1PEN
  831. depends on BF561
  832. bool "Bank 1 16 bit packing enable"
  833. default y
  834. config C_B2PEN
  835. depends on BF561
  836. bool "Bank 2 16 bit packing enable"
  837. default y
  838. config C_B3PEN
  839. depends on BF561
  840. bool "Bank 3 16 bit packing enable"
  841. default n
  842. choice
  843. prompt "Enable Asynchronous Memory Banks"
  844. default C_AMBEN_ALL
  845. config C_AMBEN
  846. bool "Disable All Banks"
  847. config C_AMBEN_B0
  848. bool "Enable Bank 0"
  849. config C_AMBEN_B0_B1
  850. bool "Enable Bank 0 & 1"
  851. config C_AMBEN_B0_B1_B2
  852. bool "Enable Bank 0 & 1 & 2"
  853. config C_AMBEN_ALL
  854. bool "Enable All Banks"
  855. endchoice
  856. endmenu
  857. menu "EBIU_AMBCTL Control"
  858. config BANK_0
  859. hex "Bank 0 (AMBCTL0.L)"
  860. default 0x7BB0
  861. help
  862. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  863. used to control the Asynchronous Memory Bank 0 settings.
  864. config BANK_1
  865. hex "Bank 1 (AMBCTL0.H)"
  866. default 0x7BB0
  867. default 0x5558 if BF54x
  868. help
  869. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  870. used to control the Asynchronous Memory Bank 1 settings.
  871. config BANK_2
  872. hex "Bank 2 (AMBCTL1.L)"
  873. default 0x7BB0
  874. help
  875. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  876. used to control the Asynchronous Memory Bank 2 settings.
  877. config BANK_3
  878. hex "Bank 3 (AMBCTL1.H)"
  879. default 0x99B3
  880. help
  881. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  882. used to control the Asynchronous Memory Bank 3 settings.
  883. endmenu
  884. config EBIU_MBSCTLVAL
  885. hex "EBIU Bank Select Control Register"
  886. depends on BF54x
  887. default 0
  888. config EBIU_MODEVAL
  889. hex "Flash Memory Mode Control Register"
  890. depends on BF54x
  891. default 1
  892. config EBIU_FCTLVAL
  893. hex "Flash Memory Bank Control Register"
  894. depends on BF54x
  895. default 6
  896. endmenu
  897. #############################################################################
  898. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  899. config PCI
  900. bool "PCI support"
  901. depends on BROKEN
  902. help
  903. Support for PCI bus.
  904. source "drivers/pci/Kconfig"
  905. config HOTPLUG
  906. bool "Support for hot-pluggable device"
  907. help
  908. Say Y here if you want to plug devices into your computer while
  909. the system is running, and be able to use them quickly. In many
  910. cases, the devices can likewise be unplugged at any time too.
  911. One well known example of this is PCMCIA- or PC-cards, credit-card
  912. size devices such as network cards, modems or hard drives which are
  913. plugged into slots found on all modern laptop computers. Another
  914. example, used on modern desktops as well as laptops, is USB.
  915. Enable HOTPLUG and build a modular kernel. Get agent software
  916. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  917. Then your kernel will automatically call out to a user mode "policy
  918. agent" (/sbin/hotplug) to load modules and set up software needed
  919. to use devices as you hotplug them.
  920. source "drivers/pcmcia/Kconfig"
  921. source "drivers/pci/hotplug/Kconfig"
  922. endmenu
  923. menu "Executable file formats"
  924. source "fs/Kconfig.binfmt"
  925. endmenu
  926. menu "Power management options"
  927. source "kernel/power/Kconfig"
  928. config ARCH_SUSPEND_POSSIBLE
  929. def_bool y
  930. depends on !SMP
  931. choice
  932. prompt "Standby Power Saving Mode"
  933. depends on PM
  934. default PM_BFIN_SLEEP_DEEPER
  935. config PM_BFIN_SLEEP_DEEPER
  936. bool "Sleep Deeper"
  937. help
  938. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  939. power dissipation by disabling the clock to the processor core (CCLK).
  940. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  941. to 0.85 V to provide the greatest power savings, while preserving the
  942. processor state.
  943. The PLL and system clock (SCLK) continue to operate at a very low
  944. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  945. the SDRAM is put into Self Refresh Mode. Typically an external event
  946. such as GPIO interrupt or RTC activity wakes up the processor.
  947. Various Peripherals such as UART, SPORT, PPI may not function as
  948. normal during Sleep Deeper, due to the reduced SCLK frequency.
  949. When in the sleep mode, system DMA access to L1 memory is not supported.
  950. If unsure, select "Sleep Deeper".
  951. config PM_BFIN_SLEEP
  952. bool "Sleep"
  953. help
  954. Sleep Mode (High Power Savings) - The sleep mode reduces power
  955. dissipation by disabling the clock to the processor core (CCLK).
  956. The PLL and system clock (SCLK), however, continue to operate in
  957. this mode. Typically an external event or RTC activity will wake
  958. up the processor. When in the sleep mode, system DMA access to L1
  959. memory is not supported.
  960. If unsure, select "Sleep Deeper".
  961. endchoice
  962. config PM_WAKEUP_BY_GPIO
  963. bool "Allow Wakeup from Standby by GPIO"
  964. depends on PM && !BF54x
  965. config PM_WAKEUP_GPIO_NUMBER
  966. int "GPIO number"
  967. range 0 47
  968. depends on PM_WAKEUP_BY_GPIO
  969. default 2
  970. choice
  971. prompt "GPIO Polarity"
  972. depends on PM_WAKEUP_BY_GPIO
  973. default PM_WAKEUP_GPIO_POLAR_H
  974. config PM_WAKEUP_GPIO_POLAR_H
  975. bool "Active High"
  976. config PM_WAKEUP_GPIO_POLAR_L
  977. bool "Active Low"
  978. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  979. bool "Falling EDGE"
  980. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  981. bool "Rising EDGE"
  982. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  983. bool "Both EDGE"
  984. endchoice
  985. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  986. depends on PM
  987. config PM_BFIN_WAKE_PH6
  988. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  989. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  990. default n
  991. help
  992. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  993. config PM_BFIN_WAKE_GP
  994. bool "Allow Wake-Up from GPIOs"
  995. depends on PM && BF54x
  996. default n
  997. help
  998. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  999. (all processors, except ADSP-BF549). This option sets
  1000. the general-purpose wake-up enable (GPWE) control bit to enable
  1001. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  1002. On ADSP-BF549 this option enables the the same functionality on the
  1003. /MRXON pin also PH7.
  1004. endmenu
  1005. menu "CPU Frequency scaling"
  1006. source "drivers/cpufreq/Kconfig"
  1007. config BFIN_CPU_FREQ
  1008. bool
  1009. depends on CPU_FREQ
  1010. select CPU_FREQ_TABLE
  1011. default y
  1012. config CPU_VOLTAGE
  1013. bool "CPU Voltage scaling"
  1014. depends on EXPERIMENTAL
  1015. depends on CPU_FREQ
  1016. default n
  1017. help
  1018. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1019. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1020. manuals. There is a theoretical risk that during VDDINT transitions
  1021. the PLL may unlock.
  1022. endmenu
  1023. source "net/Kconfig"
  1024. source "drivers/Kconfig"
  1025. source "fs/Kconfig"
  1026. source "arch/blackfin/Kconfig.debug"
  1027. source "security/Kconfig"
  1028. source "crypto/Kconfig"
  1029. source "lib/Kconfig"