nouveau_channel.c 10 KB

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  1. /*
  2. * Copyright 2005-2006 Stephane Marchesin
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. */
  24. #include "drmP.h"
  25. #include "nouveau_drv.h"
  26. #include "nouveau_drm.h"
  27. #include "nouveau_dma.h"
  28. #include "nouveau_fifo.h"
  29. #include "nouveau_ramht.h"
  30. #include "nouveau_fence.h"
  31. #include "nouveau_software.h"
  32. static int
  33. nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
  34. {
  35. u32 mem = nouveau_vram_pushbuf ? TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT;
  36. struct drm_device *dev = chan->dev;
  37. struct drm_nouveau_private *dev_priv = dev->dev_private;
  38. int ret;
  39. /* allocate buffer object */
  40. ret = nouveau_bo_new(dev, 65536, 0, mem, 0, 0, NULL, &chan->pushbuf_bo);
  41. if (ret)
  42. goto out;
  43. ret = nouveau_bo_pin(chan->pushbuf_bo, mem);
  44. if (ret)
  45. goto out;
  46. ret = nouveau_bo_map(chan->pushbuf_bo);
  47. if (ret)
  48. goto out;
  49. /* create DMA object covering the entire memtype where the push
  50. * buffer resides, userspace can submit its own push buffers from
  51. * anywhere within the same memtype.
  52. */
  53. chan->pushbuf_base = chan->pushbuf_bo->bo.offset;
  54. if (dev_priv->card_type >= NV_50) {
  55. ret = nouveau_bo_vma_add(chan->pushbuf_bo, chan->vm,
  56. &chan->pushbuf_vma);
  57. if (ret)
  58. goto out;
  59. if (dev_priv->card_type < NV_C0) {
  60. ret = nouveau_gpuobj_dma_new(chan,
  61. NV_CLASS_DMA_IN_MEMORY, 0,
  62. (1ULL << 40),
  63. NV_MEM_ACCESS_RO,
  64. NV_MEM_TARGET_VM,
  65. &chan->pushbuf);
  66. }
  67. chan->pushbuf_base = chan->pushbuf_vma.offset;
  68. } else
  69. if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_TT) {
  70. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  71. dev_priv->gart_info.aper_size,
  72. NV_MEM_ACCESS_RO,
  73. NV_MEM_TARGET_GART,
  74. &chan->pushbuf);
  75. } else
  76. if (dev_priv->card_type != NV_04) {
  77. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
  78. dev_priv->fb_available_size,
  79. NV_MEM_ACCESS_RO,
  80. NV_MEM_TARGET_VRAM,
  81. &chan->pushbuf);
  82. } else {
  83. /* NV04 cmdbuf hack, from original ddx.. not sure of it's
  84. * exact reason for existing :) PCI access to cmdbuf in
  85. * VRAM.
  86. */
  87. ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
  88. pci_resource_start(dev->pdev, 1),
  89. dev_priv->fb_available_size,
  90. NV_MEM_ACCESS_RO,
  91. NV_MEM_TARGET_PCI,
  92. &chan->pushbuf);
  93. }
  94. out:
  95. if (ret) {
  96. NV_ERROR(dev, "error initialising pushbuf: %d\n", ret);
  97. nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
  98. nouveau_gpuobj_ref(NULL, &chan->pushbuf);
  99. if (chan->pushbuf_bo) {
  100. nouveau_bo_unmap(chan->pushbuf_bo);
  101. nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  102. }
  103. }
  104. return 0;
  105. }
  106. /* allocates and initializes a fifo for user space consumption */
  107. int
  108. nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
  109. struct drm_file *file_priv,
  110. uint32_t vram_handle, uint32_t gart_handle)
  111. {
  112. struct nouveau_exec_engine *fence = nv_engine(dev, NVOBJ_ENGINE_FENCE);
  113. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  114. struct drm_nouveau_private *dev_priv = dev->dev_private;
  115. struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
  116. struct nouveau_channel *chan;
  117. unsigned long flags;
  118. int ret, i;
  119. /* allocate and lock channel structure */
  120. chan = kzalloc(sizeof(*chan), GFP_KERNEL);
  121. if (!chan)
  122. return -ENOMEM;
  123. chan->dev = dev;
  124. chan->file_priv = file_priv;
  125. chan->vram_handle = vram_handle;
  126. chan->gart_handle = gart_handle;
  127. kref_init(&chan->ref);
  128. atomic_set(&chan->users, 1);
  129. mutex_init(&chan->mutex);
  130. mutex_lock(&chan->mutex);
  131. /* allocate hw channel id */
  132. spin_lock_irqsave(&dev_priv->channels.lock, flags);
  133. for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
  134. if (!dev_priv->channels.ptr[chan->id]) {
  135. nouveau_channel_ref(chan, &dev_priv->channels.ptr[chan->id]);
  136. break;
  137. }
  138. }
  139. spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
  140. if (chan->id == pfifo->channels) {
  141. mutex_unlock(&chan->mutex);
  142. kfree(chan);
  143. return -ENODEV;
  144. }
  145. NV_DEBUG(dev, "initialising channel %d\n", chan->id);
  146. /* setup channel's memory and vm */
  147. ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
  148. if (ret) {
  149. NV_ERROR(dev, "gpuobj %d\n", ret);
  150. nouveau_channel_put(&chan);
  151. return ret;
  152. }
  153. /* Allocate space for per-channel fixed notifier memory */
  154. ret = nouveau_notifier_init_channel(chan);
  155. if (ret) {
  156. NV_ERROR(dev, "ntfy %d\n", ret);
  157. nouveau_channel_put(&chan);
  158. return ret;
  159. }
  160. /* Allocate DMA push buffer */
  161. ret = nouveau_channel_pushbuf_init(chan);
  162. if (ret) {
  163. NV_ERROR(dev, "pushbuf %d\n", ret);
  164. nouveau_channel_put(&chan);
  165. return ret;
  166. }
  167. nouveau_dma_init(chan);
  168. chan->user_put = 0x40;
  169. chan->user_get = 0x44;
  170. if (dev_priv->card_type >= NV_50)
  171. chan->user_get_hi = 0x60;
  172. /* create fifo context */
  173. ret = pfifo->base.context_new(chan, NVOBJ_ENGINE_FIFO);
  174. if (ret) {
  175. nouveau_channel_put(&chan);
  176. return ret;
  177. }
  178. /* Insert NOPs for NOUVEAU_DMA_SKIPS */
  179. ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
  180. if (ret) {
  181. nouveau_channel_put(&chan);
  182. return ret;
  183. }
  184. for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
  185. OUT_RING (chan, 0x00000000);
  186. ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
  187. if (ret) {
  188. nouveau_channel_put(&chan);
  189. return ret;
  190. }
  191. if (dev_priv->card_type < NV_C0) {
  192. ret = RING_SPACE(chan, 2);
  193. if (ret) {
  194. nouveau_channel_put(&chan);
  195. return ret;
  196. }
  197. BEGIN_NV04(chan, NvSubSw, NV01_SUBCHAN_OBJECT, 1);
  198. OUT_RING (chan, NvSw);
  199. FIRE_RING (chan);
  200. }
  201. FIRE_RING(chan);
  202. ret = fence->context_new(chan, NVOBJ_ENGINE_FENCE);
  203. if (ret) {
  204. nouveau_channel_put(&chan);
  205. return ret;
  206. }
  207. nouveau_debugfs_channel_init(chan);
  208. NV_DEBUG(dev, "channel %d initialised\n", chan->id);
  209. if (fpriv) {
  210. spin_lock(&fpriv->lock);
  211. list_add(&chan->list, &fpriv->channels);
  212. spin_unlock(&fpriv->lock);
  213. }
  214. *chan_ret = chan;
  215. return 0;
  216. }
  217. struct nouveau_channel *
  218. nouveau_channel_get_unlocked(struct nouveau_channel *ref)
  219. {
  220. struct nouveau_channel *chan = NULL;
  221. if (likely(ref && atomic_inc_not_zero(&ref->users)))
  222. nouveau_channel_ref(ref, &chan);
  223. return chan;
  224. }
  225. struct nouveau_channel *
  226. nouveau_channel_get(struct drm_file *file_priv, int id)
  227. {
  228. struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
  229. struct nouveau_channel *chan;
  230. spin_lock(&fpriv->lock);
  231. list_for_each_entry(chan, &fpriv->channels, list) {
  232. if (chan->id == id) {
  233. chan = nouveau_channel_get_unlocked(chan);
  234. spin_unlock(&fpriv->lock);
  235. mutex_lock(&chan->mutex);
  236. return chan;
  237. }
  238. }
  239. spin_unlock(&fpriv->lock);
  240. return ERR_PTR(-EINVAL);
  241. }
  242. void
  243. nouveau_channel_put_unlocked(struct nouveau_channel **pchan)
  244. {
  245. struct nouveau_channel *chan = *pchan;
  246. struct drm_device *dev = chan->dev;
  247. struct drm_nouveau_private *dev_priv = dev->dev_private;
  248. unsigned long flags;
  249. int i;
  250. /* decrement the refcount, and we're done if there's still refs */
  251. if (likely(!atomic_dec_and_test(&chan->users))) {
  252. nouveau_channel_ref(NULL, pchan);
  253. return;
  254. }
  255. /* no one wants the channel anymore */
  256. NV_DEBUG(dev, "freeing channel %d\n", chan->id);
  257. nouveau_debugfs_channel_fini(chan);
  258. /* give it chance to idle */
  259. nouveau_channel_idle(chan);
  260. /* destroy the engine specific contexts */
  261. for (i = NVOBJ_ENGINE_NR - 1; i >= 0; i--) {
  262. if (chan->engctx[i])
  263. dev_priv->eng[i]->context_del(chan, i);
  264. }
  265. /* aside from its resources, the channel should now be dead,
  266. * remove it from the channel list
  267. */
  268. spin_lock_irqsave(&dev_priv->channels.lock, flags);
  269. nouveau_channel_ref(NULL, &dev_priv->channels.ptr[chan->id]);
  270. spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
  271. /* destroy any resources the channel owned */
  272. nouveau_gpuobj_ref(NULL, &chan->pushbuf);
  273. if (chan->pushbuf_bo) {
  274. nouveau_bo_vma_del(chan->pushbuf_bo, &chan->pushbuf_vma);
  275. nouveau_bo_unmap(chan->pushbuf_bo);
  276. nouveau_bo_unpin(chan->pushbuf_bo);
  277. nouveau_bo_ref(NULL, &chan->pushbuf_bo);
  278. }
  279. nouveau_ramht_ref(NULL, &chan->ramht, chan);
  280. nouveau_notifier_takedown_channel(chan);
  281. nouveau_gpuobj_channel_takedown(chan);
  282. nouveau_channel_ref(NULL, pchan);
  283. }
  284. void
  285. nouveau_channel_put(struct nouveau_channel **pchan)
  286. {
  287. mutex_unlock(&(*pchan)->mutex);
  288. nouveau_channel_put_unlocked(pchan);
  289. }
  290. static void
  291. nouveau_channel_del(struct kref *ref)
  292. {
  293. struct nouveau_channel *chan =
  294. container_of(ref, struct nouveau_channel, ref);
  295. kfree(chan);
  296. }
  297. void
  298. nouveau_channel_ref(struct nouveau_channel *chan,
  299. struct nouveau_channel **pchan)
  300. {
  301. if (chan)
  302. kref_get(&chan->ref);
  303. if (*pchan)
  304. kref_put(&(*pchan)->ref, nouveau_channel_del);
  305. *pchan = chan;
  306. }
  307. int
  308. nouveau_channel_idle(struct nouveau_channel *chan)
  309. {
  310. struct drm_device *dev = chan->dev;
  311. struct nouveau_fence *fence = NULL;
  312. int ret;
  313. ret = nouveau_fence_new(chan, &fence);
  314. if (!ret) {
  315. ret = nouveau_fence_wait(fence, false, false);
  316. nouveau_fence_unref(&fence);
  317. }
  318. if (ret)
  319. NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
  320. return ret;
  321. }
  322. /* cleans up all the fifos from file_priv */
  323. void
  324. nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
  325. {
  326. struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
  327. struct nouveau_channel *chan;
  328. int i;
  329. if (!pfifo)
  330. return;
  331. NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
  332. for (i = 0; i < pfifo->channels; i++) {
  333. chan = nouveau_channel_get(file_priv, i);
  334. if (IS_ERR(chan))
  335. continue;
  336. list_del(&chan->list);
  337. atomic_dec(&chan->users);
  338. nouveau_channel_put(&chan);
  339. }
  340. }