omap-usb-host.c 20 KB

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  1. /**
  2. * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com
  5. * Author: Keshava Munegowda <keshava_mgowda@ti.com>
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 of
  9. * the License as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/types.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/clk.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/gpio.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/platform_data/usb-omap.h>
  29. #include <linux/pm_runtime.h>
  30. #include "omap-usb.h"
  31. #define USBHS_DRIVER_NAME "usbhs_omap"
  32. #define OMAP_EHCI_DEVICE "ehci-omap"
  33. #define OMAP_OHCI_DEVICE "ohci-omap3"
  34. /* OMAP USBHOST Register addresses */
  35. /* UHH Register Set */
  36. #define OMAP_UHH_REVISION (0x00)
  37. #define OMAP_UHH_SYSCONFIG (0x10)
  38. #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
  39. #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
  40. #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
  41. #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
  42. #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
  43. #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
  44. #define OMAP_UHH_SYSSTATUS (0x14)
  45. #define OMAP_UHH_HOSTCONFIG (0x40)
  46. #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
  47. #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
  48. #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
  49. #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
  50. #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
  51. #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
  52. #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
  53. #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
  54. #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
  55. #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
  56. #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
  57. #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31)
  58. /* OMAP4-specific defines */
  59. #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2)
  60. #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2)
  61. #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4)
  62. #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4)
  63. #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0)
  64. #define OMAP4_P1_MODE_CLEAR (3 << 16)
  65. #define OMAP4_P1_MODE_TLL (1 << 16)
  66. #define OMAP4_P1_MODE_HSIC (3 << 16)
  67. #define OMAP4_P2_MODE_CLEAR (3 << 18)
  68. #define OMAP4_P2_MODE_TLL (1 << 18)
  69. #define OMAP4_P2_MODE_HSIC (3 << 18)
  70. #define OMAP_UHH_DEBUG_CSR (0x44)
  71. /* Values of UHH_REVISION - Note: these are not given in the TRM */
  72. #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */
  73. #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */
  74. #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1)
  75. #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2)
  76. #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY)
  77. #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
  78. #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC)
  79. struct usbhs_hcd_omap {
  80. int nports;
  81. struct clk **utmi_clk;
  82. struct clk **hsic60m_clk;
  83. struct clk **hsic480m_clk;
  84. struct clk *xclk60mhsp1_ck;
  85. struct clk *xclk60mhsp2_ck;
  86. struct clk *utmi_p1_gfclk;
  87. struct clk *utmi_p2_gfclk;
  88. struct clk *init_60m_fclk;
  89. struct clk *ehci_logic_fck;
  90. void __iomem *uhh_base;
  91. struct usbhs_omap_platform_data *pdata;
  92. u32 usbhs_rev;
  93. };
  94. /*-------------------------------------------------------------------------*/
  95. const char usbhs_driver_name[] = USBHS_DRIVER_NAME;
  96. static u64 usbhs_dmamask = DMA_BIT_MASK(32);
  97. /*-------------------------------------------------------------------------*/
  98. static inline void usbhs_write(void __iomem *base, u32 reg, u32 val)
  99. {
  100. __raw_writel(val, base + reg);
  101. }
  102. static inline u32 usbhs_read(void __iomem *base, u32 reg)
  103. {
  104. return __raw_readl(base + reg);
  105. }
  106. static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val)
  107. {
  108. __raw_writeb(val, base + reg);
  109. }
  110. static inline u8 usbhs_readb(void __iomem *base, u8 reg)
  111. {
  112. return __raw_readb(base + reg);
  113. }
  114. /*-------------------------------------------------------------------------*/
  115. static struct platform_device *omap_usbhs_alloc_child(const char *name,
  116. struct resource *res, int num_resources, void *pdata,
  117. size_t pdata_size, struct device *dev)
  118. {
  119. struct platform_device *child;
  120. int ret;
  121. child = platform_device_alloc(name, 0);
  122. if (!child) {
  123. dev_err(dev, "platform_device_alloc %s failed\n", name);
  124. goto err_end;
  125. }
  126. ret = platform_device_add_resources(child, res, num_resources);
  127. if (ret) {
  128. dev_err(dev, "platform_device_add_resources failed\n");
  129. goto err_alloc;
  130. }
  131. ret = platform_device_add_data(child, pdata, pdata_size);
  132. if (ret) {
  133. dev_err(dev, "platform_device_add_data failed\n");
  134. goto err_alloc;
  135. }
  136. child->dev.dma_mask = &usbhs_dmamask;
  137. dma_set_coherent_mask(&child->dev, DMA_BIT_MASK(32));
  138. child->dev.parent = dev;
  139. ret = platform_device_add(child);
  140. if (ret) {
  141. dev_err(dev, "platform_device_add failed\n");
  142. goto err_alloc;
  143. }
  144. return child;
  145. err_alloc:
  146. platform_device_put(child);
  147. err_end:
  148. return NULL;
  149. }
  150. static int omap_usbhs_alloc_children(struct platform_device *pdev)
  151. {
  152. struct device *dev = &pdev->dev;
  153. struct usbhs_omap_platform_data *pdata = dev->platform_data;
  154. struct platform_device *ehci;
  155. struct platform_device *ohci;
  156. struct resource *res;
  157. struct resource resources[2];
  158. int ret;
  159. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci");
  160. if (!res) {
  161. dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n");
  162. ret = -ENODEV;
  163. goto err_end;
  164. }
  165. resources[0] = *res;
  166. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq");
  167. if (!res) {
  168. dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n");
  169. ret = -ENODEV;
  170. goto err_end;
  171. }
  172. resources[1] = *res;
  173. ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, pdata,
  174. sizeof(*pdata), dev);
  175. if (!ehci) {
  176. dev_err(dev, "omap_usbhs_alloc_child failed\n");
  177. ret = -ENOMEM;
  178. goto err_end;
  179. }
  180. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci");
  181. if (!res) {
  182. dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n");
  183. ret = -ENODEV;
  184. goto err_ehci;
  185. }
  186. resources[0] = *res;
  187. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq");
  188. if (!res) {
  189. dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n");
  190. ret = -ENODEV;
  191. goto err_ehci;
  192. }
  193. resources[1] = *res;
  194. ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, pdata,
  195. sizeof(*pdata), dev);
  196. if (!ohci) {
  197. dev_err(dev, "omap_usbhs_alloc_child failed\n");
  198. ret = -ENOMEM;
  199. goto err_ehci;
  200. }
  201. return 0;
  202. err_ehci:
  203. platform_device_unregister(ehci);
  204. err_end:
  205. return ret;
  206. }
  207. static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
  208. {
  209. switch (pmode) {
  210. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
  211. case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
  212. case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
  213. case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
  214. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
  215. case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
  216. case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
  217. case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
  218. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
  219. case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
  220. return true;
  221. default:
  222. return false;
  223. }
  224. }
  225. static int usbhs_runtime_resume(struct device *dev)
  226. {
  227. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  228. struct usbhs_omap_platform_data *pdata = omap->pdata;
  229. int i, r;
  230. dev_dbg(dev, "usbhs_runtime_resume\n");
  231. omap_tll_enable(pdata);
  232. if (!IS_ERR(omap->ehci_logic_fck))
  233. clk_enable(omap->ehci_logic_fck);
  234. for (i = 0; i < omap->nports; i++) {
  235. switch (pdata->port_mode[i]) {
  236. case OMAP_EHCI_PORT_MODE_HSIC:
  237. if (!IS_ERR(omap->hsic60m_clk[i])) {
  238. r = clk_enable(omap->hsic60m_clk[i]);
  239. if (r) {
  240. dev_err(dev,
  241. "Can't enable port %d hsic60m clk:%d\n",
  242. i, r);
  243. }
  244. }
  245. if (!IS_ERR(omap->hsic480m_clk[i])) {
  246. r = clk_enable(omap->hsic480m_clk[i]);
  247. if (r) {
  248. dev_err(dev,
  249. "Can't enable port %d hsic480m clk:%d\n",
  250. i, r);
  251. }
  252. }
  253. /* Fall through as HSIC mode needs utmi_clk */
  254. case OMAP_EHCI_PORT_MODE_TLL:
  255. if (!IS_ERR(omap->utmi_clk[i])) {
  256. r = clk_enable(omap->utmi_clk[i]);
  257. if (r) {
  258. dev_err(dev,
  259. "Can't enable port %d clk : %d\n",
  260. i, r);
  261. }
  262. }
  263. break;
  264. default:
  265. break;
  266. }
  267. }
  268. return 0;
  269. }
  270. static int usbhs_runtime_suspend(struct device *dev)
  271. {
  272. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  273. struct usbhs_omap_platform_data *pdata = omap->pdata;
  274. int i;
  275. dev_dbg(dev, "usbhs_runtime_suspend\n");
  276. for (i = 0; i < omap->nports; i++) {
  277. switch (pdata->port_mode[i]) {
  278. case OMAP_EHCI_PORT_MODE_HSIC:
  279. if (!IS_ERR(omap->hsic60m_clk[i]))
  280. clk_disable(omap->hsic60m_clk[i]);
  281. if (!IS_ERR(omap->hsic480m_clk[i]))
  282. clk_disable(omap->hsic480m_clk[i]);
  283. /* Fall through as utmi_clks were used in HSIC mode */
  284. case OMAP_EHCI_PORT_MODE_TLL:
  285. if (!IS_ERR(omap->utmi_clk[i]))
  286. clk_disable(omap->utmi_clk[i]);
  287. break;
  288. default:
  289. break;
  290. }
  291. }
  292. if (!IS_ERR(omap->ehci_logic_fck))
  293. clk_disable(omap->ehci_logic_fck);
  294. omap_tll_disable(pdata);
  295. return 0;
  296. }
  297. static unsigned omap_usbhs_rev1_hostconfig(struct usbhs_hcd_omap *omap,
  298. unsigned reg)
  299. {
  300. struct usbhs_omap_platform_data *pdata = omap->pdata;
  301. int i;
  302. for (i = 0; i < omap->nports; i++) {
  303. switch (pdata->port_mode[i]) {
  304. case OMAP_USBHS_PORT_MODE_UNUSED:
  305. reg &= ~(OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS << i);
  306. break;
  307. case OMAP_EHCI_PORT_MODE_PHY:
  308. if (pdata->single_ulpi_bypass)
  309. break;
  310. if (i == 0)
  311. reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
  312. else
  313. reg &= ~(OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
  314. << (i-1));
  315. break;
  316. default:
  317. if (pdata->single_ulpi_bypass)
  318. break;
  319. if (i == 0)
  320. reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
  321. else
  322. reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS
  323. << (i-1);
  324. break;
  325. }
  326. }
  327. if (pdata->single_ulpi_bypass) {
  328. /* bypass ULPI only if none of the ports use PHY mode */
  329. reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
  330. for (i = 0; i < omap->nports; i++) {
  331. if (is_ehci_phy_mode(pdata->port_mode[i])) {
  332. reg &= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
  333. break;
  334. }
  335. }
  336. }
  337. return reg;
  338. }
  339. static unsigned omap_usbhs_rev2_hostconfig(struct usbhs_hcd_omap *omap,
  340. unsigned reg)
  341. {
  342. struct usbhs_omap_platform_data *pdata = omap->pdata;
  343. int i;
  344. for (i = 0; i < omap->nports; i++) {
  345. /* Clear port mode fields for PHY mode */
  346. reg &= ~(OMAP4_P1_MODE_CLEAR << 2 * i);
  347. if (is_ehci_tll_mode(pdata->port_mode[i]) ||
  348. (is_ohci_port(pdata->port_mode[i])))
  349. reg |= OMAP4_P1_MODE_TLL << 2 * i;
  350. else if (is_ehci_hsic_mode(pdata->port_mode[i]))
  351. reg |= OMAP4_P1_MODE_HSIC << 2 * i;
  352. }
  353. return reg;
  354. }
  355. static void omap_usbhs_init(struct device *dev)
  356. {
  357. struct usbhs_hcd_omap *omap = dev_get_drvdata(dev);
  358. unsigned reg;
  359. dev_dbg(dev, "starting TI HSUSB Controller\n");
  360. pm_runtime_get_sync(dev);
  361. reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
  362. /* setup ULPI bypass and burst configurations */
  363. reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
  364. | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
  365. | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
  366. reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK;
  367. reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
  368. switch (omap->usbhs_rev) {
  369. case OMAP_USBHS_REV1:
  370. reg = omap_usbhs_rev1_hostconfig(omap, reg);
  371. break;
  372. case OMAP_USBHS_REV2:
  373. reg = omap_usbhs_rev2_hostconfig(omap, reg);
  374. break;
  375. default: /* newer revisions */
  376. reg = omap_usbhs_rev2_hostconfig(omap, reg);
  377. break;
  378. }
  379. usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
  380. dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
  381. pm_runtime_put_sync(dev);
  382. }
  383. /**
  384. * usbhs_omap_probe - initialize TI-based HCDs
  385. *
  386. * Allocates basic resources for this USB host controller.
  387. */
  388. static int usbhs_omap_probe(struct platform_device *pdev)
  389. {
  390. struct device *dev = &pdev->dev;
  391. struct usbhs_omap_platform_data *pdata = dev->platform_data;
  392. struct usbhs_hcd_omap *omap;
  393. struct resource *res;
  394. int ret = 0;
  395. int i;
  396. bool need_logic_fck;
  397. if (!pdata) {
  398. dev_err(dev, "Missing platform data\n");
  399. return -ENODEV;
  400. }
  401. omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
  402. if (!omap) {
  403. dev_err(dev, "Memory allocation failed\n");
  404. return -ENOMEM;
  405. }
  406. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh");
  407. omap->uhh_base = devm_request_and_ioremap(dev, res);
  408. if (!omap->uhh_base) {
  409. dev_err(dev, "Resource request/ioremap failed\n");
  410. return -EADDRNOTAVAIL;
  411. }
  412. omap->pdata = pdata;
  413. /* Initialize the TLL subsystem */
  414. omap_tll_init(pdata);
  415. pm_runtime_enable(dev);
  416. platform_set_drvdata(pdev, omap);
  417. pm_runtime_get_sync(dev);
  418. omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION);
  419. /* we need to call runtime suspend before we update omap->nports
  420. * to prevent unbalanced clk_disable()
  421. */
  422. pm_runtime_put_sync(dev);
  423. /*
  424. * If platform data contains nports then use that
  425. * else make out number of ports from USBHS revision
  426. */
  427. if (pdata->nports) {
  428. omap->nports = pdata->nports;
  429. } else {
  430. switch (omap->usbhs_rev) {
  431. case OMAP_USBHS_REV1:
  432. omap->nports = 3;
  433. break;
  434. case OMAP_USBHS_REV2:
  435. omap->nports = 2;
  436. break;
  437. default:
  438. omap->nports = OMAP3_HS_USB_PORTS;
  439. dev_dbg(dev,
  440. "USB HOST Rev:0x%d not recognized, assuming %d ports\n",
  441. omap->usbhs_rev, omap->nports);
  442. break;
  443. }
  444. pdata->nports = omap->nports;
  445. }
  446. i = sizeof(struct clk *) * omap->nports;
  447. omap->utmi_clk = devm_kzalloc(dev, i, GFP_KERNEL);
  448. omap->hsic480m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
  449. omap->hsic60m_clk = devm_kzalloc(dev, i, GFP_KERNEL);
  450. if (!omap->utmi_clk || !omap->hsic480m_clk || !omap->hsic60m_clk) {
  451. dev_err(dev, "Memory allocation failed\n");
  452. ret = -ENOMEM;
  453. goto err_mem;
  454. }
  455. need_logic_fck = false;
  456. for (i = 0; i < omap->nports; i++) {
  457. if (is_ehci_phy_mode(i) || is_ehci_tll_mode(i) ||
  458. is_ehci_hsic_mode(i))
  459. need_logic_fck |= true;
  460. }
  461. omap->ehci_logic_fck = ERR_PTR(-EINVAL);
  462. if (need_logic_fck) {
  463. omap->ehci_logic_fck = clk_get(dev, "ehci_logic_fck");
  464. if (IS_ERR(omap->ehci_logic_fck)) {
  465. ret = PTR_ERR(omap->ehci_logic_fck);
  466. dev_dbg(dev, "ehci_logic_fck failed:%d\n", ret);
  467. }
  468. }
  469. omap->utmi_p1_gfclk = clk_get(dev, "utmi_p1_gfclk");
  470. if (IS_ERR(omap->utmi_p1_gfclk)) {
  471. ret = PTR_ERR(omap->utmi_p1_gfclk);
  472. dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret);
  473. goto err_p1_gfclk;
  474. }
  475. omap->utmi_p2_gfclk = clk_get(dev, "utmi_p2_gfclk");
  476. if (IS_ERR(omap->utmi_p2_gfclk)) {
  477. ret = PTR_ERR(omap->utmi_p2_gfclk);
  478. dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret);
  479. goto err_p2_gfclk;
  480. }
  481. omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck");
  482. if (IS_ERR(omap->xclk60mhsp1_ck)) {
  483. ret = PTR_ERR(omap->xclk60mhsp1_ck);
  484. dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
  485. goto err_xclk60mhsp1;
  486. }
  487. omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck");
  488. if (IS_ERR(omap->xclk60mhsp2_ck)) {
  489. ret = PTR_ERR(omap->xclk60mhsp2_ck);
  490. dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
  491. goto err_xclk60mhsp2;
  492. }
  493. omap->init_60m_fclk = clk_get(dev, "init_60m_fclk");
  494. if (IS_ERR(omap->init_60m_fclk)) {
  495. ret = PTR_ERR(omap->init_60m_fclk);
  496. dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
  497. goto err_init60m;
  498. }
  499. for (i = 0; i < omap->nports; i++) {
  500. char clkname[30];
  501. /* clock names are indexed from 1*/
  502. snprintf(clkname, sizeof(clkname),
  503. "usb_host_hs_utmi_p%d_clk", i + 1);
  504. /* If a clock is not found we won't bail out as not all
  505. * platforms have all clocks and we can function without
  506. * them
  507. */
  508. omap->utmi_clk[i] = clk_get(dev, clkname);
  509. if (IS_ERR(omap->utmi_clk[i]))
  510. dev_dbg(dev, "Failed to get clock : %s : %ld\n",
  511. clkname, PTR_ERR(omap->utmi_clk[i]));
  512. snprintf(clkname, sizeof(clkname),
  513. "usb_host_hs_hsic480m_p%d_clk", i + 1);
  514. omap->hsic480m_clk[i] = clk_get(dev, clkname);
  515. if (IS_ERR(omap->hsic480m_clk[i]))
  516. dev_dbg(dev, "Failed to get clock : %s : %ld\n",
  517. clkname, PTR_ERR(omap->hsic480m_clk[i]));
  518. snprintf(clkname, sizeof(clkname),
  519. "usb_host_hs_hsic60m_p%d_clk", i + 1);
  520. omap->hsic60m_clk[i] = clk_get(dev, clkname);
  521. if (IS_ERR(omap->hsic60m_clk[i]))
  522. dev_dbg(dev, "Failed to get clock : %s : %ld\n",
  523. clkname, PTR_ERR(omap->hsic60m_clk[i]));
  524. }
  525. if (is_ehci_phy_mode(pdata->port_mode[0])) {
  526. /* for OMAP3, clk_set_parent fails */
  527. ret = clk_set_parent(omap->utmi_p1_gfclk,
  528. omap->xclk60mhsp1_ck);
  529. if (ret != 0)
  530. dev_dbg(dev, "xclk60mhsp1_ck set parent failed: %d\n",
  531. ret);
  532. } else if (is_ehci_tll_mode(pdata->port_mode[0])) {
  533. ret = clk_set_parent(omap->utmi_p1_gfclk,
  534. omap->init_60m_fclk);
  535. if (ret != 0)
  536. dev_dbg(dev, "P0 init_60m_fclk set parent failed: %d\n",
  537. ret);
  538. }
  539. if (is_ehci_phy_mode(pdata->port_mode[1])) {
  540. ret = clk_set_parent(omap->utmi_p2_gfclk,
  541. omap->xclk60mhsp2_ck);
  542. if (ret != 0)
  543. dev_dbg(dev, "xclk60mhsp2_ck set parent failed: %d\n",
  544. ret);
  545. } else if (is_ehci_tll_mode(pdata->port_mode[1])) {
  546. ret = clk_set_parent(omap->utmi_p2_gfclk,
  547. omap->init_60m_fclk);
  548. if (ret != 0)
  549. dev_dbg(dev, "P1 init_60m_fclk set parent failed: %d\n",
  550. ret);
  551. }
  552. omap_usbhs_init(dev);
  553. ret = omap_usbhs_alloc_children(pdev);
  554. if (ret) {
  555. dev_err(dev, "omap_usbhs_alloc_children failed\n");
  556. goto err_alloc;
  557. }
  558. return 0;
  559. err_alloc:
  560. for (i = 0; i < omap->nports; i++) {
  561. if (!IS_ERR(omap->utmi_clk[i]))
  562. clk_put(omap->utmi_clk[i]);
  563. if (!IS_ERR(omap->hsic60m_clk[i]))
  564. clk_put(omap->hsic60m_clk[i]);
  565. if (!IS_ERR(omap->hsic480m_clk[i]))
  566. clk_put(omap->hsic480m_clk[i]);
  567. }
  568. clk_put(omap->init_60m_fclk);
  569. err_init60m:
  570. clk_put(omap->xclk60mhsp2_ck);
  571. err_xclk60mhsp2:
  572. clk_put(omap->xclk60mhsp1_ck);
  573. err_xclk60mhsp1:
  574. clk_put(omap->utmi_p2_gfclk);
  575. err_p2_gfclk:
  576. clk_put(omap->utmi_p1_gfclk);
  577. err_p1_gfclk:
  578. if (!IS_ERR(omap->ehci_logic_fck))
  579. clk_put(omap->ehci_logic_fck);
  580. err_mem:
  581. pm_runtime_disable(dev);
  582. return ret;
  583. }
  584. /**
  585. * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs
  586. * @pdev: USB Host Controller being removed
  587. *
  588. * Reverses the effect of usbhs_omap_probe().
  589. */
  590. static int usbhs_omap_remove(struct platform_device *pdev)
  591. {
  592. struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev);
  593. int i;
  594. for (i = 0; i < omap->nports; i++) {
  595. if (!IS_ERR(omap->utmi_clk[i]))
  596. clk_put(omap->utmi_clk[i]);
  597. if (!IS_ERR(omap->hsic60m_clk[i]))
  598. clk_put(omap->hsic60m_clk[i]);
  599. if (!IS_ERR(omap->hsic480m_clk[i]))
  600. clk_put(omap->hsic480m_clk[i]);
  601. }
  602. clk_put(omap->init_60m_fclk);
  603. clk_put(omap->utmi_p1_gfclk);
  604. clk_put(omap->utmi_p2_gfclk);
  605. clk_put(omap->xclk60mhsp2_ck);
  606. clk_put(omap->xclk60mhsp1_ck);
  607. if (!IS_ERR(omap->ehci_logic_fck))
  608. clk_put(omap->ehci_logic_fck);
  609. pm_runtime_disable(&pdev->dev);
  610. return 0;
  611. }
  612. static const struct dev_pm_ops usbhsomap_dev_pm_ops = {
  613. .runtime_suspend = usbhs_runtime_suspend,
  614. .runtime_resume = usbhs_runtime_resume,
  615. };
  616. static struct platform_driver usbhs_omap_driver = {
  617. .driver = {
  618. .name = (char *)usbhs_driver_name,
  619. .owner = THIS_MODULE,
  620. .pm = &usbhsomap_dev_pm_ops,
  621. },
  622. .remove = usbhs_omap_remove,
  623. };
  624. MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
  625. MODULE_ALIAS("platform:" USBHS_DRIVER_NAME);
  626. MODULE_LICENSE("GPL v2");
  627. MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI");
  628. static int __init omap_usbhs_drvinit(void)
  629. {
  630. return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe);
  631. }
  632. /*
  633. * init before ehci and ohci drivers;
  634. * The usbhs core driver should be initialized much before
  635. * the omap ehci and ohci probe functions are called.
  636. * This usbhs core driver should be initialized after
  637. * usb tll driver
  638. */
  639. fs_initcall_sync(omap_usbhs_drvinit);
  640. static void __exit omap_usbhs_drvexit(void)
  641. {
  642. platform_driver_unregister(&usbhs_omap_driver);
  643. }
  644. module_exit(omap_usbhs_drvexit);