mpc885ads_setup.c 10 KB

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  1. /*arch/powerpc/platforms/8xx/mpc885ads_setup.c
  2. *
  3. * Platform setup for the Freescale mpc885ads board
  4. *
  5. * Vitaly Bordug <vbordug@ru.mvista.com>
  6. *
  7. * Copyright 2005 MontaVista Software Inc.
  8. *
  9. * This file is licensed under the terms of the GNU General Public License
  10. * version 2. This program is licensed "as is" without any warranty of any
  11. * kind, whether express or implied.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/param.h>
  16. #include <linux/string.h>
  17. #include <linux/ioport.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <linux/root_dev.h>
  21. #include <linux/fs_enet_pd.h>
  22. #include <linux/fs_uart_pd.h>
  23. #include <linux/fsl_devices.h>
  24. #include <linux/mii.h>
  25. #include <asm/delay.h>
  26. #include <asm/io.h>
  27. #include <asm/machdep.h>
  28. #include <asm/page.h>
  29. #include <asm/processor.h>
  30. #include <asm/system.h>
  31. #include <asm/time.h>
  32. #include <asm/mpc8xx.h>
  33. #include <asm/8xx_immap.h>
  34. #include <asm/commproc.h>
  35. #include <asm/fs_pd.h>
  36. #include <asm/prom.h>
  37. extern void cpm_reset(void);
  38. extern void mpc8xx_show_cpuinfo(struct seq_file *);
  39. extern void mpc8xx_restart(char *cmd);
  40. extern void mpc8xx_calibrate_decr(void);
  41. extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
  42. extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
  43. extern void m8xx_pic_init(void);
  44. extern unsigned int mpc8xx_get_irq(void);
  45. static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi);
  46. static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
  47. static void init_scc3_ioports(struct fs_platform_info *ptr);
  48. #ifdef CONFIG_PCMCIA_M8XX
  49. static void pcmcia_hw_setup(int slot, int enable)
  50. {
  51. unsigned *bcsr_io;
  52. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  53. if (enable)
  54. clrbits32(bcsr_io, BCSR1_PCCEN);
  55. else
  56. setbits32(bcsr_io, BCSR1_PCCEN);
  57. iounmap(bcsr_io);
  58. }
  59. static int pcmcia_set_voltage(int slot, int vcc, int vpp)
  60. {
  61. u32 reg = 0;
  62. unsigned *bcsr_io;
  63. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  64. switch (vcc) {
  65. case 0:
  66. break;
  67. case 33:
  68. reg |= BCSR1_PCCVCC0;
  69. break;
  70. case 50:
  71. reg |= BCSR1_PCCVCC1;
  72. break;
  73. default:
  74. return 1;
  75. }
  76. switch (vpp) {
  77. case 0:
  78. break;
  79. case 33:
  80. case 50:
  81. if (vcc == vpp)
  82. reg |= BCSR1_PCCVPP1;
  83. else
  84. return 1;
  85. break;
  86. case 120:
  87. if ((vcc == 33) || (vcc == 50))
  88. reg |= BCSR1_PCCVPP0;
  89. else
  90. return 1;
  91. default:
  92. return 1;
  93. }
  94. /* first, turn off all power */
  95. clrbits32(bcsr_io, 0x00610000);
  96. /* enable new powersettings */
  97. setbits32(bcsr_io, reg);
  98. iounmap(bcsr_io);
  99. return 0;
  100. }
  101. #endif
  102. void __init mpc885ads_board_setup(void)
  103. {
  104. cpm8xx_t *cp;
  105. unsigned int *bcsr_io;
  106. u8 tmpval8;
  107. #ifdef CONFIG_FS_ENET
  108. iop8xx_t *io_port;
  109. #endif
  110. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  111. cp = (cpm8xx_t *) immr_map(im_cpm);
  112. if (bcsr_io == NULL) {
  113. printk(KERN_CRIT "Could not remap BCSR\n");
  114. return;
  115. }
  116. #ifdef CONFIG_SERIAL_CPM_SMC1
  117. clrbits32(bcsr_io, BCSR1_RS232EN_1);
  118. clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
  119. tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
  120. out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
  121. clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
  122. #else
  123. setbits32(bcsr_io, BCSR1_RS232EN_1);
  124. out_be16(&cp->cp_smc[0].smc_smcmr, 0);
  125. out_8(&cp->cp_smc[0].smc_smce, 0);
  126. #endif
  127. #ifdef CONFIG_SERIAL_CPM_SMC2
  128. clrbits32(bcsr_io, BCSR1_RS232EN_2);
  129. clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
  130. setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
  131. tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
  132. out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
  133. clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
  134. init_smc2_uart_ioports(0);
  135. #else
  136. setbits32(bcsr_io, BCSR1_RS232EN_2);
  137. out_be16(&cp->cp_smc[1].smc_smcmr, 0);
  138. out_8(&cp->cp_smc[1].smc_smce, 0);
  139. #endif
  140. immr_unmap(cp);
  141. iounmap(bcsr_io);
  142. #ifdef CONFIG_FS_ENET
  143. /* use MDC for MII (common) */
  144. io_port = (iop8xx_t *) immr_map(im_ioport);
  145. setbits16(&io_port->iop_pdpar, 0x0080);
  146. clrbits16(&io_port->iop_pddir, 0x0080);
  147. bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
  148. clrbits32(bcsr_io, BCSR5_MII1_EN);
  149. clrbits32(bcsr_io, BCSR5_MII1_RST);
  150. #ifndef CONFIG_FC_ENET_HAS_SCC
  151. clrbits32(bcsr_io, BCSR5_MII2_EN);
  152. clrbits32(bcsr_io, BCSR5_MII2_RST);
  153. #endif
  154. iounmap(bcsr_io);
  155. immr_unmap(io_port);
  156. #endif
  157. #ifdef CONFIG_PCMCIA_M8XX
  158. /*Set up board specific hook-ups */
  159. m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
  160. m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
  161. #endif
  162. }
  163. static void init_fec1_ioports(struct fs_platform_info *ptr)
  164. {
  165. cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
  166. iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
  167. /* configure FEC1 pins */
  168. setbits16(&io_port->iop_papar, 0xf830);
  169. setbits16(&io_port->iop_padir, 0x0830);
  170. clrbits16(&io_port->iop_padir, 0xf000);
  171. setbits32(&cp->cp_pbpar, 0x00001001);
  172. clrbits32(&cp->cp_pbdir, 0x00001001);
  173. setbits16(&io_port->iop_pcpar, 0x000c);
  174. clrbits16(&io_port->iop_pcdir, 0x000c);
  175. setbits32(&cp->cp_pepar, 0x00000003);
  176. setbits32(&cp->cp_pedir, 0x00000003);
  177. clrbits32(&cp->cp_peso, 0x00000003);
  178. clrbits32(&cp->cp_cptr, 0x00000100);
  179. immr_unmap(io_port);
  180. immr_unmap(cp);
  181. }
  182. static void init_fec2_ioports(struct fs_platform_info *ptr)
  183. {
  184. cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
  185. iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
  186. /* configure FEC2 pins */
  187. setbits32(&cp->cp_pepar, 0x0003fffc);
  188. setbits32(&cp->cp_pedir, 0x0003fffc);
  189. clrbits32(&cp->cp_peso, 0x000087fc);
  190. setbits32(&cp->cp_peso, 0x00037800);
  191. clrbits32(&cp->cp_cptr, 0x00000080);
  192. immr_unmap(io_port);
  193. immr_unmap(cp);
  194. }
  195. void init_fec_ioports(struct fs_platform_info *fpi)
  196. {
  197. int fec_no = fs_get_fec_index(fpi->fs_no);
  198. switch (fec_no) {
  199. case 0:
  200. init_fec1_ioports(fpi);
  201. break;
  202. case 1:
  203. init_fec2_ioports(fpi);
  204. break;
  205. default:
  206. printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
  207. return;
  208. }
  209. }
  210. static void init_scc3_ioports(struct fs_platform_info *fpi)
  211. {
  212. unsigned *bcsr_io;
  213. iop8xx_t *io_port;
  214. cpm8xx_t *cp;
  215. bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
  216. io_port = (iop8xx_t *) immr_map(im_ioport);
  217. cp = (cpm8xx_t *) immr_map(im_cpm);
  218. if (bcsr_io == NULL) {
  219. printk(KERN_CRIT "Could not remap BCSR\n");
  220. return;
  221. }
  222. /* Enable the PHY.
  223. */
  224. clrbits32(bcsr_io + 4, BCSR4_ETH10_RST);
  225. udelay(1000);
  226. setbits32(bcsr_io + 4, BCSR4_ETH10_RST);
  227. /* Configure port A pins for Txd and Rxd.
  228. */
  229. setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
  230. clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
  231. /* Configure port C pins to enable CLSN and RENA.
  232. */
  233. clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
  234. clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
  235. setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
  236. /* Configure port E for TCLK and RCLK.
  237. */
  238. setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
  239. clrbits32(&cp->cp_pepar, PE_ENET_TENA);
  240. clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
  241. clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
  242. setbits32(&cp->cp_peso, PE_ENET_TENA);
  243. /* Configure Serial Interface clock routing.
  244. * First, clear all SCC bits to zero, then set the ones we want.
  245. */
  246. clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
  247. setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
  248. /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
  249. */
  250. clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
  251. /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
  252. * by H/W setting after reset. SCC ethernet controller support only half duplex.
  253. * This discrepancy of modes causes a lot of carrier lost errors.
  254. */
  255. /* In the original SCC enet driver the following code is placed at
  256. the end of the initialization */
  257. setbits32(&cp->cp_pepar, PE_ENET_TENA);
  258. clrbits32(&cp->cp_pedir, PE_ENET_TENA);
  259. setbits32(&cp->cp_peso, PE_ENET_TENA);
  260. setbits32(bcsr_io + 4, BCSR1_ETHEN);
  261. iounmap(bcsr_io);
  262. immr_unmap(io_port);
  263. immr_unmap(cp);
  264. }
  265. void init_scc_ioports(struct fs_platform_info *fpi)
  266. {
  267. int scc_no = fs_get_scc_index(fpi->fs_no);
  268. switch (scc_no) {
  269. case 2:
  270. init_scc3_ioports(fpi);
  271. break;
  272. default:
  273. printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
  274. return;
  275. }
  276. }
  277. static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr)
  278. {
  279. unsigned *bcsr_io;
  280. cpm8xx_t *cp;
  281. cp = (cpm8xx_t *) immr_map(im_cpm);
  282. setbits32(&cp->cp_pepar, 0x000000c0);
  283. clrbits32(&cp->cp_pedir, 0x000000c0);
  284. clrbits32(&cp->cp_peso, 0x00000040);
  285. setbits32(&cp->cp_peso, 0x00000080);
  286. immr_unmap(cp);
  287. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  288. if (bcsr_io == NULL) {
  289. printk(KERN_CRIT "Could not remap BCSR1\n");
  290. return;
  291. }
  292. clrbits32(bcsr_io, BCSR1_RS232EN_1);
  293. iounmap(bcsr_io);
  294. }
  295. static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi)
  296. {
  297. unsigned *bcsr_io;
  298. cpm8xx_t *cp;
  299. cp = (cpm8xx_t *) immr_map(im_cpm);
  300. setbits32(&cp->cp_pepar, 0x00000c00);
  301. clrbits32(&cp->cp_pedir, 0x00000c00);
  302. clrbits32(&cp->cp_peso, 0x00000400);
  303. setbits32(&cp->cp_peso, 0x00000800);
  304. immr_unmap(cp);
  305. bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  306. if (bcsr_io == NULL) {
  307. printk(KERN_CRIT "Could not remap BCSR1\n");
  308. return;
  309. }
  310. clrbits32(bcsr_io, BCSR1_RS232EN_2);
  311. iounmap(bcsr_io);
  312. }
  313. void init_smc_ioports(struct fs_uart_platform_info *data)
  314. {
  315. int smc_no = fs_uart_id_fsid2smc(data->fs_no);
  316. switch (smc_no) {
  317. case 0:
  318. init_smc1_uart_ioports(data);
  319. data->brg = data->clk_rx;
  320. break;
  321. case 1:
  322. init_smc2_uart_ioports(data);
  323. data->brg = data->clk_rx;
  324. break;
  325. default:
  326. printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
  327. return;
  328. }
  329. }
  330. int platform_device_skip(const char *model, int id)
  331. {
  332. #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
  333. const char *dev = "FEC";
  334. int n = 2;
  335. #else
  336. const char *dev = "SCC";
  337. int n = 3;
  338. #endif
  339. if (!strcmp(model, dev) && n == id)
  340. return 1;
  341. return 0;
  342. }
  343. static void __init mpc885ads_setup_arch(void)
  344. {
  345. cpm_reset();
  346. mpc885ads_board_setup();
  347. ROOT_DEV = Root_NFS;
  348. }
  349. static int __init mpc885ads_probe(void)
  350. {
  351. char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
  352. "model", NULL);
  353. if (model == NULL)
  354. return 0;
  355. if (strcmp(model, "MPC885ADS"))
  356. return 0;
  357. return 1;
  358. }
  359. define_machine(mpc885_ads)
  360. {
  361. .name = "MPC885 ADS",
  362. .probe = mpc885ads_probe,
  363. .setup_arch = mpc885ads_setup_arch,
  364. .init_IRQ = m8xx_pic_init,
  365. .show_cpuinfo = mpc8xx_show_cpuinfo,
  366. .get_irq = mpc8xx_get_irq,
  367. .restart = mpc8xx_restart,
  368. .calibrate_decr = mpc8xx_calibrate_decr,
  369. .set_rtc_time = mpc8xx_set_rtc_time,
  370. .get_rtc_time = mpc8xx_get_rtc_time,
  371. };