atmel_usba_udc.c 49 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/slab.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/list.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/atmel_usba_udc.h>
  23. #include <linux/delay.h>
  24. #include <linux/platform_data/atmel.h>
  25. #include <asm/gpio.h>
  26. #include "atmel_usba_udc.h"
  27. static struct usba_udc the_udc;
  28. static struct usba_ep *usba_ep;
  29. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  30. #include <linux/debugfs.h>
  31. #include <linux/uaccess.h>
  32. static int queue_dbg_open(struct inode *inode, struct file *file)
  33. {
  34. struct usba_ep *ep = inode->i_private;
  35. struct usba_request *req, *req_copy;
  36. struct list_head *queue_data;
  37. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  38. if (!queue_data)
  39. return -ENOMEM;
  40. INIT_LIST_HEAD(queue_data);
  41. spin_lock_irq(&ep->udc->lock);
  42. list_for_each_entry(req, &ep->queue, queue) {
  43. req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
  44. if (!req_copy)
  45. goto fail;
  46. list_add_tail(&req_copy->queue, queue_data);
  47. }
  48. spin_unlock_irq(&ep->udc->lock);
  49. file->private_data = queue_data;
  50. return 0;
  51. fail:
  52. spin_unlock_irq(&ep->udc->lock);
  53. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  54. list_del(&req->queue);
  55. kfree(req);
  56. }
  57. kfree(queue_data);
  58. return -ENOMEM;
  59. }
  60. /*
  61. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  62. *
  63. * b: buffer address
  64. * l: buffer length
  65. * I/i: interrupt/no interrupt
  66. * Z/z: zero/no zero
  67. * S/s: short ok/short not ok
  68. * s: status
  69. * n: nr_packets
  70. * F/f: submitted/not submitted to FIFO
  71. * D/d: using/not using DMA
  72. * L/l: last transaction/not last transaction
  73. */
  74. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  75. size_t nbytes, loff_t *ppos)
  76. {
  77. struct list_head *queue = file->private_data;
  78. struct usba_request *req, *tmp_req;
  79. size_t len, remaining, actual = 0;
  80. char tmpbuf[38];
  81. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  82. return -EFAULT;
  83. mutex_lock(&file_inode(file)->i_mutex);
  84. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  85. len = snprintf(tmpbuf, sizeof(tmpbuf),
  86. "%8p %08x %c%c%c %5d %c%c%c\n",
  87. req->req.buf, req->req.length,
  88. req->req.no_interrupt ? 'i' : 'I',
  89. req->req.zero ? 'Z' : 'z',
  90. req->req.short_not_ok ? 's' : 'S',
  91. req->req.status,
  92. req->submitted ? 'F' : 'f',
  93. req->using_dma ? 'D' : 'd',
  94. req->last_transaction ? 'L' : 'l');
  95. len = min(len, sizeof(tmpbuf));
  96. if (len > nbytes)
  97. break;
  98. list_del(&req->queue);
  99. kfree(req);
  100. remaining = __copy_to_user(buf, tmpbuf, len);
  101. actual += len - remaining;
  102. if (remaining)
  103. break;
  104. nbytes -= len;
  105. buf += len;
  106. }
  107. mutex_unlock(&file_inode(file)->i_mutex);
  108. return actual;
  109. }
  110. static int queue_dbg_release(struct inode *inode, struct file *file)
  111. {
  112. struct list_head *queue_data = file->private_data;
  113. struct usba_request *req, *tmp_req;
  114. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  115. list_del(&req->queue);
  116. kfree(req);
  117. }
  118. kfree(queue_data);
  119. return 0;
  120. }
  121. static int regs_dbg_open(struct inode *inode, struct file *file)
  122. {
  123. struct usba_udc *udc;
  124. unsigned int i;
  125. u32 *data;
  126. int ret = -ENOMEM;
  127. mutex_lock(&inode->i_mutex);
  128. udc = inode->i_private;
  129. data = kmalloc(inode->i_size, GFP_KERNEL);
  130. if (!data)
  131. goto out;
  132. spin_lock_irq(&udc->lock);
  133. for (i = 0; i < inode->i_size / 4; i++)
  134. data[i] = __raw_readl(udc->regs + i * 4);
  135. spin_unlock_irq(&udc->lock);
  136. file->private_data = data;
  137. ret = 0;
  138. out:
  139. mutex_unlock(&inode->i_mutex);
  140. return ret;
  141. }
  142. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  143. size_t nbytes, loff_t *ppos)
  144. {
  145. struct inode *inode = file_inode(file);
  146. int ret;
  147. mutex_lock(&inode->i_mutex);
  148. ret = simple_read_from_buffer(buf, nbytes, ppos,
  149. file->private_data,
  150. file_inode(file)->i_size);
  151. mutex_unlock(&inode->i_mutex);
  152. return ret;
  153. }
  154. static int regs_dbg_release(struct inode *inode, struct file *file)
  155. {
  156. kfree(file->private_data);
  157. return 0;
  158. }
  159. const struct file_operations queue_dbg_fops = {
  160. .owner = THIS_MODULE,
  161. .open = queue_dbg_open,
  162. .llseek = no_llseek,
  163. .read = queue_dbg_read,
  164. .release = queue_dbg_release,
  165. };
  166. const struct file_operations regs_dbg_fops = {
  167. .owner = THIS_MODULE,
  168. .open = regs_dbg_open,
  169. .llseek = generic_file_llseek,
  170. .read = regs_dbg_read,
  171. .release = regs_dbg_release,
  172. };
  173. static void usba_ep_init_debugfs(struct usba_udc *udc,
  174. struct usba_ep *ep)
  175. {
  176. struct dentry *ep_root;
  177. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  178. if (!ep_root)
  179. goto err_root;
  180. ep->debugfs_dir = ep_root;
  181. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  182. ep, &queue_dbg_fops);
  183. if (!ep->debugfs_queue)
  184. goto err_queue;
  185. if (ep->can_dma) {
  186. ep->debugfs_dma_status
  187. = debugfs_create_u32("dma_status", 0400, ep_root,
  188. &ep->last_dma_status);
  189. if (!ep->debugfs_dma_status)
  190. goto err_dma_status;
  191. }
  192. if (ep_is_control(ep)) {
  193. ep->debugfs_state
  194. = debugfs_create_u32("state", 0400, ep_root,
  195. &ep->state);
  196. if (!ep->debugfs_state)
  197. goto err_state;
  198. }
  199. return;
  200. err_state:
  201. if (ep->can_dma)
  202. debugfs_remove(ep->debugfs_dma_status);
  203. err_dma_status:
  204. debugfs_remove(ep->debugfs_queue);
  205. err_queue:
  206. debugfs_remove(ep_root);
  207. err_root:
  208. dev_err(&ep->udc->pdev->dev,
  209. "failed to create debugfs directory for %s\n", ep->ep.name);
  210. }
  211. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  212. {
  213. debugfs_remove(ep->debugfs_queue);
  214. debugfs_remove(ep->debugfs_dma_status);
  215. debugfs_remove(ep->debugfs_state);
  216. debugfs_remove(ep->debugfs_dir);
  217. ep->debugfs_dma_status = NULL;
  218. ep->debugfs_dir = NULL;
  219. }
  220. static void usba_init_debugfs(struct usba_udc *udc)
  221. {
  222. struct dentry *root, *regs;
  223. struct resource *regs_resource;
  224. root = debugfs_create_dir(udc->gadget.name, NULL);
  225. if (IS_ERR(root) || !root)
  226. goto err_root;
  227. udc->debugfs_root = root;
  228. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  229. if (!regs)
  230. goto err_regs;
  231. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  232. CTRL_IOMEM_ID);
  233. regs->d_inode->i_size = resource_size(regs_resource);
  234. udc->debugfs_regs = regs;
  235. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  236. return;
  237. err_regs:
  238. debugfs_remove(root);
  239. err_root:
  240. udc->debugfs_root = NULL;
  241. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  242. }
  243. static void usba_cleanup_debugfs(struct usba_udc *udc)
  244. {
  245. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  246. debugfs_remove(udc->debugfs_regs);
  247. debugfs_remove(udc->debugfs_root);
  248. udc->debugfs_regs = NULL;
  249. udc->debugfs_root = NULL;
  250. }
  251. #else
  252. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  253. struct usba_ep *ep)
  254. {
  255. }
  256. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  257. {
  258. }
  259. static inline void usba_init_debugfs(struct usba_udc *udc)
  260. {
  261. }
  262. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  263. {
  264. }
  265. #endif
  266. static int vbus_is_present(struct usba_udc *udc)
  267. {
  268. if (gpio_is_valid(udc->vbus_pin))
  269. return gpio_get_value(udc->vbus_pin) ^ udc->vbus_pin_inverted;
  270. /* No Vbus detection: Assume always present */
  271. return 1;
  272. }
  273. #if defined(CONFIG_ARCH_AT91SAM9RL)
  274. #include <mach/at91_pmc.h>
  275. static void toggle_bias(int is_on)
  276. {
  277. unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
  278. if (is_on)
  279. at91_pmc_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
  280. else
  281. at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
  282. }
  283. #else
  284. static void toggle_bias(int is_on)
  285. {
  286. }
  287. #endif /* CONFIG_ARCH_AT91SAM9RL */
  288. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  289. {
  290. unsigned int transaction_len;
  291. transaction_len = req->req.length - req->req.actual;
  292. req->last_transaction = 1;
  293. if (transaction_len > ep->ep.maxpacket) {
  294. transaction_len = ep->ep.maxpacket;
  295. req->last_transaction = 0;
  296. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  297. req->last_transaction = 0;
  298. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  299. ep->ep.name, req, transaction_len,
  300. req->last_transaction ? ", done" : "");
  301. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  302. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  303. req->req.actual += transaction_len;
  304. }
  305. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  306. {
  307. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  308. ep->ep.name, req, req->req.length);
  309. req->req.actual = 0;
  310. req->submitted = 1;
  311. if (req->using_dma) {
  312. if (req->req.length == 0) {
  313. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  314. return;
  315. }
  316. if (req->req.zero)
  317. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  318. else
  319. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  320. usba_dma_writel(ep, ADDRESS, req->req.dma);
  321. usba_dma_writel(ep, CONTROL, req->ctrl);
  322. } else {
  323. next_fifo_transaction(ep, req);
  324. if (req->last_transaction) {
  325. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  326. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  327. } else {
  328. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  329. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  330. }
  331. }
  332. }
  333. static void submit_next_request(struct usba_ep *ep)
  334. {
  335. struct usba_request *req;
  336. if (list_empty(&ep->queue)) {
  337. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  338. return;
  339. }
  340. req = list_entry(ep->queue.next, struct usba_request, queue);
  341. if (!req->submitted)
  342. submit_request(ep, req);
  343. }
  344. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  345. {
  346. ep->state = STATUS_STAGE_IN;
  347. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  348. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  349. }
  350. static void receive_data(struct usba_ep *ep)
  351. {
  352. struct usba_udc *udc = ep->udc;
  353. struct usba_request *req;
  354. unsigned long status;
  355. unsigned int bytecount, nr_busy;
  356. int is_complete = 0;
  357. status = usba_ep_readl(ep, STA);
  358. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  359. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  360. while (nr_busy > 0) {
  361. if (list_empty(&ep->queue)) {
  362. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  363. break;
  364. }
  365. req = list_entry(ep->queue.next,
  366. struct usba_request, queue);
  367. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  368. if (status & (1 << 31))
  369. is_complete = 1;
  370. if (req->req.actual + bytecount >= req->req.length) {
  371. is_complete = 1;
  372. bytecount = req->req.length - req->req.actual;
  373. }
  374. memcpy_fromio(req->req.buf + req->req.actual,
  375. ep->fifo, bytecount);
  376. req->req.actual += bytecount;
  377. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  378. if (is_complete) {
  379. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  380. req->req.status = 0;
  381. list_del_init(&req->queue);
  382. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  383. spin_unlock(&udc->lock);
  384. req->req.complete(&ep->ep, &req->req);
  385. spin_lock(&udc->lock);
  386. }
  387. status = usba_ep_readl(ep, STA);
  388. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  389. if (is_complete && ep_is_control(ep)) {
  390. send_status(udc, ep);
  391. break;
  392. }
  393. }
  394. }
  395. static void
  396. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  397. {
  398. struct usba_udc *udc = ep->udc;
  399. WARN_ON(!list_empty(&req->queue));
  400. if (req->req.status == -EINPROGRESS)
  401. req->req.status = status;
  402. if (req->using_dma)
  403. usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
  404. DBG(DBG_GADGET | DBG_REQ,
  405. "%s: req %p complete: status %d, actual %u\n",
  406. ep->ep.name, req, req->req.status, req->req.actual);
  407. spin_unlock(&udc->lock);
  408. req->req.complete(&ep->ep, &req->req);
  409. spin_lock(&udc->lock);
  410. }
  411. static void
  412. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  413. {
  414. struct usba_request *req, *tmp_req;
  415. list_for_each_entry_safe(req, tmp_req, list, queue) {
  416. list_del_init(&req->queue);
  417. request_complete(ep, req, status);
  418. }
  419. }
  420. static int
  421. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  422. {
  423. struct usba_ep *ep = to_usba_ep(_ep);
  424. struct usba_udc *udc = ep->udc;
  425. unsigned long flags, ept_cfg, maxpacket;
  426. unsigned int nr_trans;
  427. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  428. maxpacket = usb_endpoint_maxp(desc) & 0x7ff;
  429. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  430. || ep->index == 0
  431. || desc->bDescriptorType != USB_DT_ENDPOINT
  432. || maxpacket == 0
  433. || maxpacket > ep->fifo_size) {
  434. DBG(DBG_ERR, "ep_enable: Invalid argument");
  435. return -EINVAL;
  436. }
  437. ep->is_isoc = 0;
  438. ep->is_in = 0;
  439. if (maxpacket <= 8)
  440. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  441. else
  442. /* LSB is bit 1, not 0 */
  443. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  444. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  445. ep->ep.name, ept_cfg, maxpacket);
  446. if (usb_endpoint_dir_in(desc)) {
  447. ep->is_in = 1;
  448. ept_cfg |= USBA_EPT_DIR_IN;
  449. }
  450. switch (usb_endpoint_type(desc)) {
  451. case USB_ENDPOINT_XFER_CONTROL:
  452. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  453. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  454. break;
  455. case USB_ENDPOINT_XFER_ISOC:
  456. if (!ep->can_isoc) {
  457. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  458. ep->ep.name);
  459. return -EINVAL;
  460. }
  461. /*
  462. * Bits 11:12 specify number of _additional_
  463. * transactions per microframe.
  464. */
  465. nr_trans = ((usb_endpoint_maxp(desc) >> 11) & 3) + 1;
  466. if (nr_trans > 3)
  467. return -EINVAL;
  468. ep->is_isoc = 1;
  469. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  470. /*
  471. * Do triple-buffering on high-bandwidth iso endpoints.
  472. */
  473. if (nr_trans > 1 && ep->nr_banks == 3)
  474. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  475. else
  476. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  477. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  478. break;
  479. case USB_ENDPOINT_XFER_BULK:
  480. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  481. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  482. break;
  483. case USB_ENDPOINT_XFER_INT:
  484. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  485. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  486. break;
  487. }
  488. spin_lock_irqsave(&ep->udc->lock, flags);
  489. ep->ep.desc = desc;
  490. ep->ep.maxpacket = maxpacket;
  491. usba_ep_writel(ep, CFG, ept_cfg);
  492. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  493. if (ep->can_dma) {
  494. u32 ctrl;
  495. usba_writel(udc, INT_ENB,
  496. (usba_readl(udc, INT_ENB)
  497. | USBA_BF(EPT_INT, 1 << ep->index)
  498. | USBA_BF(DMA_INT, 1 << ep->index)));
  499. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  500. usba_ep_writel(ep, CTL_ENB, ctrl);
  501. } else {
  502. usba_writel(udc, INT_ENB,
  503. (usba_readl(udc, INT_ENB)
  504. | USBA_BF(EPT_INT, 1 << ep->index)));
  505. }
  506. spin_unlock_irqrestore(&udc->lock, flags);
  507. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  508. (unsigned long)usba_ep_readl(ep, CFG));
  509. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  510. (unsigned long)usba_readl(udc, INT_ENB));
  511. return 0;
  512. }
  513. static int usba_ep_disable(struct usb_ep *_ep)
  514. {
  515. struct usba_ep *ep = to_usba_ep(_ep);
  516. struct usba_udc *udc = ep->udc;
  517. LIST_HEAD(req_list);
  518. unsigned long flags;
  519. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  520. spin_lock_irqsave(&udc->lock, flags);
  521. if (!ep->ep.desc) {
  522. spin_unlock_irqrestore(&udc->lock, flags);
  523. /* REVISIT because this driver disables endpoints in
  524. * reset_all_endpoints() before calling disconnect(),
  525. * most gadget drivers would trigger this non-error ...
  526. */
  527. if (udc->gadget.speed != USB_SPEED_UNKNOWN)
  528. DBG(DBG_ERR, "ep_disable: %s not enabled\n",
  529. ep->ep.name);
  530. return -EINVAL;
  531. }
  532. ep->ep.desc = NULL;
  533. list_splice_init(&ep->queue, &req_list);
  534. if (ep->can_dma) {
  535. usba_dma_writel(ep, CONTROL, 0);
  536. usba_dma_writel(ep, ADDRESS, 0);
  537. usba_dma_readl(ep, STATUS);
  538. }
  539. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  540. usba_writel(udc, INT_ENB,
  541. usba_readl(udc, INT_ENB)
  542. & ~USBA_BF(EPT_INT, 1 << ep->index));
  543. request_complete_list(ep, &req_list, -ESHUTDOWN);
  544. spin_unlock_irqrestore(&udc->lock, flags);
  545. return 0;
  546. }
  547. static struct usb_request *
  548. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  549. {
  550. struct usba_request *req;
  551. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  552. req = kzalloc(sizeof(*req), gfp_flags);
  553. if (!req)
  554. return NULL;
  555. INIT_LIST_HEAD(&req->queue);
  556. return &req->req;
  557. }
  558. static void
  559. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  560. {
  561. struct usba_request *req = to_usba_req(_req);
  562. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  563. kfree(req);
  564. }
  565. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  566. struct usba_request *req, gfp_t gfp_flags)
  567. {
  568. unsigned long flags;
  569. int ret;
  570. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  571. ep->ep.name, req->req.length, req->req.dma,
  572. req->req.zero ? 'Z' : 'z',
  573. req->req.short_not_ok ? 'S' : 's',
  574. req->req.no_interrupt ? 'I' : 'i');
  575. if (req->req.length > 0x10000) {
  576. /* Lengths from 0 to 65536 (inclusive) are supported */
  577. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  578. return -EINVAL;
  579. }
  580. ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
  581. if (ret)
  582. return ret;
  583. req->using_dma = 1;
  584. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  585. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  586. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  587. if (ep->is_in)
  588. req->ctrl |= USBA_DMA_END_BUF_EN;
  589. /*
  590. * Add this request to the queue and submit for DMA if
  591. * possible. Check if we're still alive first -- we may have
  592. * received a reset since last time we checked.
  593. */
  594. ret = -ESHUTDOWN;
  595. spin_lock_irqsave(&udc->lock, flags);
  596. if (ep->ep.desc) {
  597. if (list_empty(&ep->queue))
  598. submit_request(ep, req);
  599. list_add_tail(&req->queue, &ep->queue);
  600. ret = 0;
  601. }
  602. spin_unlock_irqrestore(&udc->lock, flags);
  603. return ret;
  604. }
  605. static int
  606. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  607. {
  608. struct usba_request *req = to_usba_req(_req);
  609. struct usba_ep *ep = to_usba_ep(_ep);
  610. struct usba_udc *udc = ep->udc;
  611. unsigned long flags;
  612. int ret;
  613. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  614. ep->ep.name, req, _req->length);
  615. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
  616. !ep->ep.desc)
  617. return -ESHUTDOWN;
  618. req->submitted = 0;
  619. req->using_dma = 0;
  620. req->last_transaction = 0;
  621. _req->status = -EINPROGRESS;
  622. _req->actual = 0;
  623. if (ep->can_dma)
  624. return queue_dma(udc, ep, req, gfp_flags);
  625. /* May have received a reset since last time we checked */
  626. ret = -ESHUTDOWN;
  627. spin_lock_irqsave(&udc->lock, flags);
  628. if (ep->ep.desc) {
  629. list_add_tail(&req->queue, &ep->queue);
  630. if ((!ep_is_control(ep) && ep->is_in) ||
  631. (ep_is_control(ep)
  632. && (ep->state == DATA_STAGE_IN
  633. || ep->state == STATUS_STAGE_IN)))
  634. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  635. else
  636. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  637. ret = 0;
  638. }
  639. spin_unlock_irqrestore(&udc->lock, flags);
  640. return ret;
  641. }
  642. static void
  643. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  644. {
  645. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  646. }
  647. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  648. {
  649. unsigned int timeout;
  650. u32 status;
  651. /*
  652. * Stop the DMA controller. When writing both CH_EN
  653. * and LINK to 0, the other bits are not affected.
  654. */
  655. usba_dma_writel(ep, CONTROL, 0);
  656. /* Wait for the FIFO to empty */
  657. for (timeout = 40; timeout; --timeout) {
  658. status = usba_dma_readl(ep, STATUS);
  659. if (!(status & USBA_DMA_CH_EN))
  660. break;
  661. udelay(1);
  662. }
  663. if (pstatus)
  664. *pstatus = status;
  665. if (timeout == 0) {
  666. dev_err(&ep->udc->pdev->dev,
  667. "%s: timed out waiting for DMA FIFO to empty\n",
  668. ep->ep.name);
  669. return -ETIMEDOUT;
  670. }
  671. return 0;
  672. }
  673. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  674. {
  675. struct usba_ep *ep = to_usba_ep(_ep);
  676. struct usba_udc *udc = ep->udc;
  677. struct usba_request *req = to_usba_req(_req);
  678. unsigned long flags;
  679. u32 status;
  680. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  681. ep->ep.name, req);
  682. spin_lock_irqsave(&udc->lock, flags);
  683. if (req->using_dma) {
  684. /*
  685. * If this request is currently being transferred,
  686. * stop the DMA controller and reset the FIFO.
  687. */
  688. if (ep->queue.next == &req->queue) {
  689. status = usba_dma_readl(ep, STATUS);
  690. if (status & USBA_DMA_CH_EN)
  691. stop_dma(ep, &status);
  692. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  693. ep->last_dma_status = status;
  694. #endif
  695. usba_writel(udc, EPT_RST, 1 << ep->index);
  696. usba_update_req(ep, req, status);
  697. }
  698. }
  699. /*
  700. * Errors should stop the queue from advancing until the
  701. * completion function returns.
  702. */
  703. list_del_init(&req->queue);
  704. request_complete(ep, req, -ECONNRESET);
  705. /* Process the next request if any */
  706. submit_next_request(ep);
  707. spin_unlock_irqrestore(&udc->lock, flags);
  708. return 0;
  709. }
  710. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  711. {
  712. struct usba_ep *ep = to_usba_ep(_ep);
  713. struct usba_udc *udc = ep->udc;
  714. unsigned long flags;
  715. int ret = 0;
  716. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  717. value ? "set" : "clear");
  718. if (!ep->ep.desc) {
  719. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  720. ep->ep.name);
  721. return -ENODEV;
  722. }
  723. if (ep->is_isoc) {
  724. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  725. ep->ep.name);
  726. return -ENOTTY;
  727. }
  728. spin_lock_irqsave(&udc->lock, flags);
  729. /*
  730. * We can't halt IN endpoints while there are still data to be
  731. * transferred
  732. */
  733. if (!list_empty(&ep->queue)
  734. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  735. & USBA_BF(BUSY_BANKS, -1L))))) {
  736. ret = -EAGAIN;
  737. } else {
  738. if (value)
  739. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  740. else
  741. usba_ep_writel(ep, CLR_STA,
  742. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  743. usba_ep_readl(ep, STA);
  744. }
  745. spin_unlock_irqrestore(&udc->lock, flags);
  746. return ret;
  747. }
  748. static int usba_ep_fifo_status(struct usb_ep *_ep)
  749. {
  750. struct usba_ep *ep = to_usba_ep(_ep);
  751. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  752. }
  753. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  754. {
  755. struct usba_ep *ep = to_usba_ep(_ep);
  756. struct usba_udc *udc = ep->udc;
  757. usba_writel(udc, EPT_RST, 1 << ep->index);
  758. }
  759. static const struct usb_ep_ops usba_ep_ops = {
  760. .enable = usba_ep_enable,
  761. .disable = usba_ep_disable,
  762. .alloc_request = usba_ep_alloc_request,
  763. .free_request = usba_ep_free_request,
  764. .queue = usba_ep_queue,
  765. .dequeue = usba_ep_dequeue,
  766. .set_halt = usba_ep_set_halt,
  767. .fifo_status = usba_ep_fifo_status,
  768. .fifo_flush = usba_ep_fifo_flush,
  769. };
  770. static int usba_udc_get_frame(struct usb_gadget *gadget)
  771. {
  772. struct usba_udc *udc = to_usba_udc(gadget);
  773. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  774. }
  775. static int usba_udc_wakeup(struct usb_gadget *gadget)
  776. {
  777. struct usba_udc *udc = to_usba_udc(gadget);
  778. unsigned long flags;
  779. u32 ctrl;
  780. int ret = -EINVAL;
  781. spin_lock_irqsave(&udc->lock, flags);
  782. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  783. ctrl = usba_readl(udc, CTRL);
  784. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  785. ret = 0;
  786. }
  787. spin_unlock_irqrestore(&udc->lock, flags);
  788. return ret;
  789. }
  790. static int
  791. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  792. {
  793. struct usba_udc *udc = to_usba_udc(gadget);
  794. unsigned long flags;
  795. spin_lock_irqsave(&udc->lock, flags);
  796. if (is_selfpowered)
  797. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  798. else
  799. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  800. spin_unlock_irqrestore(&udc->lock, flags);
  801. return 0;
  802. }
  803. static int atmel_usba_start(struct usb_gadget *gadget,
  804. struct usb_gadget_driver *driver);
  805. static int atmel_usba_stop(struct usb_gadget *gadget,
  806. struct usb_gadget_driver *driver);
  807. static const struct usb_gadget_ops usba_udc_ops = {
  808. .get_frame = usba_udc_get_frame,
  809. .wakeup = usba_udc_wakeup,
  810. .set_selfpowered = usba_udc_set_selfpowered,
  811. .udc_start = atmel_usba_start,
  812. .udc_stop = atmel_usba_stop,
  813. };
  814. static struct usb_endpoint_descriptor usba_ep0_desc = {
  815. .bLength = USB_DT_ENDPOINT_SIZE,
  816. .bDescriptorType = USB_DT_ENDPOINT,
  817. .bEndpointAddress = 0,
  818. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  819. .wMaxPacketSize = cpu_to_le16(64),
  820. /* FIXME: I have no idea what to put here */
  821. .bInterval = 1,
  822. };
  823. static void nop_release(struct device *dev)
  824. {
  825. }
  826. static struct usba_udc the_udc = {
  827. .gadget = {
  828. .ops = &usba_udc_ops,
  829. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  830. .max_speed = USB_SPEED_HIGH,
  831. .name = "atmel_usba_udc",
  832. .dev = {
  833. .init_name = "gadget",
  834. .release = nop_release,
  835. },
  836. },
  837. };
  838. /*
  839. * Called with interrupts disabled and udc->lock held.
  840. */
  841. static void reset_all_endpoints(struct usba_udc *udc)
  842. {
  843. struct usba_ep *ep;
  844. struct usba_request *req, *tmp_req;
  845. usba_writel(udc, EPT_RST, ~0UL);
  846. ep = to_usba_ep(udc->gadget.ep0);
  847. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  848. list_del_init(&req->queue);
  849. request_complete(ep, req, -ECONNRESET);
  850. }
  851. /* NOTE: normally, the next call to the gadget driver is in
  852. * charge of disabling endpoints... usually disconnect().
  853. * The exception would be entering a high speed test mode.
  854. *
  855. * FIXME remove this code ... and retest thoroughly.
  856. */
  857. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  858. if (ep->ep.desc) {
  859. spin_unlock(&udc->lock);
  860. usba_ep_disable(&ep->ep);
  861. spin_lock(&udc->lock);
  862. }
  863. }
  864. }
  865. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  866. {
  867. struct usba_ep *ep;
  868. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  869. return to_usba_ep(udc->gadget.ep0);
  870. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  871. u8 bEndpointAddress;
  872. if (!ep->ep.desc)
  873. continue;
  874. bEndpointAddress = ep->ep.desc->bEndpointAddress;
  875. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  876. continue;
  877. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  878. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  879. return ep;
  880. }
  881. return NULL;
  882. }
  883. /* Called with interrupts disabled and udc->lock held */
  884. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  885. {
  886. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  887. ep->state = WAIT_FOR_SETUP;
  888. }
  889. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  890. {
  891. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  892. return 1;
  893. return 0;
  894. }
  895. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  896. {
  897. u32 regval;
  898. DBG(DBG_BUS, "setting address %u...\n", addr);
  899. regval = usba_readl(udc, CTRL);
  900. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  901. usba_writel(udc, CTRL, regval);
  902. }
  903. static int do_test_mode(struct usba_udc *udc)
  904. {
  905. static const char test_packet_buffer[] = {
  906. /* JKJKJKJK * 9 */
  907. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  908. /* JJKKJJKK * 8 */
  909. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  910. /* JJKKJJKK * 8 */
  911. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  912. /* JJJJJJJKKKKKKK * 8 */
  913. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  914. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  915. /* JJJJJJJK * 8 */
  916. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  917. /* {JKKKKKKK * 10}, JK */
  918. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  919. };
  920. struct usba_ep *ep;
  921. struct device *dev = &udc->pdev->dev;
  922. int test_mode;
  923. test_mode = udc->test_mode;
  924. /* Start from a clean slate */
  925. reset_all_endpoints(udc);
  926. switch (test_mode) {
  927. case 0x0100:
  928. /* Test_J */
  929. usba_writel(udc, TST, USBA_TST_J_MODE);
  930. dev_info(dev, "Entering Test_J mode...\n");
  931. break;
  932. case 0x0200:
  933. /* Test_K */
  934. usba_writel(udc, TST, USBA_TST_K_MODE);
  935. dev_info(dev, "Entering Test_K mode...\n");
  936. break;
  937. case 0x0300:
  938. /*
  939. * Test_SE0_NAK: Force high-speed mode and set up ep0
  940. * for Bulk IN transfers
  941. */
  942. ep = &usba_ep[0];
  943. usba_writel(udc, TST,
  944. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  945. usba_ep_writel(ep, CFG,
  946. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  947. | USBA_EPT_DIR_IN
  948. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  949. | USBA_BF(BK_NUMBER, 1));
  950. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  951. set_protocol_stall(udc, ep);
  952. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  953. } else {
  954. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  955. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  956. }
  957. break;
  958. case 0x0400:
  959. /* Test_Packet */
  960. ep = &usba_ep[0];
  961. usba_ep_writel(ep, CFG,
  962. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  963. | USBA_EPT_DIR_IN
  964. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  965. | USBA_BF(BK_NUMBER, 1));
  966. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  967. set_protocol_stall(udc, ep);
  968. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  969. } else {
  970. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  971. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  972. memcpy_toio(ep->fifo, test_packet_buffer,
  973. sizeof(test_packet_buffer));
  974. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  975. dev_info(dev, "Entering Test_Packet mode...\n");
  976. }
  977. break;
  978. default:
  979. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  980. return -EINVAL;
  981. }
  982. return 0;
  983. }
  984. /* Avoid overly long expressions */
  985. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  986. {
  987. if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  988. return true;
  989. return false;
  990. }
  991. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  992. {
  993. if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
  994. return true;
  995. return false;
  996. }
  997. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  998. {
  999. if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
  1000. return true;
  1001. return false;
  1002. }
  1003. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1004. struct usb_ctrlrequest *crq)
  1005. {
  1006. int retval = 0;
  1007. switch (crq->bRequest) {
  1008. case USB_REQ_GET_STATUS: {
  1009. u16 status;
  1010. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1011. status = cpu_to_le16(udc->devstatus);
  1012. } else if (crq->bRequestType
  1013. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1014. status = cpu_to_le16(0);
  1015. } else if (crq->bRequestType
  1016. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1017. struct usba_ep *target;
  1018. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1019. if (!target)
  1020. goto stall;
  1021. status = 0;
  1022. if (is_stalled(udc, target))
  1023. status |= cpu_to_le16(1);
  1024. } else
  1025. goto delegate;
  1026. /* Write directly to the FIFO. No queueing is done. */
  1027. if (crq->wLength != cpu_to_le16(sizeof(status)))
  1028. goto stall;
  1029. ep->state = DATA_STAGE_IN;
  1030. __raw_writew(status, ep->fifo);
  1031. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1032. break;
  1033. }
  1034. case USB_REQ_CLEAR_FEATURE: {
  1035. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1036. if (feature_is_dev_remote_wakeup(crq))
  1037. udc->devstatus
  1038. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1039. else
  1040. /* Can't CLEAR_FEATURE TEST_MODE */
  1041. goto stall;
  1042. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1043. struct usba_ep *target;
  1044. if (crq->wLength != cpu_to_le16(0)
  1045. || !feature_is_ep_halt(crq))
  1046. goto stall;
  1047. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1048. if (!target)
  1049. goto stall;
  1050. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1051. if (target->index != 0)
  1052. usba_ep_writel(target, CLR_STA,
  1053. USBA_TOGGLE_CLR);
  1054. } else {
  1055. goto delegate;
  1056. }
  1057. send_status(udc, ep);
  1058. break;
  1059. }
  1060. case USB_REQ_SET_FEATURE: {
  1061. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1062. if (feature_is_dev_test_mode(crq)) {
  1063. send_status(udc, ep);
  1064. ep->state = STATUS_STAGE_TEST;
  1065. udc->test_mode = le16_to_cpu(crq->wIndex);
  1066. return 0;
  1067. } else if (feature_is_dev_remote_wakeup(crq)) {
  1068. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1069. } else {
  1070. goto stall;
  1071. }
  1072. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1073. struct usba_ep *target;
  1074. if (crq->wLength != cpu_to_le16(0)
  1075. || !feature_is_ep_halt(crq))
  1076. goto stall;
  1077. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1078. if (!target)
  1079. goto stall;
  1080. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1081. } else
  1082. goto delegate;
  1083. send_status(udc, ep);
  1084. break;
  1085. }
  1086. case USB_REQ_SET_ADDRESS:
  1087. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1088. goto delegate;
  1089. set_address(udc, le16_to_cpu(crq->wValue));
  1090. send_status(udc, ep);
  1091. ep->state = STATUS_STAGE_ADDR;
  1092. break;
  1093. default:
  1094. delegate:
  1095. spin_unlock(&udc->lock);
  1096. retval = udc->driver->setup(&udc->gadget, crq);
  1097. spin_lock(&udc->lock);
  1098. }
  1099. return retval;
  1100. stall:
  1101. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1102. "halting endpoint...\n",
  1103. ep->ep.name, crq->bRequestType, crq->bRequest,
  1104. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1105. le16_to_cpu(crq->wLength));
  1106. set_protocol_stall(udc, ep);
  1107. return -1;
  1108. }
  1109. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1110. {
  1111. struct usba_request *req;
  1112. u32 epstatus;
  1113. u32 epctrl;
  1114. restart:
  1115. epstatus = usba_ep_readl(ep, STA);
  1116. epctrl = usba_ep_readl(ep, CTL);
  1117. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1118. ep->ep.name, ep->state, epstatus, epctrl);
  1119. req = NULL;
  1120. if (!list_empty(&ep->queue))
  1121. req = list_entry(ep->queue.next,
  1122. struct usba_request, queue);
  1123. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1124. if (req->submitted)
  1125. next_fifo_transaction(ep, req);
  1126. else
  1127. submit_request(ep, req);
  1128. if (req->last_transaction) {
  1129. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1130. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1131. }
  1132. goto restart;
  1133. }
  1134. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1135. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1136. switch (ep->state) {
  1137. case DATA_STAGE_IN:
  1138. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1139. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1140. ep->state = STATUS_STAGE_OUT;
  1141. break;
  1142. case STATUS_STAGE_ADDR:
  1143. /* Activate our new address */
  1144. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1145. | USBA_FADDR_EN));
  1146. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1147. ep->state = WAIT_FOR_SETUP;
  1148. break;
  1149. case STATUS_STAGE_IN:
  1150. if (req) {
  1151. list_del_init(&req->queue);
  1152. request_complete(ep, req, 0);
  1153. submit_next_request(ep);
  1154. }
  1155. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1156. ep->state = WAIT_FOR_SETUP;
  1157. break;
  1158. case STATUS_STAGE_TEST:
  1159. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1160. ep->state = WAIT_FOR_SETUP;
  1161. if (do_test_mode(udc))
  1162. set_protocol_stall(udc, ep);
  1163. break;
  1164. default:
  1165. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1166. "halting endpoint...\n",
  1167. ep->ep.name, ep->state);
  1168. set_protocol_stall(udc, ep);
  1169. break;
  1170. }
  1171. goto restart;
  1172. }
  1173. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1174. switch (ep->state) {
  1175. case STATUS_STAGE_OUT:
  1176. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1177. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1178. if (req) {
  1179. list_del_init(&req->queue);
  1180. request_complete(ep, req, 0);
  1181. }
  1182. ep->state = WAIT_FOR_SETUP;
  1183. break;
  1184. case DATA_STAGE_OUT:
  1185. receive_data(ep);
  1186. break;
  1187. default:
  1188. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1189. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1190. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1191. "halting endpoint...\n",
  1192. ep->ep.name, ep->state);
  1193. set_protocol_stall(udc, ep);
  1194. break;
  1195. }
  1196. goto restart;
  1197. }
  1198. if (epstatus & USBA_RX_SETUP) {
  1199. union {
  1200. struct usb_ctrlrequest crq;
  1201. unsigned long data[2];
  1202. } crq;
  1203. unsigned int pkt_len;
  1204. int ret;
  1205. if (ep->state != WAIT_FOR_SETUP) {
  1206. /*
  1207. * Didn't expect a SETUP packet at this
  1208. * point. Clean up any pending requests (which
  1209. * may be successful).
  1210. */
  1211. int status = -EPROTO;
  1212. /*
  1213. * RXRDY and TXCOMP are dropped when SETUP
  1214. * packets arrive. Just pretend we received
  1215. * the status packet.
  1216. */
  1217. if (ep->state == STATUS_STAGE_OUT
  1218. || ep->state == STATUS_STAGE_IN) {
  1219. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1220. status = 0;
  1221. }
  1222. if (req) {
  1223. list_del_init(&req->queue);
  1224. request_complete(ep, req, status);
  1225. }
  1226. }
  1227. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1228. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1229. if (pkt_len != sizeof(crq)) {
  1230. pr_warning("udc: Invalid packet length %u "
  1231. "(expected %zu)\n", pkt_len, sizeof(crq));
  1232. set_protocol_stall(udc, ep);
  1233. return;
  1234. }
  1235. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1236. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1237. /* Free up one bank in the FIFO so that we can
  1238. * generate or receive a reply right away. */
  1239. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1240. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1241. ep->state, crq.crq.bRequestType,
  1242. crq.crq.bRequest); */
  1243. if (crq.crq.bRequestType & USB_DIR_IN) {
  1244. /*
  1245. * The USB 2.0 spec states that "if wLength is
  1246. * zero, there is no data transfer phase."
  1247. * However, testusb #14 seems to actually
  1248. * expect a data phase even if wLength = 0...
  1249. */
  1250. ep->state = DATA_STAGE_IN;
  1251. } else {
  1252. if (crq.crq.wLength != cpu_to_le16(0))
  1253. ep->state = DATA_STAGE_OUT;
  1254. else
  1255. ep->state = STATUS_STAGE_IN;
  1256. }
  1257. ret = -1;
  1258. if (ep->index == 0)
  1259. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1260. else {
  1261. spin_unlock(&udc->lock);
  1262. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1263. spin_lock(&udc->lock);
  1264. }
  1265. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1266. crq.crq.bRequestType, crq.crq.bRequest,
  1267. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1268. if (ret < 0) {
  1269. /* Let the host know that we failed */
  1270. set_protocol_stall(udc, ep);
  1271. }
  1272. }
  1273. }
  1274. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1275. {
  1276. struct usba_request *req;
  1277. u32 epstatus;
  1278. u32 epctrl;
  1279. epstatus = usba_ep_readl(ep, STA);
  1280. epctrl = usba_ep_readl(ep, CTL);
  1281. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1282. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1283. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1284. if (list_empty(&ep->queue)) {
  1285. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1286. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1287. return;
  1288. }
  1289. req = list_entry(ep->queue.next, struct usba_request, queue);
  1290. if (req->using_dma) {
  1291. /* Send a zero-length packet */
  1292. usba_ep_writel(ep, SET_STA,
  1293. USBA_TX_PK_RDY);
  1294. usba_ep_writel(ep, CTL_DIS,
  1295. USBA_TX_PK_RDY);
  1296. list_del_init(&req->queue);
  1297. submit_next_request(ep);
  1298. request_complete(ep, req, 0);
  1299. } else {
  1300. if (req->submitted)
  1301. next_fifo_transaction(ep, req);
  1302. else
  1303. submit_request(ep, req);
  1304. if (req->last_transaction) {
  1305. list_del_init(&req->queue);
  1306. submit_next_request(ep);
  1307. request_complete(ep, req, 0);
  1308. }
  1309. }
  1310. epstatus = usba_ep_readl(ep, STA);
  1311. epctrl = usba_ep_readl(ep, CTL);
  1312. }
  1313. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1314. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1315. receive_data(ep);
  1316. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1317. }
  1318. }
  1319. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1320. {
  1321. struct usba_request *req;
  1322. u32 status, control, pending;
  1323. status = usba_dma_readl(ep, STATUS);
  1324. control = usba_dma_readl(ep, CONTROL);
  1325. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1326. ep->last_dma_status = status;
  1327. #endif
  1328. pending = status & control;
  1329. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1330. if (status & USBA_DMA_CH_EN) {
  1331. dev_err(&udc->pdev->dev,
  1332. "DMA_CH_EN is set after transfer is finished!\n");
  1333. dev_err(&udc->pdev->dev,
  1334. "status=%#08x, pending=%#08x, control=%#08x\n",
  1335. status, pending, control);
  1336. /*
  1337. * try to pretend nothing happened. We might have to
  1338. * do something here...
  1339. */
  1340. }
  1341. if (list_empty(&ep->queue))
  1342. /* Might happen if a reset comes along at the right moment */
  1343. return;
  1344. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1345. req = list_entry(ep->queue.next, struct usba_request, queue);
  1346. usba_update_req(ep, req, status);
  1347. list_del_init(&req->queue);
  1348. submit_next_request(ep);
  1349. request_complete(ep, req, 0);
  1350. }
  1351. }
  1352. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1353. {
  1354. struct usba_udc *udc = devid;
  1355. u32 status;
  1356. u32 dma_status;
  1357. u32 ep_status;
  1358. spin_lock(&udc->lock);
  1359. status = usba_readl(udc, INT_STA);
  1360. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1361. if (status & USBA_DET_SUSPEND) {
  1362. toggle_bias(0);
  1363. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1364. DBG(DBG_BUS, "Suspend detected\n");
  1365. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1366. && udc->driver && udc->driver->suspend) {
  1367. spin_unlock(&udc->lock);
  1368. udc->driver->suspend(&udc->gadget);
  1369. spin_lock(&udc->lock);
  1370. }
  1371. }
  1372. if (status & USBA_WAKE_UP) {
  1373. toggle_bias(1);
  1374. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1375. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1376. }
  1377. if (status & USBA_END_OF_RESUME) {
  1378. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1379. DBG(DBG_BUS, "Resume detected\n");
  1380. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1381. && udc->driver && udc->driver->resume) {
  1382. spin_unlock(&udc->lock);
  1383. udc->driver->resume(&udc->gadget);
  1384. spin_lock(&udc->lock);
  1385. }
  1386. }
  1387. dma_status = USBA_BFEXT(DMA_INT, status);
  1388. if (dma_status) {
  1389. int i;
  1390. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1391. if (dma_status & (1 << i))
  1392. usba_dma_irq(udc, &usba_ep[i]);
  1393. }
  1394. ep_status = USBA_BFEXT(EPT_INT, status);
  1395. if (ep_status) {
  1396. int i;
  1397. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1398. if (ep_status & (1 << i)) {
  1399. if (ep_is_control(&usba_ep[i]))
  1400. usba_control_irq(udc, &usba_ep[i]);
  1401. else
  1402. usba_ep_irq(udc, &usba_ep[i]);
  1403. }
  1404. }
  1405. if (status & USBA_END_OF_RESET) {
  1406. struct usba_ep *ep0;
  1407. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1408. reset_all_endpoints(udc);
  1409. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1410. && udc->driver->disconnect) {
  1411. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1412. spin_unlock(&udc->lock);
  1413. udc->driver->disconnect(&udc->gadget);
  1414. spin_lock(&udc->lock);
  1415. }
  1416. if (status & USBA_HIGH_SPEED)
  1417. udc->gadget.speed = USB_SPEED_HIGH;
  1418. else
  1419. udc->gadget.speed = USB_SPEED_FULL;
  1420. DBG(DBG_BUS, "%s bus reset detected\n",
  1421. usb_speed_string(udc->gadget.speed));
  1422. ep0 = &usba_ep[0];
  1423. ep0->ep.desc = &usba_ep0_desc;
  1424. ep0->state = WAIT_FOR_SETUP;
  1425. usba_ep_writel(ep0, CFG,
  1426. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1427. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1428. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1429. usba_ep_writel(ep0, CTL_ENB,
  1430. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1431. usba_writel(udc, INT_ENB,
  1432. (usba_readl(udc, INT_ENB)
  1433. | USBA_BF(EPT_INT, 1)
  1434. | USBA_DET_SUSPEND
  1435. | USBA_END_OF_RESUME));
  1436. /*
  1437. * Unclear why we hit this irregularly, e.g. in usbtest,
  1438. * but it's clearly harmless...
  1439. */
  1440. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1441. dev_dbg(&udc->pdev->dev,
  1442. "ODD: EP0 configuration is invalid!\n");
  1443. }
  1444. spin_unlock(&udc->lock);
  1445. return IRQ_HANDLED;
  1446. }
  1447. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1448. {
  1449. struct usba_udc *udc = devid;
  1450. int vbus;
  1451. /* debounce */
  1452. udelay(10);
  1453. spin_lock(&udc->lock);
  1454. /* May happen if Vbus pin toggles during probe() */
  1455. if (!udc->driver)
  1456. goto out;
  1457. vbus = vbus_is_present(udc);
  1458. if (vbus != udc->vbus_prev) {
  1459. if (vbus) {
  1460. toggle_bias(1);
  1461. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1462. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1463. } else {
  1464. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1465. reset_all_endpoints(udc);
  1466. toggle_bias(0);
  1467. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1468. if (udc->driver->disconnect) {
  1469. spin_unlock(&udc->lock);
  1470. udc->driver->disconnect(&udc->gadget);
  1471. spin_lock(&udc->lock);
  1472. }
  1473. }
  1474. udc->vbus_prev = vbus;
  1475. }
  1476. out:
  1477. spin_unlock(&udc->lock);
  1478. return IRQ_HANDLED;
  1479. }
  1480. static int atmel_usba_start(struct usb_gadget *gadget,
  1481. struct usb_gadget_driver *driver)
  1482. {
  1483. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1484. unsigned long flags;
  1485. spin_lock_irqsave(&udc->lock, flags);
  1486. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1487. udc->driver = driver;
  1488. spin_unlock_irqrestore(&udc->lock, flags);
  1489. clk_enable(udc->pclk);
  1490. clk_enable(udc->hclk);
  1491. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1492. udc->vbus_prev = 0;
  1493. if (gpio_is_valid(udc->vbus_pin))
  1494. enable_irq(gpio_to_irq(udc->vbus_pin));
  1495. /* If Vbus is present, enable the controller and wait for reset */
  1496. spin_lock_irqsave(&udc->lock, flags);
  1497. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1498. toggle_bias(1);
  1499. usba_writel(udc, CTRL, USBA_ENABLE_MASK);
  1500. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1501. }
  1502. spin_unlock_irqrestore(&udc->lock, flags);
  1503. return 0;
  1504. }
  1505. static int atmel_usba_stop(struct usb_gadget *gadget,
  1506. struct usb_gadget_driver *driver)
  1507. {
  1508. struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
  1509. unsigned long flags;
  1510. if (gpio_is_valid(udc->vbus_pin))
  1511. disable_irq(gpio_to_irq(udc->vbus_pin));
  1512. spin_lock_irqsave(&udc->lock, flags);
  1513. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1514. reset_all_endpoints(udc);
  1515. spin_unlock_irqrestore(&udc->lock, flags);
  1516. /* This will also disable the DP pullup */
  1517. toggle_bias(0);
  1518. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1519. udc->driver = NULL;
  1520. clk_disable(udc->hclk);
  1521. clk_disable(udc->pclk);
  1522. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1523. return 0;
  1524. }
  1525. static int __init usba_udc_probe(struct platform_device *pdev)
  1526. {
  1527. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1528. struct resource *regs, *fifo;
  1529. struct clk *pclk, *hclk;
  1530. struct usba_udc *udc = &the_udc;
  1531. int irq, ret, i;
  1532. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1533. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1534. if (!regs || !fifo || !pdata)
  1535. return -ENXIO;
  1536. irq = platform_get_irq(pdev, 0);
  1537. if (irq < 0)
  1538. return irq;
  1539. pclk = clk_get(&pdev->dev, "pclk");
  1540. if (IS_ERR(pclk))
  1541. return PTR_ERR(pclk);
  1542. hclk = clk_get(&pdev->dev, "hclk");
  1543. if (IS_ERR(hclk)) {
  1544. ret = PTR_ERR(hclk);
  1545. goto err_get_hclk;
  1546. }
  1547. spin_lock_init(&udc->lock);
  1548. udc->pdev = pdev;
  1549. udc->pclk = pclk;
  1550. udc->hclk = hclk;
  1551. udc->vbus_pin = -ENODEV;
  1552. ret = -ENOMEM;
  1553. udc->regs = ioremap(regs->start, resource_size(regs));
  1554. if (!udc->regs) {
  1555. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1556. goto err_map_regs;
  1557. }
  1558. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1559. (unsigned long)regs->start, udc->regs);
  1560. udc->fifo = ioremap(fifo->start, resource_size(fifo));
  1561. if (!udc->fifo) {
  1562. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1563. goto err_map_fifo;
  1564. }
  1565. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1566. (unsigned long)fifo->start, udc->fifo);
  1567. platform_set_drvdata(pdev, udc);
  1568. /* Make sure we start from a clean slate */
  1569. clk_enable(pclk);
  1570. toggle_bias(0);
  1571. usba_writel(udc, CTRL, USBA_DISABLE_MASK);
  1572. clk_disable(pclk);
  1573. usba_ep = kzalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1574. GFP_KERNEL);
  1575. if (!usba_ep)
  1576. goto err_alloc_ep;
  1577. the_udc.gadget.ep0 = &usba_ep[0].ep;
  1578. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1579. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1580. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1581. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1582. usba_ep[0].ep.ops = &usba_ep_ops;
  1583. usba_ep[0].ep.name = pdata->ep[0].name;
  1584. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1585. usba_ep[0].udc = &the_udc;
  1586. INIT_LIST_HEAD(&usba_ep[0].queue);
  1587. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1588. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1589. usba_ep[0].index = pdata->ep[0].index;
  1590. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1591. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1592. for (i = 1; i < pdata->num_ep; i++) {
  1593. struct usba_ep *ep = &usba_ep[i];
  1594. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1595. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1596. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1597. ep->ep.ops = &usba_ep_ops;
  1598. ep->ep.name = pdata->ep[i].name;
  1599. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1600. ep->udc = &the_udc;
  1601. INIT_LIST_HEAD(&ep->queue);
  1602. ep->fifo_size = pdata->ep[i].fifo_size;
  1603. ep->nr_banks = pdata->ep[i].nr_banks;
  1604. ep->index = pdata->ep[i].index;
  1605. ep->can_dma = pdata->ep[i].can_dma;
  1606. ep->can_isoc = pdata->ep[i].can_isoc;
  1607. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1608. }
  1609. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1610. if (ret) {
  1611. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1612. irq, ret);
  1613. goto err_request_irq;
  1614. }
  1615. udc->irq = irq;
  1616. if (gpio_is_valid(pdata->vbus_pin)) {
  1617. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1618. udc->vbus_pin = pdata->vbus_pin;
  1619. udc->vbus_pin_inverted = pdata->vbus_pin_inverted;
  1620. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1621. usba_vbus_irq, 0,
  1622. "atmel_usba_udc", udc);
  1623. if (ret) {
  1624. gpio_free(udc->vbus_pin);
  1625. udc->vbus_pin = -ENODEV;
  1626. dev_warn(&udc->pdev->dev,
  1627. "failed to request vbus irq; "
  1628. "assuming always on\n");
  1629. } else {
  1630. disable_irq(gpio_to_irq(udc->vbus_pin));
  1631. }
  1632. } else {
  1633. /* gpio_request fail so use -EINVAL for gpio_is_valid */
  1634. udc->vbus_pin = -EINVAL;
  1635. }
  1636. }
  1637. ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
  1638. if (ret)
  1639. goto err_add_udc;
  1640. usba_init_debugfs(udc);
  1641. for (i = 1; i < pdata->num_ep; i++)
  1642. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1643. return 0;
  1644. err_add_udc:
  1645. if (gpio_is_valid(pdata->vbus_pin)) {
  1646. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1647. gpio_free(udc->vbus_pin);
  1648. }
  1649. free_irq(irq, udc);
  1650. err_request_irq:
  1651. kfree(usba_ep);
  1652. err_alloc_ep:
  1653. iounmap(udc->fifo);
  1654. err_map_fifo:
  1655. iounmap(udc->regs);
  1656. err_map_regs:
  1657. clk_put(hclk);
  1658. err_get_hclk:
  1659. clk_put(pclk);
  1660. return ret;
  1661. }
  1662. static int __exit usba_udc_remove(struct platform_device *pdev)
  1663. {
  1664. struct usba_udc *udc;
  1665. int i;
  1666. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1667. udc = platform_get_drvdata(pdev);
  1668. usb_del_gadget_udc(&udc->gadget);
  1669. for (i = 1; i < pdata->num_ep; i++)
  1670. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1671. usba_cleanup_debugfs(udc);
  1672. if (gpio_is_valid(udc->vbus_pin)) {
  1673. free_irq(gpio_to_irq(udc->vbus_pin), udc);
  1674. gpio_free(udc->vbus_pin);
  1675. }
  1676. free_irq(udc->irq, udc);
  1677. kfree(usba_ep);
  1678. iounmap(udc->fifo);
  1679. iounmap(udc->regs);
  1680. clk_put(udc->hclk);
  1681. clk_put(udc->pclk);
  1682. return 0;
  1683. }
  1684. static struct platform_driver udc_driver = {
  1685. .remove = __exit_p(usba_udc_remove),
  1686. .driver = {
  1687. .name = "atmel_usba_udc",
  1688. .owner = THIS_MODULE,
  1689. },
  1690. };
  1691. module_platform_driver_probe(udc_driver, usba_udc_probe);
  1692. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1693. MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
  1694. MODULE_LICENSE("GPL");
  1695. MODULE_ALIAS("platform:atmel_usba_udc");