pci.c 19 KB

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  1. /*
  2. * pci.c - Low-Level PCI Access in IA-64
  3. *
  4. * Derived from bios32.c of i386 tree.
  5. *
  6. * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
  7. * David Mosberger-Tang <davidm@hpl.hp.com>
  8. * Bjorn Helgaas <bjorn.helgaas@hp.com>
  9. * Copyright (C) 2004 Silicon Graphics, Inc.
  10. *
  11. * Note: Above list of copyright holders is incomplete...
  12. */
  13. #include <linux/config.h>
  14. #include <linux/acpi.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/smp_lock.h>
  22. #include <linux/spinlock.h>
  23. #include <asm/machvec.h>
  24. #include <asm/page.h>
  25. #include <asm/system.h>
  26. #include <asm/io.h>
  27. #include <asm/sal.h>
  28. #include <asm/smp.h>
  29. #include <asm/irq.h>
  30. #include <asm/hw_irq.h>
  31. /*
  32. * Low-level SAL-based PCI configuration access functions. Note that SAL
  33. * calls are already serialized (via sal_lock), so we don't need another
  34. * synchronization mechanism here.
  35. */
  36. #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
  37. (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  38. /* SAL 3.2 adds support for extended config space. */
  39. #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
  40. (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  41. static int
  42. pci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn,
  43. int reg, int len, u32 *value)
  44. {
  45. u64 addr, data = 0;
  46. int mode, result;
  47. if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  48. return -EINVAL;
  49. if ((seg | reg) <= 255) {
  50. addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  51. mode = 0;
  52. } else {
  53. addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  54. mode = 1;
  55. }
  56. result = ia64_sal_pci_config_read(addr, mode, len, &data);
  57. if (result != 0)
  58. return -EINVAL;
  59. *value = (u32) data;
  60. return 0;
  61. }
  62. static int
  63. pci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn,
  64. int reg, int len, u32 value)
  65. {
  66. u64 addr;
  67. int mode, result;
  68. if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  69. return -EINVAL;
  70. if ((seg | reg) <= 255) {
  71. addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  72. mode = 0;
  73. } else {
  74. addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  75. mode = 1;
  76. }
  77. result = ia64_sal_pci_config_write(addr, mode, len, value);
  78. if (result != 0)
  79. return -EINVAL;
  80. return 0;
  81. }
  82. static struct pci_raw_ops pci_sal_ops = {
  83. .read = pci_sal_read,
  84. .write = pci_sal_write
  85. };
  86. struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;
  87. static int
  88. pci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
  89. {
  90. return raw_pci_ops->read(pci_domain_nr(bus), bus->number,
  91. devfn, where, size, value);
  92. }
  93. static int
  94. pci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
  95. {
  96. return raw_pci_ops->write(pci_domain_nr(bus), bus->number,
  97. devfn, where, size, value);
  98. }
  99. struct pci_ops pci_root_ops = {
  100. .read = pci_read,
  101. .write = pci_write,
  102. };
  103. /* Called by ACPI when it finds a new root bus. */
  104. static struct pci_controller * __devinit
  105. alloc_pci_controller (int seg)
  106. {
  107. struct pci_controller *controller;
  108. controller = kmalloc(sizeof(*controller), GFP_KERNEL);
  109. if (!controller)
  110. return NULL;
  111. memset(controller, 0, sizeof(*controller));
  112. controller->segment = seg;
  113. controller->node = -1;
  114. return controller;
  115. }
  116. struct pci_root_info {
  117. struct pci_controller *controller;
  118. char *name;
  119. };
  120. static unsigned int
  121. new_space (u64 phys_base, int sparse)
  122. {
  123. u64 mmio_base;
  124. int i;
  125. if (phys_base == 0)
  126. return 0; /* legacy I/O port space */
  127. mmio_base = (u64) ioremap(phys_base, 0);
  128. for (i = 0; i < num_io_spaces; i++)
  129. if (io_space[i].mmio_base == mmio_base &&
  130. io_space[i].sparse == sparse)
  131. return i;
  132. if (num_io_spaces == MAX_IO_SPACES) {
  133. printk(KERN_ERR "PCI: Too many IO port spaces "
  134. "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
  135. return ~0;
  136. }
  137. i = num_io_spaces++;
  138. io_space[i].mmio_base = mmio_base;
  139. io_space[i].sparse = sparse;
  140. return i;
  141. }
  142. static u64 __devinit
  143. add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
  144. {
  145. struct resource *resource;
  146. char *name;
  147. u64 base, min, max, base_port;
  148. unsigned int sparse = 0, space_nr, len;
  149. resource = kzalloc(sizeof(*resource), GFP_KERNEL);
  150. if (!resource) {
  151. printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
  152. info->name);
  153. goto out;
  154. }
  155. len = strlen(info->name) + 32;
  156. name = kzalloc(len, GFP_KERNEL);
  157. if (!name) {
  158. printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
  159. info->name);
  160. goto free_resource;
  161. }
  162. min = addr->min_address_range;
  163. max = min + addr->address_length - 1;
  164. if (addr->attribute.io.translation_attribute == ACPI_SPARSE_TRANSLATION)
  165. sparse = 1;
  166. space_nr = new_space(addr->address_translation_offset, sparse);
  167. if (space_nr == ~0)
  168. goto free_name;
  169. base = __pa(io_space[space_nr].mmio_base);
  170. base_port = IO_SPACE_BASE(space_nr);
  171. snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
  172. base_port + min, base_port + max);
  173. /*
  174. * The SDM guarantees the legacy 0-64K space is sparse, but if the
  175. * mapping is done by the processor (not the bridge), ACPI may not
  176. * mark it as sparse.
  177. */
  178. if (space_nr == 0)
  179. sparse = 1;
  180. resource->name = name;
  181. resource->flags = IORESOURCE_MEM;
  182. resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
  183. resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
  184. insert_resource(&iomem_resource, resource);
  185. return base_port;
  186. free_name:
  187. kfree(name);
  188. free_resource:
  189. kfree(resource);
  190. out:
  191. return ~0;
  192. }
  193. static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
  194. struct acpi_resource_address64 *addr)
  195. {
  196. acpi_status status;
  197. /*
  198. * We're only interested in _CRS descriptors that are
  199. * - address space descriptors for memory or I/O space
  200. * - non-zero size
  201. * - producers, i.e., the address space is routed downstream,
  202. * not consumed by the bridge itself
  203. */
  204. status = acpi_resource_to_address64(resource, addr);
  205. if (ACPI_SUCCESS(status) &&
  206. (addr->resource_type == ACPI_MEMORY_RANGE ||
  207. addr->resource_type == ACPI_IO_RANGE) &&
  208. addr->address_length &&
  209. addr->producer_consumer == ACPI_PRODUCER)
  210. return AE_OK;
  211. return AE_ERROR;
  212. }
  213. static acpi_status __devinit
  214. count_window (struct acpi_resource *resource, void *data)
  215. {
  216. unsigned int *windows = (unsigned int *) data;
  217. struct acpi_resource_address64 addr;
  218. acpi_status status;
  219. status = resource_to_window(resource, &addr);
  220. if (ACPI_SUCCESS(status))
  221. (*windows)++;
  222. return AE_OK;
  223. }
  224. static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
  225. {
  226. struct pci_root_info *info = data;
  227. struct pci_window *window;
  228. struct acpi_resource_address64 addr;
  229. acpi_status status;
  230. unsigned long flags, offset = 0;
  231. struct resource *root;
  232. /* Return AE_OK for non-window resources to keep scanning for more */
  233. status = resource_to_window(res, &addr);
  234. if (!ACPI_SUCCESS(status))
  235. return AE_OK;
  236. if (addr.resource_type == ACPI_MEMORY_RANGE) {
  237. flags = IORESOURCE_MEM;
  238. root = &iomem_resource;
  239. offset = addr.address_translation_offset;
  240. } else if (addr.resource_type == ACPI_IO_RANGE) {
  241. flags = IORESOURCE_IO;
  242. root = &ioport_resource;
  243. offset = add_io_space(info, &addr);
  244. if (offset == ~0)
  245. return AE_OK;
  246. } else
  247. return AE_OK;
  248. window = &info->controller->window[info->controller->windows++];
  249. window->resource.name = info->name;
  250. window->resource.flags = flags;
  251. window->resource.start = addr.min_address_range + offset;
  252. window->resource.end = window->resource.start + addr.address_length - 1;
  253. window->resource.child = NULL;
  254. window->offset = offset;
  255. if (insert_resource(root, &window->resource)) {
  256. printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n",
  257. window->resource.start, window->resource.end,
  258. root->name, info->name);
  259. }
  260. return AE_OK;
  261. }
  262. static void __devinit
  263. pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
  264. {
  265. int i, j;
  266. j = 0;
  267. for (i = 0; i < ctrl->windows; i++) {
  268. struct resource *res = &ctrl->window[i].resource;
  269. /* HP's firmware has a hack to work around a Windows bug.
  270. * Ignore these tiny memory ranges */
  271. if ((res->flags & IORESOURCE_MEM) &&
  272. (res->end - res->start < 16))
  273. continue;
  274. if (j >= PCI_BUS_NUM_RESOURCES) {
  275. printk("Ignoring range [%lx-%lx] (%lx)\n", res->start,
  276. res->end, res->flags);
  277. continue;
  278. }
  279. bus->resource[j++] = res;
  280. }
  281. }
  282. struct pci_bus * __devinit
  283. pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
  284. {
  285. struct pci_root_info info;
  286. struct pci_controller *controller;
  287. unsigned int windows = 0;
  288. struct pci_bus *pbus;
  289. char *name;
  290. int pxm;
  291. controller = alloc_pci_controller(domain);
  292. if (!controller)
  293. goto out1;
  294. controller->acpi_handle = device->handle;
  295. pxm = acpi_get_pxm(controller->acpi_handle);
  296. #ifdef CONFIG_NUMA
  297. if (pxm >= 0)
  298. controller->node = pxm_to_nid_map[pxm];
  299. #endif
  300. acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
  301. &windows);
  302. controller->window = kmalloc_node(sizeof(*controller->window) * windows,
  303. GFP_KERNEL, controller->node);
  304. if (!controller->window)
  305. goto out2;
  306. name = kmalloc(16, GFP_KERNEL);
  307. if (!name)
  308. goto out3;
  309. sprintf(name, "PCI Bus %04x:%02x", domain, bus);
  310. info.controller = controller;
  311. info.name = name;
  312. acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window,
  313. &info);
  314. pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
  315. if (pbus)
  316. pcibios_setup_root_windows(pbus, controller);
  317. return pbus;
  318. out3:
  319. kfree(controller->window);
  320. out2:
  321. kfree(controller);
  322. out1:
  323. return NULL;
  324. }
  325. void pcibios_resource_to_bus(struct pci_dev *dev,
  326. struct pci_bus_region *region, struct resource *res)
  327. {
  328. struct pci_controller *controller = PCI_CONTROLLER(dev);
  329. unsigned long offset = 0;
  330. int i;
  331. for (i = 0; i < controller->windows; i++) {
  332. struct pci_window *window = &controller->window[i];
  333. if (!(window->resource.flags & res->flags))
  334. continue;
  335. if (window->resource.start > res->start)
  336. continue;
  337. if (window->resource.end < res->end)
  338. continue;
  339. offset = window->offset;
  340. break;
  341. }
  342. region->start = res->start - offset;
  343. region->end = res->end - offset;
  344. }
  345. EXPORT_SYMBOL(pcibios_resource_to_bus);
  346. void pcibios_bus_to_resource(struct pci_dev *dev,
  347. struct resource *res, struct pci_bus_region *region)
  348. {
  349. struct pci_controller *controller = PCI_CONTROLLER(dev);
  350. unsigned long offset = 0;
  351. int i;
  352. for (i = 0; i < controller->windows; i++) {
  353. struct pci_window *window = &controller->window[i];
  354. if (!(window->resource.flags & res->flags))
  355. continue;
  356. if (window->resource.start - window->offset > region->start)
  357. continue;
  358. if (window->resource.end - window->offset < region->end)
  359. continue;
  360. offset = window->offset;
  361. break;
  362. }
  363. res->start = region->start + offset;
  364. res->end = region->end + offset;
  365. }
  366. EXPORT_SYMBOL(pcibios_bus_to_resource);
  367. static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
  368. {
  369. unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
  370. struct resource *devr = &dev->resource[idx];
  371. if (!dev->bus)
  372. return 0;
  373. for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
  374. struct resource *busr = dev->bus->resource[i];
  375. if (!busr || ((busr->flags ^ devr->flags) & type_mask))
  376. continue;
  377. if ((devr->start) && (devr->start >= busr->start) &&
  378. (devr->end <= busr->end))
  379. return 1;
  380. }
  381. return 0;
  382. }
  383. static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
  384. {
  385. struct pci_bus_region region;
  386. int i;
  387. int limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ? \
  388. PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
  389. for (i = 0; i < limit; i++) {
  390. if (!dev->resource[i].flags)
  391. continue;
  392. region.start = dev->resource[i].start;
  393. region.end = dev->resource[i].end;
  394. pcibios_bus_to_resource(dev, &dev->resource[i], &region);
  395. if ((is_valid_resource(dev, i)))
  396. pci_claim_resource(dev, i);
  397. }
  398. }
  399. /*
  400. * Called after each bus is probed, but before its children are examined.
  401. */
  402. void __devinit
  403. pcibios_fixup_bus (struct pci_bus *b)
  404. {
  405. struct pci_dev *dev;
  406. if (b->self) {
  407. pci_read_bridge_bases(b);
  408. pcibios_fixup_device_resources(b->self);
  409. }
  410. list_for_each_entry(dev, &b->devices, bus_list)
  411. pcibios_fixup_device_resources(dev);
  412. return;
  413. }
  414. void __devinit
  415. pcibios_update_irq (struct pci_dev *dev, int irq)
  416. {
  417. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
  418. /* ??? FIXME -- record old value for shutdown. */
  419. }
  420. static inline int
  421. pcibios_enable_resources (struct pci_dev *dev, int mask)
  422. {
  423. u16 cmd, old_cmd;
  424. int idx;
  425. struct resource *r;
  426. unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
  427. if (!dev)
  428. return -EINVAL;
  429. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  430. old_cmd = cmd;
  431. for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
  432. /* Only set up the desired resources. */
  433. if (!(mask & (1 << idx)))
  434. continue;
  435. r = &dev->resource[idx];
  436. if (!(r->flags & type_mask))
  437. continue;
  438. if ((idx == PCI_ROM_RESOURCE) &&
  439. (!(r->flags & IORESOURCE_ROM_ENABLE)))
  440. continue;
  441. if (!r->start && r->end) {
  442. printk(KERN_ERR
  443. "PCI: Device %s not available because of resource collisions\n",
  444. pci_name(dev));
  445. return -EINVAL;
  446. }
  447. if (r->flags & IORESOURCE_IO)
  448. cmd |= PCI_COMMAND_IO;
  449. if (r->flags & IORESOURCE_MEM)
  450. cmd |= PCI_COMMAND_MEMORY;
  451. }
  452. if (cmd != old_cmd) {
  453. printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
  454. pci_write_config_word(dev, PCI_COMMAND, cmd);
  455. }
  456. return 0;
  457. }
  458. int
  459. pcibios_enable_device (struct pci_dev *dev, int mask)
  460. {
  461. int ret;
  462. ret = pcibios_enable_resources(dev, mask);
  463. if (ret < 0)
  464. return ret;
  465. return acpi_pci_irq_enable(dev);
  466. }
  467. void
  468. pcibios_disable_device (struct pci_dev *dev)
  469. {
  470. acpi_pci_irq_disable(dev);
  471. }
  472. void
  473. pcibios_align_resource (void *data, struct resource *res,
  474. unsigned long size, unsigned long align)
  475. {
  476. }
  477. /*
  478. * PCI BIOS setup, always defaults to SAL interface
  479. */
  480. char * __init
  481. pcibios_setup (char *str)
  482. {
  483. return NULL;
  484. }
  485. int
  486. pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  487. enum pci_mmap_state mmap_state, int write_combine)
  488. {
  489. /*
  490. * I/O space cannot be accessed via normal processor loads and
  491. * stores on this platform.
  492. */
  493. if (mmap_state == pci_mmap_io)
  494. /*
  495. * XXX we could relax this for I/O spaces for which ACPI
  496. * indicates that the space is 1-to-1 mapped. But at the
  497. * moment, we don't support multiple PCI address spaces and
  498. * the legacy I/O space is not 1-to-1 mapped, so this is moot.
  499. */
  500. return -EINVAL;
  501. /*
  502. * Leave vm_pgoff as-is, the PCI space address is the physical
  503. * address on this platform.
  504. */
  505. vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
  506. if (write_combine && efi_range_is_wc(vma->vm_start,
  507. vma->vm_end - vma->vm_start))
  508. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  509. else
  510. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  511. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  512. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  513. return -EAGAIN;
  514. return 0;
  515. }
  516. /**
  517. * ia64_pci_get_legacy_mem - generic legacy mem routine
  518. * @bus: bus to get legacy memory base address for
  519. *
  520. * Find the base of legacy memory for @bus. This is typically the first
  521. * megabyte of bus address space for @bus or is simply 0 on platforms whose
  522. * chipsets support legacy I/O and memory routing. Returns the base address
  523. * or an error pointer if an error occurred.
  524. *
  525. * This is the ia64 generic version of this routine. Other platforms
  526. * are free to override it with a machine vector.
  527. */
  528. char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
  529. {
  530. return (char *)__IA64_UNCACHED_OFFSET;
  531. }
  532. /**
  533. * pci_mmap_legacy_page_range - map legacy memory space to userland
  534. * @bus: bus whose legacy space we're mapping
  535. * @vma: vma passed in by mmap
  536. *
  537. * Map legacy memory space for this device back to userspace using a machine
  538. * vector to get the base address.
  539. */
  540. int
  541. pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma)
  542. {
  543. char *addr;
  544. addr = pci_get_legacy_mem(bus);
  545. if (IS_ERR(addr))
  546. return PTR_ERR(addr);
  547. vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
  548. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  549. vma->vm_flags |= (VM_SHM | VM_RESERVED | VM_IO);
  550. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  551. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  552. return -EAGAIN;
  553. return 0;
  554. }
  555. /**
  556. * ia64_pci_legacy_read - read from legacy I/O space
  557. * @bus: bus to read
  558. * @port: legacy port value
  559. * @val: caller allocated storage for returned value
  560. * @size: number of bytes to read
  561. *
  562. * Simply reads @size bytes from @port and puts the result in @val.
  563. *
  564. * Again, this (and the write routine) are generic versions that can be
  565. * overridden by the platform. This is necessary on platforms that don't
  566. * support legacy I/O routing or that hard fail on legacy I/O timeouts.
  567. */
  568. int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
  569. {
  570. int ret = size;
  571. switch (size) {
  572. case 1:
  573. *val = inb(port);
  574. break;
  575. case 2:
  576. *val = inw(port);
  577. break;
  578. case 4:
  579. *val = inl(port);
  580. break;
  581. default:
  582. ret = -EINVAL;
  583. break;
  584. }
  585. return ret;
  586. }
  587. /**
  588. * ia64_pci_legacy_write - perform a legacy I/O write
  589. * @bus: bus pointer
  590. * @port: port to write
  591. * @val: value to write
  592. * @size: number of bytes to write from @val
  593. *
  594. * Simply writes @size bytes of @val to @port.
  595. */
  596. int ia64_pci_legacy_write(struct pci_dev *bus, u16 port, u32 val, u8 size)
  597. {
  598. int ret = size;
  599. switch (size) {
  600. case 1:
  601. outb(val, port);
  602. break;
  603. case 2:
  604. outw(val, port);
  605. break;
  606. case 4:
  607. outl(val, port);
  608. break;
  609. default:
  610. ret = -EINVAL;
  611. break;
  612. }
  613. return ret;
  614. }
  615. /**
  616. * pci_cacheline_size - determine cacheline size for PCI devices
  617. * @dev: void
  618. *
  619. * We want to use the line-size of the outer-most cache. We assume
  620. * that this line-size is the same for all CPUs.
  621. *
  622. * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
  623. *
  624. * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  625. */
  626. static unsigned long
  627. pci_cacheline_size (void)
  628. {
  629. u64 levels, unique_caches;
  630. s64 status;
  631. pal_cache_config_info_t cci;
  632. static u8 cacheline_size;
  633. if (cacheline_size)
  634. return cacheline_size;
  635. status = ia64_pal_cache_summary(&levels, &unique_caches);
  636. if (status != 0) {
  637. printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
  638. __FUNCTION__, status);
  639. return SMP_CACHE_BYTES;
  640. }
  641. status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
  642. &cci);
  643. if (status != 0) {
  644. printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
  645. __FUNCTION__, status);
  646. return SMP_CACHE_BYTES;
  647. }
  648. cacheline_size = 1 << cci.pcci_line_size;
  649. return cacheline_size;
  650. }
  651. /**
  652. * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
  653. * @dev: the PCI device for which MWI is enabled
  654. *
  655. * For ia64, we can get the cacheline sizes from PAL.
  656. *
  657. * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  658. */
  659. int
  660. pcibios_prep_mwi (struct pci_dev *dev)
  661. {
  662. unsigned long desired_linesize, current_linesize;
  663. int rc = 0;
  664. u8 pci_linesize;
  665. desired_linesize = pci_cacheline_size();
  666. pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
  667. current_linesize = 4 * pci_linesize;
  668. if (desired_linesize != current_linesize) {
  669. printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
  670. pci_name(dev), current_linesize);
  671. if (current_linesize > desired_linesize) {
  672. printk(" expected %lu bytes instead\n", desired_linesize);
  673. rc = -EINVAL;
  674. } else {
  675. printk(" correcting to %lu\n", desired_linesize);
  676. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
  677. }
  678. }
  679. return rc;
  680. }
  681. int pci_vector_resources(int last, int nr_released)
  682. {
  683. int count = nr_released;
  684. count += (IA64_LAST_DEVICE_VECTOR - last);
  685. return count;
  686. }