tg3.c 352 KB

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  1. /*
  2. * tg3.c: Broadcom Tigon3 ethernet driver.
  3. *
  4. * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
  5. * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
  6. * Copyright (C) 2004 Sun Microsystems Inc.
  7. * Copyright (C) 2005-2007 Broadcom Corporation.
  8. *
  9. * Firmware is:
  10. * Derived from proprietary unpublished source code,
  11. * Copyright (C) 2000-2003 Broadcom Corporation.
  12. *
  13. * Permission is hereby granted for the distribution of this firmware
  14. * data in hexadecimal or equivalent format, provided this copyright
  15. * notice is accompanying it.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/moduleparam.h>
  19. #include <linux/kernel.h>
  20. #include <linux/types.h>
  21. #include <linux/compiler.h>
  22. #include <linux/slab.h>
  23. #include <linux/delay.h>
  24. #include <linux/in.h>
  25. #include <linux/init.h>
  26. #include <linux/ioport.h>
  27. #include <linux/pci.h>
  28. #include <linux/netdevice.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/skbuff.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/mii.h>
  33. #include <linux/if_vlan.h>
  34. #include <linux/ip.h>
  35. #include <linux/tcp.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/prefetch.h>
  38. #include <linux/dma-mapping.h>
  39. #include <net/checksum.h>
  40. #include <net/ip.h>
  41. #include <asm/system.h>
  42. #include <asm/io.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/uaccess.h>
  45. #ifdef CONFIG_SPARC
  46. #include <asm/idprom.h>
  47. #include <asm/prom.h>
  48. #endif
  49. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  50. #define TG3_VLAN_TAG_USED 1
  51. #else
  52. #define TG3_VLAN_TAG_USED 0
  53. #endif
  54. #define TG3_TSO_SUPPORT 1
  55. #include "tg3.h"
  56. #define DRV_MODULE_NAME "tg3"
  57. #define PFX DRV_MODULE_NAME ": "
  58. #define DRV_MODULE_VERSION "3.82"
  59. #define DRV_MODULE_RELDATE "October 5, 2007"
  60. #define TG3_DEF_MAC_MODE 0
  61. #define TG3_DEF_RX_MODE 0
  62. #define TG3_DEF_TX_MODE 0
  63. #define TG3_DEF_MSG_ENABLE \
  64. (NETIF_MSG_DRV | \
  65. NETIF_MSG_PROBE | \
  66. NETIF_MSG_LINK | \
  67. NETIF_MSG_TIMER | \
  68. NETIF_MSG_IFDOWN | \
  69. NETIF_MSG_IFUP | \
  70. NETIF_MSG_RX_ERR | \
  71. NETIF_MSG_TX_ERR)
  72. /* length of time before we decide the hardware is borked,
  73. * and dev->tx_timeout() should be called to fix the problem
  74. */
  75. #define TG3_TX_TIMEOUT (5 * HZ)
  76. /* hardware minimum and maximum for a single frame's data payload */
  77. #define TG3_MIN_MTU 60
  78. #define TG3_MAX_MTU(tp) \
  79. ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  80. /* These numbers seem to be hard coded in the NIC firmware somehow.
  81. * You can't change the ring sizes, but you can change where you place
  82. * them in the NIC onboard memory.
  83. */
  84. #define TG3_RX_RING_SIZE 512
  85. #define TG3_DEF_RX_RING_PENDING 200
  86. #define TG3_RX_JUMBO_RING_SIZE 256
  87. #define TG3_DEF_RX_JUMBO_RING_PENDING 100
  88. /* Do not place this n-ring entries value into the tp struct itself,
  89. * we really want to expose these constants to GCC so that modulo et
  90. * al. operations are done with shifts and masks instead of with
  91. * hw multiply/modulo instructions. Another solution would be to
  92. * replace things like '% foo' with '& (foo - 1)'.
  93. */
  94. #define TG3_RX_RCB_RING_SIZE(tp) \
  95. ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
  96. #define TG3_TX_RING_SIZE 512
  97. #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
  98. #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  99. TG3_RX_RING_SIZE)
  100. #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
  101. TG3_RX_JUMBO_RING_SIZE)
  102. #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
  103. TG3_RX_RCB_RING_SIZE(tp))
  104. #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
  105. TG3_TX_RING_SIZE)
  106. #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
  107. #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
  108. #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
  109. /* minimum number of free TX descriptors required to wake up TX process */
  110. #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
  111. /* number of ETHTOOL_GSTATS u64's */
  112. #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
  113. #define TG3_NUM_TEST 6
  114. static char version[] __devinitdata =
  115. DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  116. MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
  117. MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
  118. MODULE_LICENSE("GPL");
  119. MODULE_VERSION(DRV_MODULE_VERSION);
  120. static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
  121. module_param(tg3_debug, int, 0);
  122. MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
  123. static struct pci_device_id tg3_pci_tbl[] = {
  124. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
  125. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
  126. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
  127. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
  128. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
  129. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
  130. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
  131. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
  132. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
  133. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
  134. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
  135. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
  153. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
  154. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
  155. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
  156. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
  157. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
  158. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
  159. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
  160. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
  161. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
  162. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
  163. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
  164. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
  165. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
  166. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
  167. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
  168. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
  169. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
  170. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
  171. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
  172. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
  173. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
  174. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
  175. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
  176. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
  177. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
  178. {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
  179. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
  180. {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
  181. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
  182. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
  183. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
  184. {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
  185. {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
  186. {}
  187. };
  188. MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
  189. static const struct {
  190. const char string[ETH_GSTRING_LEN];
  191. } ethtool_stats_keys[TG3_NUM_STATS] = {
  192. { "rx_octets" },
  193. { "rx_fragments" },
  194. { "rx_ucast_packets" },
  195. { "rx_mcast_packets" },
  196. { "rx_bcast_packets" },
  197. { "rx_fcs_errors" },
  198. { "rx_align_errors" },
  199. { "rx_xon_pause_rcvd" },
  200. { "rx_xoff_pause_rcvd" },
  201. { "rx_mac_ctrl_rcvd" },
  202. { "rx_xoff_entered" },
  203. { "rx_frame_too_long_errors" },
  204. { "rx_jabbers" },
  205. { "rx_undersize_packets" },
  206. { "rx_in_length_errors" },
  207. { "rx_out_length_errors" },
  208. { "rx_64_or_less_octet_packets" },
  209. { "rx_65_to_127_octet_packets" },
  210. { "rx_128_to_255_octet_packets" },
  211. { "rx_256_to_511_octet_packets" },
  212. { "rx_512_to_1023_octet_packets" },
  213. { "rx_1024_to_1522_octet_packets" },
  214. { "rx_1523_to_2047_octet_packets" },
  215. { "rx_2048_to_4095_octet_packets" },
  216. { "rx_4096_to_8191_octet_packets" },
  217. { "rx_8192_to_9022_octet_packets" },
  218. { "tx_octets" },
  219. { "tx_collisions" },
  220. { "tx_xon_sent" },
  221. { "tx_xoff_sent" },
  222. { "tx_flow_control" },
  223. { "tx_mac_errors" },
  224. { "tx_single_collisions" },
  225. { "tx_mult_collisions" },
  226. { "tx_deferred" },
  227. { "tx_excessive_collisions" },
  228. { "tx_late_collisions" },
  229. { "tx_collide_2times" },
  230. { "tx_collide_3times" },
  231. { "tx_collide_4times" },
  232. { "tx_collide_5times" },
  233. { "tx_collide_6times" },
  234. { "tx_collide_7times" },
  235. { "tx_collide_8times" },
  236. { "tx_collide_9times" },
  237. { "tx_collide_10times" },
  238. { "tx_collide_11times" },
  239. { "tx_collide_12times" },
  240. { "tx_collide_13times" },
  241. { "tx_collide_14times" },
  242. { "tx_collide_15times" },
  243. { "tx_ucast_packets" },
  244. { "tx_mcast_packets" },
  245. { "tx_bcast_packets" },
  246. { "tx_carrier_sense_errors" },
  247. { "tx_discards" },
  248. { "tx_errors" },
  249. { "dma_writeq_full" },
  250. { "dma_write_prioq_full" },
  251. { "rxbds_empty" },
  252. { "rx_discards" },
  253. { "rx_errors" },
  254. { "rx_threshold_hit" },
  255. { "dma_readq_full" },
  256. { "dma_read_prioq_full" },
  257. { "tx_comp_queue_full" },
  258. { "ring_set_send_prod_index" },
  259. { "ring_status_update" },
  260. { "nic_irqs" },
  261. { "nic_avoided_irqs" },
  262. { "nic_tx_threshold_hit" }
  263. };
  264. static const struct {
  265. const char string[ETH_GSTRING_LEN];
  266. } ethtool_test_keys[TG3_NUM_TEST] = {
  267. { "nvram test (online) " },
  268. { "link test (online) " },
  269. { "register test (offline)" },
  270. { "memory test (offline)" },
  271. { "loopback test (offline)" },
  272. { "interrupt test (offline)" },
  273. };
  274. static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
  275. {
  276. writel(val, tp->regs + off);
  277. }
  278. static u32 tg3_read32(struct tg3 *tp, u32 off)
  279. {
  280. return (readl(tp->regs + off));
  281. }
  282. static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
  283. {
  284. unsigned long flags;
  285. spin_lock_irqsave(&tp->indirect_lock, flags);
  286. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  287. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  288. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  289. }
  290. static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
  291. {
  292. writel(val, tp->regs + off);
  293. readl(tp->regs + off);
  294. }
  295. static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
  296. {
  297. unsigned long flags;
  298. u32 val;
  299. spin_lock_irqsave(&tp->indirect_lock, flags);
  300. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
  301. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  302. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  303. return val;
  304. }
  305. static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
  306. {
  307. unsigned long flags;
  308. if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
  309. pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
  310. TG3_64BIT_REG_LOW, val);
  311. return;
  312. }
  313. if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
  314. pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
  315. TG3_64BIT_REG_LOW, val);
  316. return;
  317. }
  318. spin_lock_irqsave(&tp->indirect_lock, flags);
  319. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  320. pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
  321. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  322. /* In indirect mode when disabling interrupts, we also need
  323. * to clear the interrupt bit in the GRC local ctrl register.
  324. */
  325. if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
  326. (val == 0x1)) {
  327. pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
  328. tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
  329. }
  330. }
  331. static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
  332. {
  333. unsigned long flags;
  334. u32 val;
  335. spin_lock_irqsave(&tp->indirect_lock, flags);
  336. pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
  337. pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
  338. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  339. return val;
  340. }
  341. /* usec_wait specifies the wait time in usec when writing to certain registers
  342. * where it is unsafe to read back the register without some delay.
  343. * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
  344. * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
  345. */
  346. static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
  347. {
  348. if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
  349. (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  350. /* Non-posted methods */
  351. tp->write32(tp, off, val);
  352. else {
  353. /* Posted method */
  354. tg3_write32(tp, off, val);
  355. if (usec_wait)
  356. udelay(usec_wait);
  357. tp->read32(tp, off);
  358. }
  359. /* Wait again after the read for the posted method to guarantee that
  360. * the wait time is met.
  361. */
  362. if (usec_wait)
  363. udelay(usec_wait);
  364. }
  365. static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
  366. {
  367. tp->write32_mbox(tp, off, val);
  368. if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
  369. !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
  370. tp->read32_mbox(tp, off);
  371. }
  372. static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
  373. {
  374. void __iomem *mbox = tp->regs + off;
  375. writel(val, mbox);
  376. if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
  377. writel(val, mbox);
  378. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  379. readl(mbox);
  380. }
  381. static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
  382. {
  383. return (readl(tp->regs + off + GRCMBOX_BASE));
  384. }
  385. static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
  386. {
  387. writel(val, tp->regs + off + GRCMBOX_BASE);
  388. }
  389. #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
  390. #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
  391. #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
  392. #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
  393. #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
  394. #define tw32(reg,val) tp->write32(tp, reg, val)
  395. #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
  396. #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
  397. #define tr32(reg) tp->read32(tp, reg)
  398. static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
  399. {
  400. unsigned long flags;
  401. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  402. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
  403. return;
  404. spin_lock_irqsave(&tp->indirect_lock, flags);
  405. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  406. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  407. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  408. /* Always leave this as zero. */
  409. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  410. } else {
  411. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  412. tw32_f(TG3PCI_MEM_WIN_DATA, val);
  413. /* Always leave this as zero. */
  414. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  415. }
  416. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  417. }
  418. static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
  419. {
  420. unsigned long flags;
  421. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
  422. (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
  423. *val = 0;
  424. return;
  425. }
  426. spin_lock_irqsave(&tp->indirect_lock, flags);
  427. if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
  428. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
  429. pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  430. /* Always leave this as zero. */
  431. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  432. } else {
  433. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
  434. *val = tr32(TG3PCI_MEM_WIN_DATA);
  435. /* Always leave this as zero. */
  436. tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  437. }
  438. spin_unlock_irqrestore(&tp->indirect_lock, flags);
  439. }
  440. static void tg3_disable_ints(struct tg3 *tp)
  441. {
  442. tw32(TG3PCI_MISC_HOST_CTRL,
  443. (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
  444. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  445. }
  446. static inline void tg3_cond_int(struct tg3 *tp)
  447. {
  448. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  449. (tp->hw_status->status & SD_STATUS_UPDATED))
  450. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  451. else
  452. tw32(HOSTCC_MODE, tp->coalesce_mode |
  453. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  454. }
  455. static void tg3_enable_ints(struct tg3 *tp)
  456. {
  457. tp->irq_sync = 0;
  458. wmb();
  459. tw32(TG3PCI_MISC_HOST_CTRL,
  460. (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
  461. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  462. (tp->last_tag << 24));
  463. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  464. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  465. (tp->last_tag << 24));
  466. tg3_cond_int(tp);
  467. }
  468. static inline unsigned int tg3_has_work(struct tg3 *tp)
  469. {
  470. struct tg3_hw_status *sblk = tp->hw_status;
  471. unsigned int work_exists = 0;
  472. /* check for phy events */
  473. if (!(tp->tg3_flags &
  474. (TG3_FLAG_USE_LINKCHG_REG |
  475. TG3_FLAG_POLL_SERDES))) {
  476. if (sblk->status & SD_STATUS_LINK_CHG)
  477. work_exists = 1;
  478. }
  479. /* check for RX/TX work to do */
  480. if (sblk->idx[0].tx_consumer != tp->tx_cons ||
  481. sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  482. work_exists = 1;
  483. return work_exists;
  484. }
  485. /* tg3_restart_ints
  486. * similar to tg3_enable_ints, but it accurately determines whether there
  487. * is new work pending and can return without flushing the PIO write
  488. * which reenables interrupts
  489. */
  490. static void tg3_restart_ints(struct tg3 *tp)
  491. {
  492. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  493. tp->last_tag << 24);
  494. mmiowb();
  495. /* When doing tagged status, this work check is unnecessary.
  496. * The last_tag we write above tells the chip which piece of
  497. * work we've completed.
  498. */
  499. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
  500. tg3_has_work(tp))
  501. tw32(HOSTCC_MODE, tp->coalesce_mode |
  502. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  503. }
  504. static inline void tg3_netif_stop(struct tg3 *tp)
  505. {
  506. tp->dev->trans_start = jiffies; /* prevent tx timeout */
  507. napi_disable(&tp->napi);
  508. netif_tx_disable(tp->dev);
  509. }
  510. static inline void tg3_netif_start(struct tg3 *tp)
  511. {
  512. netif_wake_queue(tp->dev);
  513. /* NOTE: unconditional netif_wake_queue is only appropriate
  514. * so long as all callers are assured to have free tx slots
  515. * (such as after tg3_init_hw)
  516. */
  517. napi_enable(&tp->napi);
  518. tp->hw_status->status |= SD_STATUS_UPDATED;
  519. tg3_enable_ints(tp);
  520. }
  521. static void tg3_switch_clocks(struct tg3 *tp)
  522. {
  523. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
  524. u32 orig_clock_ctrl;
  525. if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  526. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  527. return;
  528. orig_clock_ctrl = clock_ctrl;
  529. clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
  530. CLOCK_CTRL_CLKRUN_OENABLE |
  531. 0x1f);
  532. tp->pci_clock_ctrl = clock_ctrl;
  533. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  534. if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
  535. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  536. clock_ctrl | CLOCK_CTRL_625_CORE, 40);
  537. }
  538. } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
  539. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  540. clock_ctrl |
  541. (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
  542. 40);
  543. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  544. clock_ctrl | (CLOCK_CTRL_ALTCLK),
  545. 40);
  546. }
  547. tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
  548. }
  549. #define PHY_BUSY_LOOPS 5000
  550. static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  551. {
  552. u32 frame_val;
  553. unsigned int loops;
  554. int ret;
  555. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  556. tw32_f(MAC_MI_MODE,
  557. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  558. udelay(80);
  559. }
  560. *val = 0x0;
  561. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  562. MI_COM_PHY_ADDR_MASK);
  563. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  564. MI_COM_REG_ADDR_MASK);
  565. frame_val |= (MI_COM_CMD_READ | MI_COM_START);
  566. tw32_f(MAC_MI_COM, frame_val);
  567. loops = PHY_BUSY_LOOPS;
  568. while (loops != 0) {
  569. udelay(10);
  570. frame_val = tr32(MAC_MI_COM);
  571. if ((frame_val & MI_COM_BUSY) == 0) {
  572. udelay(5);
  573. frame_val = tr32(MAC_MI_COM);
  574. break;
  575. }
  576. loops -= 1;
  577. }
  578. ret = -EBUSY;
  579. if (loops != 0) {
  580. *val = frame_val & MI_COM_DATA_MASK;
  581. ret = 0;
  582. }
  583. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  584. tw32_f(MAC_MI_MODE, tp->mi_mode);
  585. udelay(80);
  586. }
  587. return ret;
  588. }
  589. static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
  590. {
  591. u32 frame_val;
  592. unsigned int loops;
  593. int ret;
  594. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
  595. (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
  596. return 0;
  597. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  598. tw32_f(MAC_MI_MODE,
  599. (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  600. udelay(80);
  601. }
  602. frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
  603. MI_COM_PHY_ADDR_MASK);
  604. frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
  605. MI_COM_REG_ADDR_MASK);
  606. frame_val |= (val & MI_COM_DATA_MASK);
  607. frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
  608. tw32_f(MAC_MI_COM, frame_val);
  609. loops = PHY_BUSY_LOOPS;
  610. while (loops != 0) {
  611. udelay(10);
  612. frame_val = tr32(MAC_MI_COM);
  613. if ((frame_val & MI_COM_BUSY) == 0) {
  614. udelay(5);
  615. frame_val = tr32(MAC_MI_COM);
  616. break;
  617. }
  618. loops -= 1;
  619. }
  620. ret = -EBUSY;
  621. if (loops != 0)
  622. ret = 0;
  623. if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  624. tw32_f(MAC_MI_MODE, tp->mi_mode);
  625. udelay(80);
  626. }
  627. return ret;
  628. }
  629. static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
  630. {
  631. u32 phy;
  632. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  633. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  634. return;
  635. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  636. u32 ephy;
  637. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
  638. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  639. ephy | MII_TG3_EPHY_SHADOW_EN);
  640. if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
  641. if (enable)
  642. phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
  643. else
  644. phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
  645. tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
  646. }
  647. tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
  648. }
  649. } else {
  650. phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
  651. MII_TG3_AUXCTL_SHDWSEL_MISC;
  652. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
  653. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
  654. if (enable)
  655. phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  656. else
  657. phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
  658. phy |= MII_TG3_AUXCTL_MISC_WREN;
  659. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
  660. }
  661. }
  662. }
  663. static void tg3_phy_set_wirespeed(struct tg3 *tp)
  664. {
  665. u32 val;
  666. if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
  667. return;
  668. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
  669. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
  670. tg3_writephy(tp, MII_TG3_AUX_CTRL,
  671. (val | (1 << 15) | (1 << 4)));
  672. }
  673. static int tg3_bmcr_reset(struct tg3 *tp)
  674. {
  675. u32 phy_control;
  676. int limit, err;
  677. /* OK, reset it, and poll the BMCR_RESET bit until it
  678. * clears or we time out.
  679. */
  680. phy_control = BMCR_RESET;
  681. err = tg3_writephy(tp, MII_BMCR, phy_control);
  682. if (err != 0)
  683. return -EBUSY;
  684. limit = 5000;
  685. while (limit--) {
  686. err = tg3_readphy(tp, MII_BMCR, &phy_control);
  687. if (err != 0)
  688. return -EBUSY;
  689. if ((phy_control & BMCR_RESET) == 0) {
  690. udelay(40);
  691. break;
  692. }
  693. udelay(10);
  694. }
  695. if (limit <= 0)
  696. return -EBUSY;
  697. return 0;
  698. }
  699. static int tg3_wait_macro_done(struct tg3 *tp)
  700. {
  701. int limit = 100;
  702. while (limit--) {
  703. u32 tmp32;
  704. if (!tg3_readphy(tp, 0x16, &tmp32)) {
  705. if ((tmp32 & 0x1000) == 0)
  706. break;
  707. }
  708. }
  709. if (limit <= 0)
  710. return -EBUSY;
  711. return 0;
  712. }
  713. static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
  714. {
  715. static const u32 test_pat[4][6] = {
  716. { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
  717. { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
  718. { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
  719. { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
  720. };
  721. int chan;
  722. for (chan = 0; chan < 4; chan++) {
  723. int i;
  724. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  725. (chan * 0x2000) | 0x0200);
  726. tg3_writephy(tp, 0x16, 0x0002);
  727. for (i = 0; i < 6; i++)
  728. tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
  729. test_pat[chan][i]);
  730. tg3_writephy(tp, 0x16, 0x0202);
  731. if (tg3_wait_macro_done(tp)) {
  732. *resetp = 1;
  733. return -EBUSY;
  734. }
  735. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  736. (chan * 0x2000) | 0x0200);
  737. tg3_writephy(tp, 0x16, 0x0082);
  738. if (tg3_wait_macro_done(tp)) {
  739. *resetp = 1;
  740. return -EBUSY;
  741. }
  742. tg3_writephy(tp, 0x16, 0x0802);
  743. if (tg3_wait_macro_done(tp)) {
  744. *resetp = 1;
  745. return -EBUSY;
  746. }
  747. for (i = 0; i < 6; i += 2) {
  748. u32 low, high;
  749. if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
  750. tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
  751. tg3_wait_macro_done(tp)) {
  752. *resetp = 1;
  753. return -EBUSY;
  754. }
  755. low &= 0x7fff;
  756. high &= 0x000f;
  757. if (low != test_pat[chan][i] ||
  758. high != test_pat[chan][i+1]) {
  759. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
  760. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
  761. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
  762. return -EBUSY;
  763. }
  764. }
  765. }
  766. return 0;
  767. }
  768. static int tg3_phy_reset_chanpat(struct tg3 *tp)
  769. {
  770. int chan;
  771. for (chan = 0; chan < 4; chan++) {
  772. int i;
  773. tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
  774. (chan * 0x2000) | 0x0200);
  775. tg3_writephy(tp, 0x16, 0x0002);
  776. for (i = 0; i < 6; i++)
  777. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
  778. tg3_writephy(tp, 0x16, 0x0202);
  779. if (tg3_wait_macro_done(tp))
  780. return -EBUSY;
  781. }
  782. return 0;
  783. }
  784. static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
  785. {
  786. u32 reg32, phy9_orig;
  787. int retries, do_phy_reset, err;
  788. retries = 10;
  789. do_phy_reset = 1;
  790. do {
  791. if (do_phy_reset) {
  792. err = tg3_bmcr_reset(tp);
  793. if (err)
  794. return err;
  795. do_phy_reset = 0;
  796. }
  797. /* Disable transmitter and interrupt. */
  798. if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
  799. continue;
  800. reg32 |= 0x3000;
  801. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  802. /* Set full-duplex, 1000 mbps. */
  803. tg3_writephy(tp, MII_BMCR,
  804. BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
  805. /* Set to master mode. */
  806. if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
  807. continue;
  808. tg3_writephy(tp, MII_TG3_CTRL,
  809. (MII_TG3_CTRL_AS_MASTER |
  810. MII_TG3_CTRL_ENABLE_AS_MASTER));
  811. /* Enable SM_DSP_CLOCK and 6dB. */
  812. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  813. /* Block the PHY control access. */
  814. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  815. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
  816. err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
  817. if (!err)
  818. break;
  819. } while (--retries);
  820. err = tg3_phy_reset_chanpat(tp);
  821. if (err)
  822. return err;
  823. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
  824. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
  825. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
  826. tg3_writephy(tp, 0x16, 0x0000);
  827. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  828. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  829. /* Set Extended packet length bit for jumbo frames */
  830. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
  831. }
  832. else {
  833. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  834. }
  835. tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
  836. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
  837. reg32 &= ~0x3000;
  838. tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
  839. } else if (!err)
  840. err = -EBUSY;
  841. return err;
  842. }
  843. static void tg3_link_report(struct tg3 *);
  844. /* This will reset the tigon3 PHY if there is no valid
  845. * link unless the FORCE argument is non-zero.
  846. */
  847. static int tg3_phy_reset(struct tg3 *tp)
  848. {
  849. u32 phy_status;
  850. int err;
  851. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  852. u32 val;
  853. val = tr32(GRC_MISC_CFG);
  854. tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
  855. udelay(40);
  856. }
  857. err = tg3_readphy(tp, MII_BMSR, &phy_status);
  858. err |= tg3_readphy(tp, MII_BMSR, &phy_status);
  859. if (err != 0)
  860. return -EBUSY;
  861. if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
  862. netif_carrier_off(tp->dev);
  863. tg3_link_report(tp);
  864. }
  865. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  866. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  867. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  868. err = tg3_phy_reset_5703_4_5(tp);
  869. if (err)
  870. return err;
  871. goto out;
  872. }
  873. err = tg3_bmcr_reset(tp);
  874. if (err)
  875. return err;
  876. out:
  877. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
  878. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  879. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  880. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
  881. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  882. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
  883. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  884. }
  885. if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
  886. tg3_writephy(tp, 0x1c, 0x8d68);
  887. tg3_writephy(tp, 0x1c, 0x8d68);
  888. }
  889. if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
  890. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  891. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  892. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
  893. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  894. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
  895. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
  896. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
  897. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  898. }
  899. else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
  900. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
  901. tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
  902. if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
  903. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
  904. tg3_writephy(tp, MII_TG3_TEST1,
  905. MII_TG3_TEST1_TRIM_EN | 0x4);
  906. } else
  907. tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
  908. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
  909. }
  910. /* Set Extended packet length bit (bit 14) on all chips that */
  911. /* support jumbo frames */
  912. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  913. /* Cannot do read-modify-write on 5401 */
  914. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  915. } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  916. u32 phy_reg;
  917. /* Set bit 14 with read-modify-write to preserve other bits */
  918. if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
  919. !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
  920. tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
  921. }
  922. /* Set phy register 0x10 bit 0 to high fifo elasticity to support
  923. * jumbo frames transmission.
  924. */
  925. if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
  926. u32 phy_reg;
  927. if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
  928. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  929. phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
  930. }
  931. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  932. /* adjust output voltage */
  933. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
  934. }
  935. tg3_phy_toggle_automdix(tp, 1);
  936. tg3_phy_set_wirespeed(tp);
  937. return 0;
  938. }
  939. static void tg3_frob_aux_power(struct tg3 *tp)
  940. {
  941. struct tg3 *tp_peer = tp;
  942. if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
  943. return;
  944. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  945. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  946. struct net_device *dev_peer;
  947. dev_peer = pci_get_drvdata(tp->pdev_peer);
  948. /* remove_one() may have been run on the peer. */
  949. if (!dev_peer)
  950. tp_peer = tp;
  951. else
  952. tp_peer = netdev_priv(dev_peer);
  953. }
  954. if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  955. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
  956. (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
  957. (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  958. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  959. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  960. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  961. (GRC_LCLCTRL_GPIO_OE0 |
  962. GRC_LCLCTRL_GPIO_OE1 |
  963. GRC_LCLCTRL_GPIO_OE2 |
  964. GRC_LCLCTRL_GPIO_OUTPUT0 |
  965. GRC_LCLCTRL_GPIO_OUTPUT1),
  966. 100);
  967. } else {
  968. u32 no_gpio2;
  969. u32 grc_local_ctrl = 0;
  970. if (tp_peer != tp &&
  971. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  972. return;
  973. /* Workaround to prevent overdrawing Amps. */
  974. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  975. ASIC_REV_5714) {
  976. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  977. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  978. grc_local_ctrl, 100);
  979. }
  980. /* On 5753 and variants, GPIO2 cannot be used. */
  981. no_gpio2 = tp->nic_sram_data_cfg &
  982. NIC_SRAM_DATA_CFG_NO_GPIO2;
  983. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
  984. GRC_LCLCTRL_GPIO_OE1 |
  985. GRC_LCLCTRL_GPIO_OE2 |
  986. GRC_LCLCTRL_GPIO_OUTPUT1 |
  987. GRC_LCLCTRL_GPIO_OUTPUT2;
  988. if (no_gpio2) {
  989. grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
  990. GRC_LCLCTRL_GPIO_OUTPUT2);
  991. }
  992. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  993. grc_local_ctrl, 100);
  994. grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
  995. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  996. grc_local_ctrl, 100);
  997. if (!no_gpio2) {
  998. grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
  999. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1000. grc_local_ctrl, 100);
  1001. }
  1002. }
  1003. } else {
  1004. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  1005. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  1006. if (tp_peer != tp &&
  1007. (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
  1008. return;
  1009. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1010. (GRC_LCLCTRL_GPIO_OE1 |
  1011. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1012. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1013. GRC_LCLCTRL_GPIO_OE1, 100);
  1014. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
  1015. (GRC_LCLCTRL_GPIO_OE1 |
  1016. GRC_LCLCTRL_GPIO_OUTPUT1), 100);
  1017. }
  1018. }
  1019. }
  1020. static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
  1021. {
  1022. if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
  1023. return 1;
  1024. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
  1025. if (speed != SPEED_10)
  1026. return 1;
  1027. } else if (speed == SPEED_10)
  1028. return 1;
  1029. return 0;
  1030. }
  1031. static int tg3_setup_phy(struct tg3 *, int);
  1032. #define RESET_KIND_SHUTDOWN 0
  1033. #define RESET_KIND_INIT 1
  1034. #define RESET_KIND_SUSPEND 2
  1035. static void tg3_write_sig_post_reset(struct tg3 *, int);
  1036. static int tg3_halt_cpu(struct tg3 *, u32);
  1037. static int tg3_nvram_lock(struct tg3 *);
  1038. static void tg3_nvram_unlock(struct tg3 *);
  1039. static void tg3_power_down_phy(struct tg3 *tp)
  1040. {
  1041. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  1042. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  1043. u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
  1044. u32 serdes_cfg = tr32(MAC_SERDES_CFG);
  1045. sg_dig_ctrl |=
  1046. SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
  1047. tw32(SG_DIG_CTRL, sg_dig_ctrl);
  1048. tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
  1049. }
  1050. return;
  1051. }
  1052. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1053. u32 val;
  1054. tg3_bmcr_reset(tp);
  1055. val = tr32(GRC_MISC_CFG);
  1056. tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
  1057. udelay(40);
  1058. return;
  1059. } else {
  1060. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1061. MII_TG3_EXT_CTRL_FORCE_LED_OFF);
  1062. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
  1063. }
  1064. /* The PHY should not be powered down on some chips because
  1065. * of bugs.
  1066. */
  1067. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1068. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1069. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
  1070. (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
  1071. return;
  1072. tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
  1073. }
  1074. static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
  1075. {
  1076. u32 misc_host_ctrl;
  1077. u16 power_control, power_caps;
  1078. int pm = tp->pm_cap;
  1079. /* Make sure register accesses (indirect or otherwise)
  1080. * will function correctly.
  1081. */
  1082. pci_write_config_dword(tp->pdev,
  1083. TG3PCI_MISC_HOST_CTRL,
  1084. tp->misc_host_ctrl);
  1085. pci_read_config_word(tp->pdev,
  1086. pm + PCI_PM_CTRL,
  1087. &power_control);
  1088. power_control |= PCI_PM_CTRL_PME_STATUS;
  1089. power_control &= ~(PCI_PM_CTRL_STATE_MASK);
  1090. switch (state) {
  1091. case PCI_D0:
  1092. power_control |= 0;
  1093. pci_write_config_word(tp->pdev,
  1094. pm + PCI_PM_CTRL,
  1095. power_control);
  1096. udelay(100); /* Delay after power state change */
  1097. /* Switch out of Vaux if it is a NIC */
  1098. if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
  1099. tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
  1100. return 0;
  1101. case PCI_D1:
  1102. power_control |= 1;
  1103. break;
  1104. case PCI_D2:
  1105. power_control |= 2;
  1106. break;
  1107. case PCI_D3hot:
  1108. power_control |= 3;
  1109. break;
  1110. default:
  1111. printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
  1112. "requested.\n",
  1113. tp->dev->name, state);
  1114. return -EINVAL;
  1115. };
  1116. power_control |= PCI_PM_CTRL_PME_ENABLE;
  1117. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  1118. tw32(TG3PCI_MISC_HOST_CTRL,
  1119. misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
  1120. if (tp->link_config.phy_is_low_power == 0) {
  1121. tp->link_config.phy_is_low_power = 1;
  1122. tp->link_config.orig_speed = tp->link_config.speed;
  1123. tp->link_config.orig_duplex = tp->link_config.duplex;
  1124. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  1125. }
  1126. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  1127. tp->link_config.speed = SPEED_10;
  1128. tp->link_config.duplex = DUPLEX_HALF;
  1129. tp->link_config.autoneg = AUTONEG_ENABLE;
  1130. tg3_setup_phy(tp, 0);
  1131. }
  1132. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1133. u32 val;
  1134. val = tr32(GRC_VCPU_EXT_CTRL);
  1135. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
  1136. } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1137. int i;
  1138. u32 val;
  1139. for (i = 0; i < 200; i++) {
  1140. tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
  1141. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  1142. break;
  1143. msleep(1);
  1144. }
  1145. }
  1146. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  1147. tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
  1148. WOL_DRV_STATE_SHUTDOWN |
  1149. WOL_DRV_WOL |
  1150. WOL_SET_MAGIC_PKT);
  1151. pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
  1152. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
  1153. u32 mac_mode;
  1154. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  1155. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
  1156. udelay(40);
  1157. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  1158. mac_mode = MAC_MODE_PORT_MODE_GMII;
  1159. else
  1160. mac_mode = MAC_MODE_PORT_MODE_MII;
  1161. mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
  1162. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  1163. ASIC_REV_5700) {
  1164. u32 speed = (tp->tg3_flags &
  1165. TG3_FLAG_WOL_SPEED_100MB) ?
  1166. SPEED_100 : SPEED_10;
  1167. if (tg3_5700_link_polarity(tp, speed))
  1168. mac_mode |= MAC_MODE_LINK_POLARITY;
  1169. else
  1170. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1171. }
  1172. } else {
  1173. mac_mode = MAC_MODE_PORT_MODE_TBI;
  1174. }
  1175. if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  1176. tw32(MAC_LED_CTRL, tp->led_ctrl);
  1177. if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
  1178. (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
  1179. mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
  1180. tw32_f(MAC_MODE, mac_mode);
  1181. udelay(100);
  1182. tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
  1183. udelay(10);
  1184. }
  1185. if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
  1186. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1187. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  1188. u32 base_val;
  1189. base_val = tp->pci_clock_ctrl;
  1190. base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
  1191. CLOCK_CTRL_TXCLK_DISABLE);
  1192. tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
  1193. CLOCK_CTRL_PWRDOWN_PLL133, 40);
  1194. } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
  1195. (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
  1196. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
  1197. /* do nothing */
  1198. } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  1199. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
  1200. u32 newbits1, newbits2;
  1201. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1202. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1203. newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
  1204. CLOCK_CTRL_TXCLK_DISABLE |
  1205. CLOCK_CTRL_ALTCLK);
  1206. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1207. } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  1208. newbits1 = CLOCK_CTRL_625_CORE;
  1209. newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
  1210. } else {
  1211. newbits1 = CLOCK_CTRL_ALTCLK;
  1212. newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
  1213. }
  1214. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
  1215. 40);
  1216. tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
  1217. 40);
  1218. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  1219. u32 newbits3;
  1220. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1221. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1222. newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
  1223. CLOCK_CTRL_TXCLK_DISABLE |
  1224. CLOCK_CTRL_44MHZ_CORE);
  1225. } else {
  1226. newbits3 = CLOCK_CTRL_44MHZ_CORE;
  1227. }
  1228. tw32_wait_f(TG3PCI_CLOCK_CTRL,
  1229. tp->pci_clock_ctrl | newbits3, 40);
  1230. }
  1231. }
  1232. if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
  1233. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  1234. tg3_power_down_phy(tp);
  1235. tg3_frob_aux_power(tp);
  1236. /* Workaround for unstable PLL clock */
  1237. if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
  1238. (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
  1239. u32 val = tr32(0x7d00);
  1240. val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
  1241. tw32(0x7d00, val);
  1242. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  1243. int err;
  1244. err = tg3_nvram_lock(tp);
  1245. tg3_halt_cpu(tp, RX_CPU_BASE);
  1246. if (!err)
  1247. tg3_nvram_unlock(tp);
  1248. }
  1249. }
  1250. tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
  1251. /* Finally, set the new power state. */
  1252. pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
  1253. udelay(100); /* Delay after power state change */
  1254. return 0;
  1255. }
  1256. static void tg3_link_report(struct tg3 *tp)
  1257. {
  1258. if (!netif_carrier_ok(tp->dev)) {
  1259. if (netif_msg_link(tp))
  1260. printk(KERN_INFO PFX "%s: Link is down.\n",
  1261. tp->dev->name);
  1262. } else if (netif_msg_link(tp)) {
  1263. printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
  1264. tp->dev->name,
  1265. (tp->link_config.active_speed == SPEED_1000 ?
  1266. 1000 :
  1267. (tp->link_config.active_speed == SPEED_100 ?
  1268. 100 : 10)),
  1269. (tp->link_config.active_duplex == DUPLEX_FULL ?
  1270. "full" : "half"));
  1271. printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
  1272. "%s for RX.\n",
  1273. tp->dev->name,
  1274. (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
  1275. (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
  1276. }
  1277. }
  1278. static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
  1279. {
  1280. u32 new_tg3_flags = 0;
  1281. u32 old_rx_mode = tp->rx_mode;
  1282. u32 old_tx_mode = tp->tx_mode;
  1283. if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
  1284. /* Convert 1000BaseX flow control bits to 1000BaseT
  1285. * bits before resolving flow control.
  1286. */
  1287. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  1288. local_adv &= ~(ADVERTISE_PAUSE_CAP |
  1289. ADVERTISE_PAUSE_ASYM);
  1290. remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  1291. if (local_adv & ADVERTISE_1000XPAUSE)
  1292. local_adv |= ADVERTISE_PAUSE_CAP;
  1293. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  1294. local_adv |= ADVERTISE_PAUSE_ASYM;
  1295. if (remote_adv & LPA_1000XPAUSE)
  1296. remote_adv |= LPA_PAUSE_CAP;
  1297. if (remote_adv & LPA_1000XPAUSE_ASYM)
  1298. remote_adv |= LPA_PAUSE_ASYM;
  1299. }
  1300. if (local_adv & ADVERTISE_PAUSE_CAP) {
  1301. if (local_adv & ADVERTISE_PAUSE_ASYM) {
  1302. if (remote_adv & LPA_PAUSE_CAP)
  1303. new_tg3_flags |=
  1304. (TG3_FLAG_RX_PAUSE |
  1305. TG3_FLAG_TX_PAUSE);
  1306. else if (remote_adv & LPA_PAUSE_ASYM)
  1307. new_tg3_flags |=
  1308. (TG3_FLAG_RX_PAUSE);
  1309. } else {
  1310. if (remote_adv & LPA_PAUSE_CAP)
  1311. new_tg3_flags |=
  1312. (TG3_FLAG_RX_PAUSE |
  1313. TG3_FLAG_TX_PAUSE);
  1314. }
  1315. } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  1316. if ((remote_adv & LPA_PAUSE_CAP) &&
  1317. (remote_adv & LPA_PAUSE_ASYM))
  1318. new_tg3_flags |= TG3_FLAG_TX_PAUSE;
  1319. }
  1320. tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
  1321. tp->tg3_flags |= new_tg3_flags;
  1322. } else {
  1323. new_tg3_flags = tp->tg3_flags;
  1324. }
  1325. if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
  1326. tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
  1327. else
  1328. tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
  1329. if (old_rx_mode != tp->rx_mode) {
  1330. tw32_f(MAC_RX_MODE, tp->rx_mode);
  1331. }
  1332. if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
  1333. tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
  1334. else
  1335. tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
  1336. if (old_tx_mode != tp->tx_mode) {
  1337. tw32_f(MAC_TX_MODE, tp->tx_mode);
  1338. }
  1339. }
  1340. static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
  1341. {
  1342. switch (val & MII_TG3_AUX_STAT_SPDMASK) {
  1343. case MII_TG3_AUX_STAT_10HALF:
  1344. *speed = SPEED_10;
  1345. *duplex = DUPLEX_HALF;
  1346. break;
  1347. case MII_TG3_AUX_STAT_10FULL:
  1348. *speed = SPEED_10;
  1349. *duplex = DUPLEX_FULL;
  1350. break;
  1351. case MII_TG3_AUX_STAT_100HALF:
  1352. *speed = SPEED_100;
  1353. *duplex = DUPLEX_HALF;
  1354. break;
  1355. case MII_TG3_AUX_STAT_100FULL:
  1356. *speed = SPEED_100;
  1357. *duplex = DUPLEX_FULL;
  1358. break;
  1359. case MII_TG3_AUX_STAT_1000HALF:
  1360. *speed = SPEED_1000;
  1361. *duplex = DUPLEX_HALF;
  1362. break;
  1363. case MII_TG3_AUX_STAT_1000FULL:
  1364. *speed = SPEED_1000;
  1365. *duplex = DUPLEX_FULL;
  1366. break;
  1367. default:
  1368. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  1369. *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
  1370. SPEED_10;
  1371. *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
  1372. DUPLEX_HALF;
  1373. break;
  1374. }
  1375. *speed = SPEED_INVALID;
  1376. *duplex = DUPLEX_INVALID;
  1377. break;
  1378. };
  1379. }
  1380. static void tg3_phy_copper_begin(struct tg3 *tp)
  1381. {
  1382. u32 new_adv;
  1383. int i;
  1384. if (tp->link_config.phy_is_low_power) {
  1385. /* Entering low power mode. Disable gigabit and
  1386. * 100baseT advertisements.
  1387. */
  1388. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1389. new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1390. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1391. if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
  1392. new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
  1393. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1394. } else if (tp->link_config.speed == SPEED_INVALID) {
  1395. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  1396. tp->link_config.advertising &=
  1397. ~(ADVERTISED_1000baseT_Half |
  1398. ADVERTISED_1000baseT_Full);
  1399. new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  1400. if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
  1401. new_adv |= ADVERTISE_10HALF;
  1402. if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
  1403. new_adv |= ADVERTISE_10FULL;
  1404. if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
  1405. new_adv |= ADVERTISE_100HALF;
  1406. if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
  1407. new_adv |= ADVERTISE_100FULL;
  1408. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1409. if (tp->link_config.advertising &
  1410. (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
  1411. new_adv = 0;
  1412. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  1413. new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
  1414. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  1415. new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
  1416. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
  1417. (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1418. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
  1419. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1420. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1421. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1422. } else {
  1423. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1424. }
  1425. } else {
  1426. /* Asking for a specific link mode. */
  1427. if (tp->link_config.speed == SPEED_1000) {
  1428. new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1429. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1430. if (tp->link_config.duplex == DUPLEX_FULL)
  1431. new_adv = MII_TG3_CTRL_ADV_1000_FULL;
  1432. else
  1433. new_adv = MII_TG3_CTRL_ADV_1000_HALF;
  1434. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1435. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  1436. new_adv |= (MII_TG3_CTRL_AS_MASTER |
  1437. MII_TG3_CTRL_ENABLE_AS_MASTER);
  1438. tg3_writephy(tp, MII_TG3_CTRL, new_adv);
  1439. } else {
  1440. tg3_writephy(tp, MII_TG3_CTRL, 0);
  1441. new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
  1442. if (tp->link_config.speed == SPEED_100) {
  1443. if (tp->link_config.duplex == DUPLEX_FULL)
  1444. new_adv |= ADVERTISE_100FULL;
  1445. else
  1446. new_adv |= ADVERTISE_100HALF;
  1447. } else {
  1448. if (tp->link_config.duplex == DUPLEX_FULL)
  1449. new_adv |= ADVERTISE_10FULL;
  1450. else
  1451. new_adv |= ADVERTISE_10HALF;
  1452. }
  1453. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  1454. }
  1455. }
  1456. if (tp->link_config.autoneg == AUTONEG_DISABLE &&
  1457. tp->link_config.speed != SPEED_INVALID) {
  1458. u32 bmcr, orig_bmcr;
  1459. tp->link_config.active_speed = tp->link_config.speed;
  1460. tp->link_config.active_duplex = tp->link_config.duplex;
  1461. bmcr = 0;
  1462. switch (tp->link_config.speed) {
  1463. default:
  1464. case SPEED_10:
  1465. break;
  1466. case SPEED_100:
  1467. bmcr |= BMCR_SPEED100;
  1468. break;
  1469. case SPEED_1000:
  1470. bmcr |= TG3_BMCR_SPEED1000;
  1471. break;
  1472. };
  1473. if (tp->link_config.duplex == DUPLEX_FULL)
  1474. bmcr |= BMCR_FULLDPLX;
  1475. if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
  1476. (bmcr != orig_bmcr)) {
  1477. tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
  1478. for (i = 0; i < 1500; i++) {
  1479. u32 tmp;
  1480. udelay(10);
  1481. if (tg3_readphy(tp, MII_BMSR, &tmp) ||
  1482. tg3_readphy(tp, MII_BMSR, &tmp))
  1483. continue;
  1484. if (!(tmp & BMSR_LSTATUS)) {
  1485. udelay(40);
  1486. break;
  1487. }
  1488. }
  1489. tg3_writephy(tp, MII_BMCR, bmcr);
  1490. udelay(40);
  1491. }
  1492. } else {
  1493. tg3_writephy(tp, MII_BMCR,
  1494. BMCR_ANENABLE | BMCR_ANRESTART);
  1495. }
  1496. }
  1497. static int tg3_init_5401phy_dsp(struct tg3 *tp)
  1498. {
  1499. int err;
  1500. /* Turn off tap power management. */
  1501. /* Set Extended packet length bit */
  1502. err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
  1503. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
  1504. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
  1505. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
  1506. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
  1507. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1508. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
  1509. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
  1510. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
  1511. err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
  1512. err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
  1513. udelay(40);
  1514. return err;
  1515. }
  1516. static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
  1517. {
  1518. u32 adv_reg, all_mask = 0;
  1519. if (mask & ADVERTISED_10baseT_Half)
  1520. all_mask |= ADVERTISE_10HALF;
  1521. if (mask & ADVERTISED_10baseT_Full)
  1522. all_mask |= ADVERTISE_10FULL;
  1523. if (mask & ADVERTISED_100baseT_Half)
  1524. all_mask |= ADVERTISE_100HALF;
  1525. if (mask & ADVERTISED_100baseT_Full)
  1526. all_mask |= ADVERTISE_100FULL;
  1527. if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
  1528. return 0;
  1529. if ((adv_reg & all_mask) != all_mask)
  1530. return 0;
  1531. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  1532. u32 tg3_ctrl;
  1533. all_mask = 0;
  1534. if (mask & ADVERTISED_1000baseT_Half)
  1535. all_mask |= ADVERTISE_1000HALF;
  1536. if (mask & ADVERTISED_1000baseT_Full)
  1537. all_mask |= ADVERTISE_1000FULL;
  1538. if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
  1539. return 0;
  1540. if ((tg3_ctrl & all_mask) != all_mask)
  1541. return 0;
  1542. }
  1543. return 1;
  1544. }
  1545. static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
  1546. {
  1547. int current_link_up;
  1548. u32 bmsr, dummy;
  1549. u16 current_speed;
  1550. u8 current_duplex;
  1551. int i, err;
  1552. tw32(MAC_EVENT, 0);
  1553. tw32_f(MAC_STATUS,
  1554. (MAC_STATUS_SYNC_CHANGED |
  1555. MAC_STATUS_CFG_CHANGED |
  1556. MAC_STATUS_MI_COMPLETION |
  1557. MAC_STATUS_LNKSTATE_CHANGED));
  1558. udelay(40);
  1559. tp->mi_mode = MAC_MI_MODE_BASE;
  1560. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1561. udelay(80);
  1562. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
  1563. /* Some third-party PHYs need to be reset on link going
  1564. * down.
  1565. */
  1566. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  1567. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
  1568. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  1569. netif_carrier_ok(tp->dev)) {
  1570. tg3_readphy(tp, MII_BMSR, &bmsr);
  1571. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1572. !(bmsr & BMSR_LSTATUS))
  1573. force_reset = 1;
  1574. }
  1575. if (force_reset)
  1576. tg3_phy_reset(tp);
  1577. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  1578. tg3_readphy(tp, MII_BMSR, &bmsr);
  1579. if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
  1580. !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
  1581. bmsr = 0;
  1582. if (!(bmsr & BMSR_LSTATUS)) {
  1583. err = tg3_init_5401phy_dsp(tp);
  1584. if (err)
  1585. return err;
  1586. tg3_readphy(tp, MII_BMSR, &bmsr);
  1587. for (i = 0; i < 1000; i++) {
  1588. udelay(10);
  1589. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1590. (bmsr & BMSR_LSTATUS)) {
  1591. udelay(40);
  1592. break;
  1593. }
  1594. }
  1595. if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
  1596. !(bmsr & BMSR_LSTATUS) &&
  1597. tp->link_config.active_speed == SPEED_1000) {
  1598. err = tg3_phy_reset(tp);
  1599. if (!err)
  1600. err = tg3_init_5401phy_dsp(tp);
  1601. if (err)
  1602. return err;
  1603. }
  1604. }
  1605. } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  1606. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
  1607. /* 5701 {A0,B0} CRC bug workaround */
  1608. tg3_writephy(tp, 0x15, 0x0a75);
  1609. tg3_writephy(tp, 0x1c, 0x8c68);
  1610. tg3_writephy(tp, 0x1c, 0x8d68);
  1611. tg3_writephy(tp, 0x1c, 0x8c68);
  1612. }
  1613. /* Clear pending interrupts... */
  1614. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1615. tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
  1616. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
  1617. tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
  1618. else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  1619. tg3_writephy(tp, MII_TG3_IMASK, ~0);
  1620. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  1621. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  1622. if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
  1623. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  1624. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  1625. else
  1626. tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
  1627. }
  1628. current_link_up = 0;
  1629. current_speed = SPEED_INVALID;
  1630. current_duplex = DUPLEX_INVALID;
  1631. if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
  1632. u32 val;
  1633. tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
  1634. tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
  1635. if (!(val & (1 << 10))) {
  1636. val |= (1 << 10);
  1637. tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
  1638. goto relink;
  1639. }
  1640. }
  1641. bmsr = 0;
  1642. for (i = 0; i < 100; i++) {
  1643. tg3_readphy(tp, MII_BMSR, &bmsr);
  1644. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  1645. (bmsr & BMSR_LSTATUS))
  1646. break;
  1647. udelay(40);
  1648. }
  1649. if (bmsr & BMSR_LSTATUS) {
  1650. u32 aux_stat, bmcr;
  1651. tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
  1652. for (i = 0; i < 2000; i++) {
  1653. udelay(10);
  1654. if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
  1655. aux_stat)
  1656. break;
  1657. }
  1658. tg3_aux_stat_to_speed_duplex(tp, aux_stat,
  1659. &current_speed,
  1660. &current_duplex);
  1661. bmcr = 0;
  1662. for (i = 0; i < 200; i++) {
  1663. tg3_readphy(tp, MII_BMCR, &bmcr);
  1664. if (tg3_readphy(tp, MII_BMCR, &bmcr))
  1665. continue;
  1666. if (bmcr && bmcr != 0x7fff)
  1667. break;
  1668. udelay(10);
  1669. }
  1670. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  1671. if (bmcr & BMCR_ANENABLE) {
  1672. current_link_up = 1;
  1673. /* Force autoneg restart if we are exiting
  1674. * low power mode.
  1675. */
  1676. if (!tg3_copper_is_advertising_all(tp,
  1677. tp->link_config.advertising))
  1678. current_link_up = 0;
  1679. } else {
  1680. current_link_up = 0;
  1681. }
  1682. } else {
  1683. if (!(bmcr & BMCR_ANENABLE) &&
  1684. tp->link_config.speed == current_speed &&
  1685. tp->link_config.duplex == current_duplex) {
  1686. current_link_up = 1;
  1687. } else {
  1688. current_link_up = 0;
  1689. }
  1690. }
  1691. tp->link_config.active_speed = current_speed;
  1692. tp->link_config.active_duplex = current_duplex;
  1693. }
  1694. if (current_link_up == 1 &&
  1695. (tp->link_config.active_duplex == DUPLEX_FULL) &&
  1696. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  1697. u32 local_adv, remote_adv;
  1698. if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
  1699. local_adv = 0;
  1700. local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  1701. if (tg3_readphy(tp, MII_LPA, &remote_adv))
  1702. remote_adv = 0;
  1703. remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  1704. /* If we are not advertising full pause capability,
  1705. * something is wrong. Bring the link down and reconfigure.
  1706. */
  1707. if (local_adv != ADVERTISE_PAUSE_CAP) {
  1708. current_link_up = 0;
  1709. } else {
  1710. tg3_setup_flow_control(tp, local_adv, remote_adv);
  1711. }
  1712. }
  1713. relink:
  1714. if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
  1715. u32 tmp;
  1716. tg3_phy_copper_begin(tp);
  1717. tg3_readphy(tp, MII_BMSR, &tmp);
  1718. if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
  1719. (tmp & BMSR_LSTATUS))
  1720. current_link_up = 1;
  1721. }
  1722. tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
  1723. if (current_link_up == 1) {
  1724. if (tp->link_config.active_speed == SPEED_100 ||
  1725. tp->link_config.active_speed == SPEED_10)
  1726. tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
  1727. else
  1728. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1729. } else
  1730. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  1731. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  1732. if (tp->link_config.active_duplex == DUPLEX_HALF)
  1733. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  1734. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  1735. if (current_link_up == 1 &&
  1736. tg3_5700_link_polarity(tp, tp->link_config.active_speed))
  1737. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  1738. else
  1739. tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
  1740. }
  1741. /* ??? Without this setting Netgear GA302T PHY does not
  1742. * ??? send/receive packets...
  1743. */
  1744. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
  1745. tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
  1746. tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
  1747. tw32_f(MAC_MI_MODE, tp->mi_mode);
  1748. udelay(80);
  1749. }
  1750. tw32_f(MAC_MODE, tp->mac_mode);
  1751. udelay(40);
  1752. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  1753. /* Polled via timer. */
  1754. tw32_f(MAC_EVENT, 0);
  1755. } else {
  1756. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  1757. }
  1758. udelay(40);
  1759. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
  1760. current_link_up == 1 &&
  1761. tp->link_config.active_speed == SPEED_1000 &&
  1762. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
  1763. (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
  1764. udelay(120);
  1765. tw32_f(MAC_STATUS,
  1766. (MAC_STATUS_SYNC_CHANGED |
  1767. MAC_STATUS_CFG_CHANGED));
  1768. udelay(40);
  1769. tg3_write_mem(tp,
  1770. NIC_SRAM_FIRMWARE_MBOX,
  1771. NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
  1772. }
  1773. if (current_link_up != netif_carrier_ok(tp->dev)) {
  1774. if (current_link_up)
  1775. netif_carrier_on(tp->dev);
  1776. else
  1777. netif_carrier_off(tp->dev);
  1778. tg3_link_report(tp);
  1779. }
  1780. return 0;
  1781. }
  1782. struct tg3_fiber_aneginfo {
  1783. int state;
  1784. #define ANEG_STATE_UNKNOWN 0
  1785. #define ANEG_STATE_AN_ENABLE 1
  1786. #define ANEG_STATE_RESTART_INIT 2
  1787. #define ANEG_STATE_RESTART 3
  1788. #define ANEG_STATE_DISABLE_LINK_OK 4
  1789. #define ANEG_STATE_ABILITY_DETECT_INIT 5
  1790. #define ANEG_STATE_ABILITY_DETECT 6
  1791. #define ANEG_STATE_ACK_DETECT_INIT 7
  1792. #define ANEG_STATE_ACK_DETECT 8
  1793. #define ANEG_STATE_COMPLETE_ACK_INIT 9
  1794. #define ANEG_STATE_COMPLETE_ACK 10
  1795. #define ANEG_STATE_IDLE_DETECT_INIT 11
  1796. #define ANEG_STATE_IDLE_DETECT 12
  1797. #define ANEG_STATE_LINK_OK 13
  1798. #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
  1799. #define ANEG_STATE_NEXT_PAGE_WAIT 15
  1800. u32 flags;
  1801. #define MR_AN_ENABLE 0x00000001
  1802. #define MR_RESTART_AN 0x00000002
  1803. #define MR_AN_COMPLETE 0x00000004
  1804. #define MR_PAGE_RX 0x00000008
  1805. #define MR_NP_LOADED 0x00000010
  1806. #define MR_TOGGLE_TX 0x00000020
  1807. #define MR_LP_ADV_FULL_DUPLEX 0x00000040
  1808. #define MR_LP_ADV_HALF_DUPLEX 0x00000080
  1809. #define MR_LP_ADV_SYM_PAUSE 0x00000100
  1810. #define MR_LP_ADV_ASYM_PAUSE 0x00000200
  1811. #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
  1812. #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
  1813. #define MR_LP_ADV_NEXT_PAGE 0x00001000
  1814. #define MR_TOGGLE_RX 0x00002000
  1815. #define MR_NP_RX 0x00004000
  1816. #define MR_LINK_OK 0x80000000
  1817. unsigned long link_time, cur_time;
  1818. u32 ability_match_cfg;
  1819. int ability_match_count;
  1820. char ability_match, idle_match, ack_match;
  1821. u32 txconfig, rxconfig;
  1822. #define ANEG_CFG_NP 0x00000080
  1823. #define ANEG_CFG_ACK 0x00000040
  1824. #define ANEG_CFG_RF2 0x00000020
  1825. #define ANEG_CFG_RF1 0x00000010
  1826. #define ANEG_CFG_PS2 0x00000001
  1827. #define ANEG_CFG_PS1 0x00008000
  1828. #define ANEG_CFG_HD 0x00004000
  1829. #define ANEG_CFG_FD 0x00002000
  1830. #define ANEG_CFG_INVAL 0x00001f06
  1831. };
  1832. #define ANEG_OK 0
  1833. #define ANEG_DONE 1
  1834. #define ANEG_TIMER_ENAB 2
  1835. #define ANEG_FAILED -1
  1836. #define ANEG_STATE_SETTLE_TIME 10000
  1837. static int tg3_fiber_aneg_smachine(struct tg3 *tp,
  1838. struct tg3_fiber_aneginfo *ap)
  1839. {
  1840. unsigned long delta;
  1841. u32 rx_cfg_reg;
  1842. int ret;
  1843. if (ap->state == ANEG_STATE_UNKNOWN) {
  1844. ap->rxconfig = 0;
  1845. ap->link_time = 0;
  1846. ap->cur_time = 0;
  1847. ap->ability_match_cfg = 0;
  1848. ap->ability_match_count = 0;
  1849. ap->ability_match = 0;
  1850. ap->idle_match = 0;
  1851. ap->ack_match = 0;
  1852. }
  1853. ap->cur_time++;
  1854. if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
  1855. rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
  1856. if (rx_cfg_reg != ap->ability_match_cfg) {
  1857. ap->ability_match_cfg = rx_cfg_reg;
  1858. ap->ability_match = 0;
  1859. ap->ability_match_count = 0;
  1860. } else {
  1861. if (++ap->ability_match_count > 1) {
  1862. ap->ability_match = 1;
  1863. ap->ability_match_cfg = rx_cfg_reg;
  1864. }
  1865. }
  1866. if (rx_cfg_reg & ANEG_CFG_ACK)
  1867. ap->ack_match = 1;
  1868. else
  1869. ap->ack_match = 0;
  1870. ap->idle_match = 0;
  1871. } else {
  1872. ap->idle_match = 1;
  1873. ap->ability_match_cfg = 0;
  1874. ap->ability_match_count = 0;
  1875. ap->ability_match = 0;
  1876. ap->ack_match = 0;
  1877. rx_cfg_reg = 0;
  1878. }
  1879. ap->rxconfig = rx_cfg_reg;
  1880. ret = ANEG_OK;
  1881. switch(ap->state) {
  1882. case ANEG_STATE_UNKNOWN:
  1883. if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
  1884. ap->state = ANEG_STATE_AN_ENABLE;
  1885. /* fallthru */
  1886. case ANEG_STATE_AN_ENABLE:
  1887. ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
  1888. if (ap->flags & MR_AN_ENABLE) {
  1889. ap->link_time = 0;
  1890. ap->cur_time = 0;
  1891. ap->ability_match_cfg = 0;
  1892. ap->ability_match_count = 0;
  1893. ap->ability_match = 0;
  1894. ap->idle_match = 0;
  1895. ap->ack_match = 0;
  1896. ap->state = ANEG_STATE_RESTART_INIT;
  1897. } else {
  1898. ap->state = ANEG_STATE_DISABLE_LINK_OK;
  1899. }
  1900. break;
  1901. case ANEG_STATE_RESTART_INIT:
  1902. ap->link_time = ap->cur_time;
  1903. ap->flags &= ~(MR_NP_LOADED);
  1904. ap->txconfig = 0;
  1905. tw32(MAC_TX_AUTO_NEG, 0);
  1906. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1907. tw32_f(MAC_MODE, tp->mac_mode);
  1908. udelay(40);
  1909. ret = ANEG_TIMER_ENAB;
  1910. ap->state = ANEG_STATE_RESTART;
  1911. /* fallthru */
  1912. case ANEG_STATE_RESTART:
  1913. delta = ap->cur_time - ap->link_time;
  1914. if (delta > ANEG_STATE_SETTLE_TIME) {
  1915. ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
  1916. } else {
  1917. ret = ANEG_TIMER_ENAB;
  1918. }
  1919. break;
  1920. case ANEG_STATE_DISABLE_LINK_OK:
  1921. ret = ANEG_DONE;
  1922. break;
  1923. case ANEG_STATE_ABILITY_DETECT_INIT:
  1924. ap->flags &= ~(MR_TOGGLE_TX);
  1925. ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
  1926. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  1927. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1928. tw32_f(MAC_MODE, tp->mac_mode);
  1929. udelay(40);
  1930. ap->state = ANEG_STATE_ABILITY_DETECT;
  1931. break;
  1932. case ANEG_STATE_ABILITY_DETECT:
  1933. if (ap->ability_match != 0 && ap->rxconfig != 0) {
  1934. ap->state = ANEG_STATE_ACK_DETECT_INIT;
  1935. }
  1936. break;
  1937. case ANEG_STATE_ACK_DETECT_INIT:
  1938. ap->txconfig |= ANEG_CFG_ACK;
  1939. tw32(MAC_TX_AUTO_NEG, ap->txconfig);
  1940. tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
  1941. tw32_f(MAC_MODE, tp->mac_mode);
  1942. udelay(40);
  1943. ap->state = ANEG_STATE_ACK_DETECT;
  1944. /* fallthru */
  1945. case ANEG_STATE_ACK_DETECT:
  1946. if (ap->ack_match != 0) {
  1947. if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
  1948. (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
  1949. ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
  1950. } else {
  1951. ap->state = ANEG_STATE_AN_ENABLE;
  1952. }
  1953. } else if (ap->ability_match != 0 &&
  1954. ap->rxconfig == 0) {
  1955. ap->state = ANEG_STATE_AN_ENABLE;
  1956. }
  1957. break;
  1958. case ANEG_STATE_COMPLETE_ACK_INIT:
  1959. if (ap->rxconfig & ANEG_CFG_INVAL) {
  1960. ret = ANEG_FAILED;
  1961. break;
  1962. }
  1963. ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
  1964. MR_LP_ADV_HALF_DUPLEX |
  1965. MR_LP_ADV_SYM_PAUSE |
  1966. MR_LP_ADV_ASYM_PAUSE |
  1967. MR_LP_ADV_REMOTE_FAULT1 |
  1968. MR_LP_ADV_REMOTE_FAULT2 |
  1969. MR_LP_ADV_NEXT_PAGE |
  1970. MR_TOGGLE_RX |
  1971. MR_NP_RX);
  1972. if (ap->rxconfig & ANEG_CFG_FD)
  1973. ap->flags |= MR_LP_ADV_FULL_DUPLEX;
  1974. if (ap->rxconfig & ANEG_CFG_HD)
  1975. ap->flags |= MR_LP_ADV_HALF_DUPLEX;
  1976. if (ap->rxconfig & ANEG_CFG_PS1)
  1977. ap->flags |= MR_LP_ADV_SYM_PAUSE;
  1978. if (ap->rxconfig & ANEG_CFG_PS2)
  1979. ap->flags |= MR_LP_ADV_ASYM_PAUSE;
  1980. if (ap->rxconfig & ANEG_CFG_RF1)
  1981. ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
  1982. if (ap->rxconfig & ANEG_CFG_RF2)
  1983. ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
  1984. if (ap->rxconfig & ANEG_CFG_NP)
  1985. ap->flags |= MR_LP_ADV_NEXT_PAGE;
  1986. ap->link_time = ap->cur_time;
  1987. ap->flags ^= (MR_TOGGLE_TX);
  1988. if (ap->rxconfig & 0x0008)
  1989. ap->flags |= MR_TOGGLE_RX;
  1990. if (ap->rxconfig & ANEG_CFG_NP)
  1991. ap->flags |= MR_NP_RX;
  1992. ap->flags |= MR_PAGE_RX;
  1993. ap->state = ANEG_STATE_COMPLETE_ACK;
  1994. ret = ANEG_TIMER_ENAB;
  1995. break;
  1996. case ANEG_STATE_COMPLETE_ACK:
  1997. if (ap->ability_match != 0 &&
  1998. ap->rxconfig == 0) {
  1999. ap->state = ANEG_STATE_AN_ENABLE;
  2000. break;
  2001. }
  2002. delta = ap->cur_time - ap->link_time;
  2003. if (delta > ANEG_STATE_SETTLE_TIME) {
  2004. if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
  2005. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2006. } else {
  2007. if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
  2008. !(ap->flags & MR_NP_RX)) {
  2009. ap->state = ANEG_STATE_IDLE_DETECT_INIT;
  2010. } else {
  2011. ret = ANEG_FAILED;
  2012. }
  2013. }
  2014. }
  2015. break;
  2016. case ANEG_STATE_IDLE_DETECT_INIT:
  2017. ap->link_time = ap->cur_time;
  2018. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2019. tw32_f(MAC_MODE, tp->mac_mode);
  2020. udelay(40);
  2021. ap->state = ANEG_STATE_IDLE_DETECT;
  2022. ret = ANEG_TIMER_ENAB;
  2023. break;
  2024. case ANEG_STATE_IDLE_DETECT:
  2025. if (ap->ability_match != 0 &&
  2026. ap->rxconfig == 0) {
  2027. ap->state = ANEG_STATE_AN_ENABLE;
  2028. break;
  2029. }
  2030. delta = ap->cur_time - ap->link_time;
  2031. if (delta > ANEG_STATE_SETTLE_TIME) {
  2032. /* XXX another gem from the Broadcom driver :( */
  2033. ap->state = ANEG_STATE_LINK_OK;
  2034. }
  2035. break;
  2036. case ANEG_STATE_LINK_OK:
  2037. ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
  2038. ret = ANEG_DONE;
  2039. break;
  2040. case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
  2041. /* ??? unimplemented */
  2042. break;
  2043. case ANEG_STATE_NEXT_PAGE_WAIT:
  2044. /* ??? unimplemented */
  2045. break;
  2046. default:
  2047. ret = ANEG_FAILED;
  2048. break;
  2049. };
  2050. return ret;
  2051. }
  2052. static int fiber_autoneg(struct tg3 *tp, u32 *flags)
  2053. {
  2054. int res = 0;
  2055. struct tg3_fiber_aneginfo aninfo;
  2056. int status = ANEG_FAILED;
  2057. unsigned int tick;
  2058. u32 tmp;
  2059. tw32_f(MAC_TX_AUTO_NEG, 0);
  2060. tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  2061. tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
  2062. udelay(40);
  2063. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
  2064. udelay(40);
  2065. memset(&aninfo, 0, sizeof(aninfo));
  2066. aninfo.flags |= MR_AN_ENABLE;
  2067. aninfo.state = ANEG_STATE_UNKNOWN;
  2068. aninfo.cur_time = 0;
  2069. tick = 0;
  2070. while (++tick < 195000) {
  2071. status = tg3_fiber_aneg_smachine(tp, &aninfo);
  2072. if (status == ANEG_DONE || status == ANEG_FAILED)
  2073. break;
  2074. udelay(1);
  2075. }
  2076. tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
  2077. tw32_f(MAC_MODE, tp->mac_mode);
  2078. udelay(40);
  2079. *flags = aninfo.flags;
  2080. if (status == ANEG_DONE &&
  2081. (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
  2082. MR_LP_ADV_FULL_DUPLEX)))
  2083. res = 1;
  2084. return res;
  2085. }
  2086. static void tg3_init_bcm8002(struct tg3 *tp)
  2087. {
  2088. u32 mac_status = tr32(MAC_STATUS);
  2089. int i;
  2090. /* Reset when initting first time or we have a link. */
  2091. if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
  2092. !(mac_status & MAC_STATUS_PCS_SYNCED))
  2093. return;
  2094. /* Set PLL lock range. */
  2095. tg3_writephy(tp, 0x16, 0x8007);
  2096. /* SW reset */
  2097. tg3_writephy(tp, MII_BMCR, BMCR_RESET);
  2098. /* Wait for reset to complete. */
  2099. /* XXX schedule_timeout() ... */
  2100. for (i = 0; i < 500; i++)
  2101. udelay(10);
  2102. /* Config mode; select PMA/Ch 1 regs. */
  2103. tg3_writephy(tp, 0x10, 0x8411);
  2104. /* Enable auto-lock and comdet, select txclk for tx. */
  2105. tg3_writephy(tp, 0x11, 0x0a10);
  2106. tg3_writephy(tp, 0x18, 0x00a0);
  2107. tg3_writephy(tp, 0x16, 0x41ff);
  2108. /* Assert and deassert POR. */
  2109. tg3_writephy(tp, 0x13, 0x0400);
  2110. udelay(40);
  2111. tg3_writephy(tp, 0x13, 0x0000);
  2112. tg3_writephy(tp, 0x11, 0x0a50);
  2113. udelay(40);
  2114. tg3_writephy(tp, 0x11, 0x0a10);
  2115. /* Wait for signal to stabilize */
  2116. /* XXX schedule_timeout() ... */
  2117. for (i = 0; i < 15000; i++)
  2118. udelay(10);
  2119. /* Deselect the channel register so we can read the PHYID
  2120. * later.
  2121. */
  2122. tg3_writephy(tp, 0x10, 0x8011);
  2123. }
  2124. static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
  2125. {
  2126. u32 sg_dig_ctrl, sg_dig_status;
  2127. u32 serdes_cfg, expected_sg_dig_ctrl;
  2128. int workaround, port_a;
  2129. int current_link_up;
  2130. serdes_cfg = 0;
  2131. expected_sg_dig_ctrl = 0;
  2132. workaround = 0;
  2133. port_a = 1;
  2134. current_link_up = 0;
  2135. if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
  2136. tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
  2137. workaround = 1;
  2138. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  2139. port_a = 0;
  2140. /* preserve bits 0-11,13,14 for signal pre-emphasis */
  2141. /* preserve bits 20-23 for voltage regulator */
  2142. serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
  2143. }
  2144. sg_dig_ctrl = tr32(SG_DIG_CTRL);
  2145. if (tp->link_config.autoneg != AUTONEG_ENABLE) {
  2146. if (sg_dig_ctrl & (1 << 31)) {
  2147. if (workaround) {
  2148. u32 val = serdes_cfg;
  2149. if (port_a)
  2150. val |= 0xc010000;
  2151. else
  2152. val |= 0x4010000;
  2153. tw32_f(MAC_SERDES_CFG, val);
  2154. }
  2155. tw32_f(SG_DIG_CTRL, 0x01388400);
  2156. }
  2157. if (mac_status & MAC_STATUS_PCS_SYNCED) {
  2158. tg3_setup_flow_control(tp, 0, 0);
  2159. current_link_up = 1;
  2160. }
  2161. goto out;
  2162. }
  2163. /* Want auto-negotiation. */
  2164. expected_sg_dig_ctrl = 0x81388400;
  2165. /* Pause capability */
  2166. expected_sg_dig_ctrl |= (1 << 11);
  2167. /* Asymettric pause */
  2168. expected_sg_dig_ctrl |= (1 << 12);
  2169. if (sg_dig_ctrl != expected_sg_dig_ctrl) {
  2170. if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
  2171. tp->serdes_counter &&
  2172. ((mac_status & (MAC_STATUS_PCS_SYNCED |
  2173. MAC_STATUS_RCVD_CFG)) ==
  2174. MAC_STATUS_PCS_SYNCED)) {
  2175. tp->serdes_counter--;
  2176. current_link_up = 1;
  2177. goto out;
  2178. }
  2179. restart_autoneg:
  2180. if (workaround)
  2181. tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
  2182. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
  2183. udelay(5);
  2184. tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
  2185. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2186. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2187. } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
  2188. MAC_STATUS_SIGNAL_DET)) {
  2189. sg_dig_status = tr32(SG_DIG_STATUS);
  2190. mac_status = tr32(MAC_STATUS);
  2191. if ((sg_dig_status & (1 << 1)) &&
  2192. (mac_status & MAC_STATUS_PCS_SYNCED)) {
  2193. u32 local_adv, remote_adv;
  2194. local_adv = ADVERTISE_PAUSE_CAP;
  2195. remote_adv = 0;
  2196. if (sg_dig_status & (1 << 19))
  2197. remote_adv |= LPA_PAUSE_CAP;
  2198. if (sg_dig_status & (1 << 20))
  2199. remote_adv |= LPA_PAUSE_ASYM;
  2200. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2201. current_link_up = 1;
  2202. tp->serdes_counter = 0;
  2203. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2204. } else if (!(sg_dig_status & (1 << 1))) {
  2205. if (tp->serdes_counter)
  2206. tp->serdes_counter--;
  2207. else {
  2208. if (workaround) {
  2209. u32 val = serdes_cfg;
  2210. if (port_a)
  2211. val |= 0xc010000;
  2212. else
  2213. val |= 0x4010000;
  2214. tw32_f(MAC_SERDES_CFG, val);
  2215. }
  2216. tw32_f(SG_DIG_CTRL, 0x01388400);
  2217. udelay(40);
  2218. /* Link parallel detection - link is up */
  2219. /* only if we have PCS_SYNC and not */
  2220. /* receiving config code words */
  2221. mac_status = tr32(MAC_STATUS);
  2222. if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
  2223. !(mac_status & MAC_STATUS_RCVD_CFG)) {
  2224. tg3_setup_flow_control(tp, 0, 0);
  2225. current_link_up = 1;
  2226. tp->tg3_flags2 |=
  2227. TG3_FLG2_PARALLEL_DETECT;
  2228. tp->serdes_counter =
  2229. SERDES_PARALLEL_DET_TIMEOUT;
  2230. } else
  2231. goto restart_autoneg;
  2232. }
  2233. }
  2234. } else {
  2235. tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
  2236. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2237. }
  2238. out:
  2239. return current_link_up;
  2240. }
  2241. static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
  2242. {
  2243. int current_link_up = 0;
  2244. if (!(mac_status & MAC_STATUS_PCS_SYNCED))
  2245. goto out;
  2246. if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2247. u32 flags;
  2248. int i;
  2249. if (fiber_autoneg(tp, &flags)) {
  2250. u32 local_adv, remote_adv;
  2251. local_adv = ADVERTISE_PAUSE_CAP;
  2252. remote_adv = 0;
  2253. if (flags & MR_LP_ADV_SYM_PAUSE)
  2254. remote_adv |= LPA_PAUSE_CAP;
  2255. if (flags & MR_LP_ADV_ASYM_PAUSE)
  2256. remote_adv |= LPA_PAUSE_ASYM;
  2257. tg3_setup_flow_control(tp, local_adv, remote_adv);
  2258. current_link_up = 1;
  2259. }
  2260. for (i = 0; i < 30; i++) {
  2261. udelay(20);
  2262. tw32_f(MAC_STATUS,
  2263. (MAC_STATUS_SYNC_CHANGED |
  2264. MAC_STATUS_CFG_CHANGED));
  2265. udelay(40);
  2266. if ((tr32(MAC_STATUS) &
  2267. (MAC_STATUS_SYNC_CHANGED |
  2268. MAC_STATUS_CFG_CHANGED)) == 0)
  2269. break;
  2270. }
  2271. mac_status = tr32(MAC_STATUS);
  2272. if (current_link_up == 0 &&
  2273. (mac_status & MAC_STATUS_PCS_SYNCED) &&
  2274. !(mac_status & MAC_STATUS_RCVD_CFG))
  2275. current_link_up = 1;
  2276. } else {
  2277. /* Forcing 1000FD link up. */
  2278. current_link_up = 1;
  2279. tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
  2280. udelay(40);
  2281. tw32_f(MAC_MODE, tp->mac_mode);
  2282. udelay(40);
  2283. }
  2284. out:
  2285. return current_link_up;
  2286. }
  2287. static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
  2288. {
  2289. u32 orig_pause_cfg;
  2290. u16 orig_active_speed;
  2291. u8 orig_active_duplex;
  2292. u32 mac_status;
  2293. int current_link_up;
  2294. int i;
  2295. orig_pause_cfg =
  2296. (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2297. TG3_FLAG_TX_PAUSE));
  2298. orig_active_speed = tp->link_config.active_speed;
  2299. orig_active_duplex = tp->link_config.active_duplex;
  2300. if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
  2301. netif_carrier_ok(tp->dev) &&
  2302. (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
  2303. mac_status = tr32(MAC_STATUS);
  2304. mac_status &= (MAC_STATUS_PCS_SYNCED |
  2305. MAC_STATUS_SIGNAL_DET |
  2306. MAC_STATUS_CFG_CHANGED |
  2307. MAC_STATUS_RCVD_CFG);
  2308. if (mac_status == (MAC_STATUS_PCS_SYNCED |
  2309. MAC_STATUS_SIGNAL_DET)) {
  2310. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2311. MAC_STATUS_CFG_CHANGED));
  2312. return 0;
  2313. }
  2314. }
  2315. tw32_f(MAC_TX_AUTO_NEG, 0);
  2316. tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
  2317. tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
  2318. tw32_f(MAC_MODE, tp->mac_mode);
  2319. udelay(40);
  2320. if (tp->phy_id == PHY_ID_BCM8002)
  2321. tg3_init_bcm8002(tp);
  2322. /* Enable link change event even when serdes polling. */
  2323. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2324. udelay(40);
  2325. current_link_up = 0;
  2326. mac_status = tr32(MAC_STATUS);
  2327. if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
  2328. current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
  2329. else
  2330. current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
  2331. tp->hw_status->status =
  2332. (SD_STATUS_UPDATED |
  2333. (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
  2334. for (i = 0; i < 100; i++) {
  2335. tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
  2336. MAC_STATUS_CFG_CHANGED));
  2337. udelay(5);
  2338. if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
  2339. MAC_STATUS_CFG_CHANGED |
  2340. MAC_STATUS_LNKSTATE_CHANGED)) == 0)
  2341. break;
  2342. }
  2343. mac_status = tr32(MAC_STATUS);
  2344. if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
  2345. current_link_up = 0;
  2346. if (tp->link_config.autoneg == AUTONEG_ENABLE &&
  2347. tp->serdes_counter == 0) {
  2348. tw32_f(MAC_MODE, (tp->mac_mode |
  2349. MAC_MODE_SEND_CONFIGS));
  2350. udelay(1);
  2351. tw32_f(MAC_MODE, tp->mac_mode);
  2352. }
  2353. }
  2354. if (current_link_up == 1) {
  2355. tp->link_config.active_speed = SPEED_1000;
  2356. tp->link_config.active_duplex = DUPLEX_FULL;
  2357. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2358. LED_CTRL_LNKLED_OVERRIDE |
  2359. LED_CTRL_1000MBPS_ON));
  2360. } else {
  2361. tp->link_config.active_speed = SPEED_INVALID;
  2362. tp->link_config.active_duplex = DUPLEX_INVALID;
  2363. tw32(MAC_LED_CTRL, (tp->led_ctrl |
  2364. LED_CTRL_LNKLED_OVERRIDE |
  2365. LED_CTRL_TRAFFIC_OVERRIDE));
  2366. }
  2367. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2368. if (current_link_up)
  2369. netif_carrier_on(tp->dev);
  2370. else
  2371. netif_carrier_off(tp->dev);
  2372. tg3_link_report(tp);
  2373. } else {
  2374. u32 now_pause_cfg =
  2375. tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
  2376. TG3_FLAG_TX_PAUSE);
  2377. if (orig_pause_cfg != now_pause_cfg ||
  2378. orig_active_speed != tp->link_config.active_speed ||
  2379. orig_active_duplex != tp->link_config.active_duplex)
  2380. tg3_link_report(tp);
  2381. }
  2382. return 0;
  2383. }
  2384. static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
  2385. {
  2386. int current_link_up, err = 0;
  2387. u32 bmsr, bmcr;
  2388. u16 current_speed;
  2389. u8 current_duplex;
  2390. tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
  2391. tw32_f(MAC_MODE, tp->mac_mode);
  2392. udelay(40);
  2393. tw32(MAC_EVENT, 0);
  2394. tw32_f(MAC_STATUS,
  2395. (MAC_STATUS_SYNC_CHANGED |
  2396. MAC_STATUS_CFG_CHANGED |
  2397. MAC_STATUS_MI_COMPLETION |
  2398. MAC_STATUS_LNKSTATE_CHANGED));
  2399. udelay(40);
  2400. if (force_reset)
  2401. tg3_phy_reset(tp);
  2402. current_link_up = 0;
  2403. current_speed = SPEED_INVALID;
  2404. current_duplex = DUPLEX_INVALID;
  2405. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2406. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2407. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  2408. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2409. bmsr |= BMSR_LSTATUS;
  2410. else
  2411. bmsr &= ~BMSR_LSTATUS;
  2412. }
  2413. err |= tg3_readphy(tp, MII_BMCR, &bmcr);
  2414. if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
  2415. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2416. /* do nothing, just check for link up at the end */
  2417. } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
  2418. u32 adv, new_adv;
  2419. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2420. new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
  2421. ADVERTISE_1000XPAUSE |
  2422. ADVERTISE_1000XPSE_ASYM |
  2423. ADVERTISE_SLCT);
  2424. /* Always advertise symmetric PAUSE just like copper */
  2425. new_adv |= ADVERTISE_1000XPAUSE;
  2426. if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
  2427. new_adv |= ADVERTISE_1000XHALF;
  2428. if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
  2429. new_adv |= ADVERTISE_1000XFULL;
  2430. if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
  2431. tg3_writephy(tp, MII_ADVERTISE, new_adv);
  2432. bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
  2433. tg3_writephy(tp, MII_BMCR, bmcr);
  2434. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2435. tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
  2436. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2437. return err;
  2438. }
  2439. } else {
  2440. u32 new_bmcr;
  2441. bmcr &= ~BMCR_SPEED1000;
  2442. new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
  2443. if (tp->link_config.duplex == DUPLEX_FULL)
  2444. new_bmcr |= BMCR_FULLDPLX;
  2445. if (new_bmcr != bmcr) {
  2446. /* BMCR_SPEED1000 is a reserved bit that needs
  2447. * to be set on write.
  2448. */
  2449. new_bmcr |= BMCR_SPEED1000;
  2450. /* Force a linkdown */
  2451. if (netif_carrier_ok(tp->dev)) {
  2452. u32 adv;
  2453. err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
  2454. adv &= ~(ADVERTISE_1000XFULL |
  2455. ADVERTISE_1000XHALF |
  2456. ADVERTISE_SLCT);
  2457. tg3_writephy(tp, MII_ADVERTISE, adv);
  2458. tg3_writephy(tp, MII_BMCR, bmcr |
  2459. BMCR_ANRESTART |
  2460. BMCR_ANENABLE);
  2461. udelay(10);
  2462. netif_carrier_off(tp->dev);
  2463. }
  2464. tg3_writephy(tp, MII_BMCR, new_bmcr);
  2465. bmcr = new_bmcr;
  2466. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2467. err |= tg3_readphy(tp, MII_BMSR, &bmsr);
  2468. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  2469. ASIC_REV_5714) {
  2470. if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
  2471. bmsr |= BMSR_LSTATUS;
  2472. else
  2473. bmsr &= ~BMSR_LSTATUS;
  2474. }
  2475. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2476. }
  2477. }
  2478. if (bmsr & BMSR_LSTATUS) {
  2479. current_speed = SPEED_1000;
  2480. current_link_up = 1;
  2481. if (bmcr & BMCR_FULLDPLX)
  2482. current_duplex = DUPLEX_FULL;
  2483. else
  2484. current_duplex = DUPLEX_HALF;
  2485. if (bmcr & BMCR_ANENABLE) {
  2486. u32 local_adv, remote_adv, common;
  2487. err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
  2488. err |= tg3_readphy(tp, MII_LPA, &remote_adv);
  2489. common = local_adv & remote_adv;
  2490. if (common & (ADVERTISE_1000XHALF |
  2491. ADVERTISE_1000XFULL)) {
  2492. if (common & ADVERTISE_1000XFULL)
  2493. current_duplex = DUPLEX_FULL;
  2494. else
  2495. current_duplex = DUPLEX_HALF;
  2496. tg3_setup_flow_control(tp, local_adv,
  2497. remote_adv);
  2498. }
  2499. else
  2500. current_link_up = 0;
  2501. }
  2502. }
  2503. tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
  2504. if (tp->link_config.active_duplex == DUPLEX_HALF)
  2505. tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
  2506. tw32_f(MAC_MODE, tp->mac_mode);
  2507. udelay(40);
  2508. tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
  2509. tp->link_config.active_speed = current_speed;
  2510. tp->link_config.active_duplex = current_duplex;
  2511. if (current_link_up != netif_carrier_ok(tp->dev)) {
  2512. if (current_link_up)
  2513. netif_carrier_on(tp->dev);
  2514. else {
  2515. netif_carrier_off(tp->dev);
  2516. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2517. }
  2518. tg3_link_report(tp);
  2519. }
  2520. return err;
  2521. }
  2522. static void tg3_serdes_parallel_detect(struct tg3 *tp)
  2523. {
  2524. if (tp->serdes_counter) {
  2525. /* Give autoneg time to complete. */
  2526. tp->serdes_counter--;
  2527. return;
  2528. }
  2529. if (!netif_carrier_ok(tp->dev) &&
  2530. (tp->link_config.autoneg == AUTONEG_ENABLE)) {
  2531. u32 bmcr;
  2532. tg3_readphy(tp, MII_BMCR, &bmcr);
  2533. if (bmcr & BMCR_ANENABLE) {
  2534. u32 phy1, phy2;
  2535. /* Select shadow register 0x1f */
  2536. tg3_writephy(tp, 0x1c, 0x7c00);
  2537. tg3_readphy(tp, 0x1c, &phy1);
  2538. /* Select expansion interrupt status register */
  2539. tg3_writephy(tp, 0x17, 0x0f01);
  2540. tg3_readphy(tp, 0x15, &phy2);
  2541. tg3_readphy(tp, 0x15, &phy2);
  2542. if ((phy1 & 0x10) && !(phy2 & 0x20)) {
  2543. /* We have signal detect and not receiving
  2544. * config code words, link is up by parallel
  2545. * detection.
  2546. */
  2547. bmcr &= ~BMCR_ANENABLE;
  2548. bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
  2549. tg3_writephy(tp, MII_BMCR, bmcr);
  2550. tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
  2551. }
  2552. }
  2553. }
  2554. else if (netif_carrier_ok(tp->dev) &&
  2555. (tp->link_config.autoneg == AUTONEG_ENABLE) &&
  2556. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
  2557. u32 phy2;
  2558. /* Select expansion interrupt status register */
  2559. tg3_writephy(tp, 0x17, 0x0f01);
  2560. tg3_readphy(tp, 0x15, &phy2);
  2561. if (phy2 & 0x20) {
  2562. u32 bmcr;
  2563. /* Config code words received, turn on autoneg. */
  2564. tg3_readphy(tp, MII_BMCR, &bmcr);
  2565. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
  2566. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  2567. }
  2568. }
  2569. }
  2570. static int tg3_setup_phy(struct tg3 *tp, int force_reset)
  2571. {
  2572. int err;
  2573. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  2574. err = tg3_setup_fiber_phy(tp, force_reset);
  2575. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  2576. err = tg3_setup_fiber_mii_phy(tp, force_reset);
  2577. } else {
  2578. err = tg3_setup_copper_phy(tp, force_reset);
  2579. }
  2580. if (tp->link_config.active_speed == SPEED_1000 &&
  2581. tp->link_config.active_duplex == DUPLEX_HALF)
  2582. tw32(MAC_TX_LENGTHS,
  2583. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2584. (6 << TX_LENGTHS_IPG_SHIFT) |
  2585. (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2586. else
  2587. tw32(MAC_TX_LENGTHS,
  2588. ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  2589. (6 << TX_LENGTHS_IPG_SHIFT) |
  2590. (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
  2591. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  2592. if (netif_carrier_ok(tp->dev)) {
  2593. tw32(HOSTCC_STAT_COAL_TICKS,
  2594. tp->coal.stats_block_coalesce_usecs);
  2595. } else {
  2596. tw32(HOSTCC_STAT_COAL_TICKS, 0);
  2597. }
  2598. }
  2599. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
  2600. u32 val = tr32(PCIE_PWR_MGMT_THRESH);
  2601. if (!netif_carrier_ok(tp->dev))
  2602. val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
  2603. tp->pwrmgmt_thresh;
  2604. else
  2605. val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
  2606. tw32(PCIE_PWR_MGMT_THRESH, val);
  2607. }
  2608. return err;
  2609. }
  2610. /* This is called whenever we suspect that the system chipset is re-
  2611. * ordering the sequence of MMIO to the tx send mailbox. The symptom
  2612. * is bogus tx completions. We try to recover by setting the
  2613. * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
  2614. * in the workqueue.
  2615. */
  2616. static void tg3_tx_recover(struct tg3 *tp)
  2617. {
  2618. BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
  2619. tp->write32_tx_mbox == tg3_write_indirect_mbox);
  2620. printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
  2621. "mapped I/O cycles to the network device, attempting to "
  2622. "recover. Please report the problem to the driver maintainer "
  2623. "and include system chipset information.\n", tp->dev->name);
  2624. spin_lock(&tp->lock);
  2625. tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
  2626. spin_unlock(&tp->lock);
  2627. }
  2628. static inline u32 tg3_tx_avail(struct tg3 *tp)
  2629. {
  2630. smp_mb();
  2631. return (tp->tx_pending -
  2632. ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
  2633. }
  2634. /* Tigon3 never reports partial packet sends. So we do not
  2635. * need special logic to handle SKBs that have not had all
  2636. * of their frags sent yet, like SunGEM does.
  2637. */
  2638. static void tg3_tx(struct tg3 *tp)
  2639. {
  2640. u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
  2641. u32 sw_idx = tp->tx_cons;
  2642. while (sw_idx != hw_idx) {
  2643. struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
  2644. struct sk_buff *skb = ri->skb;
  2645. int i, tx_bug = 0;
  2646. if (unlikely(skb == NULL)) {
  2647. tg3_tx_recover(tp);
  2648. return;
  2649. }
  2650. pci_unmap_single(tp->pdev,
  2651. pci_unmap_addr(ri, mapping),
  2652. skb_headlen(skb),
  2653. PCI_DMA_TODEVICE);
  2654. ri->skb = NULL;
  2655. sw_idx = NEXT_TX(sw_idx);
  2656. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  2657. ri = &tp->tx_buffers[sw_idx];
  2658. if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
  2659. tx_bug = 1;
  2660. pci_unmap_page(tp->pdev,
  2661. pci_unmap_addr(ri, mapping),
  2662. skb_shinfo(skb)->frags[i].size,
  2663. PCI_DMA_TODEVICE);
  2664. sw_idx = NEXT_TX(sw_idx);
  2665. }
  2666. dev_kfree_skb(skb);
  2667. if (unlikely(tx_bug)) {
  2668. tg3_tx_recover(tp);
  2669. return;
  2670. }
  2671. }
  2672. tp->tx_cons = sw_idx;
  2673. /* Need to make the tx_cons update visible to tg3_start_xmit()
  2674. * before checking for netif_queue_stopped(). Without the
  2675. * memory barrier, there is a small possibility that tg3_start_xmit()
  2676. * will miss it and cause the queue to be stopped forever.
  2677. */
  2678. smp_mb();
  2679. if (unlikely(netif_queue_stopped(tp->dev) &&
  2680. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
  2681. netif_tx_lock(tp->dev);
  2682. if (netif_queue_stopped(tp->dev) &&
  2683. (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
  2684. netif_wake_queue(tp->dev);
  2685. netif_tx_unlock(tp->dev);
  2686. }
  2687. }
  2688. /* Returns size of skb allocated or < 0 on error.
  2689. *
  2690. * We only need to fill in the address because the other members
  2691. * of the RX descriptor are invariant, see tg3_init_rings.
  2692. *
  2693. * Note the purposeful assymetry of cpu vs. chip accesses. For
  2694. * posting buffers we only dirty the first cache line of the RX
  2695. * descriptor (containing the address). Whereas for the RX status
  2696. * buffers the cpu only reads the last cacheline of the RX descriptor
  2697. * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
  2698. */
  2699. static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
  2700. int src_idx, u32 dest_idx_unmasked)
  2701. {
  2702. struct tg3_rx_buffer_desc *desc;
  2703. struct ring_info *map, *src_map;
  2704. struct sk_buff *skb;
  2705. dma_addr_t mapping;
  2706. int skb_size, dest_idx;
  2707. src_map = NULL;
  2708. switch (opaque_key) {
  2709. case RXD_OPAQUE_RING_STD:
  2710. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2711. desc = &tp->rx_std[dest_idx];
  2712. map = &tp->rx_std_buffers[dest_idx];
  2713. if (src_idx >= 0)
  2714. src_map = &tp->rx_std_buffers[src_idx];
  2715. skb_size = tp->rx_pkt_buf_sz;
  2716. break;
  2717. case RXD_OPAQUE_RING_JUMBO:
  2718. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2719. desc = &tp->rx_jumbo[dest_idx];
  2720. map = &tp->rx_jumbo_buffers[dest_idx];
  2721. if (src_idx >= 0)
  2722. src_map = &tp->rx_jumbo_buffers[src_idx];
  2723. skb_size = RX_JUMBO_PKT_BUF_SZ;
  2724. break;
  2725. default:
  2726. return -EINVAL;
  2727. };
  2728. /* Do not overwrite any of the map or rp information
  2729. * until we are sure we can commit to a new buffer.
  2730. *
  2731. * Callers depend upon this behavior and assume that
  2732. * we leave everything unchanged if we fail.
  2733. */
  2734. skb = netdev_alloc_skb(tp->dev, skb_size);
  2735. if (skb == NULL)
  2736. return -ENOMEM;
  2737. skb_reserve(skb, tp->rx_offset);
  2738. mapping = pci_map_single(tp->pdev, skb->data,
  2739. skb_size - tp->rx_offset,
  2740. PCI_DMA_FROMDEVICE);
  2741. map->skb = skb;
  2742. pci_unmap_addr_set(map, mapping, mapping);
  2743. if (src_map != NULL)
  2744. src_map->skb = NULL;
  2745. desc->addr_hi = ((u64)mapping >> 32);
  2746. desc->addr_lo = ((u64)mapping & 0xffffffff);
  2747. return skb_size;
  2748. }
  2749. /* We only need to move over in the address because the other
  2750. * members of the RX descriptor are invariant. See notes above
  2751. * tg3_alloc_rx_skb for full details.
  2752. */
  2753. static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
  2754. int src_idx, u32 dest_idx_unmasked)
  2755. {
  2756. struct tg3_rx_buffer_desc *src_desc, *dest_desc;
  2757. struct ring_info *src_map, *dest_map;
  2758. int dest_idx;
  2759. switch (opaque_key) {
  2760. case RXD_OPAQUE_RING_STD:
  2761. dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
  2762. dest_desc = &tp->rx_std[dest_idx];
  2763. dest_map = &tp->rx_std_buffers[dest_idx];
  2764. src_desc = &tp->rx_std[src_idx];
  2765. src_map = &tp->rx_std_buffers[src_idx];
  2766. break;
  2767. case RXD_OPAQUE_RING_JUMBO:
  2768. dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
  2769. dest_desc = &tp->rx_jumbo[dest_idx];
  2770. dest_map = &tp->rx_jumbo_buffers[dest_idx];
  2771. src_desc = &tp->rx_jumbo[src_idx];
  2772. src_map = &tp->rx_jumbo_buffers[src_idx];
  2773. break;
  2774. default:
  2775. return;
  2776. };
  2777. dest_map->skb = src_map->skb;
  2778. pci_unmap_addr_set(dest_map, mapping,
  2779. pci_unmap_addr(src_map, mapping));
  2780. dest_desc->addr_hi = src_desc->addr_hi;
  2781. dest_desc->addr_lo = src_desc->addr_lo;
  2782. src_map->skb = NULL;
  2783. }
  2784. #if TG3_VLAN_TAG_USED
  2785. static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
  2786. {
  2787. return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
  2788. }
  2789. #endif
  2790. /* The RX ring scheme is composed of multiple rings which post fresh
  2791. * buffers to the chip, and one special ring the chip uses to report
  2792. * status back to the host.
  2793. *
  2794. * The special ring reports the status of received packets to the
  2795. * host. The chip does not write into the original descriptor the
  2796. * RX buffer was obtained from. The chip simply takes the original
  2797. * descriptor as provided by the host, updates the status and length
  2798. * field, then writes this into the next status ring entry.
  2799. *
  2800. * Each ring the host uses to post buffers to the chip is described
  2801. * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
  2802. * it is first placed into the on-chip ram. When the packet's length
  2803. * is known, it walks down the TG3_BDINFO entries to select the ring.
  2804. * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
  2805. * which is within the range of the new packet's length is chosen.
  2806. *
  2807. * The "separate ring for rx status" scheme may sound queer, but it makes
  2808. * sense from a cache coherency perspective. If only the host writes
  2809. * to the buffer post rings, and only the chip writes to the rx status
  2810. * rings, then cache lines never move beyond shared-modified state.
  2811. * If both the host and chip were to write into the same ring, cache line
  2812. * eviction could occur since both entities want it in an exclusive state.
  2813. */
  2814. static int tg3_rx(struct tg3 *tp, int budget)
  2815. {
  2816. u32 work_mask, rx_std_posted = 0;
  2817. u32 sw_idx = tp->rx_rcb_ptr;
  2818. u16 hw_idx;
  2819. int received;
  2820. hw_idx = tp->hw_status->idx[0].rx_producer;
  2821. /*
  2822. * We need to order the read of hw_idx and the read of
  2823. * the opaque cookie.
  2824. */
  2825. rmb();
  2826. work_mask = 0;
  2827. received = 0;
  2828. while (sw_idx != hw_idx && budget > 0) {
  2829. struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
  2830. unsigned int len;
  2831. struct sk_buff *skb;
  2832. dma_addr_t dma_addr;
  2833. u32 opaque_key, desc_idx, *post_ptr;
  2834. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  2835. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  2836. if (opaque_key == RXD_OPAQUE_RING_STD) {
  2837. dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
  2838. mapping);
  2839. skb = tp->rx_std_buffers[desc_idx].skb;
  2840. post_ptr = &tp->rx_std_ptr;
  2841. rx_std_posted++;
  2842. } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
  2843. dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
  2844. mapping);
  2845. skb = tp->rx_jumbo_buffers[desc_idx].skb;
  2846. post_ptr = &tp->rx_jumbo_ptr;
  2847. }
  2848. else {
  2849. goto next_pkt_nopost;
  2850. }
  2851. work_mask |= opaque_key;
  2852. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  2853. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
  2854. drop_it:
  2855. tg3_recycle_rx(tp, opaque_key,
  2856. desc_idx, *post_ptr);
  2857. drop_it_no_recycle:
  2858. /* Other statistics kept track of by card. */
  2859. tp->net_stats.rx_dropped++;
  2860. goto next_pkt;
  2861. }
  2862. len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
  2863. if (len > RX_COPY_THRESHOLD
  2864. && tp->rx_offset == 2
  2865. /* rx_offset != 2 iff this is a 5701 card running
  2866. * in PCI-X mode [see tg3_get_invariants()] */
  2867. ) {
  2868. int skb_size;
  2869. skb_size = tg3_alloc_rx_skb(tp, opaque_key,
  2870. desc_idx, *post_ptr);
  2871. if (skb_size < 0)
  2872. goto drop_it;
  2873. pci_unmap_single(tp->pdev, dma_addr,
  2874. skb_size - tp->rx_offset,
  2875. PCI_DMA_FROMDEVICE);
  2876. skb_put(skb, len);
  2877. } else {
  2878. struct sk_buff *copy_skb;
  2879. tg3_recycle_rx(tp, opaque_key,
  2880. desc_idx, *post_ptr);
  2881. copy_skb = netdev_alloc_skb(tp->dev, len + 2);
  2882. if (copy_skb == NULL)
  2883. goto drop_it_no_recycle;
  2884. skb_reserve(copy_skb, 2);
  2885. skb_put(copy_skb, len);
  2886. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2887. skb_copy_from_linear_data(skb, copy_skb->data, len);
  2888. pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
  2889. /* We'll reuse the original ring buffer. */
  2890. skb = copy_skb;
  2891. }
  2892. if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
  2893. (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
  2894. (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
  2895. >> RXD_TCPCSUM_SHIFT) == 0xffff))
  2896. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2897. else
  2898. skb->ip_summed = CHECKSUM_NONE;
  2899. skb->protocol = eth_type_trans(skb, tp->dev);
  2900. #if TG3_VLAN_TAG_USED
  2901. if (tp->vlgrp != NULL &&
  2902. desc->type_flags & RXD_FLAG_VLAN) {
  2903. tg3_vlan_rx(tp, skb,
  2904. desc->err_vlan & RXD_VLAN_MASK);
  2905. } else
  2906. #endif
  2907. netif_receive_skb(skb);
  2908. tp->dev->last_rx = jiffies;
  2909. received++;
  2910. budget--;
  2911. next_pkt:
  2912. (*post_ptr)++;
  2913. if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
  2914. u32 idx = *post_ptr % TG3_RX_RING_SIZE;
  2915. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
  2916. TG3_64BIT_REG_LOW, idx);
  2917. work_mask &= ~RXD_OPAQUE_RING_STD;
  2918. rx_std_posted = 0;
  2919. }
  2920. next_pkt_nopost:
  2921. sw_idx++;
  2922. sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
  2923. /* Refresh hw_idx to see if there is new work */
  2924. if (sw_idx == hw_idx) {
  2925. hw_idx = tp->hw_status->idx[0].rx_producer;
  2926. rmb();
  2927. }
  2928. }
  2929. /* ACK the status ring. */
  2930. tp->rx_rcb_ptr = sw_idx;
  2931. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
  2932. /* Refill RX ring(s). */
  2933. if (work_mask & RXD_OPAQUE_RING_STD) {
  2934. sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
  2935. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  2936. sw_idx);
  2937. }
  2938. if (work_mask & RXD_OPAQUE_RING_JUMBO) {
  2939. sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
  2940. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  2941. sw_idx);
  2942. }
  2943. mmiowb();
  2944. return received;
  2945. }
  2946. static int tg3_poll(struct napi_struct *napi, int budget)
  2947. {
  2948. struct tg3 *tp = container_of(napi, struct tg3, napi);
  2949. struct net_device *netdev = tp->dev;
  2950. struct tg3_hw_status *sblk = tp->hw_status;
  2951. int work_done = 0;
  2952. /* handle link change and other phy events */
  2953. if (!(tp->tg3_flags &
  2954. (TG3_FLAG_USE_LINKCHG_REG |
  2955. TG3_FLAG_POLL_SERDES))) {
  2956. if (sblk->status & SD_STATUS_LINK_CHG) {
  2957. sblk->status = SD_STATUS_UPDATED |
  2958. (sblk->status & ~SD_STATUS_LINK_CHG);
  2959. spin_lock(&tp->lock);
  2960. tg3_setup_phy(tp, 0);
  2961. spin_unlock(&tp->lock);
  2962. }
  2963. }
  2964. /* run TX completion thread */
  2965. if (sblk->idx[0].tx_consumer != tp->tx_cons) {
  2966. tg3_tx(tp);
  2967. if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
  2968. netif_rx_complete(netdev, napi);
  2969. schedule_work(&tp->reset_task);
  2970. return 0;
  2971. }
  2972. }
  2973. /* run RX thread, within the bounds set by NAPI.
  2974. * All RX "locking" is done by ensuring outside
  2975. * code synchronizes with tg3->napi.poll()
  2976. */
  2977. if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
  2978. work_done = tg3_rx(tp, budget);
  2979. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  2980. tp->last_tag = sblk->status_tag;
  2981. rmb();
  2982. } else
  2983. sblk->status &= ~SD_STATUS_UPDATED;
  2984. /* if no more work, tell net stack and NIC we're done */
  2985. if (!tg3_has_work(tp)) {
  2986. netif_rx_complete(netdev, napi);
  2987. tg3_restart_ints(tp);
  2988. }
  2989. return work_done;
  2990. }
  2991. static void tg3_irq_quiesce(struct tg3 *tp)
  2992. {
  2993. BUG_ON(tp->irq_sync);
  2994. tp->irq_sync = 1;
  2995. smp_mb();
  2996. synchronize_irq(tp->pdev->irq);
  2997. }
  2998. static inline int tg3_irq_sync(struct tg3 *tp)
  2999. {
  3000. return tp->irq_sync;
  3001. }
  3002. /* Fully shutdown all tg3 driver activity elsewhere in the system.
  3003. * If irq_sync is non-zero, then the IRQ handler must be synchronized
  3004. * with as well. Most of the time, this is not necessary except when
  3005. * shutting down the device.
  3006. */
  3007. static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
  3008. {
  3009. spin_lock_bh(&tp->lock);
  3010. if (irq_sync)
  3011. tg3_irq_quiesce(tp);
  3012. }
  3013. static inline void tg3_full_unlock(struct tg3 *tp)
  3014. {
  3015. spin_unlock_bh(&tp->lock);
  3016. }
  3017. /* One-shot MSI handler - Chip automatically disables interrupt
  3018. * after sending MSI so driver doesn't have to do it.
  3019. */
  3020. static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
  3021. {
  3022. struct net_device *dev = dev_id;
  3023. struct tg3 *tp = netdev_priv(dev);
  3024. prefetch(tp->hw_status);
  3025. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3026. if (likely(!tg3_irq_sync(tp)))
  3027. netif_rx_schedule(dev, &tp->napi);
  3028. return IRQ_HANDLED;
  3029. }
  3030. /* MSI ISR - No need to check for interrupt sharing and no need to
  3031. * flush status block and interrupt mailbox. PCI ordering rules
  3032. * guarantee that MSI will arrive after the status block.
  3033. */
  3034. static irqreturn_t tg3_msi(int irq, void *dev_id)
  3035. {
  3036. struct net_device *dev = dev_id;
  3037. struct tg3 *tp = netdev_priv(dev);
  3038. prefetch(tp->hw_status);
  3039. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3040. /*
  3041. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3042. * chip-internal interrupt pending events.
  3043. * Writing non-zero to intr-mbox-0 additional tells the
  3044. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3045. * event coalescing.
  3046. */
  3047. tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3048. if (likely(!tg3_irq_sync(tp)))
  3049. netif_rx_schedule(dev, &tp->napi);
  3050. return IRQ_RETVAL(1);
  3051. }
  3052. static irqreturn_t tg3_interrupt(int irq, void *dev_id)
  3053. {
  3054. struct net_device *dev = dev_id;
  3055. struct tg3 *tp = netdev_priv(dev);
  3056. struct tg3_hw_status *sblk = tp->hw_status;
  3057. unsigned int handled = 1;
  3058. /* In INTx mode, it is possible for the interrupt to arrive at
  3059. * the CPU before the status block posted prior to the interrupt.
  3060. * Reading the PCI State register will confirm whether the
  3061. * interrupt is ours and will flush the status block.
  3062. */
  3063. if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
  3064. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3065. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3066. handled = 0;
  3067. goto out;
  3068. }
  3069. }
  3070. /*
  3071. * Writing any value to intr-mbox-0 clears PCI INTA# and
  3072. * chip-internal interrupt pending events.
  3073. * Writing non-zero to intr-mbox-0 additional tells the
  3074. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3075. * event coalescing.
  3076. *
  3077. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3078. * spurious interrupts. The flush impacts performance but
  3079. * excessive spurious interrupts can be worse in some cases.
  3080. */
  3081. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3082. if (tg3_irq_sync(tp))
  3083. goto out;
  3084. sblk->status &= ~SD_STATUS_UPDATED;
  3085. if (likely(tg3_has_work(tp))) {
  3086. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3087. netif_rx_schedule(dev, &tp->napi);
  3088. } else {
  3089. /* No work, shared interrupt perhaps? re-enable
  3090. * interrupts, and flush that PCI write
  3091. */
  3092. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
  3093. 0x00000000);
  3094. }
  3095. out:
  3096. return IRQ_RETVAL(handled);
  3097. }
  3098. static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
  3099. {
  3100. struct net_device *dev = dev_id;
  3101. struct tg3 *tp = netdev_priv(dev);
  3102. struct tg3_hw_status *sblk = tp->hw_status;
  3103. unsigned int handled = 1;
  3104. /* In INTx mode, it is possible for the interrupt to arrive at
  3105. * the CPU before the status block posted prior to the interrupt.
  3106. * Reading the PCI State register will confirm whether the
  3107. * interrupt is ours and will flush the status block.
  3108. */
  3109. if (unlikely(sblk->status_tag == tp->last_tag)) {
  3110. if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
  3111. (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3112. handled = 0;
  3113. goto out;
  3114. }
  3115. }
  3116. /*
  3117. * writing any value to intr-mbox-0 clears PCI INTA# and
  3118. * chip-internal interrupt pending events.
  3119. * writing non-zero to intr-mbox-0 additional tells the
  3120. * NIC to stop sending us irqs, engaging "in-intr-handler"
  3121. * event coalescing.
  3122. *
  3123. * Flush the mailbox to de-assert the IRQ immediately to prevent
  3124. * spurious interrupts. The flush impacts performance but
  3125. * excessive spurious interrupts can be worse in some cases.
  3126. */
  3127. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
  3128. if (tg3_irq_sync(tp))
  3129. goto out;
  3130. if (netif_rx_schedule_prep(dev, &tp->napi)) {
  3131. prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
  3132. /* Update last_tag to mark that this status has been
  3133. * seen. Because interrupt may be shared, we may be
  3134. * racing with tg3_poll(), so only update last_tag
  3135. * if tg3_poll() is not scheduled.
  3136. */
  3137. tp->last_tag = sblk->status_tag;
  3138. __netif_rx_schedule(dev, &tp->napi);
  3139. }
  3140. out:
  3141. return IRQ_RETVAL(handled);
  3142. }
  3143. /* ISR for interrupt test */
  3144. static irqreturn_t tg3_test_isr(int irq, void *dev_id)
  3145. {
  3146. struct net_device *dev = dev_id;
  3147. struct tg3 *tp = netdev_priv(dev);
  3148. struct tg3_hw_status *sblk = tp->hw_status;
  3149. if ((sblk->status & SD_STATUS_UPDATED) ||
  3150. !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
  3151. tg3_disable_ints(tp);
  3152. return IRQ_RETVAL(1);
  3153. }
  3154. return IRQ_RETVAL(0);
  3155. }
  3156. static int tg3_init_hw(struct tg3 *, int);
  3157. static int tg3_halt(struct tg3 *, int, int);
  3158. /* Restart hardware after configuration changes, self-test, etc.
  3159. * Invoked with tp->lock held.
  3160. */
  3161. static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
  3162. {
  3163. int err;
  3164. err = tg3_init_hw(tp, reset_phy);
  3165. if (err) {
  3166. printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
  3167. "aborting.\n", tp->dev->name);
  3168. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3169. tg3_full_unlock(tp);
  3170. del_timer_sync(&tp->timer);
  3171. tp->irq_sync = 0;
  3172. napi_enable(&tp->napi);
  3173. dev_close(tp->dev);
  3174. tg3_full_lock(tp, 0);
  3175. }
  3176. return err;
  3177. }
  3178. #ifdef CONFIG_NET_POLL_CONTROLLER
  3179. static void tg3_poll_controller(struct net_device *dev)
  3180. {
  3181. struct tg3 *tp = netdev_priv(dev);
  3182. tg3_interrupt(tp->pdev->irq, dev);
  3183. }
  3184. #endif
  3185. static void tg3_reset_task(struct work_struct *work)
  3186. {
  3187. struct tg3 *tp = container_of(work, struct tg3, reset_task);
  3188. unsigned int restart_timer;
  3189. tg3_full_lock(tp, 0);
  3190. if (!netif_running(tp->dev)) {
  3191. tg3_full_unlock(tp);
  3192. return;
  3193. }
  3194. tg3_full_unlock(tp);
  3195. tg3_netif_stop(tp);
  3196. tg3_full_lock(tp, 1);
  3197. restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
  3198. tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
  3199. if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
  3200. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  3201. tp->write32_rx_mbox = tg3_write_flush_reg32;
  3202. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  3203. tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
  3204. }
  3205. tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
  3206. if (tg3_init_hw(tp, 1))
  3207. goto out;
  3208. tg3_netif_start(tp);
  3209. if (restart_timer)
  3210. mod_timer(&tp->timer, jiffies + 1);
  3211. out:
  3212. tg3_full_unlock(tp);
  3213. }
  3214. static void tg3_dump_short_state(struct tg3 *tp)
  3215. {
  3216. printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
  3217. tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
  3218. printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
  3219. tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
  3220. }
  3221. static void tg3_tx_timeout(struct net_device *dev)
  3222. {
  3223. struct tg3 *tp = netdev_priv(dev);
  3224. if (netif_msg_tx_err(tp)) {
  3225. printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
  3226. dev->name);
  3227. tg3_dump_short_state(tp);
  3228. }
  3229. schedule_work(&tp->reset_task);
  3230. }
  3231. /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
  3232. static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
  3233. {
  3234. u32 base = (u32) mapping & 0xffffffff;
  3235. return ((base > 0xffffdcc0) &&
  3236. (base + len + 8 < base));
  3237. }
  3238. /* Test for DMA addresses > 40-bit */
  3239. static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
  3240. int len)
  3241. {
  3242. #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
  3243. if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
  3244. return (((u64) mapping + len) > DMA_40BIT_MASK);
  3245. return 0;
  3246. #else
  3247. return 0;
  3248. #endif
  3249. }
  3250. static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
  3251. /* Workaround 4GB and 40-bit hardware DMA bugs. */
  3252. static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
  3253. u32 last_plus_one, u32 *start,
  3254. u32 base_flags, u32 mss)
  3255. {
  3256. struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
  3257. dma_addr_t new_addr = 0;
  3258. u32 entry = *start;
  3259. int i, ret = 0;
  3260. if (!new_skb) {
  3261. ret = -1;
  3262. } else {
  3263. /* New SKB is guaranteed to be linear. */
  3264. entry = *start;
  3265. new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
  3266. PCI_DMA_TODEVICE);
  3267. /* Make sure new skb does not cross any 4G boundaries.
  3268. * Drop the packet if it does.
  3269. */
  3270. if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
  3271. ret = -1;
  3272. dev_kfree_skb(new_skb);
  3273. new_skb = NULL;
  3274. } else {
  3275. tg3_set_txd(tp, entry, new_addr, new_skb->len,
  3276. base_flags, 1 | (mss << 1));
  3277. *start = NEXT_TX(entry);
  3278. }
  3279. }
  3280. /* Now clean up the sw ring entries. */
  3281. i = 0;
  3282. while (entry != last_plus_one) {
  3283. int len;
  3284. if (i == 0)
  3285. len = skb_headlen(skb);
  3286. else
  3287. len = skb_shinfo(skb)->frags[i-1].size;
  3288. pci_unmap_single(tp->pdev,
  3289. pci_unmap_addr(&tp->tx_buffers[entry], mapping),
  3290. len, PCI_DMA_TODEVICE);
  3291. if (i == 0) {
  3292. tp->tx_buffers[entry].skb = new_skb;
  3293. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
  3294. } else {
  3295. tp->tx_buffers[entry].skb = NULL;
  3296. }
  3297. entry = NEXT_TX(entry);
  3298. i++;
  3299. }
  3300. dev_kfree_skb(skb);
  3301. return ret;
  3302. }
  3303. static void tg3_set_txd(struct tg3 *tp, int entry,
  3304. dma_addr_t mapping, int len, u32 flags,
  3305. u32 mss_and_is_end)
  3306. {
  3307. struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
  3308. int is_end = (mss_and_is_end & 0x1);
  3309. u32 mss = (mss_and_is_end >> 1);
  3310. u32 vlan_tag = 0;
  3311. if (is_end)
  3312. flags |= TXD_FLAG_END;
  3313. if (flags & TXD_FLAG_VLAN) {
  3314. vlan_tag = flags >> 16;
  3315. flags &= 0xffff;
  3316. }
  3317. vlan_tag |= (mss << TXD_MSS_SHIFT);
  3318. txd->addr_hi = ((u64) mapping >> 32);
  3319. txd->addr_lo = ((u64) mapping & 0xffffffff);
  3320. txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
  3321. txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
  3322. }
  3323. /* hard_start_xmit for devices that don't have any bugs and
  3324. * support TG3_FLG2_HW_TSO_2 only.
  3325. */
  3326. static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
  3327. {
  3328. struct tg3 *tp = netdev_priv(dev);
  3329. dma_addr_t mapping;
  3330. u32 len, entry, base_flags, mss;
  3331. len = skb_headlen(skb);
  3332. /* We are running in BH disabled context with netif_tx_lock
  3333. * and TX reclaim runs via tp->napi.poll inside of a software
  3334. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3335. * no IRQ context deadlocks to worry about either. Rejoice!
  3336. */
  3337. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3338. if (!netif_queue_stopped(dev)) {
  3339. netif_stop_queue(dev);
  3340. /* This is a hard error, log it. */
  3341. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3342. "queue awake!\n", dev->name);
  3343. }
  3344. return NETDEV_TX_BUSY;
  3345. }
  3346. entry = tp->tx_prod;
  3347. base_flags = 0;
  3348. mss = 0;
  3349. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3350. int tcp_opt_len, ip_tcp_len;
  3351. if (skb_header_cloned(skb) &&
  3352. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3353. dev_kfree_skb(skb);
  3354. goto out_unlock;
  3355. }
  3356. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  3357. mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
  3358. else {
  3359. struct iphdr *iph = ip_hdr(skb);
  3360. tcp_opt_len = tcp_optlen(skb);
  3361. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3362. iph->check = 0;
  3363. iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
  3364. mss |= (ip_tcp_len + tcp_opt_len) << 9;
  3365. }
  3366. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3367. TXD_FLAG_CPU_POST_DMA);
  3368. tcp_hdr(skb)->check = 0;
  3369. }
  3370. else if (skb->ip_summed == CHECKSUM_PARTIAL)
  3371. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3372. #if TG3_VLAN_TAG_USED
  3373. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3374. base_flags |= (TXD_FLAG_VLAN |
  3375. (vlan_tx_tag_get(skb) << 16));
  3376. #endif
  3377. /* Queue skb data, a.k.a. the main skb fragment. */
  3378. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3379. tp->tx_buffers[entry].skb = skb;
  3380. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3381. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3382. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3383. entry = NEXT_TX(entry);
  3384. /* Now loop through additional data fragments, and queue them. */
  3385. if (skb_shinfo(skb)->nr_frags > 0) {
  3386. unsigned int i, last;
  3387. last = skb_shinfo(skb)->nr_frags - 1;
  3388. for (i = 0; i <= last; i++) {
  3389. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3390. len = frag->size;
  3391. mapping = pci_map_page(tp->pdev,
  3392. frag->page,
  3393. frag->page_offset,
  3394. len, PCI_DMA_TODEVICE);
  3395. tp->tx_buffers[entry].skb = NULL;
  3396. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3397. tg3_set_txd(tp, entry, mapping, len,
  3398. base_flags, (i == last) | (mss << 1));
  3399. entry = NEXT_TX(entry);
  3400. }
  3401. }
  3402. /* Packets are ready, update Tx producer idx local and on card. */
  3403. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3404. tp->tx_prod = entry;
  3405. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3406. netif_stop_queue(dev);
  3407. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3408. netif_wake_queue(tp->dev);
  3409. }
  3410. out_unlock:
  3411. mmiowb();
  3412. dev->trans_start = jiffies;
  3413. return NETDEV_TX_OK;
  3414. }
  3415. static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
  3416. /* Use GSO to workaround a rare TSO bug that may be triggered when the
  3417. * TSO header is greater than 80 bytes.
  3418. */
  3419. static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
  3420. {
  3421. struct sk_buff *segs, *nskb;
  3422. /* Estimate the number of fragments in the worst case */
  3423. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
  3424. netif_stop_queue(tp->dev);
  3425. if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
  3426. return NETDEV_TX_BUSY;
  3427. netif_wake_queue(tp->dev);
  3428. }
  3429. segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
  3430. if (unlikely(IS_ERR(segs)))
  3431. goto tg3_tso_bug_end;
  3432. do {
  3433. nskb = segs;
  3434. segs = segs->next;
  3435. nskb->next = NULL;
  3436. tg3_start_xmit_dma_bug(nskb, tp->dev);
  3437. } while (segs);
  3438. tg3_tso_bug_end:
  3439. dev_kfree_skb(skb);
  3440. return NETDEV_TX_OK;
  3441. }
  3442. /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
  3443. * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
  3444. */
  3445. static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
  3446. {
  3447. struct tg3 *tp = netdev_priv(dev);
  3448. dma_addr_t mapping;
  3449. u32 len, entry, base_flags, mss;
  3450. int would_hit_hwbug;
  3451. len = skb_headlen(skb);
  3452. /* We are running in BH disabled context with netif_tx_lock
  3453. * and TX reclaim runs via tp->napi.poll inside of a software
  3454. * interrupt. Furthermore, IRQ processing runs lockless so we have
  3455. * no IRQ context deadlocks to worry about either. Rejoice!
  3456. */
  3457. if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
  3458. if (!netif_queue_stopped(dev)) {
  3459. netif_stop_queue(dev);
  3460. /* This is a hard error, log it. */
  3461. printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
  3462. "queue awake!\n", dev->name);
  3463. }
  3464. return NETDEV_TX_BUSY;
  3465. }
  3466. entry = tp->tx_prod;
  3467. base_flags = 0;
  3468. if (skb->ip_summed == CHECKSUM_PARTIAL)
  3469. base_flags |= TXD_FLAG_TCPUDP_CSUM;
  3470. mss = 0;
  3471. if ((mss = skb_shinfo(skb)->gso_size) != 0) {
  3472. struct iphdr *iph;
  3473. int tcp_opt_len, ip_tcp_len, hdr_len;
  3474. if (skb_header_cloned(skb) &&
  3475. pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
  3476. dev_kfree_skb(skb);
  3477. goto out_unlock;
  3478. }
  3479. tcp_opt_len = tcp_optlen(skb);
  3480. ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
  3481. hdr_len = ip_tcp_len + tcp_opt_len;
  3482. if (unlikely((ETH_HLEN + hdr_len) > 80) &&
  3483. (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
  3484. return (tg3_tso_bug(tp, skb));
  3485. base_flags |= (TXD_FLAG_CPU_PRE_DMA |
  3486. TXD_FLAG_CPU_POST_DMA);
  3487. iph = ip_hdr(skb);
  3488. iph->check = 0;
  3489. iph->tot_len = htons(mss + hdr_len);
  3490. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  3491. tcp_hdr(skb)->check = 0;
  3492. base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
  3493. } else
  3494. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  3495. iph->daddr, 0,
  3496. IPPROTO_TCP,
  3497. 0);
  3498. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
  3499. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
  3500. if (tcp_opt_len || iph->ihl > 5) {
  3501. int tsflags;
  3502. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  3503. mss |= (tsflags << 11);
  3504. }
  3505. } else {
  3506. if (tcp_opt_len || iph->ihl > 5) {
  3507. int tsflags;
  3508. tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
  3509. base_flags |= tsflags << 12;
  3510. }
  3511. }
  3512. }
  3513. #if TG3_VLAN_TAG_USED
  3514. if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
  3515. base_flags |= (TXD_FLAG_VLAN |
  3516. (vlan_tx_tag_get(skb) << 16));
  3517. #endif
  3518. /* Queue skb data, a.k.a. the main skb fragment. */
  3519. mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
  3520. tp->tx_buffers[entry].skb = skb;
  3521. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3522. would_hit_hwbug = 0;
  3523. if (tg3_4g_overflow_test(mapping, len))
  3524. would_hit_hwbug = 1;
  3525. tg3_set_txd(tp, entry, mapping, len, base_flags,
  3526. (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
  3527. entry = NEXT_TX(entry);
  3528. /* Now loop through additional data fragments, and queue them. */
  3529. if (skb_shinfo(skb)->nr_frags > 0) {
  3530. unsigned int i, last;
  3531. last = skb_shinfo(skb)->nr_frags - 1;
  3532. for (i = 0; i <= last; i++) {
  3533. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  3534. len = frag->size;
  3535. mapping = pci_map_page(tp->pdev,
  3536. frag->page,
  3537. frag->page_offset,
  3538. len, PCI_DMA_TODEVICE);
  3539. tp->tx_buffers[entry].skb = NULL;
  3540. pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
  3541. if (tg3_4g_overflow_test(mapping, len))
  3542. would_hit_hwbug = 1;
  3543. if (tg3_40bit_overflow_test(tp, mapping, len))
  3544. would_hit_hwbug = 1;
  3545. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  3546. tg3_set_txd(tp, entry, mapping, len,
  3547. base_flags, (i == last)|(mss << 1));
  3548. else
  3549. tg3_set_txd(tp, entry, mapping, len,
  3550. base_flags, (i == last));
  3551. entry = NEXT_TX(entry);
  3552. }
  3553. }
  3554. if (would_hit_hwbug) {
  3555. u32 last_plus_one = entry;
  3556. u32 start;
  3557. start = entry - 1 - skb_shinfo(skb)->nr_frags;
  3558. start &= (TG3_TX_RING_SIZE - 1);
  3559. /* If the workaround fails due to memory/mapping
  3560. * failure, silently drop this packet.
  3561. */
  3562. if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
  3563. &start, base_flags, mss))
  3564. goto out_unlock;
  3565. entry = start;
  3566. }
  3567. /* Packets are ready, update Tx producer idx local and on card. */
  3568. tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
  3569. tp->tx_prod = entry;
  3570. if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
  3571. netif_stop_queue(dev);
  3572. if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
  3573. netif_wake_queue(tp->dev);
  3574. }
  3575. out_unlock:
  3576. mmiowb();
  3577. dev->trans_start = jiffies;
  3578. return NETDEV_TX_OK;
  3579. }
  3580. static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
  3581. int new_mtu)
  3582. {
  3583. dev->mtu = new_mtu;
  3584. if (new_mtu > ETH_DATA_LEN) {
  3585. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  3586. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  3587. ethtool_op_set_tso(dev, 0);
  3588. }
  3589. else
  3590. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  3591. } else {
  3592. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  3593. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  3594. tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
  3595. }
  3596. }
  3597. static int tg3_change_mtu(struct net_device *dev, int new_mtu)
  3598. {
  3599. struct tg3 *tp = netdev_priv(dev);
  3600. int err;
  3601. if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
  3602. return -EINVAL;
  3603. if (!netif_running(dev)) {
  3604. /* We'll just catch it later when the
  3605. * device is up'd.
  3606. */
  3607. tg3_set_mtu(dev, tp, new_mtu);
  3608. return 0;
  3609. }
  3610. tg3_netif_stop(tp);
  3611. tg3_full_lock(tp, 1);
  3612. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  3613. tg3_set_mtu(dev, tp, new_mtu);
  3614. err = tg3_restart_hw(tp, 0);
  3615. if (!err)
  3616. tg3_netif_start(tp);
  3617. tg3_full_unlock(tp);
  3618. return err;
  3619. }
  3620. /* Free up pending packets in all rx/tx rings.
  3621. *
  3622. * The chip has been shut down and the driver detached from
  3623. * the networking, so no interrupts or new tx packets will
  3624. * end up in the driver. tp->{tx,}lock is not held and we are not
  3625. * in an interrupt context and thus may sleep.
  3626. */
  3627. static void tg3_free_rings(struct tg3 *tp)
  3628. {
  3629. struct ring_info *rxp;
  3630. int i;
  3631. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3632. rxp = &tp->rx_std_buffers[i];
  3633. if (rxp->skb == NULL)
  3634. continue;
  3635. pci_unmap_single(tp->pdev,
  3636. pci_unmap_addr(rxp, mapping),
  3637. tp->rx_pkt_buf_sz - tp->rx_offset,
  3638. PCI_DMA_FROMDEVICE);
  3639. dev_kfree_skb_any(rxp->skb);
  3640. rxp->skb = NULL;
  3641. }
  3642. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3643. rxp = &tp->rx_jumbo_buffers[i];
  3644. if (rxp->skb == NULL)
  3645. continue;
  3646. pci_unmap_single(tp->pdev,
  3647. pci_unmap_addr(rxp, mapping),
  3648. RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
  3649. PCI_DMA_FROMDEVICE);
  3650. dev_kfree_skb_any(rxp->skb);
  3651. rxp->skb = NULL;
  3652. }
  3653. for (i = 0; i < TG3_TX_RING_SIZE; ) {
  3654. struct tx_ring_info *txp;
  3655. struct sk_buff *skb;
  3656. int j;
  3657. txp = &tp->tx_buffers[i];
  3658. skb = txp->skb;
  3659. if (skb == NULL) {
  3660. i++;
  3661. continue;
  3662. }
  3663. pci_unmap_single(tp->pdev,
  3664. pci_unmap_addr(txp, mapping),
  3665. skb_headlen(skb),
  3666. PCI_DMA_TODEVICE);
  3667. txp->skb = NULL;
  3668. i++;
  3669. for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
  3670. txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
  3671. pci_unmap_page(tp->pdev,
  3672. pci_unmap_addr(txp, mapping),
  3673. skb_shinfo(skb)->frags[j].size,
  3674. PCI_DMA_TODEVICE);
  3675. i++;
  3676. }
  3677. dev_kfree_skb_any(skb);
  3678. }
  3679. }
  3680. /* Initialize tx/rx rings for packet processing.
  3681. *
  3682. * The chip has been shut down and the driver detached from
  3683. * the networking, so no interrupts or new tx packets will
  3684. * end up in the driver. tp->{tx,}lock are held and thus
  3685. * we may not sleep.
  3686. */
  3687. static int tg3_init_rings(struct tg3 *tp)
  3688. {
  3689. u32 i;
  3690. /* Free up all the SKBs. */
  3691. tg3_free_rings(tp);
  3692. /* Zero out all descriptors. */
  3693. memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
  3694. memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
  3695. memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
  3696. memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
  3697. tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
  3698. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  3699. (tp->dev->mtu > ETH_DATA_LEN))
  3700. tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
  3701. /* Initialize invariants of the rings, we only set this
  3702. * stuff once. This works because the card does not
  3703. * write into the rx buffer posting rings.
  3704. */
  3705. for (i = 0; i < TG3_RX_RING_SIZE; i++) {
  3706. struct tg3_rx_buffer_desc *rxd;
  3707. rxd = &tp->rx_std[i];
  3708. rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
  3709. << RXD_LEN_SHIFT;
  3710. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
  3711. rxd->opaque = (RXD_OPAQUE_RING_STD |
  3712. (i << RXD_OPAQUE_INDEX_SHIFT));
  3713. }
  3714. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  3715. for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
  3716. struct tg3_rx_buffer_desc *rxd;
  3717. rxd = &tp->rx_jumbo[i];
  3718. rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
  3719. << RXD_LEN_SHIFT;
  3720. rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
  3721. RXD_FLAG_JUMBO;
  3722. rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
  3723. (i << RXD_OPAQUE_INDEX_SHIFT));
  3724. }
  3725. }
  3726. /* Now allocate fresh SKBs for each rx ring. */
  3727. for (i = 0; i < tp->rx_pending; i++) {
  3728. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
  3729. printk(KERN_WARNING PFX
  3730. "%s: Using a smaller RX standard ring, "
  3731. "only %d out of %d buffers were allocated "
  3732. "successfully.\n",
  3733. tp->dev->name, i, tp->rx_pending);
  3734. if (i == 0)
  3735. return -ENOMEM;
  3736. tp->rx_pending = i;
  3737. break;
  3738. }
  3739. }
  3740. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  3741. for (i = 0; i < tp->rx_jumbo_pending; i++) {
  3742. if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
  3743. -1, i) < 0) {
  3744. printk(KERN_WARNING PFX
  3745. "%s: Using a smaller RX jumbo ring, "
  3746. "only %d out of %d buffers were "
  3747. "allocated successfully.\n",
  3748. tp->dev->name, i, tp->rx_jumbo_pending);
  3749. if (i == 0) {
  3750. tg3_free_rings(tp);
  3751. return -ENOMEM;
  3752. }
  3753. tp->rx_jumbo_pending = i;
  3754. break;
  3755. }
  3756. }
  3757. }
  3758. return 0;
  3759. }
  3760. /*
  3761. * Must not be invoked with interrupt sources disabled and
  3762. * the hardware shutdown down.
  3763. */
  3764. static void tg3_free_consistent(struct tg3 *tp)
  3765. {
  3766. kfree(tp->rx_std_buffers);
  3767. tp->rx_std_buffers = NULL;
  3768. if (tp->rx_std) {
  3769. pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
  3770. tp->rx_std, tp->rx_std_mapping);
  3771. tp->rx_std = NULL;
  3772. }
  3773. if (tp->rx_jumbo) {
  3774. pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  3775. tp->rx_jumbo, tp->rx_jumbo_mapping);
  3776. tp->rx_jumbo = NULL;
  3777. }
  3778. if (tp->rx_rcb) {
  3779. pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  3780. tp->rx_rcb, tp->rx_rcb_mapping);
  3781. tp->rx_rcb = NULL;
  3782. }
  3783. if (tp->tx_ring) {
  3784. pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
  3785. tp->tx_ring, tp->tx_desc_mapping);
  3786. tp->tx_ring = NULL;
  3787. }
  3788. if (tp->hw_status) {
  3789. pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
  3790. tp->hw_status, tp->status_mapping);
  3791. tp->hw_status = NULL;
  3792. }
  3793. if (tp->hw_stats) {
  3794. pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
  3795. tp->hw_stats, tp->stats_mapping);
  3796. tp->hw_stats = NULL;
  3797. }
  3798. }
  3799. /*
  3800. * Must not be invoked with interrupt sources disabled and
  3801. * the hardware shutdown down. Can sleep.
  3802. */
  3803. static int tg3_alloc_consistent(struct tg3 *tp)
  3804. {
  3805. tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
  3806. (TG3_RX_RING_SIZE +
  3807. TG3_RX_JUMBO_RING_SIZE)) +
  3808. (sizeof(struct tx_ring_info) *
  3809. TG3_TX_RING_SIZE),
  3810. GFP_KERNEL);
  3811. if (!tp->rx_std_buffers)
  3812. return -ENOMEM;
  3813. tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
  3814. tp->tx_buffers = (struct tx_ring_info *)
  3815. &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
  3816. tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
  3817. &tp->rx_std_mapping);
  3818. if (!tp->rx_std)
  3819. goto err_out;
  3820. tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
  3821. &tp->rx_jumbo_mapping);
  3822. if (!tp->rx_jumbo)
  3823. goto err_out;
  3824. tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
  3825. &tp->rx_rcb_mapping);
  3826. if (!tp->rx_rcb)
  3827. goto err_out;
  3828. tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
  3829. &tp->tx_desc_mapping);
  3830. if (!tp->tx_ring)
  3831. goto err_out;
  3832. tp->hw_status = pci_alloc_consistent(tp->pdev,
  3833. TG3_HW_STATUS_SIZE,
  3834. &tp->status_mapping);
  3835. if (!tp->hw_status)
  3836. goto err_out;
  3837. tp->hw_stats = pci_alloc_consistent(tp->pdev,
  3838. sizeof(struct tg3_hw_stats),
  3839. &tp->stats_mapping);
  3840. if (!tp->hw_stats)
  3841. goto err_out;
  3842. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  3843. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  3844. return 0;
  3845. err_out:
  3846. tg3_free_consistent(tp);
  3847. return -ENOMEM;
  3848. }
  3849. #define MAX_WAIT_CNT 1000
  3850. /* To stop a block, clear the enable bit and poll till it
  3851. * clears. tp->lock is held.
  3852. */
  3853. static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
  3854. {
  3855. unsigned int i;
  3856. u32 val;
  3857. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  3858. switch (ofs) {
  3859. case RCVLSC_MODE:
  3860. case DMAC_MODE:
  3861. case MBFREE_MODE:
  3862. case BUFMGR_MODE:
  3863. case MEMARB_MODE:
  3864. /* We can't enable/disable these bits of the
  3865. * 5705/5750, just say success.
  3866. */
  3867. return 0;
  3868. default:
  3869. break;
  3870. };
  3871. }
  3872. val = tr32(ofs);
  3873. val &= ~enable_bit;
  3874. tw32_f(ofs, val);
  3875. for (i = 0; i < MAX_WAIT_CNT; i++) {
  3876. udelay(100);
  3877. val = tr32(ofs);
  3878. if ((val & enable_bit) == 0)
  3879. break;
  3880. }
  3881. if (i == MAX_WAIT_CNT && !silent) {
  3882. printk(KERN_ERR PFX "tg3_stop_block timed out, "
  3883. "ofs=%lx enable_bit=%x\n",
  3884. ofs, enable_bit);
  3885. return -ENODEV;
  3886. }
  3887. return 0;
  3888. }
  3889. /* tp->lock is held. */
  3890. static int tg3_abort_hw(struct tg3 *tp, int silent)
  3891. {
  3892. int i, err;
  3893. tg3_disable_ints(tp);
  3894. tp->rx_mode &= ~RX_MODE_ENABLE;
  3895. tw32_f(MAC_RX_MODE, tp->rx_mode);
  3896. udelay(10);
  3897. err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
  3898. err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
  3899. err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
  3900. err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
  3901. err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
  3902. err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
  3903. err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
  3904. err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
  3905. err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
  3906. err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
  3907. err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
  3908. err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
  3909. err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
  3910. tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
  3911. tw32_f(MAC_MODE, tp->mac_mode);
  3912. udelay(40);
  3913. tp->tx_mode &= ~TX_MODE_ENABLE;
  3914. tw32_f(MAC_TX_MODE, tp->tx_mode);
  3915. for (i = 0; i < MAX_WAIT_CNT; i++) {
  3916. udelay(100);
  3917. if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
  3918. break;
  3919. }
  3920. if (i >= MAX_WAIT_CNT) {
  3921. printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
  3922. "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
  3923. tp->dev->name, tr32(MAC_TX_MODE));
  3924. err |= -ENODEV;
  3925. }
  3926. err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
  3927. err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
  3928. err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
  3929. tw32(FTQ_RESET, 0xffffffff);
  3930. tw32(FTQ_RESET, 0x00000000);
  3931. err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
  3932. err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
  3933. if (tp->hw_status)
  3934. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  3935. if (tp->hw_stats)
  3936. memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
  3937. return err;
  3938. }
  3939. /* tp->lock is held. */
  3940. static int tg3_nvram_lock(struct tg3 *tp)
  3941. {
  3942. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  3943. int i;
  3944. if (tp->nvram_lock_cnt == 0) {
  3945. tw32(NVRAM_SWARB, SWARB_REQ_SET1);
  3946. for (i = 0; i < 8000; i++) {
  3947. if (tr32(NVRAM_SWARB) & SWARB_GNT1)
  3948. break;
  3949. udelay(20);
  3950. }
  3951. if (i == 8000) {
  3952. tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
  3953. return -ENODEV;
  3954. }
  3955. }
  3956. tp->nvram_lock_cnt++;
  3957. }
  3958. return 0;
  3959. }
  3960. /* tp->lock is held. */
  3961. static void tg3_nvram_unlock(struct tg3 *tp)
  3962. {
  3963. if (tp->tg3_flags & TG3_FLAG_NVRAM) {
  3964. if (tp->nvram_lock_cnt > 0)
  3965. tp->nvram_lock_cnt--;
  3966. if (tp->nvram_lock_cnt == 0)
  3967. tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
  3968. }
  3969. }
  3970. /* tp->lock is held. */
  3971. static void tg3_enable_nvram_access(struct tg3 *tp)
  3972. {
  3973. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  3974. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  3975. u32 nvaccess = tr32(NVRAM_ACCESS);
  3976. tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
  3977. }
  3978. }
  3979. /* tp->lock is held. */
  3980. static void tg3_disable_nvram_access(struct tg3 *tp)
  3981. {
  3982. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  3983. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
  3984. u32 nvaccess = tr32(NVRAM_ACCESS);
  3985. tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
  3986. }
  3987. }
  3988. /* tp->lock is held. */
  3989. static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
  3990. {
  3991. tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
  3992. NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
  3993. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  3994. switch (kind) {
  3995. case RESET_KIND_INIT:
  3996. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  3997. DRV_STATE_START);
  3998. break;
  3999. case RESET_KIND_SHUTDOWN:
  4000. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4001. DRV_STATE_UNLOAD);
  4002. break;
  4003. case RESET_KIND_SUSPEND:
  4004. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4005. DRV_STATE_SUSPEND);
  4006. break;
  4007. default:
  4008. break;
  4009. };
  4010. }
  4011. }
  4012. /* tp->lock is held. */
  4013. static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
  4014. {
  4015. if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
  4016. switch (kind) {
  4017. case RESET_KIND_INIT:
  4018. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4019. DRV_STATE_START_DONE);
  4020. break;
  4021. case RESET_KIND_SHUTDOWN:
  4022. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4023. DRV_STATE_UNLOAD_DONE);
  4024. break;
  4025. default:
  4026. break;
  4027. };
  4028. }
  4029. }
  4030. /* tp->lock is held. */
  4031. static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
  4032. {
  4033. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4034. switch (kind) {
  4035. case RESET_KIND_INIT:
  4036. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4037. DRV_STATE_START);
  4038. break;
  4039. case RESET_KIND_SHUTDOWN:
  4040. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4041. DRV_STATE_UNLOAD);
  4042. break;
  4043. case RESET_KIND_SUSPEND:
  4044. tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
  4045. DRV_STATE_SUSPEND);
  4046. break;
  4047. default:
  4048. break;
  4049. };
  4050. }
  4051. }
  4052. static int tg3_poll_fw(struct tg3 *tp)
  4053. {
  4054. int i;
  4055. u32 val;
  4056. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4057. /* Wait up to 20ms for init done. */
  4058. for (i = 0; i < 200; i++) {
  4059. if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
  4060. return 0;
  4061. udelay(100);
  4062. }
  4063. return -ENODEV;
  4064. }
  4065. /* Wait for firmware initialization to complete. */
  4066. for (i = 0; i < 100000; i++) {
  4067. tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
  4068. if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
  4069. break;
  4070. udelay(10);
  4071. }
  4072. /* Chip might not be fitted with firmware. Some Sun onboard
  4073. * parts are configured like that. So don't signal the timeout
  4074. * of the above loop as an error, but do report the lack of
  4075. * running firmware once.
  4076. */
  4077. if (i >= 100000 &&
  4078. !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
  4079. tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
  4080. printk(KERN_INFO PFX "%s: No firmware running.\n",
  4081. tp->dev->name);
  4082. }
  4083. return 0;
  4084. }
  4085. /* Save PCI command register before chip reset */
  4086. static void tg3_save_pci_state(struct tg3 *tp)
  4087. {
  4088. u32 val;
  4089. pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
  4090. tp->pci_cmd = val;
  4091. }
  4092. /* Restore PCI state after chip reset */
  4093. static void tg3_restore_pci_state(struct tg3 *tp)
  4094. {
  4095. u32 val;
  4096. /* Re-enable indirect register accesses. */
  4097. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  4098. tp->misc_host_ctrl);
  4099. /* Set MAX PCI retry to zero. */
  4100. val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
  4101. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  4102. (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
  4103. val |= PCISTATE_RETRY_SAME_DMA;
  4104. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
  4105. pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
  4106. /* Make sure PCI-X relaxed ordering bit is clear. */
  4107. if (tp->pcix_cap) {
  4108. u16 pcix_cmd;
  4109. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  4110. &pcix_cmd);
  4111. pcix_cmd &= ~PCI_X_CMD_ERO;
  4112. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  4113. pcix_cmd);
  4114. }
  4115. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
  4116. /* Chip reset on 5780 will reset MSI enable bit,
  4117. * so need to restore it.
  4118. */
  4119. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  4120. u16 ctrl;
  4121. pci_read_config_word(tp->pdev,
  4122. tp->msi_cap + PCI_MSI_FLAGS,
  4123. &ctrl);
  4124. pci_write_config_word(tp->pdev,
  4125. tp->msi_cap + PCI_MSI_FLAGS,
  4126. ctrl | PCI_MSI_FLAGS_ENABLE);
  4127. val = tr32(MSGINT_MODE);
  4128. tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
  4129. }
  4130. }
  4131. }
  4132. static void tg3_stop_fw(struct tg3 *);
  4133. /* tp->lock is held. */
  4134. static int tg3_chip_reset(struct tg3 *tp)
  4135. {
  4136. u32 val;
  4137. void (*write_op)(struct tg3 *, u32, u32);
  4138. int err;
  4139. tg3_nvram_lock(tp);
  4140. /* No matching tg3_nvram_unlock() after this because
  4141. * chip reset below will undo the nvram lock.
  4142. */
  4143. tp->nvram_lock_cnt = 0;
  4144. /* GRC_MISC_CFG core clock reset will clear the memory
  4145. * enable bit in PCI register 4 and the MSI enable bit
  4146. * on some chips, so we save relevant registers here.
  4147. */
  4148. tg3_save_pci_state(tp);
  4149. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  4150. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  4151. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  4152. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  4153. tw32(GRC_FASTBOOT_PC, 0);
  4154. /*
  4155. * We must avoid the readl() that normally takes place.
  4156. * It locks machines, causes machine checks, and other
  4157. * fun things. So, temporarily disable the 5701
  4158. * hardware workaround, while we do the reset.
  4159. */
  4160. write_op = tp->write32;
  4161. if (write_op == tg3_write_flush_reg32)
  4162. tp->write32 = tg3_write32;
  4163. /* Prevent the irq handler from reading or writing PCI registers
  4164. * during chip reset when the memory enable bit in the PCI command
  4165. * register may be cleared. The chip does not generate interrupt
  4166. * at this time, but the irq handler may still be called due to irq
  4167. * sharing or irqpoll.
  4168. */
  4169. tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
  4170. if (tp->hw_status) {
  4171. tp->hw_status->status = 0;
  4172. tp->hw_status->status_tag = 0;
  4173. }
  4174. tp->last_tag = 0;
  4175. smp_mb();
  4176. synchronize_irq(tp->pdev->irq);
  4177. /* do the reset */
  4178. val = GRC_MISC_CFG_CORECLK_RESET;
  4179. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4180. if (tr32(0x7e2c) == 0x60) {
  4181. tw32(0x7e2c, 0x20);
  4182. }
  4183. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4184. tw32(GRC_MISC_CFG, (1 << 29));
  4185. val |= (1 << 29);
  4186. }
  4187. }
  4188. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4189. tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
  4190. tw32(GRC_VCPU_EXT_CTRL,
  4191. tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
  4192. }
  4193. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4194. val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
  4195. tw32(GRC_MISC_CFG, val);
  4196. /* restore 5701 hardware bug workaround write method */
  4197. tp->write32 = write_op;
  4198. /* Unfortunately, we have to delay before the PCI read back.
  4199. * Some 575X chips even will not respond to a PCI cfg access
  4200. * when the reset command is given to the chip.
  4201. *
  4202. * How do these hardware designers expect things to work
  4203. * properly if the PCI write is posted for a long period
  4204. * of time? It is always necessary to have some method by
  4205. * which a register read back can occur to push the write
  4206. * out which does the reset.
  4207. *
  4208. * For most tg3 variants the trick below was working.
  4209. * Ho hum...
  4210. */
  4211. udelay(120);
  4212. /* Flush PCI posted writes. The normal MMIO registers
  4213. * are inaccessible at this time so this is the only
  4214. * way to make this reliably (actually, this is no longer
  4215. * the case, see above). I tried to use indirect
  4216. * register read/write but this upset some 5701 variants.
  4217. */
  4218. pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
  4219. udelay(120);
  4220. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  4221. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
  4222. int i;
  4223. u32 cfg_val;
  4224. /* Wait for link training to complete. */
  4225. for (i = 0; i < 5000; i++)
  4226. udelay(100);
  4227. pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
  4228. pci_write_config_dword(tp->pdev, 0xc4,
  4229. cfg_val | (1 << 15));
  4230. }
  4231. /* Set PCIE max payload size and clear error status. */
  4232. pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
  4233. }
  4234. tg3_restore_pci_state(tp);
  4235. tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
  4236. val = 0;
  4237. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  4238. val = tr32(MEMARB_MODE);
  4239. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  4240. if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
  4241. tg3_stop_fw(tp);
  4242. tw32(0x5000, 0x400);
  4243. }
  4244. tw32(GRC_MODE, tp->grc_mode);
  4245. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
  4246. val = tr32(0xc4);
  4247. tw32(0xc4, val | (1 << 15));
  4248. }
  4249. if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
  4250. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  4251. tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
  4252. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
  4253. tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
  4254. tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  4255. }
  4256. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  4257. tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
  4258. tw32_f(MAC_MODE, tp->mac_mode);
  4259. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  4260. tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
  4261. tw32_f(MAC_MODE, tp->mac_mode);
  4262. } else
  4263. tw32_f(MAC_MODE, 0);
  4264. udelay(40);
  4265. err = tg3_poll_fw(tp);
  4266. if (err)
  4267. return err;
  4268. if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  4269. tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
  4270. val = tr32(0x7c00);
  4271. tw32(0x7c00, val | (1 << 25));
  4272. }
  4273. /* Reprobe ASF enable state. */
  4274. tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
  4275. tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
  4276. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  4277. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  4278. u32 nic_cfg;
  4279. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  4280. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  4281. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  4282. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  4283. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  4284. }
  4285. }
  4286. return 0;
  4287. }
  4288. /* tp->lock is held. */
  4289. static void tg3_stop_fw(struct tg3 *tp)
  4290. {
  4291. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  4292. u32 val;
  4293. int i;
  4294. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
  4295. val = tr32(GRC_RX_CPU_EVENT);
  4296. val |= (1 << 14);
  4297. tw32(GRC_RX_CPU_EVENT, val);
  4298. /* Wait for RX cpu to ACK the event. */
  4299. for (i = 0; i < 100; i++) {
  4300. if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
  4301. break;
  4302. udelay(1);
  4303. }
  4304. }
  4305. }
  4306. /* tp->lock is held. */
  4307. static int tg3_halt(struct tg3 *tp, int kind, int silent)
  4308. {
  4309. int err;
  4310. tg3_stop_fw(tp);
  4311. tg3_write_sig_pre_reset(tp, kind);
  4312. tg3_abort_hw(tp, silent);
  4313. err = tg3_chip_reset(tp);
  4314. tg3_write_sig_legacy(tp, kind);
  4315. tg3_write_sig_post_reset(tp, kind);
  4316. if (err)
  4317. return err;
  4318. return 0;
  4319. }
  4320. #define TG3_FW_RELEASE_MAJOR 0x0
  4321. #define TG3_FW_RELASE_MINOR 0x0
  4322. #define TG3_FW_RELEASE_FIX 0x0
  4323. #define TG3_FW_START_ADDR 0x08000000
  4324. #define TG3_FW_TEXT_ADDR 0x08000000
  4325. #define TG3_FW_TEXT_LEN 0x9c0
  4326. #define TG3_FW_RODATA_ADDR 0x080009c0
  4327. #define TG3_FW_RODATA_LEN 0x60
  4328. #define TG3_FW_DATA_ADDR 0x08000a40
  4329. #define TG3_FW_DATA_LEN 0x20
  4330. #define TG3_FW_SBSS_ADDR 0x08000a60
  4331. #define TG3_FW_SBSS_LEN 0xc
  4332. #define TG3_FW_BSS_ADDR 0x08000a70
  4333. #define TG3_FW_BSS_LEN 0x10
  4334. static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
  4335. 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
  4336. 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
  4337. 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
  4338. 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
  4339. 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
  4340. 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
  4341. 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
  4342. 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
  4343. 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
  4344. 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
  4345. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
  4346. 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
  4347. 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
  4348. 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
  4349. 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
  4350. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  4351. 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
  4352. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
  4353. 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
  4354. 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  4355. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
  4356. 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
  4357. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  4358. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4359. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4360. 0, 0, 0, 0, 0, 0,
  4361. 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
  4362. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4363. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4364. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4365. 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
  4366. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
  4367. 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
  4368. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
  4369. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4370. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
  4371. 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
  4372. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4373. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4374. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  4375. 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
  4376. 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
  4377. 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
  4378. 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
  4379. 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
  4380. 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
  4381. 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
  4382. 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
  4383. 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
  4384. 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
  4385. 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
  4386. 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
  4387. 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
  4388. 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
  4389. 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
  4390. 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
  4391. 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
  4392. 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
  4393. 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
  4394. 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
  4395. 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
  4396. 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
  4397. 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
  4398. 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
  4399. 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
  4400. 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
  4401. 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
  4402. 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
  4403. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
  4404. 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
  4405. 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
  4406. 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
  4407. 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
  4408. 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
  4409. 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
  4410. 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
  4411. 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
  4412. 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
  4413. 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
  4414. 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
  4415. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
  4416. 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
  4417. 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
  4418. 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
  4419. 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
  4420. 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
  4421. 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
  4422. 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
  4423. 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
  4424. 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
  4425. 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
  4426. };
  4427. static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
  4428. 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
  4429. 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
  4430. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  4431. 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
  4432. 0x00000000
  4433. };
  4434. #if 0 /* All zeros, don't eat up space with it. */
  4435. u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
  4436. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4437. 0x00000000, 0x00000000, 0x00000000, 0x00000000
  4438. };
  4439. #endif
  4440. #define RX_CPU_SCRATCH_BASE 0x30000
  4441. #define RX_CPU_SCRATCH_SIZE 0x04000
  4442. #define TX_CPU_SCRATCH_BASE 0x34000
  4443. #define TX_CPU_SCRATCH_SIZE 0x04000
  4444. /* tp->lock is held. */
  4445. static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
  4446. {
  4447. int i;
  4448. BUG_ON(offset == TX_CPU_BASE &&
  4449. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
  4450. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  4451. u32 val = tr32(GRC_VCPU_EXT_CTRL);
  4452. tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
  4453. return 0;
  4454. }
  4455. if (offset == RX_CPU_BASE) {
  4456. for (i = 0; i < 10000; i++) {
  4457. tw32(offset + CPU_STATE, 0xffffffff);
  4458. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4459. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4460. break;
  4461. }
  4462. tw32(offset + CPU_STATE, 0xffffffff);
  4463. tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
  4464. udelay(10);
  4465. } else {
  4466. for (i = 0; i < 10000; i++) {
  4467. tw32(offset + CPU_STATE, 0xffffffff);
  4468. tw32(offset + CPU_MODE, CPU_MODE_HALT);
  4469. if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
  4470. break;
  4471. }
  4472. }
  4473. if (i >= 10000) {
  4474. printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
  4475. "and %s CPU\n",
  4476. tp->dev->name,
  4477. (offset == RX_CPU_BASE ? "RX" : "TX"));
  4478. return -ENODEV;
  4479. }
  4480. /* Clear firmware's nvram arbitration. */
  4481. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  4482. tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
  4483. return 0;
  4484. }
  4485. struct fw_info {
  4486. unsigned int text_base;
  4487. unsigned int text_len;
  4488. const u32 *text_data;
  4489. unsigned int rodata_base;
  4490. unsigned int rodata_len;
  4491. const u32 *rodata_data;
  4492. unsigned int data_base;
  4493. unsigned int data_len;
  4494. const u32 *data_data;
  4495. };
  4496. /* tp->lock is held. */
  4497. static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
  4498. int cpu_scratch_size, struct fw_info *info)
  4499. {
  4500. int err, lock_err, i;
  4501. void (*write_op)(struct tg3 *, u32, u32);
  4502. if (cpu_base == TX_CPU_BASE &&
  4503. (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  4504. printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
  4505. "TX cpu firmware on %s which is 5705.\n",
  4506. tp->dev->name);
  4507. return -EINVAL;
  4508. }
  4509. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  4510. write_op = tg3_write_mem;
  4511. else
  4512. write_op = tg3_write_indirect_reg32;
  4513. /* It is possible that bootcode is still loading at this point.
  4514. * Get the nvram lock first before halting the cpu.
  4515. */
  4516. lock_err = tg3_nvram_lock(tp);
  4517. err = tg3_halt_cpu(tp, cpu_base);
  4518. if (!lock_err)
  4519. tg3_nvram_unlock(tp);
  4520. if (err)
  4521. goto out;
  4522. for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
  4523. write_op(tp, cpu_scratch_base + i, 0);
  4524. tw32(cpu_base + CPU_STATE, 0xffffffff);
  4525. tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
  4526. for (i = 0; i < (info->text_len / sizeof(u32)); i++)
  4527. write_op(tp, (cpu_scratch_base +
  4528. (info->text_base & 0xffff) +
  4529. (i * sizeof(u32))),
  4530. (info->text_data ?
  4531. info->text_data[i] : 0));
  4532. for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
  4533. write_op(tp, (cpu_scratch_base +
  4534. (info->rodata_base & 0xffff) +
  4535. (i * sizeof(u32))),
  4536. (info->rodata_data ?
  4537. info->rodata_data[i] : 0));
  4538. for (i = 0; i < (info->data_len / sizeof(u32)); i++)
  4539. write_op(tp, (cpu_scratch_base +
  4540. (info->data_base & 0xffff) +
  4541. (i * sizeof(u32))),
  4542. (info->data_data ?
  4543. info->data_data[i] : 0));
  4544. err = 0;
  4545. out:
  4546. return err;
  4547. }
  4548. /* tp->lock is held. */
  4549. static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
  4550. {
  4551. struct fw_info info;
  4552. int err, i;
  4553. info.text_base = TG3_FW_TEXT_ADDR;
  4554. info.text_len = TG3_FW_TEXT_LEN;
  4555. info.text_data = &tg3FwText[0];
  4556. info.rodata_base = TG3_FW_RODATA_ADDR;
  4557. info.rodata_len = TG3_FW_RODATA_LEN;
  4558. info.rodata_data = &tg3FwRodata[0];
  4559. info.data_base = TG3_FW_DATA_ADDR;
  4560. info.data_len = TG3_FW_DATA_LEN;
  4561. info.data_data = NULL;
  4562. err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
  4563. RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
  4564. &info);
  4565. if (err)
  4566. return err;
  4567. err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
  4568. TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
  4569. &info);
  4570. if (err)
  4571. return err;
  4572. /* Now startup only the RX cpu. */
  4573. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4574. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4575. for (i = 0; i < 5; i++) {
  4576. if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
  4577. break;
  4578. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4579. tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
  4580. tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
  4581. udelay(1000);
  4582. }
  4583. if (i >= 5) {
  4584. printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
  4585. "to set RX CPU PC, is %08x should be %08x\n",
  4586. tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
  4587. TG3_FW_TEXT_ADDR);
  4588. return -ENODEV;
  4589. }
  4590. tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
  4591. tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
  4592. return 0;
  4593. }
  4594. #define TG3_TSO_FW_RELEASE_MAJOR 0x1
  4595. #define TG3_TSO_FW_RELASE_MINOR 0x6
  4596. #define TG3_TSO_FW_RELEASE_FIX 0x0
  4597. #define TG3_TSO_FW_START_ADDR 0x08000000
  4598. #define TG3_TSO_FW_TEXT_ADDR 0x08000000
  4599. #define TG3_TSO_FW_TEXT_LEN 0x1aa0
  4600. #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
  4601. #define TG3_TSO_FW_RODATA_LEN 0x60
  4602. #define TG3_TSO_FW_DATA_ADDR 0x08001b20
  4603. #define TG3_TSO_FW_DATA_LEN 0x30
  4604. #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
  4605. #define TG3_TSO_FW_SBSS_LEN 0x2c
  4606. #define TG3_TSO_FW_BSS_ADDR 0x08001b80
  4607. #define TG3_TSO_FW_BSS_LEN 0x894
  4608. static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
  4609. 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
  4610. 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
  4611. 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4612. 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
  4613. 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
  4614. 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
  4615. 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
  4616. 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
  4617. 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
  4618. 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
  4619. 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
  4620. 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
  4621. 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
  4622. 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
  4623. 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
  4624. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
  4625. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
  4626. 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
  4627. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4628. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
  4629. 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
  4630. 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
  4631. 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
  4632. 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
  4633. 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
  4634. 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
  4635. 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
  4636. 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
  4637. 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
  4638. 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4639. 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
  4640. 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
  4641. 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
  4642. 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
  4643. 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
  4644. 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
  4645. 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
  4646. 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
  4647. 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
  4648. 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
  4649. 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
  4650. 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
  4651. 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
  4652. 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
  4653. 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
  4654. 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
  4655. 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
  4656. 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  4657. 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
  4658. 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
  4659. 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
  4660. 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
  4661. 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
  4662. 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
  4663. 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
  4664. 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
  4665. 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
  4666. 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
  4667. 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
  4668. 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
  4669. 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
  4670. 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
  4671. 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
  4672. 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
  4673. 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
  4674. 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
  4675. 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
  4676. 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
  4677. 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
  4678. 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
  4679. 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
  4680. 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
  4681. 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
  4682. 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
  4683. 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
  4684. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
  4685. 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
  4686. 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
  4687. 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
  4688. 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
  4689. 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
  4690. 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
  4691. 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
  4692. 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
  4693. 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
  4694. 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
  4695. 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
  4696. 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
  4697. 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
  4698. 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
  4699. 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
  4700. 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
  4701. 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
  4702. 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
  4703. 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
  4704. 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
  4705. 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
  4706. 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
  4707. 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
  4708. 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
  4709. 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
  4710. 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
  4711. 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
  4712. 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
  4713. 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
  4714. 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
  4715. 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
  4716. 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
  4717. 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
  4718. 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
  4719. 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
  4720. 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
  4721. 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
  4722. 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
  4723. 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
  4724. 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
  4725. 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
  4726. 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
  4727. 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
  4728. 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
  4729. 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
  4730. 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
  4731. 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
  4732. 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
  4733. 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
  4734. 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
  4735. 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
  4736. 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
  4737. 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
  4738. 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
  4739. 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
  4740. 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
  4741. 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
  4742. 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
  4743. 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
  4744. 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
  4745. 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
  4746. 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
  4747. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  4748. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
  4749. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
  4750. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
  4751. 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
  4752. 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
  4753. 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
  4754. 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
  4755. 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
  4756. 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
  4757. 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
  4758. 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
  4759. 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
  4760. 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
  4761. 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
  4762. 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
  4763. 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
  4764. 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
  4765. 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
  4766. 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
  4767. 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
  4768. 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
  4769. 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
  4770. 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
  4771. 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
  4772. 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
  4773. 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
  4774. 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
  4775. 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
  4776. 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
  4777. 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
  4778. 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
  4779. 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
  4780. 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
  4781. 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
  4782. 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
  4783. 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
  4784. 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
  4785. 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
  4786. 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
  4787. 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
  4788. 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
  4789. 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
  4790. 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
  4791. 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
  4792. 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
  4793. 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
  4794. 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
  4795. 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
  4796. 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
  4797. 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
  4798. 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
  4799. 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
  4800. 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
  4801. 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
  4802. 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
  4803. 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
  4804. 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
  4805. 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
  4806. 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
  4807. 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
  4808. 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
  4809. 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
  4810. 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
  4811. 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
  4812. 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
  4813. 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
  4814. 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
  4815. 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
  4816. 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
  4817. 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
  4818. 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
  4819. 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
  4820. 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
  4821. 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
  4822. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
  4823. 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
  4824. 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
  4825. 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
  4826. 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
  4827. 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
  4828. 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
  4829. 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  4830. 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
  4831. 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
  4832. 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
  4833. 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
  4834. 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
  4835. 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
  4836. 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
  4837. 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
  4838. 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
  4839. 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
  4840. 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
  4841. 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
  4842. 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
  4843. 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
  4844. 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
  4845. 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
  4846. 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
  4847. 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
  4848. 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
  4849. 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
  4850. 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
  4851. 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
  4852. 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
  4853. 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
  4854. 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
  4855. 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
  4856. 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
  4857. 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
  4858. 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
  4859. 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
  4860. 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
  4861. 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
  4862. 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
  4863. 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
  4864. 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
  4865. 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
  4866. 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
  4867. 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
  4868. 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
  4869. 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
  4870. 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
  4871. 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
  4872. 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
  4873. 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
  4874. 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
  4875. 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
  4876. 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
  4877. 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
  4878. 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
  4879. 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
  4880. 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
  4881. 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
  4882. 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
  4883. 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
  4884. 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
  4885. 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
  4886. 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
  4887. 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
  4888. 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
  4889. 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
  4890. 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
  4891. 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
  4892. 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
  4893. };
  4894. static const u32 tg3TsoFwRodata[] = {
  4895. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  4896. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
  4897. 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
  4898. 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
  4899. 0x00000000,
  4900. };
  4901. static const u32 tg3TsoFwData[] = {
  4902. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
  4903. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  4904. 0x00000000,
  4905. };
  4906. /* 5705 needs a special version of the TSO firmware. */
  4907. #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
  4908. #define TG3_TSO5_FW_RELASE_MINOR 0x2
  4909. #define TG3_TSO5_FW_RELEASE_FIX 0x0
  4910. #define TG3_TSO5_FW_START_ADDR 0x00010000
  4911. #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
  4912. #define TG3_TSO5_FW_TEXT_LEN 0xe90
  4913. #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
  4914. #define TG3_TSO5_FW_RODATA_LEN 0x50
  4915. #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
  4916. #define TG3_TSO5_FW_DATA_LEN 0x20
  4917. #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
  4918. #define TG3_TSO5_FW_SBSS_LEN 0x28
  4919. #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
  4920. #define TG3_TSO5_FW_BSS_LEN 0x88
  4921. static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
  4922. 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
  4923. 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
  4924. 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
  4925. 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
  4926. 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
  4927. 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
  4928. 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  4929. 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
  4930. 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
  4931. 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
  4932. 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
  4933. 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
  4934. 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
  4935. 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
  4936. 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
  4937. 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
  4938. 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
  4939. 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
  4940. 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
  4941. 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
  4942. 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
  4943. 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
  4944. 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
  4945. 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
  4946. 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
  4947. 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
  4948. 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
  4949. 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
  4950. 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
  4951. 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
  4952. 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  4953. 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
  4954. 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
  4955. 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
  4956. 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
  4957. 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
  4958. 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
  4959. 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
  4960. 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
  4961. 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
  4962. 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
  4963. 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
  4964. 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
  4965. 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
  4966. 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
  4967. 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
  4968. 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
  4969. 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
  4970. 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
  4971. 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
  4972. 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
  4973. 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
  4974. 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
  4975. 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
  4976. 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
  4977. 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
  4978. 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
  4979. 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
  4980. 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
  4981. 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
  4982. 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
  4983. 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
  4984. 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
  4985. 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
  4986. 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
  4987. 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
  4988. 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
  4989. 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
  4990. 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
  4991. 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
  4992. 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
  4993. 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
  4994. 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
  4995. 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
  4996. 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
  4997. 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
  4998. 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
  4999. 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
  5000. 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
  5001. 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
  5002. 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
  5003. 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
  5004. 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
  5005. 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
  5006. 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
  5007. 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
  5008. 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
  5009. 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
  5010. 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
  5011. 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
  5012. 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
  5013. 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
  5014. 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
  5015. 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
  5016. 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
  5017. 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
  5018. 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
  5019. 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
  5020. 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
  5021. 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
  5022. 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
  5023. 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
  5024. 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
  5025. 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
  5026. 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
  5027. 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
  5028. 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5029. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5030. 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
  5031. 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
  5032. 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
  5033. 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
  5034. 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
  5035. 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
  5036. 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
  5037. 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
  5038. 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
  5039. 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
  5040. 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
  5041. 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
  5042. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
  5043. 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
  5044. 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
  5045. 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
  5046. 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
  5047. 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
  5048. 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
  5049. 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
  5050. 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
  5051. 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
  5052. 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
  5053. 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
  5054. 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
  5055. 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
  5056. 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
  5057. 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
  5058. 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
  5059. 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
  5060. 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
  5061. 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
  5062. 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
  5063. 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
  5064. 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
  5065. 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
  5066. 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
  5067. 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
  5068. 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
  5069. 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
  5070. 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
  5071. 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
  5072. 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
  5073. 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
  5074. 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
  5075. 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
  5076. 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
  5077. 0x00000000, 0x00000000, 0x00000000,
  5078. };
  5079. static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
  5080. 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
  5081. 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
  5082. 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
  5083. 0x00000000, 0x00000000, 0x00000000,
  5084. };
  5085. static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
  5086. 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
  5087. 0x00000000, 0x00000000, 0x00000000,
  5088. };
  5089. /* tp->lock is held. */
  5090. static int tg3_load_tso_firmware(struct tg3 *tp)
  5091. {
  5092. struct fw_info info;
  5093. unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
  5094. int err, i;
  5095. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5096. return 0;
  5097. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5098. info.text_base = TG3_TSO5_FW_TEXT_ADDR;
  5099. info.text_len = TG3_TSO5_FW_TEXT_LEN;
  5100. info.text_data = &tg3Tso5FwText[0];
  5101. info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
  5102. info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
  5103. info.rodata_data = &tg3Tso5FwRodata[0];
  5104. info.data_base = TG3_TSO5_FW_DATA_ADDR;
  5105. info.data_len = TG3_TSO5_FW_DATA_LEN;
  5106. info.data_data = &tg3Tso5FwData[0];
  5107. cpu_base = RX_CPU_BASE;
  5108. cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
  5109. cpu_scratch_size = (info.text_len +
  5110. info.rodata_len +
  5111. info.data_len +
  5112. TG3_TSO5_FW_SBSS_LEN +
  5113. TG3_TSO5_FW_BSS_LEN);
  5114. } else {
  5115. info.text_base = TG3_TSO_FW_TEXT_ADDR;
  5116. info.text_len = TG3_TSO_FW_TEXT_LEN;
  5117. info.text_data = &tg3TsoFwText[0];
  5118. info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
  5119. info.rodata_len = TG3_TSO_FW_RODATA_LEN;
  5120. info.rodata_data = &tg3TsoFwRodata[0];
  5121. info.data_base = TG3_TSO_FW_DATA_ADDR;
  5122. info.data_len = TG3_TSO_FW_DATA_LEN;
  5123. info.data_data = &tg3TsoFwData[0];
  5124. cpu_base = TX_CPU_BASE;
  5125. cpu_scratch_base = TX_CPU_SCRATCH_BASE;
  5126. cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
  5127. }
  5128. err = tg3_load_firmware_cpu(tp, cpu_base,
  5129. cpu_scratch_base, cpu_scratch_size,
  5130. &info);
  5131. if (err)
  5132. return err;
  5133. /* Now startup the cpu. */
  5134. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5135. tw32_f(cpu_base + CPU_PC, info.text_base);
  5136. for (i = 0; i < 5; i++) {
  5137. if (tr32(cpu_base + CPU_PC) == info.text_base)
  5138. break;
  5139. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5140. tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
  5141. tw32_f(cpu_base + CPU_PC, info.text_base);
  5142. udelay(1000);
  5143. }
  5144. if (i >= 5) {
  5145. printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
  5146. "to set CPU PC, is %08x should be %08x\n",
  5147. tp->dev->name, tr32(cpu_base + CPU_PC),
  5148. info.text_base);
  5149. return -ENODEV;
  5150. }
  5151. tw32(cpu_base + CPU_STATE, 0xffffffff);
  5152. tw32_f(cpu_base + CPU_MODE, 0x00000000);
  5153. return 0;
  5154. }
  5155. /* tp->lock is held. */
  5156. static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
  5157. {
  5158. u32 addr_high, addr_low;
  5159. int i;
  5160. addr_high = ((tp->dev->dev_addr[0] << 8) |
  5161. tp->dev->dev_addr[1]);
  5162. addr_low = ((tp->dev->dev_addr[2] << 24) |
  5163. (tp->dev->dev_addr[3] << 16) |
  5164. (tp->dev->dev_addr[4] << 8) |
  5165. (tp->dev->dev_addr[5] << 0));
  5166. for (i = 0; i < 4; i++) {
  5167. if (i == 1 && skip_mac_1)
  5168. continue;
  5169. tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
  5170. tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
  5171. }
  5172. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  5173. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5174. for (i = 0; i < 12; i++) {
  5175. tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
  5176. tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
  5177. }
  5178. }
  5179. addr_high = (tp->dev->dev_addr[0] +
  5180. tp->dev->dev_addr[1] +
  5181. tp->dev->dev_addr[2] +
  5182. tp->dev->dev_addr[3] +
  5183. tp->dev->dev_addr[4] +
  5184. tp->dev->dev_addr[5]) &
  5185. TX_BACKOFF_SEED_MASK;
  5186. tw32(MAC_TX_BACKOFF_SEED, addr_high);
  5187. }
  5188. static int tg3_set_mac_addr(struct net_device *dev, void *p)
  5189. {
  5190. struct tg3 *tp = netdev_priv(dev);
  5191. struct sockaddr *addr = p;
  5192. int err = 0, skip_mac_1 = 0;
  5193. if (!is_valid_ether_addr(addr->sa_data))
  5194. return -EINVAL;
  5195. memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
  5196. if (!netif_running(dev))
  5197. return 0;
  5198. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5199. u32 addr0_high, addr0_low, addr1_high, addr1_low;
  5200. addr0_high = tr32(MAC_ADDR_0_HIGH);
  5201. addr0_low = tr32(MAC_ADDR_0_LOW);
  5202. addr1_high = tr32(MAC_ADDR_1_HIGH);
  5203. addr1_low = tr32(MAC_ADDR_1_LOW);
  5204. /* Skip MAC addr 1 if ASF is using it. */
  5205. if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
  5206. !(addr1_high == 0 && addr1_low == 0))
  5207. skip_mac_1 = 1;
  5208. }
  5209. spin_lock_bh(&tp->lock);
  5210. __tg3_set_mac_addr(tp, skip_mac_1);
  5211. spin_unlock_bh(&tp->lock);
  5212. return err;
  5213. }
  5214. /* tp->lock is held. */
  5215. static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
  5216. dma_addr_t mapping, u32 maxlen_flags,
  5217. u32 nic_addr)
  5218. {
  5219. tg3_write_mem(tp,
  5220. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
  5221. ((u64) mapping >> 32));
  5222. tg3_write_mem(tp,
  5223. (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
  5224. ((u64) mapping & 0xffffffff));
  5225. tg3_write_mem(tp,
  5226. (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
  5227. maxlen_flags);
  5228. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5229. tg3_write_mem(tp,
  5230. (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
  5231. nic_addr);
  5232. }
  5233. static void __tg3_set_rx_mode(struct net_device *);
  5234. static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
  5235. {
  5236. tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
  5237. tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
  5238. tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
  5239. tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
  5240. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5241. tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
  5242. tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
  5243. }
  5244. tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
  5245. tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
  5246. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5247. u32 val = ec->stats_block_coalesce_usecs;
  5248. if (!netif_carrier_ok(tp->dev))
  5249. val = 0;
  5250. tw32(HOSTCC_STAT_COAL_TICKS, val);
  5251. }
  5252. }
  5253. /* tp->lock is held. */
  5254. static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
  5255. {
  5256. u32 val, rdmac_mode;
  5257. int i, err, limit;
  5258. tg3_disable_ints(tp);
  5259. tg3_stop_fw(tp);
  5260. tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
  5261. if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
  5262. tg3_abort_hw(tp, 1);
  5263. }
  5264. if (reset_phy)
  5265. tg3_phy_reset(tp);
  5266. err = tg3_chip_reset(tp);
  5267. if (err)
  5268. return err;
  5269. tg3_write_sig_legacy(tp, RESET_KIND_INIT);
  5270. if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0) {
  5271. val = tr32(TG3_CPMU_CTRL);
  5272. val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
  5273. tw32(TG3_CPMU_CTRL, val);
  5274. }
  5275. /* This works around an issue with Athlon chipsets on
  5276. * B3 tigon3 silicon. This bit has no effect on any
  5277. * other revision. But do not set this on PCI Express
  5278. * chips and don't even touch the clocks if the CPMU is present.
  5279. */
  5280. if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
  5281. if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  5282. tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
  5283. tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
  5284. }
  5285. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
  5286. (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  5287. val = tr32(TG3PCI_PCISTATE);
  5288. val |= PCISTATE_RETRY_SAME_DMA;
  5289. tw32(TG3PCI_PCISTATE, val);
  5290. }
  5291. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
  5292. /* Enable some hw fixes. */
  5293. val = tr32(TG3PCI_MSI_DATA);
  5294. val |= (1 << 26) | (1 << 28) | (1 << 29);
  5295. tw32(TG3PCI_MSI_DATA, val);
  5296. }
  5297. /* Descriptor ring init may make accesses to the
  5298. * NIC SRAM area to setup the TX descriptors, so we
  5299. * can only do this after the hardware has been
  5300. * successfully reset.
  5301. */
  5302. err = tg3_init_rings(tp);
  5303. if (err)
  5304. return err;
  5305. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) {
  5306. /* This value is determined during the probe time DMA
  5307. * engine test, tg3_test_dma.
  5308. */
  5309. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  5310. }
  5311. tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
  5312. GRC_MODE_4X_NIC_SEND_RINGS |
  5313. GRC_MODE_NO_TX_PHDR_CSUM |
  5314. GRC_MODE_NO_RX_PHDR_CSUM);
  5315. tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
  5316. /* Pseudo-header checksum is done by hardware logic and not
  5317. * the offload processers, so make the chip do the pseudo-
  5318. * header checksums on receive. For transmit it is more
  5319. * convenient to do the pseudo-header checksum in software
  5320. * as Linux does that on transmit for us in all cases.
  5321. */
  5322. tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
  5323. tw32(GRC_MODE,
  5324. tp->grc_mode |
  5325. (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
  5326. /* Setup the timer prescalar register. Clock is always 66Mhz. */
  5327. val = tr32(GRC_MISC_CFG);
  5328. val &= ~0xff;
  5329. val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
  5330. tw32(GRC_MISC_CFG, val);
  5331. /* Initialize MBUF/DESC pool. */
  5332. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5333. /* Do nothing. */
  5334. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
  5335. tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
  5336. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  5337. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
  5338. else
  5339. tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
  5340. tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
  5341. tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
  5342. }
  5343. else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5344. int fw_len;
  5345. fw_len = (TG3_TSO5_FW_TEXT_LEN +
  5346. TG3_TSO5_FW_RODATA_LEN +
  5347. TG3_TSO5_FW_DATA_LEN +
  5348. TG3_TSO5_FW_SBSS_LEN +
  5349. TG3_TSO5_FW_BSS_LEN);
  5350. fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
  5351. tw32(BUFMGR_MB_POOL_ADDR,
  5352. NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
  5353. tw32(BUFMGR_MB_POOL_SIZE,
  5354. NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
  5355. }
  5356. if (tp->dev->mtu <= ETH_DATA_LEN) {
  5357. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5358. tp->bufmgr_config.mbuf_read_dma_low_water);
  5359. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5360. tp->bufmgr_config.mbuf_mac_rx_low_water);
  5361. tw32(BUFMGR_MB_HIGH_WATER,
  5362. tp->bufmgr_config.mbuf_high_water);
  5363. } else {
  5364. tw32(BUFMGR_MB_RDMA_LOW_WATER,
  5365. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
  5366. tw32(BUFMGR_MB_MACRX_LOW_WATER,
  5367. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
  5368. tw32(BUFMGR_MB_HIGH_WATER,
  5369. tp->bufmgr_config.mbuf_high_water_jumbo);
  5370. }
  5371. tw32(BUFMGR_DMA_LOW_WATER,
  5372. tp->bufmgr_config.dma_low_water);
  5373. tw32(BUFMGR_DMA_HIGH_WATER,
  5374. tp->bufmgr_config.dma_high_water);
  5375. tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
  5376. for (i = 0; i < 2000; i++) {
  5377. if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
  5378. break;
  5379. udelay(10);
  5380. }
  5381. if (i >= 2000) {
  5382. printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
  5383. tp->dev->name);
  5384. return -ENODEV;
  5385. }
  5386. /* Setup replenish threshold. */
  5387. val = tp->rx_pending / 8;
  5388. if (val == 0)
  5389. val = 1;
  5390. else if (val > tp->rx_std_max_post)
  5391. val = tp->rx_std_max_post;
  5392. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  5393. if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
  5394. tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
  5395. if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
  5396. val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
  5397. }
  5398. tw32(RCVBDI_STD_THRESH, val);
  5399. /* Initialize TG3_BDINFO's at:
  5400. * RCVDBDI_STD_BD: standard eth size rx ring
  5401. * RCVDBDI_JUMBO_BD: jumbo frame rx ring
  5402. * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
  5403. *
  5404. * like so:
  5405. * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
  5406. * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
  5407. * ring attribute flags
  5408. * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
  5409. *
  5410. * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
  5411. * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
  5412. *
  5413. * The size of each ring is fixed in the firmware, but the location is
  5414. * configurable.
  5415. */
  5416. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5417. ((u64) tp->rx_std_mapping >> 32));
  5418. tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5419. ((u64) tp->rx_std_mapping & 0xffffffff));
  5420. tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
  5421. NIC_SRAM_RX_BUFFER_DESC);
  5422. /* Don't even try to program the JUMBO/MINI buffer descriptor
  5423. * configs on 5705.
  5424. */
  5425. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  5426. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5427. RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
  5428. } else {
  5429. tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5430. RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5431. tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5432. BDINFO_FLAGS_DISABLED);
  5433. /* Setup replenish threshold. */
  5434. tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
  5435. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
  5436. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5437. ((u64) tp->rx_jumbo_mapping >> 32));
  5438. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
  5439. ((u64) tp->rx_jumbo_mapping & 0xffffffff));
  5440. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5441. RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
  5442. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
  5443. NIC_SRAM_RX_JUMBO_BUFFER_DESC);
  5444. } else {
  5445. tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
  5446. BDINFO_FLAGS_DISABLED);
  5447. }
  5448. }
  5449. /* There is only one send ring on 5705/5750, no need to explicitly
  5450. * disable the others.
  5451. */
  5452. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5453. /* Clear out send RCB ring in SRAM. */
  5454. for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
  5455. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5456. BDINFO_FLAGS_DISABLED);
  5457. }
  5458. tp->tx_prod = 0;
  5459. tp->tx_cons = 0;
  5460. tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5461. tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5462. tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
  5463. tp->tx_desc_mapping,
  5464. (TG3_TX_RING_SIZE <<
  5465. BDINFO_FLAGS_MAXLEN_SHIFT),
  5466. NIC_SRAM_TX_BUFFER_DESC);
  5467. /* There is only one receive return ring on 5705/5750, no need
  5468. * to explicitly disable the others.
  5469. */
  5470. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5471. for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
  5472. i += TG3_BDINFO_SIZE) {
  5473. tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
  5474. BDINFO_FLAGS_DISABLED);
  5475. }
  5476. }
  5477. tp->rx_rcb_ptr = 0;
  5478. tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
  5479. tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
  5480. tp->rx_rcb_mapping,
  5481. (TG3_RX_RCB_RING_SIZE(tp) <<
  5482. BDINFO_FLAGS_MAXLEN_SHIFT),
  5483. 0);
  5484. tp->rx_std_ptr = tp->rx_pending;
  5485. tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
  5486. tp->rx_std_ptr);
  5487. tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
  5488. tp->rx_jumbo_pending : 0;
  5489. tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
  5490. tp->rx_jumbo_ptr);
  5491. /* Initialize MAC address and backoff seed. */
  5492. __tg3_set_mac_addr(tp, 0);
  5493. /* MTU + ethernet header + FCS + optional VLAN tag */
  5494. tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
  5495. /* The slot time is changed by tg3_setup_phy if we
  5496. * run at gigabit with half duplex.
  5497. */
  5498. tw32(MAC_TX_LENGTHS,
  5499. (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
  5500. (6 << TX_LENGTHS_IPG_SHIFT) |
  5501. (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
  5502. /* Receive rules. */
  5503. tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
  5504. tw32(RCVLPC_CONFIG, 0x0181);
  5505. /* Calculate RDMAC_MODE setting early, we need it to determine
  5506. * the RCVLPC_STATE_ENABLE mask.
  5507. */
  5508. rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
  5509. RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
  5510. RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
  5511. RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
  5512. RDMAC_MODE_LNGREAD_ENAB);
  5513. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  5514. rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
  5515. RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
  5516. RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
  5517. /* If statement applies to 5705 and 5750 PCI devices only */
  5518. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5519. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5520. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
  5521. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
  5522. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
  5523. rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
  5524. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5525. !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
  5526. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5527. }
  5528. }
  5529. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
  5530. rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
  5531. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5532. rdmac_mode |= (1 << 27);
  5533. /* Receive/send statistics. */
  5534. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  5535. val = tr32(RCVLPC_STATS_ENABLE);
  5536. val &= ~RCVLPC_STATSENAB_DACK_FIX;
  5537. tw32(RCVLPC_STATS_ENABLE, val);
  5538. } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
  5539. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  5540. val = tr32(RCVLPC_STATS_ENABLE);
  5541. val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
  5542. tw32(RCVLPC_STATS_ENABLE, val);
  5543. } else {
  5544. tw32(RCVLPC_STATS_ENABLE, 0xffffff);
  5545. }
  5546. tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
  5547. tw32(SNDDATAI_STATSENAB, 0xffffff);
  5548. tw32(SNDDATAI_STATSCTRL,
  5549. (SNDDATAI_SCTRL_ENABLE |
  5550. SNDDATAI_SCTRL_FASTUPD));
  5551. /* Setup host coalescing engine. */
  5552. tw32(HOSTCC_MODE, 0);
  5553. for (i = 0; i < 2000; i++) {
  5554. if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
  5555. break;
  5556. udelay(10);
  5557. }
  5558. __tg3_set_coalesce(tp, &tp->coal);
  5559. /* set status block DMA address */
  5560. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5561. ((u64) tp->status_mapping >> 32));
  5562. tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5563. ((u64) tp->status_mapping & 0xffffffff));
  5564. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5565. /* Status/statistics block address. See tg3_timer,
  5566. * the tg3_periodic_fetch_stats call there, and
  5567. * tg3_get_stats to see how this works for 5705/5750 chips.
  5568. */
  5569. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
  5570. ((u64) tp->stats_mapping >> 32));
  5571. tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
  5572. ((u64) tp->stats_mapping & 0xffffffff));
  5573. tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
  5574. tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
  5575. }
  5576. tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
  5577. tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
  5578. tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
  5579. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5580. tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
  5581. /* Clear statistics/status block in chip, and status block in ram. */
  5582. for (i = NIC_SRAM_STATS_BLK;
  5583. i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
  5584. i += sizeof(u32)) {
  5585. tg3_write_mem(tp, i, 0);
  5586. udelay(40);
  5587. }
  5588. memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
  5589. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  5590. tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
  5591. /* reset to prevent losing 1st rx packet intermittently */
  5592. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5593. udelay(10);
  5594. }
  5595. tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
  5596. MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
  5597. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5598. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  5599. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
  5600. tp->mac_mode |= MAC_MODE_LINK_POLARITY;
  5601. tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
  5602. udelay(40);
  5603. /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
  5604. * If TG3_FLG2_IS_NIC is zero, we should read the
  5605. * register to preserve the GPIO settings for LOMs. The GPIOs,
  5606. * whether used as inputs or outputs, are set by boot code after
  5607. * reset.
  5608. */
  5609. if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
  5610. u32 gpio_mask;
  5611. gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
  5612. GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
  5613. GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
  5614. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  5615. gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
  5616. GRC_LCLCTRL_GPIO_OUTPUT3;
  5617. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  5618. gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
  5619. tp->grc_local_ctrl &= ~gpio_mask;
  5620. tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
  5621. /* GPIO1 must be driven high for eeprom write protect */
  5622. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
  5623. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  5624. GRC_LCLCTRL_GPIO_OUTPUT1);
  5625. }
  5626. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  5627. udelay(100);
  5628. tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
  5629. tp->last_tag = 0;
  5630. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  5631. tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
  5632. udelay(40);
  5633. }
  5634. val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
  5635. WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
  5636. WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
  5637. WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
  5638. WDMAC_MODE_LNGREAD_ENAB);
  5639. /* If statement applies to 5705 and 5750 PCI devices only */
  5640. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  5641. tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
  5642. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
  5643. if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
  5644. (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
  5645. tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
  5646. /* nothing */
  5647. } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
  5648. !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  5649. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  5650. val |= WDMAC_MODE_RX_ACCEL;
  5651. }
  5652. }
  5653. /* Enable host coalescing bug fix */
  5654. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
  5655. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
  5656. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
  5657. val |= (1 << 29);
  5658. tw32_f(WDMAC_MODE, val);
  5659. udelay(40);
  5660. if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  5661. u16 pcix_cmd;
  5662. pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  5663. &pcix_cmd);
  5664. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
  5665. pcix_cmd &= ~PCI_X_CMD_MAX_READ;
  5666. pcix_cmd |= PCI_X_CMD_READ_2K;
  5667. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  5668. pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
  5669. pcix_cmd |= PCI_X_CMD_READ_2K;
  5670. }
  5671. pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
  5672. pcix_cmd);
  5673. }
  5674. tw32_f(RDMAC_MODE, rdmac_mode);
  5675. udelay(40);
  5676. tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
  5677. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  5678. tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
  5679. tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
  5680. tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
  5681. tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
  5682. tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
  5683. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
  5684. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
  5685. tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
  5686. tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
  5687. tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
  5688. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
  5689. err = tg3_load_5701_a0_firmware_fix(tp);
  5690. if (err)
  5691. return err;
  5692. }
  5693. if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
  5694. err = tg3_load_tso_firmware(tp);
  5695. if (err)
  5696. return err;
  5697. }
  5698. tp->tx_mode = TX_MODE_ENABLE;
  5699. tw32_f(MAC_TX_MODE, tp->tx_mode);
  5700. udelay(100);
  5701. tp->rx_mode = RX_MODE_ENABLE;
  5702. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  5703. tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
  5704. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5705. udelay(10);
  5706. if (tp->link_config.phy_is_low_power) {
  5707. tp->link_config.phy_is_low_power = 0;
  5708. tp->link_config.speed = tp->link_config.orig_speed;
  5709. tp->link_config.duplex = tp->link_config.orig_duplex;
  5710. tp->link_config.autoneg = tp->link_config.orig_autoneg;
  5711. }
  5712. tp->mi_mode = MAC_MI_MODE_BASE;
  5713. tw32_f(MAC_MI_MODE, tp->mi_mode);
  5714. udelay(80);
  5715. tw32(MAC_LED_CTRL, tp->led_ctrl);
  5716. tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
  5717. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5718. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  5719. udelay(10);
  5720. }
  5721. tw32_f(MAC_RX_MODE, tp->rx_mode);
  5722. udelay(10);
  5723. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  5724. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
  5725. !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
  5726. /* Set drive transmission level to 1.2V */
  5727. /* only if the signal pre-emphasis bit is not set */
  5728. val = tr32(MAC_SERDES_CFG);
  5729. val &= 0xfffff000;
  5730. val |= 0x880;
  5731. tw32(MAC_SERDES_CFG, val);
  5732. }
  5733. if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
  5734. tw32(MAC_SERDES_CFG, 0x616000);
  5735. }
  5736. /* Prevent chip from dropping frames when flow control
  5737. * is enabled.
  5738. */
  5739. tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
  5740. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
  5741. (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  5742. /* Use hardware link auto-negotiation */
  5743. tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
  5744. }
  5745. if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
  5746. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
  5747. u32 tmp;
  5748. tmp = tr32(SERDES_RX_CTRL);
  5749. tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
  5750. tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
  5751. tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
  5752. tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  5753. }
  5754. err = tg3_setup_phy(tp, 0);
  5755. if (err)
  5756. return err;
  5757. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  5758. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
  5759. u32 tmp;
  5760. /* Clear CRC stats. */
  5761. if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
  5762. tg3_writephy(tp, MII_TG3_TEST1,
  5763. tmp | MII_TG3_TEST1_CRC_EN);
  5764. tg3_readphy(tp, 0x14, &tmp);
  5765. }
  5766. }
  5767. __tg3_set_rx_mode(tp->dev);
  5768. /* Initialize receive rules. */
  5769. tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
  5770. tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
  5771. tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
  5772. tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
  5773. if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
  5774. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  5775. limit = 8;
  5776. else
  5777. limit = 16;
  5778. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
  5779. limit -= 4;
  5780. switch (limit) {
  5781. case 16:
  5782. tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
  5783. case 15:
  5784. tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
  5785. case 14:
  5786. tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
  5787. case 13:
  5788. tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
  5789. case 12:
  5790. tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
  5791. case 11:
  5792. tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
  5793. case 10:
  5794. tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
  5795. case 9:
  5796. tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
  5797. case 8:
  5798. tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
  5799. case 7:
  5800. tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
  5801. case 6:
  5802. tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
  5803. case 5:
  5804. tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
  5805. case 4:
  5806. /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
  5807. case 3:
  5808. /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
  5809. case 2:
  5810. case 1:
  5811. default:
  5812. break;
  5813. };
  5814. tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
  5815. return 0;
  5816. }
  5817. /* Called at device open time to get the chip ready for
  5818. * packet processing. Invoked with tp->lock held.
  5819. */
  5820. static int tg3_init_hw(struct tg3 *tp, int reset_phy)
  5821. {
  5822. int err;
  5823. /* Force the chip into D0. */
  5824. err = tg3_set_power_state(tp, PCI_D0);
  5825. if (err)
  5826. goto out;
  5827. tg3_switch_clocks(tp);
  5828. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  5829. err = tg3_reset_hw(tp, reset_phy);
  5830. out:
  5831. return err;
  5832. }
  5833. #define TG3_STAT_ADD32(PSTAT, REG) \
  5834. do { u32 __val = tr32(REG); \
  5835. (PSTAT)->low += __val; \
  5836. if ((PSTAT)->low < __val) \
  5837. (PSTAT)->high += 1; \
  5838. } while (0)
  5839. static void tg3_periodic_fetch_stats(struct tg3 *tp)
  5840. {
  5841. struct tg3_hw_stats *sp = tp->hw_stats;
  5842. if (!netif_carrier_ok(tp->dev))
  5843. return;
  5844. TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
  5845. TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
  5846. TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
  5847. TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
  5848. TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
  5849. TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
  5850. TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
  5851. TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
  5852. TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
  5853. TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
  5854. TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
  5855. TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
  5856. TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
  5857. TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
  5858. TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
  5859. TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
  5860. TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
  5861. TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
  5862. TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
  5863. TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
  5864. TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
  5865. TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
  5866. TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
  5867. TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
  5868. TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
  5869. TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
  5870. TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
  5871. TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
  5872. TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
  5873. TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
  5874. }
  5875. static void tg3_timer(unsigned long __opaque)
  5876. {
  5877. struct tg3 *tp = (struct tg3 *) __opaque;
  5878. if (tp->irq_sync)
  5879. goto restart_timer;
  5880. spin_lock(&tp->lock);
  5881. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  5882. /* All of this garbage is because when using non-tagged
  5883. * IRQ status the mailbox/status_block protocol the chip
  5884. * uses with the cpu is race prone.
  5885. */
  5886. if (tp->hw_status->status & SD_STATUS_UPDATED) {
  5887. tw32(GRC_LOCAL_CTRL,
  5888. tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
  5889. } else {
  5890. tw32(HOSTCC_MODE, tp->coalesce_mode |
  5891. (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
  5892. }
  5893. if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  5894. tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
  5895. spin_unlock(&tp->lock);
  5896. schedule_work(&tp->reset_task);
  5897. return;
  5898. }
  5899. }
  5900. /* This part only runs once per second. */
  5901. if (!--tp->timer_counter) {
  5902. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
  5903. tg3_periodic_fetch_stats(tp);
  5904. if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
  5905. u32 mac_stat;
  5906. int phy_event;
  5907. mac_stat = tr32(MAC_STATUS);
  5908. phy_event = 0;
  5909. if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
  5910. if (mac_stat & MAC_STATUS_MI_INTERRUPT)
  5911. phy_event = 1;
  5912. } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
  5913. phy_event = 1;
  5914. if (phy_event)
  5915. tg3_setup_phy(tp, 0);
  5916. } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
  5917. u32 mac_stat = tr32(MAC_STATUS);
  5918. int need_setup = 0;
  5919. if (netif_carrier_ok(tp->dev) &&
  5920. (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
  5921. need_setup = 1;
  5922. }
  5923. if (! netif_carrier_ok(tp->dev) &&
  5924. (mac_stat & (MAC_STATUS_PCS_SYNCED |
  5925. MAC_STATUS_SIGNAL_DET))) {
  5926. need_setup = 1;
  5927. }
  5928. if (need_setup) {
  5929. if (!tp->serdes_counter) {
  5930. tw32_f(MAC_MODE,
  5931. (tp->mac_mode &
  5932. ~MAC_MODE_PORT_MODE_MASK));
  5933. udelay(40);
  5934. tw32_f(MAC_MODE, tp->mac_mode);
  5935. udelay(40);
  5936. }
  5937. tg3_setup_phy(tp, 0);
  5938. }
  5939. } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  5940. tg3_serdes_parallel_detect(tp);
  5941. tp->timer_counter = tp->timer_multiplier;
  5942. }
  5943. /* Heartbeat is only sent once every 2 seconds.
  5944. *
  5945. * The heartbeat is to tell the ASF firmware that the host
  5946. * driver is still alive. In the event that the OS crashes,
  5947. * ASF needs to reset the hardware to free up the FIFO space
  5948. * that may be filled with rx packets destined for the host.
  5949. * If the FIFO is full, ASF will no longer function properly.
  5950. *
  5951. * Unintended resets have been reported on real time kernels
  5952. * where the timer doesn't run on time. Netpoll will also have
  5953. * same problem.
  5954. *
  5955. * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
  5956. * to check the ring condition when the heartbeat is expiring
  5957. * before doing the reset. This will prevent most unintended
  5958. * resets.
  5959. */
  5960. if (!--tp->asf_counter) {
  5961. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  5962. u32 val;
  5963. tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
  5964. FWCMD_NICDRV_ALIVE3);
  5965. tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
  5966. /* 5 seconds timeout */
  5967. tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
  5968. val = tr32(GRC_RX_CPU_EVENT);
  5969. val |= (1 << 14);
  5970. tw32(GRC_RX_CPU_EVENT, val);
  5971. }
  5972. tp->asf_counter = tp->asf_multiplier;
  5973. }
  5974. spin_unlock(&tp->lock);
  5975. restart_timer:
  5976. tp->timer.expires = jiffies + tp->timer_offset;
  5977. add_timer(&tp->timer);
  5978. }
  5979. static int tg3_request_irq(struct tg3 *tp)
  5980. {
  5981. irq_handler_t fn;
  5982. unsigned long flags;
  5983. struct net_device *dev = tp->dev;
  5984. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  5985. fn = tg3_msi;
  5986. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
  5987. fn = tg3_msi_1shot;
  5988. flags = IRQF_SAMPLE_RANDOM;
  5989. } else {
  5990. fn = tg3_interrupt;
  5991. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  5992. fn = tg3_interrupt_tagged;
  5993. flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
  5994. }
  5995. return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
  5996. }
  5997. static int tg3_test_interrupt(struct tg3 *tp)
  5998. {
  5999. struct net_device *dev = tp->dev;
  6000. int err, i, intr_ok = 0;
  6001. if (!netif_running(dev))
  6002. return -ENODEV;
  6003. tg3_disable_ints(tp);
  6004. free_irq(tp->pdev->irq, dev);
  6005. err = request_irq(tp->pdev->irq, tg3_test_isr,
  6006. IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
  6007. if (err)
  6008. return err;
  6009. tp->hw_status->status &= ~SD_STATUS_UPDATED;
  6010. tg3_enable_ints(tp);
  6011. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  6012. HOSTCC_MODE_NOW);
  6013. for (i = 0; i < 5; i++) {
  6014. u32 int_mbox, misc_host_ctrl;
  6015. int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
  6016. TG3_64BIT_REG_LOW);
  6017. misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
  6018. if ((int_mbox != 0) ||
  6019. (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
  6020. intr_ok = 1;
  6021. break;
  6022. }
  6023. msleep(10);
  6024. }
  6025. tg3_disable_ints(tp);
  6026. free_irq(tp->pdev->irq, dev);
  6027. err = tg3_request_irq(tp);
  6028. if (err)
  6029. return err;
  6030. if (intr_ok)
  6031. return 0;
  6032. return -EIO;
  6033. }
  6034. /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
  6035. * successfully restored
  6036. */
  6037. static int tg3_test_msi(struct tg3 *tp)
  6038. {
  6039. struct net_device *dev = tp->dev;
  6040. int err;
  6041. u16 pci_cmd;
  6042. if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  6043. return 0;
  6044. /* Turn off SERR reporting in case MSI terminates with Master
  6045. * Abort.
  6046. */
  6047. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  6048. pci_write_config_word(tp->pdev, PCI_COMMAND,
  6049. pci_cmd & ~PCI_COMMAND_SERR);
  6050. err = tg3_test_interrupt(tp);
  6051. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  6052. if (!err)
  6053. return 0;
  6054. /* other failures */
  6055. if (err != -EIO)
  6056. return err;
  6057. /* MSI test failed, go back to INTx mode */
  6058. printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
  6059. "switching to INTx mode. Please report this failure to "
  6060. "the PCI maintainer and include system chipset information.\n",
  6061. tp->dev->name);
  6062. free_irq(tp->pdev->irq, dev);
  6063. pci_disable_msi(tp->pdev);
  6064. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6065. err = tg3_request_irq(tp);
  6066. if (err)
  6067. return err;
  6068. /* Need to reset the chip because the MSI cycle may have terminated
  6069. * with Master Abort.
  6070. */
  6071. tg3_full_lock(tp, 1);
  6072. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6073. err = tg3_init_hw(tp, 1);
  6074. tg3_full_unlock(tp);
  6075. if (err)
  6076. free_irq(tp->pdev->irq, dev);
  6077. return err;
  6078. }
  6079. static int tg3_open(struct net_device *dev)
  6080. {
  6081. struct tg3 *tp = netdev_priv(dev);
  6082. int err;
  6083. netif_carrier_off(tp->dev);
  6084. tg3_full_lock(tp, 0);
  6085. err = tg3_set_power_state(tp, PCI_D0);
  6086. if (err) {
  6087. tg3_full_unlock(tp);
  6088. return err;
  6089. }
  6090. tg3_disable_ints(tp);
  6091. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6092. tg3_full_unlock(tp);
  6093. /* The placement of this call is tied
  6094. * to the setup and use of Host TX descriptors.
  6095. */
  6096. err = tg3_alloc_consistent(tp);
  6097. if (err)
  6098. return err;
  6099. if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
  6100. /* All MSI supporting chips should support tagged
  6101. * status. Assert that this is the case.
  6102. */
  6103. if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
  6104. printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
  6105. "Not using MSI.\n", tp->dev->name);
  6106. } else if (pci_enable_msi(tp->pdev) == 0) {
  6107. u32 msi_mode;
  6108. /* Hardware bug - MSI won't work if INTX disabled. */
  6109. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  6110. pci_intx(tp->pdev, 1);
  6111. msi_mode = tr32(MSGINT_MODE);
  6112. tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
  6113. tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
  6114. }
  6115. }
  6116. err = tg3_request_irq(tp);
  6117. if (err) {
  6118. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6119. pci_disable_msi(tp->pdev);
  6120. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6121. }
  6122. tg3_free_consistent(tp);
  6123. return err;
  6124. }
  6125. napi_enable(&tp->napi);
  6126. tg3_full_lock(tp, 0);
  6127. err = tg3_init_hw(tp, 1);
  6128. if (err) {
  6129. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6130. tg3_free_rings(tp);
  6131. } else {
  6132. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
  6133. tp->timer_offset = HZ;
  6134. else
  6135. tp->timer_offset = HZ / 10;
  6136. BUG_ON(tp->timer_offset > HZ);
  6137. tp->timer_counter = tp->timer_multiplier =
  6138. (HZ / tp->timer_offset);
  6139. tp->asf_counter = tp->asf_multiplier =
  6140. ((HZ / tp->timer_offset) * 2);
  6141. init_timer(&tp->timer);
  6142. tp->timer.expires = jiffies + tp->timer_offset;
  6143. tp->timer.data = (unsigned long) tp;
  6144. tp->timer.function = tg3_timer;
  6145. }
  6146. tg3_full_unlock(tp);
  6147. if (err) {
  6148. napi_disable(&tp->napi);
  6149. free_irq(tp->pdev->irq, dev);
  6150. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6151. pci_disable_msi(tp->pdev);
  6152. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6153. }
  6154. tg3_free_consistent(tp);
  6155. return err;
  6156. }
  6157. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6158. err = tg3_test_msi(tp);
  6159. if (err) {
  6160. tg3_full_lock(tp, 0);
  6161. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6162. pci_disable_msi(tp->pdev);
  6163. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6164. }
  6165. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6166. tg3_free_rings(tp);
  6167. tg3_free_consistent(tp);
  6168. tg3_full_unlock(tp);
  6169. napi_disable(&tp->napi);
  6170. return err;
  6171. }
  6172. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6173. if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
  6174. u32 val = tr32(PCIE_TRANSACTION_CFG);
  6175. tw32(PCIE_TRANSACTION_CFG,
  6176. val | PCIE_TRANS_CFG_1SHOT_MSI);
  6177. }
  6178. }
  6179. }
  6180. tg3_full_lock(tp, 0);
  6181. add_timer(&tp->timer);
  6182. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  6183. tg3_enable_ints(tp);
  6184. tg3_full_unlock(tp);
  6185. netif_start_queue(dev);
  6186. return 0;
  6187. }
  6188. #if 0
  6189. /*static*/ void tg3_dump_state(struct tg3 *tp)
  6190. {
  6191. u32 val32, val32_2, val32_3, val32_4, val32_5;
  6192. u16 val16;
  6193. int i;
  6194. pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
  6195. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
  6196. printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
  6197. val16, val32);
  6198. /* MAC block */
  6199. printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
  6200. tr32(MAC_MODE), tr32(MAC_STATUS));
  6201. printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
  6202. tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
  6203. printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
  6204. tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
  6205. printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
  6206. tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
  6207. /* Send data initiator control block */
  6208. printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
  6209. tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
  6210. printk(" SNDDATAI_STATSCTRL[%08x]\n",
  6211. tr32(SNDDATAI_STATSCTRL));
  6212. /* Send data completion control block */
  6213. printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
  6214. /* Send BD ring selector block */
  6215. printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
  6216. tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
  6217. /* Send BD initiator control block */
  6218. printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
  6219. tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
  6220. /* Send BD completion control block */
  6221. printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
  6222. /* Receive list placement control block */
  6223. printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
  6224. tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
  6225. printk(" RCVLPC_STATSCTRL[%08x]\n",
  6226. tr32(RCVLPC_STATSCTRL));
  6227. /* Receive data and receive BD initiator control block */
  6228. printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
  6229. tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
  6230. /* Receive data completion control block */
  6231. printk("DEBUG: RCVDCC_MODE[%08x]\n",
  6232. tr32(RCVDCC_MODE));
  6233. /* Receive BD initiator control block */
  6234. printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
  6235. tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
  6236. /* Receive BD completion control block */
  6237. printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
  6238. tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
  6239. /* Receive list selector control block */
  6240. printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
  6241. tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
  6242. /* Mbuf cluster free block */
  6243. printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
  6244. tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
  6245. /* Host coalescing control block */
  6246. printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
  6247. tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
  6248. printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
  6249. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6250. tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6251. printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
  6252. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
  6253. tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
  6254. printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
  6255. tr32(HOSTCC_STATS_BLK_NIC_ADDR));
  6256. printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
  6257. tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
  6258. /* Memory arbiter control block */
  6259. printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
  6260. tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
  6261. /* Buffer manager control block */
  6262. printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
  6263. tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
  6264. printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
  6265. tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
  6266. printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
  6267. "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
  6268. tr32(BUFMGR_DMA_DESC_POOL_ADDR),
  6269. tr32(BUFMGR_DMA_DESC_POOL_SIZE));
  6270. /* Read DMA control block */
  6271. printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
  6272. tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
  6273. /* Write DMA control block */
  6274. printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
  6275. tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
  6276. /* DMA completion block */
  6277. printk("DEBUG: DMAC_MODE[%08x]\n",
  6278. tr32(DMAC_MODE));
  6279. /* GRC block */
  6280. printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
  6281. tr32(GRC_MODE), tr32(GRC_MISC_CFG));
  6282. printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
  6283. tr32(GRC_LOCAL_CTRL));
  6284. /* TG3_BDINFOs */
  6285. printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
  6286. tr32(RCVDBDI_JUMBO_BD + 0x0),
  6287. tr32(RCVDBDI_JUMBO_BD + 0x4),
  6288. tr32(RCVDBDI_JUMBO_BD + 0x8),
  6289. tr32(RCVDBDI_JUMBO_BD + 0xc));
  6290. printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
  6291. tr32(RCVDBDI_STD_BD + 0x0),
  6292. tr32(RCVDBDI_STD_BD + 0x4),
  6293. tr32(RCVDBDI_STD_BD + 0x8),
  6294. tr32(RCVDBDI_STD_BD + 0xc));
  6295. printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
  6296. tr32(RCVDBDI_MINI_BD + 0x0),
  6297. tr32(RCVDBDI_MINI_BD + 0x4),
  6298. tr32(RCVDBDI_MINI_BD + 0x8),
  6299. tr32(RCVDBDI_MINI_BD + 0xc));
  6300. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
  6301. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
  6302. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
  6303. tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
  6304. printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
  6305. val32, val32_2, val32_3, val32_4);
  6306. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
  6307. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
  6308. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
  6309. tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
  6310. printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
  6311. val32, val32_2, val32_3, val32_4);
  6312. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
  6313. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
  6314. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
  6315. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
  6316. tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
  6317. printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
  6318. val32, val32_2, val32_3, val32_4, val32_5);
  6319. /* SW status block */
  6320. printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
  6321. tp->hw_status->status,
  6322. tp->hw_status->status_tag,
  6323. tp->hw_status->rx_jumbo_consumer,
  6324. tp->hw_status->rx_consumer,
  6325. tp->hw_status->rx_mini_consumer,
  6326. tp->hw_status->idx[0].rx_producer,
  6327. tp->hw_status->idx[0].tx_consumer);
  6328. /* SW statistics block */
  6329. printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
  6330. ((u32 *)tp->hw_stats)[0],
  6331. ((u32 *)tp->hw_stats)[1],
  6332. ((u32 *)tp->hw_stats)[2],
  6333. ((u32 *)tp->hw_stats)[3]);
  6334. /* Mailboxes */
  6335. printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
  6336. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
  6337. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
  6338. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
  6339. tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
  6340. /* NIC side send descriptors. */
  6341. for (i = 0; i < 6; i++) {
  6342. unsigned long txd;
  6343. txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
  6344. + (i * sizeof(struct tg3_tx_buffer_desc));
  6345. printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
  6346. i,
  6347. readl(txd + 0x0), readl(txd + 0x4),
  6348. readl(txd + 0x8), readl(txd + 0xc));
  6349. }
  6350. /* NIC side RX descriptors. */
  6351. for (i = 0; i < 6; i++) {
  6352. unsigned long rxd;
  6353. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
  6354. + (i * sizeof(struct tg3_rx_buffer_desc));
  6355. printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
  6356. i,
  6357. readl(rxd + 0x0), readl(rxd + 0x4),
  6358. readl(rxd + 0x8), readl(rxd + 0xc));
  6359. rxd += (4 * sizeof(u32));
  6360. printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
  6361. i,
  6362. readl(rxd + 0x0), readl(rxd + 0x4),
  6363. readl(rxd + 0x8), readl(rxd + 0xc));
  6364. }
  6365. for (i = 0; i < 6; i++) {
  6366. unsigned long rxd;
  6367. rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
  6368. + (i * sizeof(struct tg3_rx_buffer_desc));
  6369. printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
  6370. i,
  6371. readl(rxd + 0x0), readl(rxd + 0x4),
  6372. readl(rxd + 0x8), readl(rxd + 0xc));
  6373. rxd += (4 * sizeof(u32));
  6374. printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
  6375. i,
  6376. readl(rxd + 0x0), readl(rxd + 0x4),
  6377. readl(rxd + 0x8), readl(rxd + 0xc));
  6378. }
  6379. }
  6380. #endif
  6381. static struct net_device_stats *tg3_get_stats(struct net_device *);
  6382. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
  6383. static int tg3_close(struct net_device *dev)
  6384. {
  6385. struct tg3 *tp = netdev_priv(dev);
  6386. napi_disable(&tp->napi);
  6387. cancel_work_sync(&tp->reset_task);
  6388. netif_stop_queue(dev);
  6389. del_timer_sync(&tp->timer);
  6390. tg3_full_lock(tp, 1);
  6391. #if 0
  6392. tg3_dump_state(tp);
  6393. #endif
  6394. tg3_disable_ints(tp);
  6395. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  6396. tg3_free_rings(tp);
  6397. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  6398. tg3_full_unlock(tp);
  6399. free_irq(tp->pdev->irq, dev);
  6400. if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
  6401. pci_disable_msi(tp->pdev);
  6402. tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
  6403. }
  6404. memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
  6405. sizeof(tp->net_stats_prev));
  6406. memcpy(&tp->estats_prev, tg3_get_estats(tp),
  6407. sizeof(tp->estats_prev));
  6408. tg3_free_consistent(tp);
  6409. tg3_set_power_state(tp, PCI_D3hot);
  6410. netif_carrier_off(tp->dev);
  6411. return 0;
  6412. }
  6413. static inline unsigned long get_stat64(tg3_stat64_t *val)
  6414. {
  6415. unsigned long ret;
  6416. #if (BITS_PER_LONG == 32)
  6417. ret = val->low;
  6418. #else
  6419. ret = ((u64)val->high << 32) | ((u64)val->low);
  6420. #endif
  6421. return ret;
  6422. }
  6423. static unsigned long calc_crc_errors(struct tg3 *tp)
  6424. {
  6425. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6426. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
  6427. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  6428. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
  6429. u32 val;
  6430. spin_lock_bh(&tp->lock);
  6431. if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
  6432. tg3_writephy(tp, MII_TG3_TEST1,
  6433. val | MII_TG3_TEST1_CRC_EN);
  6434. tg3_readphy(tp, 0x14, &val);
  6435. } else
  6436. val = 0;
  6437. spin_unlock_bh(&tp->lock);
  6438. tp->phy_crc_errors += val;
  6439. return tp->phy_crc_errors;
  6440. }
  6441. return get_stat64(&hw_stats->rx_fcs_errors);
  6442. }
  6443. #define ESTAT_ADD(member) \
  6444. estats->member = old_estats->member + \
  6445. get_stat64(&hw_stats->member)
  6446. static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
  6447. {
  6448. struct tg3_ethtool_stats *estats = &tp->estats;
  6449. struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
  6450. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6451. if (!hw_stats)
  6452. return old_estats;
  6453. ESTAT_ADD(rx_octets);
  6454. ESTAT_ADD(rx_fragments);
  6455. ESTAT_ADD(rx_ucast_packets);
  6456. ESTAT_ADD(rx_mcast_packets);
  6457. ESTAT_ADD(rx_bcast_packets);
  6458. ESTAT_ADD(rx_fcs_errors);
  6459. ESTAT_ADD(rx_align_errors);
  6460. ESTAT_ADD(rx_xon_pause_rcvd);
  6461. ESTAT_ADD(rx_xoff_pause_rcvd);
  6462. ESTAT_ADD(rx_mac_ctrl_rcvd);
  6463. ESTAT_ADD(rx_xoff_entered);
  6464. ESTAT_ADD(rx_frame_too_long_errors);
  6465. ESTAT_ADD(rx_jabbers);
  6466. ESTAT_ADD(rx_undersize_packets);
  6467. ESTAT_ADD(rx_in_length_errors);
  6468. ESTAT_ADD(rx_out_length_errors);
  6469. ESTAT_ADD(rx_64_or_less_octet_packets);
  6470. ESTAT_ADD(rx_65_to_127_octet_packets);
  6471. ESTAT_ADD(rx_128_to_255_octet_packets);
  6472. ESTAT_ADD(rx_256_to_511_octet_packets);
  6473. ESTAT_ADD(rx_512_to_1023_octet_packets);
  6474. ESTAT_ADD(rx_1024_to_1522_octet_packets);
  6475. ESTAT_ADD(rx_1523_to_2047_octet_packets);
  6476. ESTAT_ADD(rx_2048_to_4095_octet_packets);
  6477. ESTAT_ADD(rx_4096_to_8191_octet_packets);
  6478. ESTAT_ADD(rx_8192_to_9022_octet_packets);
  6479. ESTAT_ADD(tx_octets);
  6480. ESTAT_ADD(tx_collisions);
  6481. ESTAT_ADD(tx_xon_sent);
  6482. ESTAT_ADD(tx_xoff_sent);
  6483. ESTAT_ADD(tx_flow_control);
  6484. ESTAT_ADD(tx_mac_errors);
  6485. ESTAT_ADD(tx_single_collisions);
  6486. ESTAT_ADD(tx_mult_collisions);
  6487. ESTAT_ADD(tx_deferred);
  6488. ESTAT_ADD(tx_excessive_collisions);
  6489. ESTAT_ADD(tx_late_collisions);
  6490. ESTAT_ADD(tx_collide_2times);
  6491. ESTAT_ADD(tx_collide_3times);
  6492. ESTAT_ADD(tx_collide_4times);
  6493. ESTAT_ADD(tx_collide_5times);
  6494. ESTAT_ADD(tx_collide_6times);
  6495. ESTAT_ADD(tx_collide_7times);
  6496. ESTAT_ADD(tx_collide_8times);
  6497. ESTAT_ADD(tx_collide_9times);
  6498. ESTAT_ADD(tx_collide_10times);
  6499. ESTAT_ADD(tx_collide_11times);
  6500. ESTAT_ADD(tx_collide_12times);
  6501. ESTAT_ADD(tx_collide_13times);
  6502. ESTAT_ADD(tx_collide_14times);
  6503. ESTAT_ADD(tx_collide_15times);
  6504. ESTAT_ADD(tx_ucast_packets);
  6505. ESTAT_ADD(tx_mcast_packets);
  6506. ESTAT_ADD(tx_bcast_packets);
  6507. ESTAT_ADD(tx_carrier_sense_errors);
  6508. ESTAT_ADD(tx_discards);
  6509. ESTAT_ADD(tx_errors);
  6510. ESTAT_ADD(dma_writeq_full);
  6511. ESTAT_ADD(dma_write_prioq_full);
  6512. ESTAT_ADD(rxbds_empty);
  6513. ESTAT_ADD(rx_discards);
  6514. ESTAT_ADD(rx_errors);
  6515. ESTAT_ADD(rx_threshold_hit);
  6516. ESTAT_ADD(dma_readq_full);
  6517. ESTAT_ADD(dma_read_prioq_full);
  6518. ESTAT_ADD(tx_comp_queue_full);
  6519. ESTAT_ADD(ring_set_send_prod_index);
  6520. ESTAT_ADD(ring_status_update);
  6521. ESTAT_ADD(nic_irqs);
  6522. ESTAT_ADD(nic_avoided_irqs);
  6523. ESTAT_ADD(nic_tx_threshold_hit);
  6524. return estats;
  6525. }
  6526. static struct net_device_stats *tg3_get_stats(struct net_device *dev)
  6527. {
  6528. struct tg3 *tp = netdev_priv(dev);
  6529. struct net_device_stats *stats = &tp->net_stats;
  6530. struct net_device_stats *old_stats = &tp->net_stats_prev;
  6531. struct tg3_hw_stats *hw_stats = tp->hw_stats;
  6532. if (!hw_stats)
  6533. return old_stats;
  6534. stats->rx_packets = old_stats->rx_packets +
  6535. get_stat64(&hw_stats->rx_ucast_packets) +
  6536. get_stat64(&hw_stats->rx_mcast_packets) +
  6537. get_stat64(&hw_stats->rx_bcast_packets);
  6538. stats->tx_packets = old_stats->tx_packets +
  6539. get_stat64(&hw_stats->tx_ucast_packets) +
  6540. get_stat64(&hw_stats->tx_mcast_packets) +
  6541. get_stat64(&hw_stats->tx_bcast_packets);
  6542. stats->rx_bytes = old_stats->rx_bytes +
  6543. get_stat64(&hw_stats->rx_octets);
  6544. stats->tx_bytes = old_stats->tx_bytes +
  6545. get_stat64(&hw_stats->tx_octets);
  6546. stats->rx_errors = old_stats->rx_errors +
  6547. get_stat64(&hw_stats->rx_errors);
  6548. stats->tx_errors = old_stats->tx_errors +
  6549. get_stat64(&hw_stats->tx_errors) +
  6550. get_stat64(&hw_stats->tx_mac_errors) +
  6551. get_stat64(&hw_stats->tx_carrier_sense_errors) +
  6552. get_stat64(&hw_stats->tx_discards);
  6553. stats->multicast = old_stats->multicast +
  6554. get_stat64(&hw_stats->rx_mcast_packets);
  6555. stats->collisions = old_stats->collisions +
  6556. get_stat64(&hw_stats->tx_collisions);
  6557. stats->rx_length_errors = old_stats->rx_length_errors +
  6558. get_stat64(&hw_stats->rx_frame_too_long_errors) +
  6559. get_stat64(&hw_stats->rx_undersize_packets);
  6560. stats->rx_over_errors = old_stats->rx_over_errors +
  6561. get_stat64(&hw_stats->rxbds_empty);
  6562. stats->rx_frame_errors = old_stats->rx_frame_errors +
  6563. get_stat64(&hw_stats->rx_align_errors);
  6564. stats->tx_aborted_errors = old_stats->tx_aborted_errors +
  6565. get_stat64(&hw_stats->tx_discards);
  6566. stats->tx_carrier_errors = old_stats->tx_carrier_errors +
  6567. get_stat64(&hw_stats->tx_carrier_sense_errors);
  6568. stats->rx_crc_errors = old_stats->rx_crc_errors +
  6569. calc_crc_errors(tp);
  6570. stats->rx_missed_errors = old_stats->rx_missed_errors +
  6571. get_stat64(&hw_stats->rx_discards);
  6572. return stats;
  6573. }
  6574. static inline u32 calc_crc(unsigned char *buf, int len)
  6575. {
  6576. u32 reg;
  6577. u32 tmp;
  6578. int j, k;
  6579. reg = 0xffffffff;
  6580. for (j = 0; j < len; j++) {
  6581. reg ^= buf[j];
  6582. for (k = 0; k < 8; k++) {
  6583. tmp = reg & 0x01;
  6584. reg >>= 1;
  6585. if (tmp) {
  6586. reg ^= 0xedb88320;
  6587. }
  6588. }
  6589. }
  6590. return ~reg;
  6591. }
  6592. static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
  6593. {
  6594. /* accept or reject all multicast frames */
  6595. tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
  6596. tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
  6597. tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
  6598. tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
  6599. }
  6600. static void __tg3_set_rx_mode(struct net_device *dev)
  6601. {
  6602. struct tg3 *tp = netdev_priv(dev);
  6603. u32 rx_mode;
  6604. rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
  6605. RX_MODE_KEEP_VLAN_TAG);
  6606. /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
  6607. * flag clear.
  6608. */
  6609. #if TG3_VLAN_TAG_USED
  6610. if (!tp->vlgrp &&
  6611. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  6612. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  6613. #else
  6614. /* By definition, VLAN is disabled always in this
  6615. * case.
  6616. */
  6617. if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
  6618. rx_mode |= RX_MODE_KEEP_VLAN_TAG;
  6619. #endif
  6620. if (dev->flags & IFF_PROMISC) {
  6621. /* Promiscuous mode. */
  6622. rx_mode |= RX_MODE_PROMISC;
  6623. } else if (dev->flags & IFF_ALLMULTI) {
  6624. /* Accept all multicast. */
  6625. tg3_set_multi (tp, 1);
  6626. } else if (dev->mc_count < 1) {
  6627. /* Reject all multicast. */
  6628. tg3_set_multi (tp, 0);
  6629. } else {
  6630. /* Accept one or more multicast(s). */
  6631. struct dev_mc_list *mclist;
  6632. unsigned int i;
  6633. u32 mc_filter[4] = { 0, };
  6634. u32 regidx;
  6635. u32 bit;
  6636. u32 crc;
  6637. for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  6638. i++, mclist = mclist->next) {
  6639. crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
  6640. bit = ~crc & 0x7f;
  6641. regidx = (bit & 0x60) >> 5;
  6642. bit &= 0x1f;
  6643. mc_filter[regidx] |= (1 << bit);
  6644. }
  6645. tw32(MAC_HASH_REG_0, mc_filter[0]);
  6646. tw32(MAC_HASH_REG_1, mc_filter[1]);
  6647. tw32(MAC_HASH_REG_2, mc_filter[2]);
  6648. tw32(MAC_HASH_REG_3, mc_filter[3]);
  6649. }
  6650. if (rx_mode != tp->rx_mode) {
  6651. tp->rx_mode = rx_mode;
  6652. tw32_f(MAC_RX_MODE, rx_mode);
  6653. udelay(10);
  6654. }
  6655. }
  6656. static void tg3_set_rx_mode(struct net_device *dev)
  6657. {
  6658. struct tg3 *tp = netdev_priv(dev);
  6659. if (!netif_running(dev))
  6660. return;
  6661. tg3_full_lock(tp, 0);
  6662. __tg3_set_rx_mode(dev);
  6663. tg3_full_unlock(tp);
  6664. }
  6665. #define TG3_REGDUMP_LEN (32 * 1024)
  6666. static int tg3_get_regs_len(struct net_device *dev)
  6667. {
  6668. return TG3_REGDUMP_LEN;
  6669. }
  6670. static void tg3_get_regs(struct net_device *dev,
  6671. struct ethtool_regs *regs, void *_p)
  6672. {
  6673. u32 *p = _p;
  6674. struct tg3 *tp = netdev_priv(dev);
  6675. u8 *orig_p = _p;
  6676. int i;
  6677. regs->version = 0;
  6678. memset(p, 0, TG3_REGDUMP_LEN);
  6679. if (tp->link_config.phy_is_low_power)
  6680. return;
  6681. tg3_full_lock(tp, 0);
  6682. #define __GET_REG32(reg) (*(p)++ = tr32(reg))
  6683. #define GET_REG32_LOOP(base,len) \
  6684. do { p = (u32 *)(orig_p + (base)); \
  6685. for (i = 0; i < len; i += 4) \
  6686. __GET_REG32((base) + i); \
  6687. } while (0)
  6688. #define GET_REG32_1(reg) \
  6689. do { p = (u32 *)(orig_p + (reg)); \
  6690. __GET_REG32((reg)); \
  6691. } while (0)
  6692. GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
  6693. GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
  6694. GET_REG32_LOOP(MAC_MODE, 0x4f0);
  6695. GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
  6696. GET_REG32_1(SNDDATAC_MODE);
  6697. GET_REG32_LOOP(SNDBDS_MODE, 0x80);
  6698. GET_REG32_LOOP(SNDBDI_MODE, 0x48);
  6699. GET_REG32_1(SNDBDC_MODE);
  6700. GET_REG32_LOOP(RCVLPC_MODE, 0x20);
  6701. GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
  6702. GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
  6703. GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
  6704. GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
  6705. GET_REG32_1(RCVDCC_MODE);
  6706. GET_REG32_LOOP(RCVBDI_MODE, 0x20);
  6707. GET_REG32_LOOP(RCVCC_MODE, 0x14);
  6708. GET_REG32_LOOP(RCVLSC_MODE, 0x08);
  6709. GET_REG32_1(MBFREE_MODE);
  6710. GET_REG32_LOOP(HOSTCC_MODE, 0x100);
  6711. GET_REG32_LOOP(MEMARB_MODE, 0x10);
  6712. GET_REG32_LOOP(BUFMGR_MODE, 0x58);
  6713. GET_REG32_LOOP(RDMAC_MODE, 0x08);
  6714. GET_REG32_LOOP(WDMAC_MODE, 0x08);
  6715. GET_REG32_1(RX_CPU_MODE);
  6716. GET_REG32_1(RX_CPU_STATE);
  6717. GET_REG32_1(RX_CPU_PGMCTR);
  6718. GET_REG32_1(RX_CPU_HWBKPT);
  6719. GET_REG32_1(TX_CPU_MODE);
  6720. GET_REG32_1(TX_CPU_STATE);
  6721. GET_REG32_1(TX_CPU_PGMCTR);
  6722. GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
  6723. GET_REG32_LOOP(FTQ_RESET, 0x120);
  6724. GET_REG32_LOOP(MSGINT_MODE, 0x0c);
  6725. GET_REG32_1(DMAC_MODE);
  6726. GET_REG32_LOOP(GRC_MODE, 0x4c);
  6727. if (tp->tg3_flags & TG3_FLAG_NVRAM)
  6728. GET_REG32_LOOP(NVRAM_CMD, 0x24);
  6729. #undef __GET_REG32
  6730. #undef GET_REG32_LOOP
  6731. #undef GET_REG32_1
  6732. tg3_full_unlock(tp);
  6733. }
  6734. static int tg3_get_eeprom_len(struct net_device *dev)
  6735. {
  6736. struct tg3 *tp = netdev_priv(dev);
  6737. return tp->nvram_size;
  6738. }
  6739. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
  6740. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
  6741. static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  6742. {
  6743. struct tg3 *tp = netdev_priv(dev);
  6744. int ret;
  6745. u8 *pd;
  6746. u32 i, offset, len, val, b_offset, b_count;
  6747. if (tp->link_config.phy_is_low_power)
  6748. return -EAGAIN;
  6749. offset = eeprom->offset;
  6750. len = eeprom->len;
  6751. eeprom->len = 0;
  6752. eeprom->magic = TG3_EEPROM_MAGIC;
  6753. if (offset & 3) {
  6754. /* adjustments to start on required 4 byte boundary */
  6755. b_offset = offset & 3;
  6756. b_count = 4 - b_offset;
  6757. if (b_count > len) {
  6758. /* i.e. offset=1 len=2 */
  6759. b_count = len;
  6760. }
  6761. ret = tg3_nvram_read(tp, offset-b_offset, &val);
  6762. if (ret)
  6763. return ret;
  6764. val = cpu_to_le32(val);
  6765. memcpy(data, ((char*)&val) + b_offset, b_count);
  6766. len -= b_count;
  6767. offset += b_count;
  6768. eeprom->len += b_count;
  6769. }
  6770. /* read bytes upto the last 4 byte boundary */
  6771. pd = &data[eeprom->len];
  6772. for (i = 0; i < (len - (len & 3)); i += 4) {
  6773. ret = tg3_nvram_read(tp, offset + i, &val);
  6774. if (ret) {
  6775. eeprom->len += i;
  6776. return ret;
  6777. }
  6778. val = cpu_to_le32(val);
  6779. memcpy(pd + i, &val, 4);
  6780. }
  6781. eeprom->len += i;
  6782. if (len & 3) {
  6783. /* read last bytes not ending on 4 byte boundary */
  6784. pd = &data[eeprom->len];
  6785. b_count = len & 3;
  6786. b_offset = offset + len - b_count;
  6787. ret = tg3_nvram_read(tp, b_offset, &val);
  6788. if (ret)
  6789. return ret;
  6790. val = cpu_to_le32(val);
  6791. memcpy(pd, ((char*)&val), b_count);
  6792. eeprom->len += b_count;
  6793. }
  6794. return 0;
  6795. }
  6796. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
  6797. static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
  6798. {
  6799. struct tg3 *tp = netdev_priv(dev);
  6800. int ret;
  6801. u32 offset, len, b_offset, odd_len, start, end;
  6802. u8 *buf;
  6803. if (tp->link_config.phy_is_low_power)
  6804. return -EAGAIN;
  6805. if (eeprom->magic != TG3_EEPROM_MAGIC)
  6806. return -EINVAL;
  6807. offset = eeprom->offset;
  6808. len = eeprom->len;
  6809. if ((b_offset = (offset & 3))) {
  6810. /* adjustments to start on required 4 byte boundary */
  6811. ret = tg3_nvram_read(tp, offset-b_offset, &start);
  6812. if (ret)
  6813. return ret;
  6814. start = cpu_to_le32(start);
  6815. len += b_offset;
  6816. offset &= ~3;
  6817. if (len < 4)
  6818. len = 4;
  6819. }
  6820. odd_len = 0;
  6821. if (len & 3) {
  6822. /* adjustments to end on required 4 byte boundary */
  6823. odd_len = 1;
  6824. len = (len + 3) & ~3;
  6825. ret = tg3_nvram_read(tp, offset+len-4, &end);
  6826. if (ret)
  6827. return ret;
  6828. end = cpu_to_le32(end);
  6829. }
  6830. buf = data;
  6831. if (b_offset || odd_len) {
  6832. buf = kmalloc(len, GFP_KERNEL);
  6833. if (!buf)
  6834. return -ENOMEM;
  6835. if (b_offset)
  6836. memcpy(buf, &start, 4);
  6837. if (odd_len)
  6838. memcpy(buf+len-4, &end, 4);
  6839. memcpy(buf + b_offset, data, eeprom->len);
  6840. }
  6841. ret = tg3_nvram_write_block(tp, offset, len, buf);
  6842. if (buf != data)
  6843. kfree(buf);
  6844. return ret;
  6845. }
  6846. static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  6847. {
  6848. struct tg3 *tp = netdev_priv(dev);
  6849. cmd->supported = (SUPPORTED_Autoneg);
  6850. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  6851. cmd->supported |= (SUPPORTED_1000baseT_Half |
  6852. SUPPORTED_1000baseT_Full);
  6853. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
  6854. cmd->supported |= (SUPPORTED_100baseT_Half |
  6855. SUPPORTED_100baseT_Full |
  6856. SUPPORTED_10baseT_Half |
  6857. SUPPORTED_10baseT_Full |
  6858. SUPPORTED_MII);
  6859. cmd->port = PORT_TP;
  6860. } else {
  6861. cmd->supported |= SUPPORTED_FIBRE;
  6862. cmd->port = PORT_FIBRE;
  6863. }
  6864. cmd->advertising = tp->link_config.advertising;
  6865. if (netif_running(dev)) {
  6866. cmd->speed = tp->link_config.active_speed;
  6867. cmd->duplex = tp->link_config.active_duplex;
  6868. }
  6869. cmd->phy_address = PHY_ADDR;
  6870. cmd->transceiver = 0;
  6871. cmd->autoneg = tp->link_config.autoneg;
  6872. cmd->maxtxpkt = 0;
  6873. cmd->maxrxpkt = 0;
  6874. return 0;
  6875. }
  6876. static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  6877. {
  6878. struct tg3 *tp = netdev_priv(dev);
  6879. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
  6880. /* These are the only valid advertisement bits allowed. */
  6881. if (cmd->autoneg == AUTONEG_ENABLE &&
  6882. (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
  6883. ADVERTISED_1000baseT_Full |
  6884. ADVERTISED_Autoneg |
  6885. ADVERTISED_FIBRE)))
  6886. return -EINVAL;
  6887. /* Fiber can only do SPEED_1000. */
  6888. else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  6889. (cmd->speed != SPEED_1000))
  6890. return -EINVAL;
  6891. /* Copper cannot force SPEED_1000. */
  6892. } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
  6893. (cmd->speed == SPEED_1000))
  6894. return -EINVAL;
  6895. else if ((cmd->speed == SPEED_1000) &&
  6896. (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
  6897. return -EINVAL;
  6898. tg3_full_lock(tp, 0);
  6899. tp->link_config.autoneg = cmd->autoneg;
  6900. if (cmd->autoneg == AUTONEG_ENABLE) {
  6901. tp->link_config.advertising = (cmd->advertising |
  6902. ADVERTISED_Autoneg);
  6903. tp->link_config.speed = SPEED_INVALID;
  6904. tp->link_config.duplex = DUPLEX_INVALID;
  6905. } else {
  6906. tp->link_config.advertising = 0;
  6907. tp->link_config.speed = cmd->speed;
  6908. tp->link_config.duplex = cmd->duplex;
  6909. }
  6910. tp->link_config.orig_speed = tp->link_config.speed;
  6911. tp->link_config.orig_duplex = tp->link_config.duplex;
  6912. tp->link_config.orig_autoneg = tp->link_config.autoneg;
  6913. if (netif_running(dev))
  6914. tg3_setup_phy(tp, 1);
  6915. tg3_full_unlock(tp);
  6916. return 0;
  6917. }
  6918. static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  6919. {
  6920. struct tg3 *tp = netdev_priv(dev);
  6921. strcpy(info->driver, DRV_MODULE_NAME);
  6922. strcpy(info->version, DRV_MODULE_VERSION);
  6923. strcpy(info->fw_version, tp->fw_ver);
  6924. strcpy(info->bus_info, pci_name(tp->pdev));
  6925. }
  6926. static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  6927. {
  6928. struct tg3 *tp = netdev_priv(dev);
  6929. if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
  6930. wol->supported = WAKE_MAGIC;
  6931. else
  6932. wol->supported = 0;
  6933. wol->wolopts = 0;
  6934. if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
  6935. wol->wolopts = WAKE_MAGIC;
  6936. memset(&wol->sopass, 0, sizeof(wol->sopass));
  6937. }
  6938. static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  6939. {
  6940. struct tg3 *tp = netdev_priv(dev);
  6941. if (wol->wolopts & ~WAKE_MAGIC)
  6942. return -EINVAL;
  6943. if ((wol->wolopts & WAKE_MAGIC) &&
  6944. !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
  6945. return -EINVAL;
  6946. spin_lock_bh(&tp->lock);
  6947. if (wol->wolopts & WAKE_MAGIC)
  6948. tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
  6949. else
  6950. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  6951. spin_unlock_bh(&tp->lock);
  6952. return 0;
  6953. }
  6954. static u32 tg3_get_msglevel(struct net_device *dev)
  6955. {
  6956. struct tg3 *tp = netdev_priv(dev);
  6957. return tp->msg_enable;
  6958. }
  6959. static void tg3_set_msglevel(struct net_device *dev, u32 value)
  6960. {
  6961. struct tg3 *tp = netdev_priv(dev);
  6962. tp->msg_enable = value;
  6963. }
  6964. static int tg3_set_tso(struct net_device *dev, u32 value)
  6965. {
  6966. struct tg3 *tp = netdev_priv(dev);
  6967. if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
  6968. if (value)
  6969. return -EINVAL;
  6970. return 0;
  6971. }
  6972. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  6973. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
  6974. if (value)
  6975. dev->features |= NETIF_F_TSO6;
  6976. else
  6977. dev->features &= ~NETIF_F_TSO6;
  6978. }
  6979. return ethtool_op_set_tso(dev, value);
  6980. }
  6981. static int tg3_nway_reset(struct net_device *dev)
  6982. {
  6983. struct tg3 *tp = netdev_priv(dev);
  6984. u32 bmcr;
  6985. int r;
  6986. if (!netif_running(dev))
  6987. return -EAGAIN;
  6988. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  6989. return -EINVAL;
  6990. spin_lock_bh(&tp->lock);
  6991. r = -EINVAL;
  6992. tg3_readphy(tp, MII_BMCR, &bmcr);
  6993. if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
  6994. ((bmcr & BMCR_ANENABLE) ||
  6995. (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
  6996. tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
  6997. BMCR_ANENABLE);
  6998. r = 0;
  6999. }
  7000. spin_unlock_bh(&tp->lock);
  7001. return r;
  7002. }
  7003. static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  7004. {
  7005. struct tg3 *tp = netdev_priv(dev);
  7006. ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
  7007. ering->rx_mini_max_pending = 0;
  7008. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  7009. ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
  7010. else
  7011. ering->rx_jumbo_max_pending = 0;
  7012. ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
  7013. ering->rx_pending = tp->rx_pending;
  7014. ering->rx_mini_pending = 0;
  7015. if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
  7016. ering->rx_jumbo_pending = tp->rx_jumbo_pending;
  7017. else
  7018. ering->rx_jumbo_pending = 0;
  7019. ering->tx_pending = tp->tx_pending;
  7020. }
  7021. static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  7022. {
  7023. struct tg3 *tp = netdev_priv(dev);
  7024. int irq_sync = 0, err = 0;
  7025. if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
  7026. (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
  7027. (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
  7028. (ering->tx_pending <= MAX_SKB_FRAGS) ||
  7029. ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
  7030. (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
  7031. return -EINVAL;
  7032. if (netif_running(dev)) {
  7033. tg3_netif_stop(tp);
  7034. irq_sync = 1;
  7035. }
  7036. tg3_full_lock(tp, irq_sync);
  7037. tp->rx_pending = ering->rx_pending;
  7038. if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
  7039. tp->rx_pending > 63)
  7040. tp->rx_pending = 63;
  7041. tp->rx_jumbo_pending = ering->rx_jumbo_pending;
  7042. tp->tx_pending = ering->tx_pending;
  7043. if (netif_running(dev)) {
  7044. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7045. err = tg3_restart_hw(tp, 1);
  7046. if (!err)
  7047. tg3_netif_start(tp);
  7048. }
  7049. tg3_full_unlock(tp);
  7050. return err;
  7051. }
  7052. static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7053. {
  7054. struct tg3 *tp = netdev_priv(dev);
  7055. epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
  7056. epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
  7057. epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
  7058. }
  7059. static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
  7060. {
  7061. struct tg3 *tp = netdev_priv(dev);
  7062. int irq_sync = 0, err = 0;
  7063. if (netif_running(dev)) {
  7064. tg3_netif_stop(tp);
  7065. irq_sync = 1;
  7066. }
  7067. tg3_full_lock(tp, irq_sync);
  7068. if (epause->autoneg)
  7069. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  7070. else
  7071. tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
  7072. if (epause->rx_pause)
  7073. tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
  7074. else
  7075. tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
  7076. if (epause->tx_pause)
  7077. tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
  7078. else
  7079. tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
  7080. if (netif_running(dev)) {
  7081. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7082. err = tg3_restart_hw(tp, 1);
  7083. if (!err)
  7084. tg3_netif_start(tp);
  7085. }
  7086. tg3_full_unlock(tp);
  7087. return err;
  7088. }
  7089. static u32 tg3_get_rx_csum(struct net_device *dev)
  7090. {
  7091. struct tg3 *tp = netdev_priv(dev);
  7092. return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
  7093. }
  7094. static int tg3_set_rx_csum(struct net_device *dev, u32 data)
  7095. {
  7096. struct tg3 *tp = netdev_priv(dev);
  7097. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7098. if (data != 0)
  7099. return -EINVAL;
  7100. return 0;
  7101. }
  7102. spin_lock_bh(&tp->lock);
  7103. if (data)
  7104. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  7105. else
  7106. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  7107. spin_unlock_bh(&tp->lock);
  7108. return 0;
  7109. }
  7110. static int tg3_set_tx_csum(struct net_device *dev, u32 data)
  7111. {
  7112. struct tg3 *tp = netdev_priv(dev);
  7113. if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
  7114. if (data != 0)
  7115. return -EINVAL;
  7116. return 0;
  7117. }
  7118. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7119. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  7120. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  7121. ethtool_op_set_tx_ipv6_csum(dev, data);
  7122. else
  7123. ethtool_op_set_tx_csum(dev, data);
  7124. return 0;
  7125. }
  7126. static int tg3_get_sset_count (struct net_device *dev, int sset)
  7127. {
  7128. switch (sset) {
  7129. case ETH_SS_TEST:
  7130. return TG3_NUM_TEST;
  7131. case ETH_SS_STATS:
  7132. return TG3_NUM_STATS;
  7133. default:
  7134. return -EOPNOTSUPP;
  7135. }
  7136. }
  7137. static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
  7138. {
  7139. switch (stringset) {
  7140. case ETH_SS_STATS:
  7141. memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
  7142. break;
  7143. case ETH_SS_TEST:
  7144. memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
  7145. break;
  7146. default:
  7147. WARN_ON(1); /* we need a WARN() */
  7148. break;
  7149. }
  7150. }
  7151. static int tg3_phys_id(struct net_device *dev, u32 data)
  7152. {
  7153. struct tg3 *tp = netdev_priv(dev);
  7154. int i;
  7155. if (!netif_running(tp->dev))
  7156. return -EAGAIN;
  7157. if (data == 0)
  7158. data = 2;
  7159. for (i = 0; i < (data * 2); i++) {
  7160. if ((i % 2) == 0)
  7161. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7162. LED_CTRL_1000MBPS_ON |
  7163. LED_CTRL_100MBPS_ON |
  7164. LED_CTRL_10MBPS_ON |
  7165. LED_CTRL_TRAFFIC_OVERRIDE |
  7166. LED_CTRL_TRAFFIC_BLINK |
  7167. LED_CTRL_TRAFFIC_LED);
  7168. else
  7169. tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
  7170. LED_CTRL_TRAFFIC_OVERRIDE);
  7171. if (msleep_interruptible(500))
  7172. break;
  7173. }
  7174. tw32(MAC_LED_CTRL, tp->led_ctrl);
  7175. return 0;
  7176. }
  7177. static void tg3_get_ethtool_stats (struct net_device *dev,
  7178. struct ethtool_stats *estats, u64 *tmp_stats)
  7179. {
  7180. struct tg3 *tp = netdev_priv(dev);
  7181. memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
  7182. }
  7183. #define NVRAM_TEST_SIZE 0x100
  7184. #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
  7185. #define NVRAM_SELFBOOT_HW_SIZE 0x20
  7186. #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
  7187. static int tg3_test_nvram(struct tg3 *tp)
  7188. {
  7189. u32 *buf, csum, magic;
  7190. int i, j, k, err = 0, size;
  7191. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7192. return -EIO;
  7193. if (magic == TG3_EEPROM_MAGIC)
  7194. size = NVRAM_TEST_SIZE;
  7195. else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
  7196. if ((magic & 0xe00000) == 0x200000)
  7197. size = NVRAM_SELFBOOT_FORMAT1_SIZE;
  7198. else
  7199. return 0;
  7200. } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
  7201. size = NVRAM_SELFBOOT_HW_SIZE;
  7202. else
  7203. return -EIO;
  7204. buf = kmalloc(size, GFP_KERNEL);
  7205. if (buf == NULL)
  7206. return -ENOMEM;
  7207. err = -EIO;
  7208. for (i = 0, j = 0; i < size; i += 4, j++) {
  7209. u32 val;
  7210. if ((err = tg3_nvram_read(tp, i, &val)) != 0)
  7211. break;
  7212. buf[j] = cpu_to_le32(val);
  7213. }
  7214. if (i < size)
  7215. goto out;
  7216. /* Selfboot format */
  7217. if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
  7218. TG3_EEPROM_MAGIC_FW) {
  7219. u8 *buf8 = (u8 *) buf, csum8 = 0;
  7220. for (i = 0; i < size; i++)
  7221. csum8 += buf8[i];
  7222. if (csum8 == 0) {
  7223. err = 0;
  7224. goto out;
  7225. }
  7226. err = -EIO;
  7227. goto out;
  7228. }
  7229. if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
  7230. TG3_EEPROM_MAGIC_HW) {
  7231. u8 data[NVRAM_SELFBOOT_DATA_SIZE];
  7232. u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
  7233. u8 *buf8 = (u8 *) buf;
  7234. /* Separate the parity bits and the data bytes. */
  7235. for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
  7236. if ((i == 0) || (i == 8)) {
  7237. int l;
  7238. u8 msk;
  7239. for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
  7240. parity[k++] = buf8[i] & msk;
  7241. i++;
  7242. }
  7243. else if (i == 16) {
  7244. int l;
  7245. u8 msk;
  7246. for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
  7247. parity[k++] = buf8[i] & msk;
  7248. i++;
  7249. for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
  7250. parity[k++] = buf8[i] & msk;
  7251. i++;
  7252. }
  7253. data[j++] = buf8[i];
  7254. }
  7255. err = -EIO;
  7256. for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
  7257. u8 hw8 = hweight8(data[i]);
  7258. if ((hw8 & 0x1) && parity[i])
  7259. goto out;
  7260. else if (!(hw8 & 0x1) && !parity[i])
  7261. goto out;
  7262. }
  7263. err = 0;
  7264. goto out;
  7265. }
  7266. /* Bootstrap checksum at offset 0x10 */
  7267. csum = calc_crc((unsigned char *) buf, 0x10);
  7268. if(csum != cpu_to_le32(buf[0x10/4]))
  7269. goto out;
  7270. /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
  7271. csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
  7272. if (csum != cpu_to_le32(buf[0xfc/4]))
  7273. goto out;
  7274. err = 0;
  7275. out:
  7276. kfree(buf);
  7277. return err;
  7278. }
  7279. #define TG3_SERDES_TIMEOUT_SEC 2
  7280. #define TG3_COPPER_TIMEOUT_SEC 6
  7281. static int tg3_test_link(struct tg3 *tp)
  7282. {
  7283. int i, max;
  7284. if (!netif_running(tp->dev))
  7285. return -ENODEV;
  7286. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  7287. max = TG3_SERDES_TIMEOUT_SEC;
  7288. else
  7289. max = TG3_COPPER_TIMEOUT_SEC;
  7290. for (i = 0; i < max; i++) {
  7291. if (netif_carrier_ok(tp->dev))
  7292. return 0;
  7293. if (msleep_interruptible(1000))
  7294. break;
  7295. }
  7296. return -EIO;
  7297. }
  7298. /* Only test the commonly used registers */
  7299. static int tg3_test_registers(struct tg3 *tp)
  7300. {
  7301. int i, is_5705, is_5750;
  7302. u32 offset, read_mask, write_mask, val, save_val, read_val;
  7303. static struct {
  7304. u16 offset;
  7305. u16 flags;
  7306. #define TG3_FL_5705 0x1
  7307. #define TG3_FL_NOT_5705 0x2
  7308. #define TG3_FL_NOT_5788 0x4
  7309. #define TG3_FL_NOT_5750 0x8
  7310. u32 read_mask;
  7311. u32 write_mask;
  7312. } reg_tbl[] = {
  7313. /* MAC Control Registers */
  7314. { MAC_MODE, TG3_FL_NOT_5705,
  7315. 0x00000000, 0x00ef6f8c },
  7316. { MAC_MODE, TG3_FL_5705,
  7317. 0x00000000, 0x01ef6b8c },
  7318. { MAC_STATUS, TG3_FL_NOT_5705,
  7319. 0x03800107, 0x00000000 },
  7320. { MAC_STATUS, TG3_FL_5705,
  7321. 0x03800100, 0x00000000 },
  7322. { MAC_ADDR_0_HIGH, 0x0000,
  7323. 0x00000000, 0x0000ffff },
  7324. { MAC_ADDR_0_LOW, 0x0000,
  7325. 0x00000000, 0xffffffff },
  7326. { MAC_RX_MTU_SIZE, 0x0000,
  7327. 0x00000000, 0x0000ffff },
  7328. { MAC_TX_MODE, 0x0000,
  7329. 0x00000000, 0x00000070 },
  7330. { MAC_TX_LENGTHS, 0x0000,
  7331. 0x00000000, 0x00003fff },
  7332. { MAC_RX_MODE, TG3_FL_NOT_5705,
  7333. 0x00000000, 0x000007fc },
  7334. { MAC_RX_MODE, TG3_FL_5705,
  7335. 0x00000000, 0x000007dc },
  7336. { MAC_HASH_REG_0, 0x0000,
  7337. 0x00000000, 0xffffffff },
  7338. { MAC_HASH_REG_1, 0x0000,
  7339. 0x00000000, 0xffffffff },
  7340. { MAC_HASH_REG_2, 0x0000,
  7341. 0x00000000, 0xffffffff },
  7342. { MAC_HASH_REG_3, 0x0000,
  7343. 0x00000000, 0xffffffff },
  7344. /* Receive Data and Receive BD Initiator Control Registers. */
  7345. { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
  7346. 0x00000000, 0xffffffff },
  7347. { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
  7348. 0x00000000, 0xffffffff },
  7349. { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
  7350. 0x00000000, 0x00000003 },
  7351. { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
  7352. 0x00000000, 0xffffffff },
  7353. { RCVDBDI_STD_BD+0, 0x0000,
  7354. 0x00000000, 0xffffffff },
  7355. { RCVDBDI_STD_BD+4, 0x0000,
  7356. 0x00000000, 0xffffffff },
  7357. { RCVDBDI_STD_BD+8, 0x0000,
  7358. 0x00000000, 0xffff0002 },
  7359. { RCVDBDI_STD_BD+0xc, 0x0000,
  7360. 0x00000000, 0xffffffff },
  7361. /* Receive BD Initiator Control Registers. */
  7362. { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
  7363. 0x00000000, 0xffffffff },
  7364. { RCVBDI_STD_THRESH, TG3_FL_5705,
  7365. 0x00000000, 0x000003ff },
  7366. { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
  7367. 0x00000000, 0xffffffff },
  7368. /* Host Coalescing Control Registers. */
  7369. { HOSTCC_MODE, TG3_FL_NOT_5705,
  7370. 0x00000000, 0x00000004 },
  7371. { HOSTCC_MODE, TG3_FL_5705,
  7372. 0x00000000, 0x000000f6 },
  7373. { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
  7374. 0x00000000, 0xffffffff },
  7375. { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
  7376. 0x00000000, 0x000003ff },
  7377. { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
  7378. 0x00000000, 0xffffffff },
  7379. { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
  7380. 0x00000000, 0x000003ff },
  7381. { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
  7382. 0x00000000, 0xffffffff },
  7383. { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7384. 0x00000000, 0x000000ff },
  7385. { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
  7386. 0x00000000, 0xffffffff },
  7387. { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
  7388. 0x00000000, 0x000000ff },
  7389. { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7390. 0x00000000, 0xffffffff },
  7391. { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
  7392. 0x00000000, 0xffffffff },
  7393. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7394. 0x00000000, 0xffffffff },
  7395. { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7396. 0x00000000, 0x000000ff },
  7397. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
  7398. 0x00000000, 0xffffffff },
  7399. { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
  7400. 0x00000000, 0x000000ff },
  7401. { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
  7402. 0x00000000, 0xffffffff },
  7403. { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
  7404. 0x00000000, 0xffffffff },
  7405. { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
  7406. 0x00000000, 0xffffffff },
  7407. { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
  7408. 0x00000000, 0xffffffff },
  7409. { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
  7410. 0x00000000, 0xffffffff },
  7411. { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
  7412. 0xffffffff, 0x00000000 },
  7413. { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
  7414. 0xffffffff, 0x00000000 },
  7415. /* Buffer Manager Control Registers. */
  7416. { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
  7417. 0x00000000, 0x007fff80 },
  7418. { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
  7419. 0x00000000, 0x007fffff },
  7420. { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
  7421. 0x00000000, 0x0000003f },
  7422. { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
  7423. 0x00000000, 0x000001ff },
  7424. { BUFMGR_MB_HIGH_WATER, 0x0000,
  7425. 0x00000000, 0x000001ff },
  7426. { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
  7427. 0xffffffff, 0x00000000 },
  7428. { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
  7429. 0xffffffff, 0x00000000 },
  7430. /* Mailbox Registers */
  7431. { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
  7432. 0x00000000, 0x000001ff },
  7433. { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
  7434. 0x00000000, 0x000001ff },
  7435. { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
  7436. 0x00000000, 0x000007ff },
  7437. { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
  7438. 0x00000000, 0x000001ff },
  7439. { 0xffff, 0x0000, 0x00000000, 0x00000000 },
  7440. };
  7441. is_5705 = is_5750 = 0;
  7442. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7443. is_5705 = 1;
  7444. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  7445. is_5750 = 1;
  7446. }
  7447. for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
  7448. if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
  7449. continue;
  7450. if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
  7451. continue;
  7452. if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  7453. (reg_tbl[i].flags & TG3_FL_NOT_5788))
  7454. continue;
  7455. if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
  7456. continue;
  7457. offset = (u32) reg_tbl[i].offset;
  7458. read_mask = reg_tbl[i].read_mask;
  7459. write_mask = reg_tbl[i].write_mask;
  7460. /* Save the original register content */
  7461. save_val = tr32(offset);
  7462. /* Determine the read-only value. */
  7463. read_val = save_val & read_mask;
  7464. /* Write zero to the register, then make sure the read-only bits
  7465. * are not changed and the read/write bits are all zeros.
  7466. */
  7467. tw32(offset, 0);
  7468. val = tr32(offset);
  7469. /* Test the read-only and read/write bits. */
  7470. if (((val & read_mask) != read_val) || (val & write_mask))
  7471. goto out;
  7472. /* Write ones to all the bits defined by RdMask and WrMask, then
  7473. * make sure the read-only bits are not changed and the
  7474. * read/write bits are all ones.
  7475. */
  7476. tw32(offset, read_mask | write_mask);
  7477. val = tr32(offset);
  7478. /* Test the read-only bits. */
  7479. if ((val & read_mask) != read_val)
  7480. goto out;
  7481. /* Test the read/write bits. */
  7482. if ((val & write_mask) != write_mask)
  7483. goto out;
  7484. tw32(offset, save_val);
  7485. }
  7486. return 0;
  7487. out:
  7488. if (netif_msg_hw(tp))
  7489. printk(KERN_ERR PFX "Register test failed at offset %x\n",
  7490. offset);
  7491. tw32(offset, save_val);
  7492. return -EIO;
  7493. }
  7494. static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
  7495. {
  7496. static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
  7497. int i;
  7498. u32 j;
  7499. for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
  7500. for (j = 0; j < len; j += 4) {
  7501. u32 val;
  7502. tg3_write_mem(tp, offset + j, test_pattern[i]);
  7503. tg3_read_mem(tp, offset + j, &val);
  7504. if (val != test_pattern[i])
  7505. return -EIO;
  7506. }
  7507. }
  7508. return 0;
  7509. }
  7510. static int tg3_test_memory(struct tg3 *tp)
  7511. {
  7512. static struct mem_entry {
  7513. u32 offset;
  7514. u32 len;
  7515. } mem_tbl_570x[] = {
  7516. { 0x00000000, 0x00b50},
  7517. { 0x00002000, 0x1c000},
  7518. { 0xffffffff, 0x00000}
  7519. }, mem_tbl_5705[] = {
  7520. { 0x00000100, 0x0000c},
  7521. { 0x00000200, 0x00008},
  7522. { 0x00004000, 0x00800},
  7523. { 0x00006000, 0x01000},
  7524. { 0x00008000, 0x02000},
  7525. { 0x00010000, 0x0e000},
  7526. { 0xffffffff, 0x00000}
  7527. }, mem_tbl_5755[] = {
  7528. { 0x00000200, 0x00008},
  7529. { 0x00004000, 0x00800},
  7530. { 0x00006000, 0x00800},
  7531. { 0x00008000, 0x02000},
  7532. { 0x00010000, 0x0c000},
  7533. { 0xffffffff, 0x00000}
  7534. }, mem_tbl_5906[] = {
  7535. { 0x00000200, 0x00008},
  7536. { 0x00004000, 0x00400},
  7537. { 0x00006000, 0x00400},
  7538. { 0x00008000, 0x01000},
  7539. { 0x00010000, 0x01000},
  7540. { 0xffffffff, 0x00000}
  7541. };
  7542. struct mem_entry *mem_tbl;
  7543. int err = 0;
  7544. int i;
  7545. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  7546. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  7547. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  7548. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  7549. mem_tbl = mem_tbl_5755;
  7550. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  7551. mem_tbl = mem_tbl_5906;
  7552. else
  7553. mem_tbl = mem_tbl_5705;
  7554. } else
  7555. mem_tbl = mem_tbl_570x;
  7556. for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
  7557. if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
  7558. mem_tbl[i].len)) != 0)
  7559. break;
  7560. }
  7561. return err;
  7562. }
  7563. #define TG3_MAC_LOOPBACK 0
  7564. #define TG3_PHY_LOOPBACK 1
  7565. static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
  7566. {
  7567. u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
  7568. u32 desc_idx;
  7569. struct sk_buff *skb, *rx_skb;
  7570. u8 *tx_data;
  7571. dma_addr_t map;
  7572. int num_pkts, tx_len, rx_len, i, err;
  7573. struct tg3_rx_buffer_desc *desc;
  7574. if (loopback_mode == TG3_MAC_LOOPBACK) {
  7575. /* HW errata - mac loopback fails in some cases on 5780.
  7576. * Normal traffic and PHY loopback are not affected by
  7577. * errata.
  7578. */
  7579. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
  7580. return 0;
  7581. mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
  7582. MAC_MODE_PORT_INT_LPBACK;
  7583. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  7584. mac_mode |= MAC_MODE_LINK_POLARITY;
  7585. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  7586. mac_mode |= MAC_MODE_PORT_MODE_MII;
  7587. else
  7588. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  7589. tw32(MAC_MODE, mac_mode);
  7590. } else if (loopback_mode == TG3_PHY_LOOPBACK) {
  7591. u32 val;
  7592. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  7593. u32 phytest;
  7594. if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
  7595. u32 phy;
  7596. tg3_writephy(tp, MII_TG3_EPHY_TEST,
  7597. phytest | MII_TG3_EPHY_SHADOW_EN);
  7598. if (!tg3_readphy(tp, 0x1b, &phy))
  7599. tg3_writephy(tp, 0x1b, phy & ~0x20);
  7600. tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
  7601. }
  7602. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
  7603. } else
  7604. val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
  7605. tg3_phy_toggle_automdix(tp, 0);
  7606. tg3_writephy(tp, MII_BMCR, val);
  7607. udelay(40);
  7608. mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
  7609. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  7610. tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
  7611. mac_mode |= MAC_MODE_PORT_MODE_MII;
  7612. } else
  7613. mac_mode |= MAC_MODE_PORT_MODE_GMII;
  7614. /* reset to prevent losing 1st rx packet intermittently */
  7615. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
  7616. tw32_f(MAC_RX_MODE, RX_MODE_RESET);
  7617. udelay(10);
  7618. tw32_f(MAC_RX_MODE, tp->rx_mode);
  7619. }
  7620. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
  7621. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
  7622. mac_mode &= ~MAC_MODE_LINK_POLARITY;
  7623. else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
  7624. mac_mode |= MAC_MODE_LINK_POLARITY;
  7625. tg3_writephy(tp, MII_TG3_EXT_CTRL,
  7626. MII_TG3_EXT_CTRL_LNK3_LED_MODE);
  7627. }
  7628. tw32(MAC_MODE, mac_mode);
  7629. }
  7630. else
  7631. return -EINVAL;
  7632. err = -EIO;
  7633. tx_len = 1514;
  7634. skb = netdev_alloc_skb(tp->dev, tx_len);
  7635. if (!skb)
  7636. return -ENOMEM;
  7637. tx_data = skb_put(skb, tx_len);
  7638. memcpy(tx_data, tp->dev->dev_addr, 6);
  7639. memset(tx_data + 6, 0x0, 8);
  7640. tw32(MAC_RX_MTU_SIZE, tx_len + 4);
  7641. for (i = 14; i < tx_len; i++)
  7642. tx_data[i] = (u8) (i & 0xff);
  7643. map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
  7644. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7645. HOSTCC_MODE_NOW);
  7646. udelay(10);
  7647. rx_start_idx = tp->hw_status->idx[0].rx_producer;
  7648. num_pkts = 0;
  7649. tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
  7650. tp->tx_prod++;
  7651. num_pkts++;
  7652. tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
  7653. tp->tx_prod);
  7654. tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
  7655. udelay(10);
  7656. /* 250 usec to allow enough time on some 10/100 Mbps devices. */
  7657. for (i = 0; i < 25; i++) {
  7658. tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
  7659. HOSTCC_MODE_NOW);
  7660. udelay(10);
  7661. tx_idx = tp->hw_status->idx[0].tx_consumer;
  7662. rx_idx = tp->hw_status->idx[0].rx_producer;
  7663. if ((tx_idx == tp->tx_prod) &&
  7664. (rx_idx == (rx_start_idx + num_pkts)))
  7665. break;
  7666. }
  7667. pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
  7668. dev_kfree_skb(skb);
  7669. if (tx_idx != tp->tx_prod)
  7670. goto out;
  7671. if (rx_idx != rx_start_idx + num_pkts)
  7672. goto out;
  7673. desc = &tp->rx_rcb[rx_start_idx];
  7674. desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
  7675. opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
  7676. if (opaque_key != RXD_OPAQUE_RING_STD)
  7677. goto out;
  7678. if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
  7679. (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
  7680. goto out;
  7681. rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
  7682. if (rx_len != tx_len)
  7683. goto out;
  7684. rx_skb = tp->rx_std_buffers[desc_idx].skb;
  7685. map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
  7686. pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
  7687. for (i = 14; i < tx_len; i++) {
  7688. if (*(rx_skb->data + i) != (u8) (i & 0xff))
  7689. goto out;
  7690. }
  7691. err = 0;
  7692. /* tg3_free_rings will unmap and free the rx_skb */
  7693. out:
  7694. return err;
  7695. }
  7696. #define TG3_MAC_LOOPBACK_FAILED 1
  7697. #define TG3_PHY_LOOPBACK_FAILED 2
  7698. #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
  7699. TG3_PHY_LOOPBACK_FAILED)
  7700. static int tg3_test_loopback(struct tg3 *tp)
  7701. {
  7702. int err = 0;
  7703. if (!netif_running(tp->dev))
  7704. return TG3_LOOPBACK_FAILED;
  7705. err = tg3_reset_hw(tp, 1);
  7706. if (err)
  7707. return TG3_LOOPBACK_FAILED;
  7708. if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
  7709. err |= TG3_MAC_LOOPBACK_FAILED;
  7710. if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  7711. if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
  7712. err |= TG3_PHY_LOOPBACK_FAILED;
  7713. }
  7714. return err;
  7715. }
  7716. static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
  7717. u64 *data)
  7718. {
  7719. struct tg3 *tp = netdev_priv(dev);
  7720. if (tp->link_config.phy_is_low_power)
  7721. tg3_set_power_state(tp, PCI_D0);
  7722. memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
  7723. if (tg3_test_nvram(tp) != 0) {
  7724. etest->flags |= ETH_TEST_FL_FAILED;
  7725. data[0] = 1;
  7726. }
  7727. if (tg3_test_link(tp) != 0) {
  7728. etest->flags |= ETH_TEST_FL_FAILED;
  7729. data[1] = 1;
  7730. }
  7731. if (etest->flags & ETH_TEST_FL_OFFLINE) {
  7732. int err, irq_sync = 0;
  7733. if (netif_running(dev)) {
  7734. tg3_netif_stop(tp);
  7735. irq_sync = 1;
  7736. }
  7737. tg3_full_lock(tp, irq_sync);
  7738. tg3_halt(tp, RESET_KIND_SUSPEND, 1);
  7739. err = tg3_nvram_lock(tp);
  7740. tg3_halt_cpu(tp, RX_CPU_BASE);
  7741. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
  7742. tg3_halt_cpu(tp, TX_CPU_BASE);
  7743. if (!err)
  7744. tg3_nvram_unlock(tp);
  7745. if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
  7746. tg3_phy_reset(tp);
  7747. if (tg3_test_registers(tp) != 0) {
  7748. etest->flags |= ETH_TEST_FL_FAILED;
  7749. data[2] = 1;
  7750. }
  7751. if (tg3_test_memory(tp) != 0) {
  7752. etest->flags |= ETH_TEST_FL_FAILED;
  7753. data[3] = 1;
  7754. }
  7755. if ((data[4] = tg3_test_loopback(tp)) != 0)
  7756. etest->flags |= ETH_TEST_FL_FAILED;
  7757. tg3_full_unlock(tp);
  7758. if (tg3_test_interrupt(tp) != 0) {
  7759. etest->flags |= ETH_TEST_FL_FAILED;
  7760. data[5] = 1;
  7761. }
  7762. tg3_full_lock(tp, 0);
  7763. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  7764. if (netif_running(dev)) {
  7765. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  7766. if (!tg3_restart_hw(tp, 1))
  7767. tg3_netif_start(tp);
  7768. }
  7769. tg3_full_unlock(tp);
  7770. }
  7771. if (tp->link_config.phy_is_low_power)
  7772. tg3_set_power_state(tp, PCI_D3hot);
  7773. }
  7774. static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  7775. {
  7776. struct mii_ioctl_data *data = if_mii(ifr);
  7777. struct tg3 *tp = netdev_priv(dev);
  7778. int err;
  7779. switch(cmd) {
  7780. case SIOCGMIIPHY:
  7781. data->phy_id = PHY_ADDR;
  7782. /* fallthru */
  7783. case SIOCGMIIREG: {
  7784. u32 mii_regval;
  7785. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7786. break; /* We have no PHY */
  7787. if (tp->link_config.phy_is_low_power)
  7788. return -EAGAIN;
  7789. spin_lock_bh(&tp->lock);
  7790. err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
  7791. spin_unlock_bh(&tp->lock);
  7792. data->val_out = mii_regval;
  7793. return err;
  7794. }
  7795. case SIOCSMIIREG:
  7796. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  7797. break; /* We have no PHY */
  7798. if (!capable(CAP_NET_ADMIN))
  7799. return -EPERM;
  7800. if (tp->link_config.phy_is_low_power)
  7801. return -EAGAIN;
  7802. spin_lock_bh(&tp->lock);
  7803. err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
  7804. spin_unlock_bh(&tp->lock);
  7805. return err;
  7806. default:
  7807. /* do nothing */
  7808. break;
  7809. }
  7810. return -EOPNOTSUPP;
  7811. }
  7812. #if TG3_VLAN_TAG_USED
  7813. static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  7814. {
  7815. struct tg3 *tp = netdev_priv(dev);
  7816. if (netif_running(dev))
  7817. tg3_netif_stop(tp);
  7818. tg3_full_lock(tp, 0);
  7819. tp->vlgrp = grp;
  7820. /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
  7821. __tg3_set_rx_mode(dev);
  7822. if (netif_running(dev))
  7823. tg3_netif_start(tp);
  7824. tg3_full_unlock(tp);
  7825. }
  7826. #endif
  7827. static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  7828. {
  7829. struct tg3 *tp = netdev_priv(dev);
  7830. memcpy(ec, &tp->coal, sizeof(*ec));
  7831. return 0;
  7832. }
  7833. static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
  7834. {
  7835. struct tg3 *tp = netdev_priv(dev);
  7836. u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
  7837. u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
  7838. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
  7839. max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
  7840. max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
  7841. max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
  7842. min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
  7843. }
  7844. if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
  7845. (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
  7846. (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
  7847. (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
  7848. (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
  7849. (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
  7850. (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
  7851. (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
  7852. (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
  7853. (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
  7854. return -EINVAL;
  7855. /* No rx interrupts will be generated if both are zero */
  7856. if ((ec->rx_coalesce_usecs == 0) &&
  7857. (ec->rx_max_coalesced_frames == 0))
  7858. return -EINVAL;
  7859. /* No tx interrupts will be generated if both are zero */
  7860. if ((ec->tx_coalesce_usecs == 0) &&
  7861. (ec->tx_max_coalesced_frames == 0))
  7862. return -EINVAL;
  7863. /* Only copy relevant parameters, ignore all others. */
  7864. tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
  7865. tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
  7866. tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
  7867. tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
  7868. tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
  7869. tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
  7870. tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
  7871. tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
  7872. tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
  7873. if (netif_running(dev)) {
  7874. tg3_full_lock(tp, 0);
  7875. __tg3_set_coalesce(tp, &tp->coal);
  7876. tg3_full_unlock(tp);
  7877. }
  7878. return 0;
  7879. }
  7880. static const struct ethtool_ops tg3_ethtool_ops = {
  7881. .get_settings = tg3_get_settings,
  7882. .set_settings = tg3_set_settings,
  7883. .get_drvinfo = tg3_get_drvinfo,
  7884. .get_regs_len = tg3_get_regs_len,
  7885. .get_regs = tg3_get_regs,
  7886. .get_wol = tg3_get_wol,
  7887. .set_wol = tg3_set_wol,
  7888. .get_msglevel = tg3_get_msglevel,
  7889. .set_msglevel = tg3_set_msglevel,
  7890. .nway_reset = tg3_nway_reset,
  7891. .get_link = ethtool_op_get_link,
  7892. .get_eeprom_len = tg3_get_eeprom_len,
  7893. .get_eeprom = tg3_get_eeprom,
  7894. .set_eeprom = tg3_set_eeprom,
  7895. .get_ringparam = tg3_get_ringparam,
  7896. .set_ringparam = tg3_set_ringparam,
  7897. .get_pauseparam = tg3_get_pauseparam,
  7898. .set_pauseparam = tg3_set_pauseparam,
  7899. .get_rx_csum = tg3_get_rx_csum,
  7900. .set_rx_csum = tg3_set_rx_csum,
  7901. .set_tx_csum = tg3_set_tx_csum,
  7902. .set_sg = ethtool_op_set_sg,
  7903. .set_tso = tg3_set_tso,
  7904. .self_test = tg3_self_test,
  7905. .get_strings = tg3_get_strings,
  7906. .phys_id = tg3_phys_id,
  7907. .get_ethtool_stats = tg3_get_ethtool_stats,
  7908. .get_coalesce = tg3_get_coalesce,
  7909. .set_coalesce = tg3_set_coalesce,
  7910. .get_sset_count = tg3_get_sset_count,
  7911. };
  7912. static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
  7913. {
  7914. u32 cursize, val, magic;
  7915. tp->nvram_size = EEPROM_CHIP_SIZE;
  7916. if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
  7917. return;
  7918. if ((magic != TG3_EEPROM_MAGIC) &&
  7919. ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
  7920. ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
  7921. return;
  7922. /*
  7923. * Size the chip by reading offsets at increasing powers of two.
  7924. * When we encounter our validation signature, we know the addressing
  7925. * has wrapped around, and thus have our chip size.
  7926. */
  7927. cursize = 0x10;
  7928. while (cursize < tp->nvram_size) {
  7929. if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
  7930. return;
  7931. if (val == magic)
  7932. break;
  7933. cursize <<= 1;
  7934. }
  7935. tp->nvram_size = cursize;
  7936. }
  7937. static void __devinit tg3_get_nvram_size(struct tg3 *tp)
  7938. {
  7939. u32 val;
  7940. if (tg3_nvram_read_swab(tp, 0, &val) != 0)
  7941. return;
  7942. /* Selfboot format */
  7943. if (val != TG3_EEPROM_MAGIC) {
  7944. tg3_get_eeprom_size(tp);
  7945. return;
  7946. }
  7947. if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
  7948. if (val != 0) {
  7949. tp->nvram_size = (val >> 16) * 1024;
  7950. return;
  7951. }
  7952. }
  7953. tp->nvram_size = 0x80000;
  7954. }
  7955. static void __devinit tg3_get_nvram_info(struct tg3 *tp)
  7956. {
  7957. u32 nvcfg1;
  7958. nvcfg1 = tr32(NVRAM_CFG1);
  7959. if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
  7960. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  7961. }
  7962. else {
  7963. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  7964. tw32(NVRAM_CFG1, nvcfg1);
  7965. }
  7966. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
  7967. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  7968. switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
  7969. case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
  7970. tp->nvram_jedecnum = JEDEC_ATMEL;
  7971. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  7972. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7973. break;
  7974. case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
  7975. tp->nvram_jedecnum = JEDEC_ATMEL;
  7976. tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
  7977. break;
  7978. case FLASH_VENDOR_ATMEL_EEPROM:
  7979. tp->nvram_jedecnum = JEDEC_ATMEL;
  7980. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  7981. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7982. break;
  7983. case FLASH_VENDOR_ST:
  7984. tp->nvram_jedecnum = JEDEC_ST;
  7985. tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
  7986. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  7987. break;
  7988. case FLASH_VENDOR_SAIFUN:
  7989. tp->nvram_jedecnum = JEDEC_SAIFUN;
  7990. tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
  7991. break;
  7992. case FLASH_VENDOR_SST_SMALL:
  7993. case FLASH_VENDOR_SST_LARGE:
  7994. tp->nvram_jedecnum = JEDEC_SST;
  7995. tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
  7996. break;
  7997. }
  7998. }
  7999. else {
  8000. tp->nvram_jedecnum = JEDEC_ATMEL;
  8001. tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
  8002. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8003. }
  8004. }
  8005. static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
  8006. {
  8007. u32 nvcfg1;
  8008. nvcfg1 = tr32(NVRAM_CFG1);
  8009. /* NVRAM protection for TPM */
  8010. if (nvcfg1 & (1 << 27))
  8011. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8012. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8013. case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
  8014. case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
  8015. tp->nvram_jedecnum = JEDEC_ATMEL;
  8016. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8017. break;
  8018. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8019. tp->nvram_jedecnum = JEDEC_ATMEL;
  8020. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8021. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8022. break;
  8023. case FLASH_5752VENDOR_ST_M45PE10:
  8024. case FLASH_5752VENDOR_ST_M45PE20:
  8025. case FLASH_5752VENDOR_ST_M45PE40:
  8026. tp->nvram_jedecnum = JEDEC_ST;
  8027. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8028. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8029. break;
  8030. }
  8031. if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
  8032. switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
  8033. case FLASH_5752PAGE_SIZE_256:
  8034. tp->nvram_pagesize = 256;
  8035. break;
  8036. case FLASH_5752PAGE_SIZE_512:
  8037. tp->nvram_pagesize = 512;
  8038. break;
  8039. case FLASH_5752PAGE_SIZE_1K:
  8040. tp->nvram_pagesize = 1024;
  8041. break;
  8042. case FLASH_5752PAGE_SIZE_2K:
  8043. tp->nvram_pagesize = 2048;
  8044. break;
  8045. case FLASH_5752PAGE_SIZE_4K:
  8046. tp->nvram_pagesize = 4096;
  8047. break;
  8048. case FLASH_5752PAGE_SIZE_264:
  8049. tp->nvram_pagesize = 264;
  8050. break;
  8051. }
  8052. }
  8053. else {
  8054. /* For eeprom, set pagesize to maximum eeprom size */
  8055. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8056. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8057. tw32(NVRAM_CFG1, nvcfg1);
  8058. }
  8059. }
  8060. static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
  8061. {
  8062. u32 nvcfg1, protect = 0;
  8063. nvcfg1 = tr32(NVRAM_CFG1);
  8064. /* NVRAM protection for TPM */
  8065. if (nvcfg1 & (1 << 27)) {
  8066. tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
  8067. protect = 1;
  8068. }
  8069. nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
  8070. switch (nvcfg1) {
  8071. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8072. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8073. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8074. case FLASH_5755VENDOR_ATMEL_FLASH_5:
  8075. tp->nvram_jedecnum = JEDEC_ATMEL;
  8076. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8077. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8078. tp->nvram_pagesize = 264;
  8079. if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
  8080. nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
  8081. tp->nvram_size = (protect ? 0x3e200 : 0x80000);
  8082. else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
  8083. tp->nvram_size = (protect ? 0x1f200 : 0x40000);
  8084. else
  8085. tp->nvram_size = (protect ? 0x1f200 : 0x20000);
  8086. break;
  8087. case FLASH_5752VENDOR_ST_M45PE10:
  8088. case FLASH_5752VENDOR_ST_M45PE20:
  8089. case FLASH_5752VENDOR_ST_M45PE40:
  8090. tp->nvram_jedecnum = JEDEC_ST;
  8091. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8092. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8093. tp->nvram_pagesize = 256;
  8094. if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
  8095. tp->nvram_size = (protect ? 0x10000 : 0x20000);
  8096. else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
  8097. tp->nvram_size = (protect ? 0x10000 : 0x40000);
  8098. else
  8099. tp->nvram_size = (protect ? 0x20000 : 0x80000);
  8100. break;
  8101. }
  8102. }
  8103. static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
  8104. {
  8105. u32 nvcfg1;
  8106. nvcfg1 = tr32(NVRAM_CFG1);
  8107. switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
  8108. case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
  8109. case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
  8110. case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
  8111. case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
  8112. tp->nvram_jedecnum = JEDEC_ATMEL;
  8113. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8114. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8115. nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
  8116. tw32(NVRAM_CFG1, nvcfg1);
  8117. break;
  8118. case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
  8119. case FLASH_5755VENDOR_ATMEL_FLASH_1:
  8120. case FLASH_5755VENDOR_ATMEL_FLASH_2:
  8121. case FLASH_5755VENDOR_ATMEL_FLASH_3:
  8122. tp->nvram_jedecnum = JEDEC_ATMEL;
  8123. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8124. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8125. tp->nvram_pagesize = 264;
  8126. break;
  8127. case FLASH_5752VENDOR_ST_M45PE10:
  8128. case FLASH_5752VENDOR_ST_M45PE20:
  8129. case FLASH_5752VENDOR_ST_M45PE40:
  8130. tp->nvram_jedecnum = JEDEC_ST;
  8131. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8132. tp->tg3_flags2 |= TG3_FLG2_FLASH;
  8133. tp->nvram_pagesize = 256;
  8134. break;
  8135. }
  8136. }
  8137. static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
  8138. {
  8139. tp->nvram_jedecnum = JEDEC_ATMEL;
  8140. tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
  8141. tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
  8142. }
  8143. /* Chips other than 5700/5701 use the NVRAM for fetching info. */
  8144. static void __devinit tg3_nvram_init(struct tg3 *tp)
  8145. {
  8146. tw32_f(GRC_EEPROM_ADDR,
  8147. (EEPROM_ADDR_FSM_RESET |
  8148. (EEPROM_DEFAULT_CLOCK_PERIOD <<
  8149. EEPROM_ADDR_CLKPERD_SHIFT)));
  8150. msleep(1);
  8151. /* Enable seeprom accesses. */
  8152. tw32_f(GRC_LOCAL_CTRL,
  8153. tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
  8154. udelay(100);
  8155. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  8156. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
  8157. tp->tg3_flags |= TG3_FLAG_NVRAM;
  8158. if (tg3_nvram_lock(tp)) {
  8159. printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
  8160. "tg3_nvram_init failed.\n", tp->dev->name);
  8161. return;
  8162. }
  8163. tg3_enable_nvram_access(tp);
  8164. tp->nvram_size = 0;
  8165. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  8166. tg3_get_5752_nvram_info(tp);
  8167. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  8168. tg3_get_5755_nvram_info(tp);
  8169. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  8170. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  8171. tg3_get_5787_nvram_info(tp);
  8172. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8173. tg3_get_5906_nvram_info(tp);
  8174. else
  8175. tg3_get_nvram_info(tp);
  8176. if (tp->nvram_size == 0)
  8177. tg3_get_nvram_size(tp);
  8178. tg3_disable_nvram_access(tp);
  8179. tg3_nvram_unlock(tp);
  8180. } else {
  8181. tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
  8182. tg3_get_eeprom_size(tp);
  8183. }
  8184. }
  8185. static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
  8186. u32 offset, u32 *val)
  8187. {
  8188. u32 tmp;
  8189. int i;
  8190. if (offset > EEPROM_ADDR_ADDR_MASK ||
  8191. (offset % 4) != 0)
  8192. return -EINVAL;
  8193. tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
  8194. EEPROM_ADDR_DEVID_MASK |
  8195. EEPROM_ADDR_READ);
  8196. tw32(GRC_EEPROM_ADDR,
  8197. tmp |
  8198. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8199. ((offset << EEPROM_ADDR_ADDR_SHIFT) &
  8200. EEPROM_ADDR_ADDR_MASK) |
  8201. EEPROM_ADDR_READ | EEPROM_ADDR_START);
  8202. for (i = 0; i < 1000; i++) {
  8203. tmp = tr32(GRC_EEPROM_ADDR);
  8204. if (tmp & EEPROM_ADDR_COMPLETE)
  8205. break;
  8206. msleep(1);
  8207. }
  8208. if (!(tmp & EEPROM_ADDR_COMPLETE))
  8209. return -EBUSY;
  8210. *val = tr32(GRC_EEPROM_DATA);
  8211. return 0;
  8212. }
  8213. #define NVRAM_CMD_TIMEOUT 10000
  8214. static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
  8215. {
  8216. int i;
  8217. tw32(NVRAM_CMD, nvram_cmd);
  8218. for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
  8219. udelay(10);
  8220. if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
  8221. udelay(10);
  8222. break;
  8223. }
  8224. }
  8225. if (i == NVRAM_CMD_TIMEOUT) {
  8226. return -EBUSY;
  8227. }
  8228. return 0;
  8229. }
  8230. static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
  8231. {
  8232. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8233. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8234. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8235. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8236. addr = ((addr / tp->nvram_pagesize) <<
  8237. ATMEL_AT45DB0X1B_PAGE_POS) +
  8238. (addr % tp->nvram_pagesize);
  8239. return addr;
  8240. }
  8241. static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
  8242. {
  8243. if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
  8244. (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
  8245. (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
  8246. (tp->nvram_jedecnum == JEDEC_ATMEL))
  8247. addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
  8248. tp->nvram_pagesize) +
  8249. (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
  8250. return addr;
  8251. }
  8252. static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
  8253. {
  8254. int ret;
  8255. if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
  8256. return tg3_nvram_read_using_eeprom(tp, offset, val);
  8257. offset = tg3_nvram_phys_addr(tp, offset);
  8258. if (offset > NVRAM_ADDR_MSK)
  8259. return -EINVAL;
  8260. ret = tg3_nvram_lock(tp);
  8261. if (ret)
  8262. return ret;
  8263. tg3_enable_nvram_access(tp);
  8264. tw32(NVRAM_ADDR, offset);
  8265. ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
  8266. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
  8267. if (ret == 0)
  8268. *val = swab32(tr32(NVRAM_RDDATA));
  8269. tg3_disable_nvram_access(tp);
  8270. tg3_nvram_unlock(tp);
  8271. return ret;
  8272. }
  8273. static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
  8274. {
  8275. int err;
  8276. u32 tmp;
  8277. err = tg3_nvram_read(tp, offset, &tmp);
  8278. *val = swab32(tmp);
  8279. return err;
  8280. }
  8281. static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
  8282. u32 offset, u32 len, u8 *buf)
  8283. {
  8284. int i, j, rc = 0;
  8285. u32 val;
  8286. for (i = 0; i < len; i += 4) {
  8287. u32 addr, data;
  8288. addr = offset + i;
  8289. memcpy(&data, buf + i, 4);
  8290. tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
  8291. val = tr32(GRC_EEPROM_ADDR);
  8292. tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
  8293. val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
  8294. EEPROM_ADDR_READ);
  8295. tw32(GRC_EEPROM_ADDR, val |
  8296. (0 << EEPROM_ADDR_DEVID_SHIFT) |
  8297. (addr & EEPROM_ADDR_ADDR_MASK) |
  8298. EEPROM_ADDR_START |
  8299. EEPROM_ADDR_WRITE);
  8300. for (j = 0; j < 1000; j++) {
  8301. val = tr32(GRC_EEPROM_ADDR);
  8302. if (val & EEPROM_ADDR_COMPLETE)
  8303. break;
  8304. msleep(1);
  8305. }
  8306. if (!(val & EEPROM_ADDR_COMPLETE)) {
  8307. rc = -EBUSY;
  8308. break;
  8309. }
  8310. }
  8311. return rc;
  8312. }
  8313. /* offset and length are dword aligned */
  8314. static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
  8315. u8 *buf)
  8316. {
  8317. int ret = 0;
  8318. u32 pagesize = tp->nvram_pagesize;
  8319. u32 pagemask = pagesize - 1;
  8320. u32 nvram_cmd;
  8321. u8 *tmp;
  8322. tmp = kmalloc(pagesize, GFP_KERNEL);
  8323. if (tmp == NULL)
  8324. return -ENOMEM;
  8325. while (len) {
  8326. int j;
  8327. u32 phy_addr, page_off, size;
  8328. phy_addr = offset & ~pagemask;
  8329. for (j = 0; j < pagesize; j += 4) {
  8330. if ((ret = tg3_nvram_read(tp, phy_addr + j,
  8331. (u32 *) (tmp + j))))
  8332. break;
  8333. }
  8334. if (ret)
  8335. break;
  8336. page_off = offset & pagemask;
  8337. size = pagesize;
  8338. if (len < size)
  8339. size = len;
  8340. len -= size;
  8341. memcpy(tmp + page_off, buf, size);
  8342. offset = offset + (pagesize - page_off);
  8343. tg3_enable_nvram_access(tp);
  8344. /*
  8345. * Before we can erase the flash page, we need
  8346. * to issue a special "write enable" command.
  8347. */
  8348. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8349. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8350. break;
  8351. /* Erase the target page */
  8352. tw32(NVRAM_ADDR, phy_addr);
  8353. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
  8354. NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
  8355. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8356. break;
  8357. /* Issue another write enable to start the write. */
  8358. nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8359. if (tg3_nvram_exec_cmd(tp, nvram_cmd))
  8360. break;
  8361. for (j = 0; j < pagesize; j += 4) {
  8362. u32 data;
  8363. data = *((u32 *) (tmp + j));
  8364. tw32(NVRAM_WRDATA, cpu_to_be32(data));
  8365. tw32(NVRAM_ADDR, phy_addr + j);
  8366. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
  8367. NVRAM_CMD_WR;
  8368. if (j == 0)
  8369. nvram_cmd |= NVRAM_CMD_FIRST;
  8370. else if (j == (pagesize - 4))
  8371. nvram_cmd |= NVRAM_CMD_LAST;
  8372. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8373. break;
  8374. }
  8375. if (ret)
  8376. break;
  8377. }
  8378. nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
  8379. tg3_nvram_exec_cmd(tp, nvram_cmd);
  8380. kfree(tmp);
  8381. return ret;
  8382. }
  8383. /* offset and length are dword aligned */
  8384. static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
  8385. u8 *buf)
  8386. {
  8387. int i, ret = 0;
  8388. for (i = 0; i < len; i += 4, offset += 4) {
  8389. u32 data, page_off, phy_addr, nvram_cmd;
  8390. memcpy(&data, buf + i, 4);
  8391. tw32(NVRAM_WRDATA, cpu_to_be32(data));
  8392. page_off = offset % tp->nvram_pagesize;
  8393. phy_addr = tg3_nvram_phys_addr(tp, offset);
  8394. tw32(NVRAM_ADDR, phy_addr);
  8395. nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
  8396. if ((page_off == 0) || (i == 0))
  8397. nvram_cmd |= NVRAM_CMD_FIRST;
  8398. if (page_off == (tp->nvram_pagesize - 4))
  8399. nvram_cmd |= NVRAM_CMD_LAST;
  8400. if (i == (len - 4))
  8401. nvram_cmd |= NVRAM_CMD_LAST;
  8402. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
  8403. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
  8404. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
  8405. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
  8406. (tp->nvram_jedecnum == JEDEC_ST) &&
  8407. (nvram_cmd & NVRAM_CMD_FIRST)) {
  8408. if ((ret = tg3_nvram_exec_cmd(tp,
  8409. NVRAM_CMD_WREN | NVRAM_CMD_GO |
  8410. NVRAM_CMD_DONE)))
  8411. break;
  8412. }
  8413. if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8414. /* We always do complete word writes to eeprom. */
  8415. nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
  8416. }
  8417. if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
  8418. break;
  8419. }
  8420. return ret;
  8421. }
  8422. /* offset and length are dword aligned */
  8423. static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
  8424. {
  8425. int ret;
  8426. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8427. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
  8428. ~GRC_LCLCTRL_GPIO_OUTPUT1);
  8429. udelay(40);
  8430. }
  8431. if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
  8432. ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
  8433. }
  8434. else {
  8435. u32 grc_mode;
  8436. ret = tg3_nvram_lock(tp);
  8437. if (ret)
  8438. return ret;
  8439. tg3_enable_nvram_access(tp);
  8440. if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
  8441. !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
  8442. tw32(NVRAM_WRITE1, 0x406);
  8443. grc_mode = tr32(GRC_MODE);
  8444. tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
  8445. if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
  8446. !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
  8447. ret = tg3_nvram_write_block_buffered(tp, offset, len,
  8448. buf);
  8449. }
  8450. else {
  8451. ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
  8452. buf);
  8453. }
  8454. grc_mode = tr32(GRC_MODE);
  8455. tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
  8456. tg3_disable_nvram_access(tp);
  8457. tg3_nvram_unlock(tp);
  8458. }
  8459. if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
  8460. tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
  8461. udelay(40);
  8462. }
  8463. return ret;
  8464. }
  8465. struct subsys_tbl_ent {
  8466. u16 subsys_vendor, subsys_devid;
  8467. u32 phy_id;
  8468. };
  8469. static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
  8470. /* Broadcom boards. */
  8471. { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
  8472. { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
  8473. { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
  8474. { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
  8475. { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
  8476. { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
  8477. { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
  8478. { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
  8479. { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
  8480. { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
  8481. { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
  8482. /* 3com boards. */
  8483. { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
  8484. { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
  8485. { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
  8486. { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
  8487. { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
  8488. /* DELL boards. */
  8489. { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
  8490. { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
  8491. { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
  8492. { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
  8493. /* Compaq boards. */
  8494. { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
  8495. { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
  8496. { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
  8497. { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
  8498. { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
  8499. /* IBM boards. */
  8500. { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
  8501. };
  8502. static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
  8503. {
  8504. int i;
  8505. for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
  8506. if ((subsys_id_to_phy_id[i].subsys_vendor ==
  8507. tp->pdev->subsystem_vendor) &&
  8508. (subsys_id_to_phy_id[i].subsys_devid ==
  8509. tp->pdev->subsystem_device))
  8510. return &subsys_id_to_phy_id[i];
  8511. }
  8512. return NULL;
  8513. }
  8514. static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
  8515. {
  8516. u32 val;
  8517. u16 pmcsr;
  8518. /* On some early chips the SRAM cannot be accessed in D3hot state,
  8519. * so need make sure we're in D0.
  8520. */
  8521. pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
  8522. pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  8523. pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
  8524. msleep(1);
  8525. /* Make sure register accesses (indirect or otherwise)
  8526. * will function correctly.
  8527. */
  8528. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8529. tp->misc_host_ctrl);
  8530. /* The memory arbiter has to be enabled in order for SRAM accesses
  8531. * to succeed. Normally on powerup the tg3 chip firmware will make
  8532. * sure it is enabled, but other entities such as system netboot
  8533. * code might disable it.
  8534. */
  8535. val = tr32(MEMARB_MODE);
  8536. tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
  8537. tp->phy_id = PHY_ID_INVALID;
  8538. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8539. /* Assume an onboard device and WOL capable by default. */
  8540. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
  8541. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  8542. if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
  8543. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8544. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  8545. }
  8546. if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
  8547. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  8548. return;
  8549. }
  8550. tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
  8551. if (val == NIC_SRAM_DATA_SIG_MAGIC) {
  8552. u32 nic_cfg, led_cfg;
  8553. u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
  8554. int eeprom_phy_serdes = 0;
  8555. tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
  8556. tp->nic_sram_data_cfg = nic_cfg;
  8557. tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
  8558. ver >>= NIC_SRAM_DATA_VER_SHIFT;
  8559. if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
  8560. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
  8561. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
  8562. (ver > 0) && (ver < 0x100))
  8563. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
  8564. if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
  8565. NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
  8566. eeprom_phy_serdes = 1;
  8567. tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
  8568. if (nic_phy_id != 0) {
  8569. u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
  8570. u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
  8571. eeprom_phy_id = (id1 >> 16) << 10;
  8572. eeprom_phy_id |= (id2 & 0xfc00) << 16;
  8573. eeprom_phy_id |= (id2 & 0x03ff) << 0;
  8574. } else
  8575. eeprom_phy_id = 0;
  8576. tp->phy_id = eeprom_phy_id;
  8577. if (eeprom_phy_serdes) {
  8578. if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
  8579. tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
  8580. else
  8581. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8582. }
  8583. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8584. led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
  8585. SHASTA_EXT_LED_MODE_MASK);
  8586. else
  8587. led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
  8588. switch (led_cfg) {
  8589. default:
  8590. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
  8591. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8592. break;
  8593. case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
  8594. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  8595. break;
  8596. case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
  8597. tp->led_ctrl = LED_CTRL_MODE_MAC;
  8598. /* Default to PHY_1_MODE if 0 (MAC_MODE) is
  8599. * read on some older 5700/5701 bootcode.
  8600. */
  8601. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8602. ASIC_REV_5700 ||
  8603. GET_ASIC_REV(tp->pci_chip_rev_id) ==
  8604. ASIC_REV_5701)
  8605. tp->led_ctrl = LED_CTRL_MODE_PHY_1;
  8606. break;
  8607. case SHASTA_EXT_LED_SHARED:
  8608. tp->led_ctrl = LED_CTRL_MODE_SHARED;
  8609. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
  8610. tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
  8611. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  8612. LED_CTRL_MODE_PHY_2);
  8613. break;
  8614. case SHASTA_EXT_LED_MAC:
  8615. tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
  8616. break;
  8617. case SHASTA_EXT_LED_COMBO:
  8618. tp->led_ctrl = LED_CTRL_MODE_COMBO;
  8619. if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
  8620. tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
  8621. LED_CTRL_MODE_PHY_2);
  8622. break;
  8623. };
  8624. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  8625. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
  8626. tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
  8627. tp->led_ctrl = LED_CTRL_MODE_PHY_2;
  8628. if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
  8629. tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
  8630. if ((tp->pdev->subsystem_vendor ==
  8631. PCI_VENDOR_ID_ARIMA) &&
  8632. (tp->pdev->subsystem_device == 0x205a ||
  8633. tp->pdev->subsystem_device == 0x2063))
  8634. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8635. } else {
  8636. tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
  8637. tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
  8638. }
  8639. if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
  8640. tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
  8641. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
  8642. tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
  8643. }
  8644. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
  8645. !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
  8646. tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
  8647. if (cfg2 & (1 << 17))
  8648. tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
  8649. /* serdes signal pre-emphasis in register 0x590 set by */
  8650. /* bootcode if bit 18 is set */
  8651. if (cfg2 & (1 << 18))
  8652. tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
  8653. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  8654. u32 cfg3;
  8655. tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
  8656. if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
  8657. tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
  8658. }
  8659. }
  8660. }
  8661. static int __devinit tg3_phy_probe(struct tg3 *tp)
  8662. {
  8663. u32 hw_phy_id_1, hw_phy_id_2;
  8664. u32 hw_phy_id, hw_phy_id_masked;
  8665. int err;
  8666. /* Reading the PHY ID register can conflict with ASF
  8667. * firwmare access to the PHY hardware.
  8668. */
  8669. err = 0;
  8670. if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
  8671. hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
  8672. } else {
  8673. /* Now read the physical PHY_ID from the chip and verify
  8674. * that it is sane. If it doesn't look good, we fall back
  8675. * to either the hard-coded table based PHY_ID and failing
  8676. * that the value found in the eeprom area.
  8677. */
  8678. err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
  8679. err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
  8680. hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
  8681. hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
  8682. hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
  8683. hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
  8684. }
  8685. if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
  8686. tp->phy_id = hw_phy_id;
  8687. if (hw_phy_id_masked == PHY_ID_BCM8002)
  8688. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8689. else
  8690. tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
  8691. } else {
  8692. if (tp->phy_id != PHY_ID_INVALID) {
  8693. /* Do nothing, phy ID already set up in
  8694. * tg3_get_eeprom_hw_cfg().
  8695. */
  8696. } else {
  8697. struct subsys_tbl_ent *p;
  8698. /* No eeprom signature? Try the hardcoded
  8699. * subsys device table.
  8700. */
  8701. p = lookup_by_subsys(tp);
  8702. if (!p)
  8703. return -ENODEV;
  8704. tp->phy_id = p->phy_id;
  8705. if (!tp->phy_id ||
  8706. tp->phy_id == PHY_ID_BCM8002)
  8707. tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
  8708. }
  8709. }
  8710. if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
  8711. !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
  8712. u32 bmsr, adv_reg, tg3_ctrl, mask;
  8713. tg3_readphy(tp, MII_BMSR, &bmsr);
  8714. if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
  8715. (bmsr & BMSR_LSTATUS))
  8716. goto skip_phy_reset;
  8717. err = tg3_phy_reset(tp);
  8718. if (err)
  8719. return err;
  8720. adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
  8721. ADVERTISE_100HALF | ADVERTISE_100FULL |
  8722. ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  8723. tg3_ctrl = 0;
  8724. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
  8725. tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
  8726. MII_TG3_CTRL_ADV_1000_FULL);
  8727. if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  8728. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
  8729. tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
  8730. MII_TG3_CTRL_ENABLE_AS_MASTER);
  8731. }
  8732. mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  8733. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  8734. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
  8735. if (!tg3_copper_is_advertising_all(tp, mask)) {
  8736. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  8737. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8738. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  8739. tg3_writephy(tp, MII_BMCR,
  8740. BMCR_ANENABLE | BMCR_ANRESTART);
  8741. }
  8742. tg3_phy_set_wirespeed(tp);
  8743. tg3_writephy(tp, MII_ADVERTISE, adv_reg);
  8744. if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
  8745. tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
  8746. }
  8747. skip_phy_reset:
  8748. if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
  8749. err = tg3_init_5401phy_dsp(tp);
  8750. if (err)
  8751. return err;
  8752. }
  8753. if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
  8754. err = tg3_init_5401phy_dsp(tp);
  8755. }
  8756. if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
  8757. tp->link_config.advertising =
  8758. (ADVERTISED_1000baseT_Half |
  8759. ADVERTISED_1000baseT_Full |
  8760. ADVERTISED_Autoneg |
  8761. ADVERTISED_FIBRE);
  8762. if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
  8763. tp->link_config.advertising &=
  8764. ~(ADVERTISED_1000baseT_Half |
  8765. ADVERTISED_1000baseT_Full);
  8766. return err;
  8767. }
  8768. static void __devinit tg3_read_partno(struct tg3 *tp)
  8769. {
  8770. unsigned char vpd_data[256];
  8771. unsigned int i;
  8772. u32 magic;
  8773. if (tg3_nvram_read_swab(tp, 0x0, &magic))
  8774. goto out_not_found;
  8775. if (magic == TG3_EEPROM_MAGIC) {
  8776. for (i = 0; i < 256; i += 4) {
  8777. u32 tmp;
  8778. if (tg3_nvram_read(tp, 0x100 + i, &tmp))
  8779. goto out_not_found;
  8780. vpd_data[i + 0] = ((tmp >> 0) & 0xff);
  8781. vpd_data[i + 1] = ((tmp >> 8) & 0xff);
  8782. vpd_data[i + 2] = ((tmp >> 16) & 0xff);
  8783. vpd_data[i + 3] = ((tmp >> 24) & 0xff);
  8784. }
  8785. } else {
  8786. int vpd_cap;
  8787. vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
  8788. for (i = 0; i < 256; i += 4) {
  8789. u32 tmp, j = 0;
  8790. u16 tmp16;
  8791. pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
  8792. i);
  8793. while (j++ < 100) {
  8794. pci_read_config_word(tp->pdev, vpd_cap +
  8795. PCI_VPD_ADDR, &tmp16);
  8796. if (tmp16 & 0x8000)
  8797. break;
  8798. msleep(1);
  8799. }
  8800. if (!(tmp16 & 0x8000))
  8801. goto out_not_found;
  8802. pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
  8803. &tmp);
  8804. tmp = cpu_to_le32(tmp);
  8805. memcpy(&vpd_data[i], &tmp, 4);
  8806. }
  8807. }
  8808. /* Now parse and find the part number. */
  8809. for (i = 0; i < 254; ) {
  8810. unsigned char val = vpd_data[i];
  8811. unsigned int block_end;
  8812. if (val == 0x82 || val == 0x91) {
  8813. i = (i + 3 +
  8814. (vpd_data[i + 1] +
  8815. (vpd_data[i + 2] << 8)));
  8816. continue;
  8817. }
  8818. if (val != 0x90)
  8819. goto out_not_found;
  8820. block_end = (i + 3 +
  8821. (vpd_data[i + 1] +
  8822. (vpd_data[i + 2] << 8)));
  8823. i += 3;
  8824. if (block_end > 256)
  8825. goto out_not_found;
  8826. while (i < (block_end - 2)) {
  8827. if (vpd_data[i + 0] == 'P' &&
  8828. vpd_data[i + 1] == 'N') {
  8829. int partno_len = vpd_data[i + 2];
  8830. i += 3;
  8831. if (partno_len > 24 || (partno_len + i) > 256)
  8832. goto out_not_found;
  8833. memcpy(tp->board_part_number,
  8834. &vpd_data[i], partno_len);
  8835. /* Success. */
  8836. return;
  8837. }
  8838. i += 3 + vpd_data[i + 2];
  8839. }
  8840. /* Part number not found. */
  8841. goto out_not_found;
  8842. }
  8843. out_not_found:
  8844. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  8845. strcpy(tp->board_part_number, "BCM95906");
  8846. else
  8847. strcpy(tp->board_part_number, "none");
  8848. }
  8849. static void __devinit tg3_read_fw_ver(struct tg3 *tp)
  8850. {
  8851. u32 val, offset, start;
  8852. if (tg3_nvram_read_swab(tp, 0, &val))
  8853. return;
  8854. if (val != TG3_EEPROM_MAGIC)
  8855. return;
  8856. if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
  8857. tg3_nvram_read_swab(tp, 0x4, &start))
  8858. return;
  8859. offset = tg3_nvram_logical_addr(tp, offset);
  8860. if (tg3_nvram_read_swab(tp, offset, &val))
  8861. return;
  8862. if ((val & 0xfc000000) == 0x0c000000) {
  8863. u32 ver_offset, addr;
  8864. int i;
  8865. if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
  8866. tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
  8867. return;
  8868. if (val != 0)
  8869. return;
  8870. addr = offset + ver_offset - start;
  8871. for (i = 0; i < 16; i += 4) {
  8872. if (tg3_nvram_read(tp, addr + i, &val))
  8873. return;
  8874. val = cpu_to_le32(val);
  8875. memcpy(tp->fw_ver + i, &val, 4);
  8876. }
  8877. }
  8878. }
  8879. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
  8880. static int __devinit tg3_get_invariants(struct tg3 *tp)
  8881. {
  8882. static struct pci_device_id write_reorder_chipsets[] = {
  8883. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  8884. PCI_DEVICE_ID_AMD_FE_GATE_700C) },
  8885. { PCI_DEVICE(PCI_VENDOR_ID_AMD,
  8886. PCI_DEVICE_ID_AMD_8131_BRIDGE) },
  8887. { PCI_DEVICE(PCI_VENDOR_ID_VIA,
  8888. PCI_DEVICE_ID_VIA_8385_0) },
  8889. { },
  8890. };
  8891. u32 misc_ctrl_reg;
  8892. u32 cacheline_sz_reg;
  8893. u32 pci_state_reg, grc_misc_cfg;
  8894. u32 val;
  8895. u16 pci_cmd;
  8896. int err, pcie_cap;
  8897. /* Force memory write invalidate off. If we leave it on,
  8898. * then on 5700_BX chips we have to enable a workaround.
  8899. * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
  8900. * to match the cacheline size. The Broadcom driver have this
  8901. * workaround but turns MWI off all the times so never uses
  8902. * it. This seems to suggest that the workaround is insufficient.
  8903. */
  8904. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  8905. pci_cmd &= ~PCI_COMMAND_INVALIDATE;
  8906. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  8907. /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
  8908. * has the register indirect write enable bit set before
  8909. * we try to access any of the MMIO registers. It is also
  8910. * critical that the PCI-X hw workaround situation is decided
  8911. * before that as well.
  8912. */
  8913. pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  8914. &misc_ctrl_reg);
  8915. tp->pci_chip_rev_id = (misc_ctrl_reg >>
  8916. MISC_HOST_CTRL_CHIPREV_SHIFT);
  8917. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
  8918. u32 prod_id_asic_rev;
  8919. pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
  8920. &prod_id_asic_rev);
  8921. tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
  8922. }
  8923. /* Wrong chip ID in 5752 A0. This code can be removed later
  8924. * as A0 is not in production.
  8925. */
  8926. if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
  8927. tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
  8928. /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
  8929. * we need to disable memory and use config. cycles
  8930. * only to access all registers. The 5702/03 chips
  8931. * can mistakenly decode the special cycles from the
  8932. * ICH chipsets as memory write cycles, causing corruption
  8933. * of register and memory space. Only certain ICH bridges
  8934. * will drive special cycles with non-zero data during the
  8935. * address phase which can fall within the 5703's address
  8936. * range. This is not an ICH bug as the PCI spec allows
  8937. * non-zero address during special cycles. However, only
  8938. * these ICH bridges are known to drive non-zero addresses
  8939. * during special cycles.
  8940. *
  8941. * Since special cycles do not cross PCI bridges, we only
  8942. * enable this workaround if the 5703 is on the secondary
  8943. * bus of these ICH bridges.
  8944. */
  8945. if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
  8946. (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
  8947. static struct tg3_dev_id {
  8948. u32 vendor;
  8949. u32 device;
  8950. u32 rev;
  8951. } ich_chipsets[] = {
  8952. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
  8953. PCI_ANY_ID },
  8954. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
  8955. PCI_ANY_ID },
  8956. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
  8957. 0xa },
  8958. { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
  8959. PCI_ANY_ID },
  8960. { },
  8961. };
  8962. struct tg3_dev_id *pci_id = &ich_chipsets[0];
  8963. struct pci_dev *bridge = NULL;
  8964. while (pci_id->vendor != 0) {
  8965. bridge = pci_get_device(pci_id->vendor, pci_id->device,
  8966. bridge);
  8967. if (!bridge) {
  8968. pci_id++;
  8969. continue;
  8970. }
  8971. if (pci_id->rev != PCI_ANY_ID) {
  8972. if (bridge->revision > pci_id->rev)
  8973. continue;
  8974. }
  8975. if (bridge->subordinate &&
  8976. (bridge->subordinate->number ==
  8977. tp->pdev->bus->number)) {
  8978. tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
  8979. pci_dev_put(bridge);
  8980. break;
  8981. }
  8982. }
  8983. }
  8984. /* The EPB bridge inside 5714, 5715, and 5780 cannot support
  8985. * DMA addresses > 40-bit. This bridge may have other additional
  8986. * 57xx devices behind it in some 4-port NIC designs for example.
  8987. * Any tg3 device found behind the bridge will also need the 40-bit
  8988. * DMA workaround.
  8989. */
  8990. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
  8991. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  8992. tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
  8993. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  8994. tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
  8995. }
  8996. else {
  8997. struct pci_dev *bridge = NULL;
  8998. do {
  8999. bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
  9000. PCI_DEVICE_ID_SERVERWORKS_EPB,
  9001. bridge);
  9002. if (bridge && bridge->subordinate &&
  9003. (bridge->subordinate->number <=
  9004. tp->pdev->bus->number) &&
  9005. (bridge->subordinate->subordinate >=
  9006. tp->pdev->bus->number)) {
  9007. tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
  9008. pci_dev_put(bridge);
  9009. break;
  9010. }
  9011. } while (bridge);
  9012. }
  9013. /* Initialize misc host control in PCI block. */
  9014. tp->misc_host_ctrl |= (misc_ctrl_reg &
  9015. MISC_HOST_CTRL_CHIPREV);
  9016. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9017. tp->misc_host_ctrl);
  9018. pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  9019. &cacheline_sz_reg);
  9020. tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
  9021. tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
  9022. tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
  9023. tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
  9024. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  9025. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
  9026. tp->pdev_peer = tg3_find_peer(tp);
  9027. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  9028. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  9029. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9030. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9031. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9032. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  9033. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  9034. tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
  9035. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
  9036. (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
  9037. tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
  9038. if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
  9039. tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
  9040. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
  9041. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
  9042. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
  9043. tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
  9044. tp->pdev_peer == tp->pdev))
  9045. tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
  9046. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9047. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9048. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9049. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9050. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
  9051. tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
  9052. } else {
  9053. tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
  9054. if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
  9055. ASIC_REV_5750 &&
  9056. tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
  9057. tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
  9058. }
  9059. }
  9060. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
  9061. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
  9062. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
  9063. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
  9064. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
  9065. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
  9066. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9067. tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
  9068. pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
  9069. if (pcie_cap != 0) {
  9070. tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
  9071. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9072. u16 lnkctl;
  9073. pci_read_config_word(tp->pdev,
  9074. pcie_cap + PCI_EXP_LNKCTL,
  9075. &lnkctl);
  9076. if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
  9077. tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
  9078. }
  9079. }
  9080. /* If we have an AMD 762 or VIA K8T800 chipset, write
  9081. * reordering to the mailbox registers done by the host
  9082. * controller can cause major troubles. We read back from
  9083. * every mailbox register write to force the writes to be
  9084. * posted to the chip in order.
  9085. */
  9086. if (pci_dev_present(write_reorder_chipsets) &&
  9087. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  9088. tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
  9089. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  9090. tp->pci_lat_timer < 64) {
  9091. tp->pci_lat_timer = 64;
  9092. cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
  9093. cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
  9094. cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
  9095. cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
  9096. pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
  9097. cacheline_sz_reg);
  9098. }
  9099. if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
  9100. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9101. tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
  9102. if (!tp->pcix_cap) {
  9103. printk(KERN_ERR PFX "Cannot find PCI-X "
  9104. "capability, aborting.\n");
  9105. return -EIO;
  9106. }
  9107. }
  9108. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9109. &pci_state_reg);
  9110. if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
  9111. tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
  9112. /* If this is a 5700 BX chipset, and we are in PCI-X
  9113. * mode, enable register write workaround.
  9114. *
  9115. * The workaround is to use indirect register accesses
  9116. * for all chip writes not to mailbox registers.
  9117. */
  9118. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
  9119. u32 pm_reg;
  9120. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  9121. /* The chip can have it's power management PCI config
  9122. * space registers clobbered due to this bug.
  9123. * So explicitly force the chip into D0 here.
  9124. */
  9125. pci_read_config_dword(tp->pdev,
  9126. tp->pm_cap + PCI_PM_CTRL,
  9127. &pm_reg);
  9128. pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
  9129. pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
  9130. pci_write_config_dword(tp->pdev,
  9131. tp->pm_cap + PCI_PM_CTRL,
  9132. pm_reg);
  9133. /* Also, force SERR#/PERR# in PCI command. */
  9134. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9135. pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  9136. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9137. }
  9138. }
  9139. /* 5700 BX chips need to have their TX producer index mailboxes
  9140. * written twice to workaround a bug.
  9141. */
  9142. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
  9143. tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
  9144. if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
  9145. tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
  9146. if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
  9147. tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
  9148. /* Chip-specific fixup from Broadcom driver */
  9149. if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
  9150. (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
  9151. pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
  9152. pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
  9153. }
  9154. /* Default fast path register access methods */
  9155. tp->read32 = tg3_read32;
  9156. tp->write32 = tg3_write32;
  9157. tp->read32_mbox = tg3_read32;
  9158. tp->write32_mbox = tg3_write32;
  9159. tp->write32_tx_mbox = tg3_write32;
  9160. tp->write32_rx_mbox = tg3_write32;
  9161. /* Various workaround register access methods */
  9162. if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
  9163. tp->write32 = tg3_write_indirect_reg32;
  9164. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  9165. ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
  9166. tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
  9167. /*
  9168. * Back to back register writes can cause problems on these
  9169. * chips, the workaround is to read back all reg writes
  9170. * except those to mailbox regs.
  9171. *
  9172. * See tg3_write_indirect_reg32().
  9173. */
  9174. tp->write32 = tg3_write_flush_reg32;
  9175. }
  9176. if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
  9177. (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
  9178. tp->write32_tx_mbox = tg3_write32_tx_mbox;
  9179. if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
  9180. tp->write32_rx_mbox = tg3_write_flush_reg32;
  9181. }
  9182. if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
  9183. tp->read32 = tg3_read_indirect_reg32;
  9184. tp->write32 = tg3_write_indirect_reg32;
  9185. tp->read32_mbox = tg3_read_indirect_mbox;
  9186. tp->write32_mbox = tg3_write_indirect_mbox;
  9187. tp->write32_tx_mbox = tg3_write_indirect_mbox;
  9188. tp->write32_rx_mbox = tg3_write_indirect_mbox;
  9189. iounmap(tp->regs);
  9190. tp->regs = NULL;
  9191. pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
  9192. pci_cmd &= ~PCI_COMMAND_MEMORY;
  9193. pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
  9194. }
  9195. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9196. tp->read32_mbox = tg3_read32_mbox_5906;
  9197. tp->write32_mbox = tg3_write32_mbox_5906;
  9198. tp->write32_tx_mbox = tg3_write32_mbox_5906;
  9199. tp->write32_rx_mbox = tg3_write32_mbox_5906;
  9200. }
  9201. if (tp->write32 == tg3_write_indirect_reg32 ||
  9202. ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9203. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9204. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
  9205. tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
  9206. /* Get eeprom hw config before calling tg3_set_power_state().
  9207. * In particular, the TG3_FLG2_IS_NIC flag must be
  9208. * determined before calling tg3_set_power_state() so that
  9209. * we know whether or not to switch out of Vaux power.
  9210. * When the flag is set, it means that GPIO1 is used for eeprom
  9211. * write protect and also implies that it is a LOM where GPIOs
  9212. * are not used to switch power.
  9213. */
  9214. tg3_get_eeprom_hw_cfg(tp);
  9215. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  9216. tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
  9217. /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
  9218. * GPIO1 driven high will bring 5700's external PHY out of reset.
  9219. * It is also used as eeprom write protect on LOMs.
  9220. */
  9221. tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
  9222. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9223. (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
  9224. tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
  9225. GRC_LCLCTRL_GPIO_OUTPUT1);
  9226. /* Unused GPIO3 must be driven as output on 5752 because there
  9227. * are no pull-up resistors on unused GPIO pins.
  9228. */
  9229. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
  9230. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
  9231. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9232. tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
  9233. /* Force the chip into D0. */
  9234. err = tg3_set_power_state(tp, PCI_D0);
  9235. if (err) {
  9236. printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
  9237. pci_name(tp->pdev));
  9238. return err;
  9239. }
  9240. /* 5700 B0 chips do not support checksumming correctly due
  9241. * to hardware bugs.
  9242. */
  9243. if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
  9244. tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
  9245. /* Derive initial jumbo mode from MTU assigned in
  9246. * ether_setup() via the alloc_etherdev() call
  9247. */
  9248. if (tp->dev->mtu > ETH_DATA_LEN &&
  9249. !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
  9250. tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
  9251. /* Determine WakeOnLan speed to use. */
  9252. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9253. tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
  9254. tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
  9255. tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
  9256. tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
  9257. } else {
  9258. tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
  9259. }
  9260. /* A few boards don't want Ethernet@WireSpeed phy feature */
  9261. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
  9262. ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
  9263. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
  9264. (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
  9265. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
  9266. (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
  9267. tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
  9268. if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
  9269. GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
  9270. tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
  9271. if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
  9272. tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
  9273. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9274. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9275. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9276. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) {
  9277. if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
  9278. tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
  9279. tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
  9280. if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
  9281. tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
  9282. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
  9283. tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
  9284. }
  9285. tp->coalesce_mode = 0;
  9286. if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
  9287. GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
  9288. tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
  9289. /* Initialize MAC MI mode, polling disabled. */
  9290. tw32_f(MAC_MI_MODE, tp->mi_mode);
  9291. udelay(80);
  9292. /* Initialize data/descriptor byte/word swapping. */
  9293. val = tr32(GRC_MODE);
  9294. val &= GRC_MODE_HOST_STACKUP;
  9295. tw32(GRC_MODE, val | tp->grc_mode);
  9296. tg3_switch_clocks(tp);
  9297. /* Clear this out for sanity. */
  9298. tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
  9299. pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
  9300. &pci_state_reg);
  9301. if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
  9302. (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
  9303. u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
  9304. if (chiprevid == CHIPREV_ID_5701_A0 ||
  9305. chiprevid == CHIPREV_ID_5701_B0 ||
  9306. chiprevid == CHIPREV_ID_5701_B2 ||
  9307. chiprevid == CHIPREV_ID_5701_B5) {
  9308. void __iomem *sram_base;
  9309. /* Write some dummy words into the SRAM status block
  9310. * area, see if it reads back correctly. If the return
  9311. * value is bad, force enable the PCIX workaround.
  9312. */
  9313. sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
  9314. writel(0x00000000, sram_base);
  9315. writel(0x00000000, sram_base + 4);
  9316. writel(0xffffffff, sram_base + 4);
  9317. if (readl(sram_base) != 0x00000000)
  9318. tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
  9319. }
  9320. }
  9321. udelay(50);
  9322. tg3_nvram_init(tp);
  9323. grc_misc_cfg = tr32(GRC_MISC_CFG);
  9324. grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
  9325. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  9326. (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
  9327. grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
  9328. tp->tg3_flags2 |= TG3_FLG2_IS_5788;
  9329. if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
  9330. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
  9331. tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
  9332. if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
  9333. tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
  9334. HOSTCC_MODE_CLRTICK_TXBD);
  9335. tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
  9336. pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
  9337. tp->misc_host_ctrl);
  9338. }
  9339. /* these are limited to 10/100 only */
  9340. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
  9341. (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
  9342. (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
  9343. tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  9344. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
  9345. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
  9346. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
  9347. (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
  9348. (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
  9349. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
  9350. tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
  9351. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9352. tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
  9353. err = tg3_phy_probe(tp);
  9354. if (err) {
  9355. printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
  9356. pci_name(tp->pdev), err);
  9357. /* ... but do not return immediately ... */
  9358. }
  9359. tg3_read_partno(tp);
  9360. tg3_read_fw_ver(tp);
  9361. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
  9362. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  9363. } else {
  9364. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  9365. tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
  9366. else
  9367. tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
  9368. }
  9369. /* 5700 {AX,BX} chips have a broken status block link
  9370. * change bit implementation, so we must use the
  9371. * status register in those cases.
  9372. */
  9373. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
  9374. tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
  9375. else
  9376. tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
  9377. /* The led_ctrl is set during tg3_phy_probe, here we might
  9378. * have to force the link status polling mechanism based
  9379. * upon subsystem IDs.
  9380. */
  9381. if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
  9382. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  9383. !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
  9384. tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
  9385. TG3_FLAG_USE_LINKCHG_REG);
  9386. }
  9387. /* For all SERDES we poll the MAC status register. */
  9388. if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
  9389. tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
  9390. else
  9391. tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
  9392. /* All chips before 5787 can get confused if TX buffers
  9393. * straddle the 4GB address boundary in some cases.
  9394. */
  9395. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  9396. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  9397. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
  9398. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9399. tp->dev->hard_start_xmit = tg3_start_xmit;
  9400. else
  9401. tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
  9402. tp->rx_offset = 2;
  9403. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
  9404. (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
  9405. tp->rx_offset = 0;
  9406. tp->rx_std_max_post = TG3_RX_RING_SIZE;
  9407. /* Increment the rx prod index on the rx std ring by at most
  9408. * 8 for these chips to workaround hw errata.
  9409. */
  9410. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
  9411. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
  9412. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
  9413. tp->rx_std_max_post = 8;
  9414. /* By default, disable wake-on-lan. User can change this
  9415. * using ETHTOOL_SWOL.
  9416. */
  9417. tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
  9418. if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
  9419. tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
  9420. PCIE_PWR_MGMT_L1_THRESH_MSK;
  9421. return err;
  9422. }
  9423. #ifdef CONFIG_SPARC
  9424. static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
  9425. {
  9426. struct net_device *dev = tp->dev;
  9427. struct pci_dev *pdev = tp->pdev;
  9428. struct device_node *dp = pci_device_to_OF_node(pdev);
  9429. const unsigned char *addr;
  9430. int len;
  9431. addr = of_get_property(dp, "local-mac-address", &len);
  9432. if (addr && len == 6) {
  9433. memcpy(dev->dev_addr, addr, 6);
  9434. memcpy(dev->perm_addr, dev->dev_addr, 6);
  9435. return 0;
  9436. }
  9437. return -ENODEV;
  9438. }
  9439. static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
  9440. {
  9441. struct net_device *dev = tp->dev;
  9442. memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
  9443. memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
  9444. return 0;
  9445. }
  9446. #endif
  9447. static int __devinit tg3_get_device_address(struct tg3 *tp)
  9448. {
  9449. struct net_device *dev = tp->dev;
  9450. u32 hi, lo, mac_offset;
  9451. int addr_ok = 0;
  9452. #ifdef CONFIG_SPARC
  9453. if (!tg3_get_macaddr_sparc(tp))
  9454. return 0;
  9455. #endif
  9456. mac_offset = 0x7c;
  9457. if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
  9458. (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
  9459. if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
  9460. mac_offset = 0xcc;
  9461. if (tg3_nvram_lock(tp))
  9462. tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
  9463. else
  9464. tg3_nvram_unlock(tp);
  9465. }
  9466. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
  9467. mac_offset = 0x10;
  9468. /* First try to get it from MAC address mailbox. */
  9469. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
  9470. if ((hi >> 16) == 0x484b) {
  9471. dev->dev_addr[0] = (hi >> 8) & 0xff;
  9472. dev->dev_addr[1] = (hi >> 0) & 0xff;
  9473. tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
  9474. dev->dev_addr[2] = (lo >> 24) & 0xff;
  9475. dev->dev_addr[3] = (lo >> 16) & 0xff;
  9476. dev->dev_addr[4] = (lo >> 8) & 0xff;
  9477. dev->dev_addr[5] = (lo >> 0) & 0xff;
  9478. /* Some old bootcode may report a 0 MAC address in SRAM */
  9479. addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
  9480. }
  9481. if (!addr_ok) {
  9482. /* Next, try NVRAM. */
  9483. if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
  9484. !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
  9485. dev->dev_addr[0] = ((hi >> 16) & 0xff);
  9486. dev->dev_addr[1] = ((hi >> 24) & 0xff);
  9487. dev->dev_addr[2] = ((lo >> 0) & 0xff);
  9488. dev->dev_addr[3] = ((lo >> 8) & 0xff);
  9489. dev->dev_addr[4] = ((lo >> 16) & 0xff);
  9490. dev->dev_addr[5] = ((lo >> 24) & 0xff);
  9491. }
  9492. /* Finally just fetch it out of the MAC control regs. */
  9493. else {
  9494. hi = tr32(MAC_ADDR_0_HIGH);
  9495. lo = tr32(MAC_ADDR_0_LOW);
  9496. dev->dev_addr[5] = lo & 0xff;
  9497. dev->dev_addr[4] = (lo >> 8) & 0xff;
  9498. dev->dev_addr[3] = (lo >> 16) & 0xff;
  9499. dev->dev_addr[2] = (lo >> 24) & 0xff;
  9500. dev->dev_addr[1] = hi & 0xff;
  9501. dev->dev_addr[0] = (hi >> 8) & 0xff;
  9502. }
  9503. }
  9504. if (!is_valid_ether_addr(&dev->dev_addr[0])) {
  9505. #ifdef CONFIG_SPARC64
  9506. if (!tg3_get_default_macaddr_sparc(tp))
  9507. return 0;
  9508. #endif
  9509. return -EINVAL;
  9510. }
  9511. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  9512. return 0;
  9513. }
  9514. #define BOUNDARY_SINGLE_CACHELINE 1
  9515. #define BOUNDARY_MULTI_CACHELINE 2
  9516. static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
  9517. {
  9518. int cacheline_size;
  9519. u8 byte;
  9520. int goal;
  9521. pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
  9522. if (byte == 0)
  9523. cacheline_size = 1024;
  9524. else
  9525. cacheline_size = (int) byte * 4;
  9526. /* On 5703 and later chips, the boundary bits have no
  9527. * effect.
  9528. */
  9529. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9530. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
  9531. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
  9532. goto out;
  9533. #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
  9534. goal = BOUNDARY_MULTI_CACHELINE;
  9535. #else
  9536. #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
  9537. goal = BOUNDARY_SINGLE_CACHELINE;
  9538. #else
  9539. goal = 0;
  9540. #endif
  9541. #endif
  9542. if (!goal)
  9543. goto out;
  9544. /* PCI controllers on most RISC systems tend to disconnect
  9545. * when a device tries to burst across a cache-line boundary.
  9546. * Therefore, letting tg3 do so just wastes PCI bandwidth.
  9547. *
  9548. * Unfortunately, for PCI-E there are only limited
  9549. * write-side controls for this, and thus for reads
  9550. * we will still get the disconnects. We'll also waste
  9551. * these PCI cycles for both read and write for chips
  9552. * other than 5700 and 5701 which do not implement the
  9553. * boundary bits.
  9554. */
  9555. if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
  9556. !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
  9557. switch (cacheline_size) {
  9558. case 16:
  9559. case 32:
  9560. case 64:
  9561. case 128:
  9562. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9563. val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
  9564. DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
  9565. } else {
  9566. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  9567. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  9568. }
  9569. break;
  9570. case 256:
  9571. val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
  9572. DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
  9573. break;
  9574. default:
  9575. val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
  9576. DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
  9577. break;
  9578. };
  9579. } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9580. switch (cacheline_size) {
  9581. case 16:
  9582. case 32:
  9583. case 64:
  9584. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9585. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  9586. val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
  9587. break;
  9588. }
  9589. /* fallthrough */
  9590. case 128:
  9591. default:
  9592. val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
  9593. val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
  9594. break;
  9595. };
  9596. } else {
  9597. switch (cacheline_size) {
  9598. case 16:
  9599. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9600. val |= (DMA_RWCTRL_READ_BNDRY_16 |
  9601. DMA_RWCTRL_WRITE_BNDRY_16);
  9602. break;
  9603. }
  9604. /* fallthrough */
  9605. case 32:
  9606. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9607. val |= (DMA_RWCTRL_READ_BNDRY_32 |
  9608. DMA_RWCTRL_WRITE_BNDRY_32);
  9609. break;
  9610. }
  9611. /* fallthrough */
  9612. case 64:
  9613. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9614. val |= (DMA_RWCTRL_READ_BNDRY_64 |
  9615. DMA_RWCTRL_WRITE_BNDRY_64);
  9616. break;
  9617. }
  9618. /* fallthrough */
  9619. case 128:
  9620. if (goal == BOUNDARY_SINGLE_CACHELINE) {
  9621. val |= (DMA_RWCTRL_READ_BNDRY_128 |
  9622. DMA_RWCTRL_WRITE_BNDRY_128);
  9623. break;
  9624. }
  9625. /* fallthrough */
  9626. case 256:
  9627. val |= (DMA_RWCTRL_READ_BNDRY_256 |
  9628. DMA_RWCTRL_WRITE_BNDRY_256);
  9629. break;
  9630. case 512:
  9631. val |= (DMA_RWCTRL_READ_BNDRY_512 |
  9632. DMA_RWCTRL_WRITE_BNDRY_512);
  9633. break;
  9634. case 1024:
  9635. default:
  9636. val |= (DMA_RWCTRL_READ_BNDRY_1024 |
  9637. DMA_RWCTRL_WRITE_BNDRY_1024);
  9638. break;
  9639. };
  9640. }
  9641. out:
  9642. return val;
  9643. }
  9644. static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
  9645. {
  9646. struct tg3_internal_buffer_desc test_desc;
  9647. u32 sram_dma_descs;
  9648. int i, ret;
  9649. sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
  9650. tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
  9651. tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
  9652. tw32(RDMAC_STATUS, 0);
  9653. tw32(WDMAC_STATUS, 0);
  9654. tw32(BUFMGR_MODE, 0);
  9655. tw32(FTQ_RESET, 0);
  9656. test_desc.addr_hi = ((u64) buf_dma) >> 32;
  9657. test_desc.addr_lo = buf_dma & 0xffffffff;
  9658. test_desc.nic_mbuf = 0x00002100;
  9659. test_desc.len = size;
  9660. /*
  9661. * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
  9662. * the *second* time the tg3 driver was getting loaded after an
  9663. * initial scan.
  9664. *
  9665. * Broadcom tells me:
  9666. * ...the DMA engine is connected to the GRC block and a DMA
  9667. * reset may affect the GRC block in some unpredictable way...
  9668. * The behavior of resets to individual blocks has not been tested.
  9669. *
  9670. * Broadcom noted the GRC reset will also reset all sub-components.
  9671. */
  9672. if (to_device) {
  9673. test_desc.cqid_sqid = (13 << 8) | 2;
  9674. tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
  9675. udelay(40);
  9676. } else {
  9677. test_desc.cqid_sqid = (16 << 8) | 7;
  9678. tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
  9679. udelay(40);
  9680. }
  9681. test_desc.flags = 0x00000005;
  9682. for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
  9683. u32 val;
  9684. val = *(((u32 *)&test_desc) + i);
  9685. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
  9686. sram_dma_descs + (i * sizeof(u32)));
  9687. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
  9688. }
  9689. pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
  9690. if (to_device) {
  9691. tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
  9692. } else {
  9693. tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
  9694. }
  9695. ret = -ENODEV;
  9696. for (i = 0; i < 40; i++) {
  9697. u32 val;
  9698. if (to_device)
  9699. val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
  9700. else
  9701. val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
  9702. if ((val & 0xffff) == sram_dma_descs) {
  9703. ret = 0;
  9704. break;
  9705. }
  9706. udelay(100);
  9707. }
  9708. return ret;
  9709. }
  9710. #define TEST_BUFFER_SIZE 0x2000
  9711. static int __devinit tg3_test_dma(struct tg3 *tp)
  9712. {
  9713. dma_addr_t buf_dma;
  9714. u32 *buf, saved_dma_rwctrl;
  9715. int ret;
  9716. buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
  9717. if (!buf) {
  9718. ret = -ENOMEM;
  9719. goto out_nofree;
  9720. }
  9721. tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
  9722. (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
  9723. tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
  9724. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9725. /* DMA read watermark not used on PCIE */
  9726. tp->dma_rwctrl |= 0x00180000;
  9727. } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
  9728. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
  9729. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
  9730. tp->dma_rwctrl |= 0x003f0000;
  9731. else
  9732. tp->dma_rwctrl |= 0x003f000f;
  9733. } else {
  9734. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  9735. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
  9736. u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
  9737. u32 read_water = 0x7;
  9738. /* If the 5704 is behind the EPB bridge, we can
  9739. * do the less restrictive ONE_DMA workaround for
  9740. * better performance.
  9741. */
  9742. if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
  9743. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  9744. tp->dma_rwctrl |= 0x8000;
  9745. else if (ccval == 0x6 || ccval == 0x7)
  9746. tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
  9747. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
  9748. read_water = 4;
  9749. /* Set bit 23 to enable PCIX hw bug fix */
  9750. tp->dma_rwctrl |=
  9751. (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
  9752. (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
  9753. (1 << 23);
  9754. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
  9755. /* 5780 always in PCIX mode */
  9756. tp->dma_rwctrl |= 0x00144000;
  9757. } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
  9758. /* 5714 always in PCIX mode */
  9759. tp->dma_rwctrl |= 0x00148000;
  9760. } else {
  9761. tp->dma_rwctrl |= 0x001b000f;
  9762. }
  9763. }
  9764. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
  9765. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
  9766. tp->dma_rwctrl &= 0xfffffff0;
  9767. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  9768. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
  9769. /* Remove this if it causes problems for some boards. */
  9770. tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
  9771. /* On 5700/5701 chips, we need to set this bit.
  9772. * Otherwise the chip will issue cacheline transactions
  9773. * to streamable DMA memory with not all the byte
  9774. * enables turned on. This is an error on several
  9775. * RISC PCI controllers, in particular sparc64.
  9776. *
  9777. * On 5703/5704 chips, this bit has been reassigned
  9778. * a different meaning. In particular, it is used
  9779. * on those chips to enable a PCI-X workaround.
  9780. */
  9781. tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
  9782. }
  9783. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9784. #if 0
  9785. /* Unneeded, already done by tg3_get_invariants. */
  9786. tg3_switch_clocks(tp);
  9787. #endif
  9788. ret = 0;
  9789. if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
  9790. GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
  9791. goto out;
  9792. /* It is best to perform DMA test with maximum write burst size
  9793. * to expose the 5700/5701 write DMA bug.
  9794. */
  9795. saved_dma_rwctrl = tp->dma_rwctrl;
  9796. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9797. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9798. while (1) {
  9799. u32 *p = buf, i;
  9800. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
  9801. p[i] = i;
  9802. /* Send the buffer to the chip. */
  9803. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
  9804. if (ret) {
  9805. printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
  9806. break;
  9807. }
  9808. #if 0
  9809. /* validate data reached card RAM correctly. */
  9810. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  9811. u32 val;
  9812. tg3_read_mem(tp, 0x2100 + (i*4), &val);
  9813. if (le32_to_cpu(val) != p[i]) {
  9814. printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
  9815. /* ret = -ENODEV here? */
  9816. }
  9817. p[i] = 0;
  9818. }
  9819. #endif
  9820. /* Now read it back. */
  9821. ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
  9822. if (ret) {
  9823. printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
  9824. break;
  9825. }
  9826. /* Verify it. */
  9827. for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
  9828. if (p[i] == i)
  9829. continue;
  9830. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  9831. DMA_RWCTRL_WRITE_BNDRY_16) {
  9832. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9833. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  9834. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9835. break;
  9836. } else {
  9837. printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
  9838. ret = -ENODEV;
  9839. goto out;
  9840. }
  9841. }
  9842. if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
  9843. /* Success. */
  9844. ret = 0;
  9845. break;
  9846. }
  9847. }
  9848. if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
  9849. DMA_RWCTRL_WRITE_BNDRY_16) {
  9850. static struct pci_device_id dma_wait_state_chipsets[] = {
  9851. { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
  9852. PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
  9853. { },
  9854. };
  9855. /* DMA test passed without adjusting DMA boundary,
  9856. * now look for chipsets that are known to expose the
  9857. * DMA bug without failing the test.
  9858. */
  9859. if (pci_dev_present(dma_wait_state_chipsets)) {
  9860. tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
  9861. tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
  9862. }
  9863. else
  9864. /* Safe to use the calculated DMA boundary. */
  9865. tp->dma_rwctrl = saved_dma_rwctrl;
  9866. tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
  9867. }
  9868. out:
  9869. pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
  9870. out_nofree:
  9871. return ret;
  9872. }
  9873. static void __devinit tg3_init_link_config(struct tg3 *tp)
  9874. {
  9875. tp->link_config.advertising =
  9876. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  9877. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
  9878. ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
  9879. ADVERTISED_Autoneg | ADVERTISED_MII);
  9880. tp->link_config.speed = SPEED_INVALID;
  9881. tp->link_config.duplex = DUPLEX_INVALID;
  9882. tp->link_config.autoneg = AUTONEG_ENABLE;
  9883. tp->link_config.active_speed = SPEED_INVALID;
  9884. tp->link_config.active_duplex = DUPLEX_INVALID;
  9885. tp->link_config.phy_is_low_power = 0;
  9886. tp->link_config.orig_speed = SPEED_INVALID;
  9887. tp->link_config.orig_duplex = DUPLEX_INVALID;
  9888. tp->link_config.orig_autoneg = AUTONEG_INVALID;
  9889. }
  9890. static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
  9891. {
  9892. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  9893. tp->bufmgr_config.mbuf_read_dma_low_water =
  9894. DEFAULT_MB_RDMA_LOW_WATER_5705;
  9895. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9896. DEFAULT_MB_MACRX_LOW_WATER_5705;
  9897. tp->bufmgr_config.mbuf_high_water =
  9898. DEFAULT_MB_HIGH_WATER_5705;
  9899. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
  9900. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9901. DEFAULT_MB_MACRX_LOW_WATER_5906;
  9902. tp->bufmgr_config.mbuf_high_water =
  9903. DEFAULT_MB_HIGH_WATER_5906;
  9904. }
  9905. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  9906. DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
  9907. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  9908. DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
  9909. tp->bufmgr_config.mbuf_high_water_jumbo =
  9910. DEFAULT_MB_HIGH_WATER_JUMBO_5780;
  9911. } else {
  9912. tp->bufmgr_config.mbuf_read_dma_low_water =
  9913. DEFAULT_MB_RDMA_LOW_WATER;
  9914. tp->bufmgr_config.mbuf_mac_rx_low_water =
  9915. DEFAULT_MB_MACRX_LOW_WATER;
  9916. tp->bufmgr_config.mbuf_high_water =
  9917. DEFAULT_MB_HIGH_WATER;
  9918. tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
  9919. DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
  9920. tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
  9921. DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
  9922. tp->bufmgr_config.mbuf_high_water_jumbo =
  9923. DEFAULT_MB_HIGH_WATER_JUMBO;
  9924. }
  9925. tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
  9926. tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
  9927. }
  9928. static char * __devinit tg3_phy_string(struct tg3 *tp)
  9929. {
  9930. switch (tp->phy_id & PHY_ID_MASK) {
  9931. case PHY_ID_BCM5400: return "5400";
  9932. case PHY_ID_BCM5401: return "5401";
  9933. case PHY_ID_BCM5411: return "5411";
  9934. case PHY_ID_BCM5701: return "5701";
  9935. case PHY_ID_BCM5703: return "5703";
  9936. case PHY_ID_BCM5704: return "5704";
  9937. case PHY_ID_BCM5705: return "5705";
  9938. case PHY_ID_BCM5750: return "5750";
  9939. case PHY_ID_BCM5752: return "5752";
  9940. case PHY_ID_BCM5714: return "5714";
  9941. case PHY_ID_BCM5780: return "5780";
  9942. case PHY_ID_BCM5755: return "5755";
  9943. case PHY_ID_BCM5787: return "5787";
  9944. case PHY_ID_BCM5784: return "5784";
  9945. case PHY_ID_BCM5756: return "5722/5756";
  9946. case PHY_ID_BCM5906: return "5906";
  9947. case PHY_ID_BCM8002: return "8002/serdes";
  9948. case 0: return "serdes";
  9949. default: return "unknown";
  9950. };
  9951. }
  9952. static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
  9953. {
  9954. if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
  9955. strcpy(str, "PCI Express");
  9956. return str;
  9957. } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
  9958. u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
  9959. strcpy(str, "PCIX:");
  9960. if ((clock_ctrl == 7) ||
  9961. ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
  9962. GRC_MISC_CFG_BOARD_ID_5704CIOBE))
  9963. strcat(str, "133MHz");
  9964. else if (clock_ctrl == 0)
  9965. strcat(str, "33MHz");
  9966. else if (clock_ctrl == 2)
  9967. strcat(str, "50MHz");
  9968. else if (clock_ctrl == 4)
  9969. strcat(str, "66MHz");
  9970. else if (clock_ctrl == 6)
  9971. strcat(str, "100MHz");
  9972. } else {
  9973. strcpy(str, "PCI:");
  9974. if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
  9975. strcat(str, "66MHz");
  9976. else
  9977. strcat(str, "33MHz");
  9978. }
  9979. if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
  9980. strcat(str, ":32-bit");
  9981. else
  9982. strcat(str, ":64-bit");
  9983. return str;
  9984. }
  9985. static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
  9986. {
  9987. struct pci_dev *peer;
  9988. unsigned int func, devnr = tp->pdev->devfn & ~7;
  9989. for (func = 0; func < 8; func++) {
  9990. peer = pci_get_slot(tp->pdev->bus, devnr | func);
  9991. if (peer && peer != tp->pdev)
  9992. break;
  9993. pci_dev_put(peer);
  9994. }
  9995. /* 5704 can be configured in single-port mode, set peer to
  9996. * tp->pdev in that case.
  9997. */
  9998. if (!peer) {
  9999. peer = tp->pdev;
  10000. return peer;
  10001. }
  10002. /*
  10003. * We don't need to keep the refcount elevated; there's no way
  10004. * to remove one half of this device without removing the other
  10005. */
  10006. pci_dev_put(peer);
  10007. return peer;
  10008. }
  10009. static void __devinit tg3_init_coal(struct tg3 *tp)
  10010. {
  10011. struct ethtool_coalesce *ec = &tp->coal;
  10012. memset(ec, 0, sizeof(*ec));
  10013. ec->cmd = ETHTOOL_GCOALESCE;
  10014. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
  10015. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
  10016. ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
  10017. ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
  10018. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
  10019. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
  10020. ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
  10021. ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
  10022. ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
  10023. if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
  10024. HOSTCC_MODE_CLRTICK_TXBD)) {
  10025. ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
  10026. ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
  10027. ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
  10028. ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
  10029. }
  10030. if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
  10031. ec->rx_coalesce_usecs_irq = 0;
  10032. ec->tx_coalesce_usecs_irq = 0;
  10033. ec->stats_block_coalesce_usecs = 0;
  10034. }
  10035. }
  10036. static int __devinit tg3_init_one(struct pci_dev *pdev,
  10037. const struct pci_device_id *ent)
  10038. {
  10039. static int tg3_version_printed = 0;
  10040. unsigned long tg3reg_base, tg3reg_len;
  10041. struct net_device *dev;
  10042. struct tg3 *tp;
  10043. int i, err, pm_cap;
  10044. char str[40];
  10045. u64 dma_mask, persist_dma_mask;
  10046. if (tg3_version_printed++ == 0)
  10047. printk(KERN_INFO "%s", version);
  10048. err = pci_enable_device(pdev);
  10049. if (err) {
  10050. printk(KERN_ERR PFX "Cannot enable PCI device, "
  10051. "aborting.\n");
  10052. return err;
  10053. }
  10054. if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
  10055. printk(KERN_ERR PFX "Cannot find proper PCI device "
  10056. "base address, aborting.\n");
  10057. err = -ENODEV;
  10058. goto err_out_disable_pdev;
  10059. }
  10060. err = pci_request_regions(pdev, DRV_MODULE_NAME);
  10061. if (err) {
  10062. printk(KERN_ERR PFX "Cannot obtain PCI resources, "
  10063. "aborting.\n");
  10064. goto err_out_disable_pdev;
  10065. }
  10066. pci_set_master(pdev);
  10067. /* Find power-management capability. */
  10068. pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  10069. if (pm_cap == 0) {
  10070. printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
  10071. "aborting.\n");
  10072. err = -EIO;
  10073. goto err_out_free_res;
  10074. }
  10075. tg3reg_base = pci_resource_start(pdev, 0);
  10076. tg3reg_len = pci_resource_len(pdev, 0);
  10077. dev = alloc_etherdev(sizeof(*tp));
  10078. if (!dev) {
  10079. printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
  10080. err = -ENOMEM;
  10081. goto err_out_free_res;
  10082. }
  10083. SET_NETDEV_DEV(dev, &pdev->dev);
  10084. #if TG3_VLAN_TAG_USED
  10085. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  10086. dev->vlan_rx_register = tg3_vlan_rx_register;
  10087. #endif
  10088. tp = netdev_priv(dev);
  10089. tp->pdev = pdev;
  10090. tp->dev = dev;
  10091. tp->pm_cap = pm_cap;
  10092. tp->mac_mode = TG3_DEF_MAC_MODE;
  10093. tp->rx_mode = TG3_DEF_RX_MODE;
  10094. tp->tx_mode = TG3_DEF_TX_MODE;
  10095. tp->mi_mode = MAC_MI_MODE_BASE;
  10096. if (tg3_debug > 0)
  10097. tp->msg_enable = tg3_debug;
  10098. else
  10099. tp->msg_enable = TG3_DEF_MSG_ENABLE;
  10100. /* The word/byte swap controls here control register access byte
  10101. * swapping. DMA data byte swapping is controlled in the GRC_MODE
  10102. * setting below.
  10103. */
  10104. tp->misc_host_ctrl =
  10105. MISC_HOST_CTRL_MASK_PCI_INT |
  10106. MISC_HOST_CTRL_WORD_SWAP |
  10107. MISC_HOST_CTRL_INDIR_ACCESS |
  10108. MISC_HOST_CTRL_PCISTATE_RW;
  10109. /* The NONFRM (non-frame) byte/word swap controls take effect
  10110. * on descriptor entries, anything which isn't packet data.
  10111. *
  10112. * The StrongARM chips on the board (one for tx, one for rx)
  10113. * are running in big-endian mode.
  10114. */
  10115. tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
  10116. GRC_MODE_WSWAP_NONFRM_DATA);
  10117. #ifdef __BIG_ENDIAN
  10118. tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
  10119. #endif
  10120. spin_lock_init(&tp->lock);
  10121. spin_lock_init(&tp->indirect_lock);
  10122. INIT_WORK(&tp->reset_task, tg3_reset_task);
  10123. tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
  10124. if (!tp->regs) {
  10125. printk(KERN_ERR PFX "Cannot map device registers, "
  10126. "aborting.\n");
  10127. err = -ENOMEM;
  10128. goto err_out_free_dev;
  10129. }
  10130. tg3_init_link_config(tp);
  10131. tp->rx_pending = TG3_DEF_RX_RING_PENDING;
  10132. tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
  10133. tp->tx_pending = TG3_DEF_TX_RING_PENDING;
  10134. dev->open = tg3_open;
  10135. dev->stop = tg3_close;
  10136. dev->get_stats = tg3_get_stats;
  10137. dev->set_multicast_list = tg3_set_rx_mode;
  10138. dev->set_mac_address = tg3_set_mac_addr;
  10139. dev->do_ioctl = tg3_ioctl;
  10140. dev->tx_timeout = tg3_tx_timeout;
  10141. netif_napi_add(dev, &tp->napi, tg3_poll, 64);
  10142. dev->ethtool_ops = &tg3_ethtool_ops;
  10143. dev->watchdog_timeo = TG3_TX_TIMEOUT;
  10144. dev->change_mtu = tg3_change_mtu;
  10145. dev->irq = pdev->irq;
  10146. #ifdef CONFIG_NET_POLL_CONTROLLER
  10147. dev->poll_controller = tg3_poll_controller;
  10148. #endif
  10149. err = tg3_get_invariants(tp);
  10150. if (err) {
  10151. printk(KERN_ERR PFX "Problem fetching invariants of chip, "
  10152. "aborting.\n");
  10153. goto err_out_iounmap;
  10154. }
  10155. /* The EPB bridge inside 5714, 5715, and 5780 and any
  10156. * device behind the EPB cannot support DMA addresses > 40-bit.
  10157. * On 64-bit systems with IOMMU, use 40-bit dma_mask.
  10158. * On 64-bit systems without IOMMU, use 64-bit dma_mask and
  10159. * do DMA address check in tg3_start_xmit().
  10160. */
  10161. if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
  10162. persist_dma_mask = dma_mask = DMA_32BIT_MASK;
  10163. else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
  10164. persist_dma_mask = dma_mask = DMA_40BIT_MASK;
  10165. #ifdef CONFIG_HIGHMEM
  10166. dma_mask = DMA_64BIT_MASK;
  10167. #endif
  10168. } else
  10169. persist_dma_mask = dma_mask = DMA_64BIT_MASK;
  10170. /* Configure DMA attributes. */
  10171. if (dma_mask > DMA_32BIT_MASK) {
  10172. err = pci_set_dma_mask(pdev, dma_mask);
  10173. if (!err) {
  10174. dev->features |= NETIF_F_HIGHDMA;
  10175. err = pci_set_consistent_dma_mask(pdev,
  10176. persist_dma_mask);
  10177. if (err < 0) {
  10178. printk(KERN_ERR PFX "Unable to obtain 64 bit "
  10179. "DMA for consistent allocations\n");
  10180. goto err_out_iounmap;
  10181. }
  10182. }
  10183. }
  10184. if (err || dma_mask == DMA_32BIT_MASK) {
  10185. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  10186. if (err) {
  10187. printk(KERN_ERR PFX "No usable DMA configuration, "
  10188. "aborting.\n");
  10189. goto err_out_iounmap;
  10190. }
  10191. }
  10192. tg3_init_bufmgr_config(tp);
  10193. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10194. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
  10195. }
  10196. else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
  10197. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
  10198. tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
  10199. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
  10200. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
  10201. tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
  10202. } else {
  10203. tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
  10204. }
  10205. /* TSO is on by default on chips that support hardware TSO.
  10206. * Firmware TSO on older chips gives lower performance, so it
  10207. * is off by default, but can be enabled using ethtool.
  10208. */
  10209. if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
  10210. dev->features |= NETIF_F_TSO;
  10211. if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
  10212. (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
  10213. dev->features |= NETIF_F_TSO6;
  10214. }
  10215. if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
  10216. !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
  10217. !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
  10218. tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
  10219. tp->rx_pending = 63;
  10220. }
  10221. err = tg3_get_device_address(tp);
  10222. if (err) {
  10223. printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
  10224. "aborting.\n");
  10225. goto err_out_iounmap;
  10226. }
  10227. /*
  10228. * Reset chip in case UNDI or EFI driver did not shutdown
  10229. * DMA self test will enable WDMAC and we'll see (spurious)
  10230. * pending DMA on the PCI bus at that point.
  10231. */
  10232. if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
  10233. (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
  10234. tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
  10235. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10236. }
  10237. err = tg3_test_dma(tp);
  10238. if (err) {
  10239. printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
  10240. goto err_out_iounmap;
  10241. }
  10242. /* Tigon3 can do ipv4 only... and some chips have buggy
  10243. * checksumming.
  10244. */
  10245. if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
  10246. dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
  10247. if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
  10248. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
  10249. GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)
  10250. dev->features |= NETIF_F_IPV6_CSUM;
  10251. tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
  10252. } else
  10253. tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
  10254. /* flow control autonegotiation is default behavior */
  10255. tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
  10256. tg3_init_coal(tp);
  10257. pci_set_drvdata(pdev, dev);
  10258. err = register_netdev(dev);
  10259. if (err) {
  10260. printk(KERN_ERR PFX "Cannot register net device, "
  10261. "aborting.\n");
  10262. goto err_out_iounmap;
  10263. }
  10264. printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
  10265. dev->name,
  10266. tp->board_part_number,
  10267. tp->pci_chip_rev_id,
  10268. tg3_phy_string(tp),
  10269. tg3_bus_string(tp, str),
  10270. ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
  10271. ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
  10272. "10/100/1000Base-T")));
  10273. for (i = 0; i < 6; i++)
  10274. printk("%2.2x%c", dev->dev_addr[i],
  10275. i == 5 ? '\n' : ':');
  10276. printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
  10277. "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
  10278. dev->name,
  10279. (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
  10280. (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
  10281. (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
  10282. (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
  10283. (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
  10284. (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
  10285. printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
  10286. dev->name, tp->dma_rwctrl,
  10287. (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
  10288. (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
  10289. return 0;
  10290. err_out_iounmap:
  10291. if (tp->regs) {
  10292. iounmap(tp->regs);
  10293. tp->regs = NULL;
  10294. }
  10295. err_out_free_dev:
  10296. free_netdev(dev);
  10297. err_out_free_res:
  10298. pci_release_regions(pdev);
  10299. err_out_disable_pdev:
  10300. pci_disable_device(pdev);
  10301. pci_set_drvdata(pdev, NULL);
  10302. return err;
  10303. }
  10304. static void __devexit tg3_remove_one(struct pci_dev *pdev)
  10305. {
  10306. struct net_device *dev = pci_get_drvdata(pdev);
  10307. if (dev) {
  10308. struct tg3 *tp = netdev_priv(dev);
  10309. flush_scheduled_work();
  10310. unregister_netdev(dev);
  10311. if (tp->regs) {
  10312. iounmap(tp->regs);
  10313. tp->regs = NULL;
  10314. }
  10315. free_netdev(dev);
  10316. pci_release_regions(pdev);
  10317. pci_disable_device(pdev);
  10318. pci_set_drvdata(pdev, NULL);
  10319. }
  10320. }
  10321. static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
  10322. {
  10323. struct net_device *dev = pci_get_drvdata(pdev);
  10324. struct tg3 *tp = netdev_priv(dev);
  10325. int err;
  10326. /* PCI register 4 needs to be saved whether netif_running() or not.
  10327. * MSI address and data need to be saved if using MSI and
  10328. * netif_running().
  10329. */
  10330. pci_save_state(pdev);
  10331. if (!netif_running(dev))
  10332. return 0;
  10333. flush_scheduled_work();
  10334. tg3_netif_stop(tp);
  10335. del_timer_sync(&tp->timer);
  10336. tg3_full_lock(tp, 1);
  10337. tg3_disable_ints(tp);
  10338. tg3_full_unlock(tp);
  10339. netif_device_detach(dev);
  10340. tg3_full_lock(tp, 0);
  10341. tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
  10342. tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
  10343. tg3_full_unlock(tp);
  10344. err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
  10345. if (err) {
  10346. tg3_full_lock(tp, 0);
  10347. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  10348. if (tg3_restart_hw(tp, 1))
  10349. goto out;
  10350. tp->timer.expires = jiffies + tp->timer_offset;
  10351. add_timer(&tp->timer);
  10352. netif_device_attach(dev);
  10353. tg3_netif_start(tp);
  10354. out:
  10355. tg3_full_unlock(tp);
  10356. }
  10357. return err;
  10358. }
  10359. static int tg3_resume(struct pci_dev *pdev)
  10360. {
  10361. struct net_device *dev = pci_get_drvdata(pdev);
  10362. struct tg3 *tp = netdev_priv(dev);
  10363. int err;
  10364. pci_restore_state(tp->pdev);
  10365. if (!netif_running(dev))
  10366. return 0;
  10367. err = tg3_set_power_state(tp, PCI_D0);
  10368. if (err)
  10369. return err;
  10370. /* Hardware bug - MSI won't work if INTX disabled. */
  10371. if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
  10372. (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
  10373. pci_intx(tp->pdev, 1);
  10374. netif_device_attach(dev);
  10375. tg3_full_lock(tp, 0);
  10376. tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
  10377. err = tg3_restart_hw(tp, 1);
  10378. if (err)
  10379. goto out;
  10380. tp->timer.expires = jiffies + tp->timer_offset;
  10381. add_timer(&tp->timer);
  10382. tg3_netif_start(tp);
  10383. out:
  10384. tg3_full_unlock(tp);
  10385. return err;
  10386. }
  10387. static struct pci_driver tg3_driver = {
  10388. .name = DRV_MODULE_NAME,
  10389. .id_table = tg3_pci_tbl,
  10390. .probe = tg3_init_one,
  10391. .remove = __devexit_p(tg3_remove_one),
  10392. .suspend = tg3_suspend,
  10393. .resume = tg3_resume
  10394. };
  10395. static int __init tg3_init(void)
  10396. {
  10397. return pci_register_driver(&tg3_driver);
  10398. }
  10399. static void __exit tg3_cleanup(void)
  10400. {
  10401. pci_unregister_driver(&tg3_driver);
  10402. }
  10403. module_init(tg3_init);
  10404. module_exit(tg3_cleanup);