board-bockw.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239
  1. /*
  2. * Bock-W board support
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/mfd/tmio.h>
  21. #include <linux/mmc/host.h>
  22. #include <linux/mtd/partitions.h>
  23. #include <linux/pinctrl/machine.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/regulator/fixed.h>
  26. #include <linux/regulator/machine.h>
  27. #include <linux/smsc911x.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/spi/flash.h>
  30. #include <mach/common.h>
  31. #include <mach/irqs.h>
  32. #include <mach/r8a7778.h>
  33. #include <asm/mach/arch.h>
  34. /*
  35. * CN9(Upper side) SCIF/RCAN selection
  36. *
  37. * 1,4 3,6
  38. * SW40 SCIF RCAN
  39. * SW41 SCIF RCAN
  40. */
  41. /*
  42. * MMC (CN26) pin
  43. *
  44. * SW6 (D2) 3 pin
  45. * SW7 (D5) ON
  46. * SW8 (D3) 3 pin
  47. * SW10 (D4) 1 pin
  48. * SW12 (CLK) 1 pin
  49. * SW13 (D6) 3 pin
  50. * SW14 (CMD) ON
  51. * SW15 (D6) 1 pin
  52. * SW16 (D0) ON
  53. * SW17 (D1) ON
  54. * SW18 (D7) 3 pin
  55. * SW19 (MMC) 1 pin
  56. */
  57. /* Dummy supplies, where voltage doesn't matter */
  58. static struct regulator_consumer_supply dummy_supplies[] = {
  59. REGULATOR_SUPPLY("vddvario", "smsc911x"),
  60. REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  61. };
  62. static struct smsc911x_platform_config smsc911x_data = {
  63. .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  64. .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
  65. .flags = SMSC911X_USE_32BIT,
  66. .phy_interface = PHY_INTERFACE_MODE_MII,
  67. };
  68. static struct resource smsc911x_resources[] = {
  69. DEFINE_RES_MEM(0x18300000, 0x1000),
  70. DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  71. };
  72. /* SDHI */
  73. static struct sh_mobile_sdhi_info sdhi0_info = {
  74. .tmio_caps = MMC_CAP_SD_HIGHSPEED,
  75. .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  76. .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
  77. };
  78. static struct sh_eth_plat_data ether_platform_data __initdata = {
  79. .phy = 0x01,
  80. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  81. .register_type = SH_ETH_REG_FAST_RCAR,
  82. .phy_interface = PHY_INTERFACE_MODE_RMII,
  83. /*
  84. * Although the LINK signal is available on the board, it's connected to
  85. * the link/activity LED output of the PHY, thus the link disappears and
  86. * reappears after each packet. We'd be better off ignoring such signal
  87. * and getting the link state from the PHY indirectly.
  88. */
  89. .no_ether_link = 1,
  90. };
  91. /* I2C */
  92. static struct i2c_board_info i2c0_devices[] = {
  93. {
  94. I2C_BOARD_INFO("rx8581", 0x51),
  95. },
  96. };
  97. /* HSPI*/
  98. static struct mtd_partition m25p80_spi_flash_partitions[] = {
  99. {
  100. .name = "data(spi)",
  101. .size = 0x0100000,
  102. .offset = 0,
  103. },
  104. };
  105. static struct flash_platform_data spi_flash_data = {
  106. .name = "m25p80",
  107. .type = "s25fl008k",
  108. .parts = m25p80_spi_flash_partitions,
  109. .nr_parts = ARRAY_SIZE(m25p80_spi_flash_partitions),
  110. };
  111. static struct spi_board_info spi_board_info[] __initdata = {
  112. {
  113. .modalias = "m25p80",
  114. .max_speed_hz = 104000000,
  115. .chip_select = 0,
  116. .bus_num = 0,
  117. .mode = SPI_MODE_0,
  118. .platform_data = &spi_flash_data,
  119. },
  120. };
  121. /* MMC */
  122. static struct sh_mmcif_plat_data sh_mmcif_plat = {
  123. .sup_pclk = 0,
  124. .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  125. .caps = MMC_CAP_4_BIT_DATA |
  126. MMC_CAP_8_BIT_DATA |
  127. MMC_CAP_NEEDS_POLL,
  128. };
  129. static const struct pinctrl_map bockw_pinctrl_map[] = {
  130. /* Ether */
  131. PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
  132. "ether_rmii", "ether"),
  133. /* HSPI0 */
  134. PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
  135. "hspi0_a", "hspi0"),
  136. /* MMC */
  137. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  138. "mmc_data8", "mmc"),
  139. PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
  140. "mmc_ctrl", "mmc"),
  141. /* SCIF0 */
  142. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  143. "scif0_data_a", "scif0"),
  144. PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
  145. "scif0_ctrl", "scif0"),
  146. /* SDHI0 */
  147. PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
  148. "sdhi0", "sdhi0"),
  149. };
  150. #define FPGA 0x18200000
  151. #define IRQ0MR 0x30
  152. #define PFC 0xfffc0000
  153. #define PUPR4 0x110
  154. static void __init bockw_init(void)
  155. {
  156. void __iomem *base;
  157. r8a7778_clock_init();
  158. r8a7778_init_irq_extpin(1);
  159. r8a7778_add_standard_devices();
  160. r8a7778_add_ether_device(&ether_platform_data);
  161. r8a7778_add_i2c_device(0);
  162. r8a7778_add_hspi_device(0);
  163. r8a7778_add_mmc_device(&sh_mmcif_plat);
  164. i2c_register_board_info(0, i2c0_devices,
  165. ARRAY_SIZE(i2c0_devices));
  166. spi_register_board_info(spi_board_info,
  167. ARRAY_SIZE(spi_board_info));
  168. pinctrl_register_mappings(bockw_pinctrl_map,
  169. ARRAY_SIZE(bockw_pinctrl_map));
  170. r8a7778_pinmux_init();
  171. /* for SMSC */
  172. base = ioremap_nocache(FPGA, SZ_1M);
  173. if (base) {
  174. /*
  175. * CAUTION
  176. *
  177. * IRQ0/1 is cascaded interrupt from FPGA.
  178. * it should be cared in the future
  179. * Now, it is assuming IRQ0 was used only from SMSC.
  180. */
  181. u16 val = ioread16(base + IRQ0MR);
  182. val &= ~(1 << 4); /* enable SMSC911x */
  183. iowrite16(val, base + IRQ0MR);
  184. iounmap(base);
  185. regulator_register_fixed(0, dummy_supplies,
  186. ARRAY_SIZE(dummy_supplies));
  187. platform_device_register_resndata(
  188. &platform_bus, "smsc911x", -1,
  189. smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
  190. &smsc911x_data, sizeof(smsc911x_data));
  191. }
  192. /* for SDHI */
  193. base = ioremap_nocache(PFC, 0x200);
  194. if (base) {
  195. /*
  196. * FIXME
  197. *
  198. * SDHI CD/WP pin needs pull-up
  199. */
  200. iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
  201. iounmap(base);
  202. r8a7778_sdhi_init(0, &sdhi0_info);
  203. }
  204. }
  205. static const char *bockw_boards_compat_dt[] __initdata = {
  206. "renesas,bockw",
  207. NULL,
  208. };
  209. DT_MACHINE_START(BOCKW_DT, "bockw")
  210. .init_early = r8a7778_init_delay,
  211. .init_irq = r8a7778_init_irq_dt,
  212. .init_machine = bockw_init,
  213. .init_time = shmobile_timer_init,
  214. .dt_compat = bockw_boards_compat_dt,
  215. MACHINE_END