main.c 224 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929593059315932593359345935593659375938593959405941594259435944594559465947594859495950595159525953595459555956595759585959596059615962596359645965596659675968596959705971597259735974597559765977597859795980598159825983598459855986598759885989599059915992599359945995599659975998599960006001600260036004600560066007600860096010601160126013601460156016601760186019602060216022602360246025602660276028602960306031603260336034603560366037603860396040604160426043604460456046604760486049605060516052605360546055605660576058605960606061606260636064606560666067606860696070607160726073607460756076607760786079608060816082608360846085608660876088608960906091609260936094609560966097609860996100610161026103610461056106610761086109611061116112611361146115611661176118611961206121612261236124612561266127612861296130613161326133613461356136613761386139614061416142614361446145614661476148614961506151615261536154615561566157615861596160616161626163616461656166616761686169617061716172617361746175617661776178617961806181618261836184618561866187618861896190619161926193619461956196619761986199620062016202620362046205620662076208620962106211621262136214621562166217621862196220622162226223622462256226622762286229623062316232623362346235623662376238623962406241624262436244624562466247624862496250625162526253625462556256625762586259626062616262626362646265626662676268626962706271627262736274627562766277627862796280628162826283628462856286628762886289629062916292629362946295629662976298629963006301630263036304630563066307630863096310631163126313631463156316631763186319632063216322632363246325632663276328632963306331633263336334633563366337633863396340634163426343634463456346634763486349635063516352635363546355635663576358635963606361636263636364636563666367636863696370637163726373637463756376637763786379638063816382638363846385638663876388638963906391639263936394639563966397639863996400640164026403640464056406640764086409641064116412641364146415641664176418641964206421642264236424642564266427642864296430643164326433643464356436643764386439644064416442644364446445644664476448644964506451645264536454645564566457645864596460646164626463646464656466646764686469647064716472647364746475647664776478647964806481648264836484648564866487648864896490649164926493649464956496649764986499650065016502650365046505650665076508650965106511651265136514651565166517651865196520652165226523652465256526652765286529653065316532653365346535653665376538653965406541654265436544654565466547654865496550655165526553655465556556655765586559656065616562656365646565656665676568656965706571657265736574657565766577657865796580658165826583658465856586658765886589659065916592659365946595659665976598659966006601660266036604660566066607660866096610661166126613661466156616661766186619662066216622662366246625662666276628662966306631663266336634663566366637663866396640664166426643664466456646664766486649665066516652665366546655665666576658665966606661666266636664666566666667666866696670667166726673667466756676667766786679668066816682668366846685668666876688668966906691669266936694669566966697669866996700670167026703670467056706670767086709671067116712671367146715671667176718671967206721672267236724672567266727672867296730673167326733673467356736673767386739674067416742674367446745674667476748674967506751675267536754675567566757675867596760676167626763676467656766676767686769677067716772677367746775677667776778677967806781678267836784678567866787678867896790679167926793679467956796679767986799680068016802680368046805680668076808680968106811681268136814681568166817681868196820682168226823682468256826682768286829683068316832683368346835683668376838683968406841684268436844684568466847684868496850685168526853685468556856685768586859686068616862686368646865686668676868686968706871687268736874687568766877687868796880688168826883688468856886688768886889689068916892689368946895689668976898689969006901690269036904690569066907690869096910691169126913691469156916691769186919692069216922692369246925692669276928692969306931693269336934693569366937693869396940694169426943694469456946694769486949695069516952695369546955695669576958695969606961696269636964696569666967696869696970697169726973697469756976697769786979698069816982698369846985698669876988698969906991699269936994699569966997699869997000700170027003700470057006700770087009701070117012701370147015701670177018701970207021702270237024702570267027702870297030703170327033703470357036703770387039704070417042704370447045704670477048704970507051705270537054705570567057705870597060706170627063706470657066706770687069707070717072707370747075707670777078707970807081708270837084708570867087708870897090709170927093709470957096709770987099710071017102710371047105710671077108710971107111711271137114711571167117711871197120712171227123712471257126712771287129713071317132713371347135713671377138713971407141714271437144714571467147714871497150715171527153715471557156715771587159716071617162716371647165716671677168716971707171717271737174717571767177717871797180718171827183718471857186718771887189719071917192719371947195719671977198719972007201720272037204720572067207720872097210721172127213721472157216721772187219722072217222722372247225722672277228722972307231723272337234723572367237723872397240724172427243724472457246724772487249725072517252725372547255725672577258725972607261726272637264726572667267726872697270727172727273727472757276727772787279728072817282728372847285728672877288728972907291729272937294729572967297729872997300730173027303730473057306730773087309731073117312731373147315731673177318731973207321732273237324732573267327732873297330733173327333733473357336733773387339734073417342734373447345734673477348734973507351735273537354735573567357735873597360736173627363736473657366736773687369737073717372737373747375737673777378737973807381738273837384738573867387738873897390739173927393739473957396739773987399740074017402740374047405740674077408740974107411741274137414741574167417741874197420742174227423742474257426742774287429743074317432743374347435743674377438743974407441744274437444744574467447744874497450745174527453745474557456745774587459746074617462746374647465746674677468746974707471747274737474747574767477747874797480748174827483748474857486748774887489749074917492749374947495749674977498749975007501750275037504750575067507750875097510751175127513751475157516751775187519752075217522752375247525752675277528752975307531753275337534753575367537753875397540754175427543754475457546754775487549755075517552755375547555755675577558755975607561756275637564756575667567756875697570757175727573757475757576757775787579758075817582758375847585758675877588758975907591759275937594759575967597759875997600760176027603760476057606760776087609761076117612761376147615761676177618761976207621762276237624762576267627762876297630763176327633763476357636763776387639764076417642764376447645764676477648764976507651765276537654765576567657765876597660766176627663766476657666766776687669767076717672767376747675767676777678767976807681768276837684768576867687768876897690769176927693769476957696769776987699770077017702770377047705770677077708770977107711771277137714771577167717771877197720772177227723772477257726772777287729773077317732773377347735773677377738773977407741774277437744774577467747774877497750775177527753775477557756775777587759776077617762776377647765776677677768776977707771777277737774777577767777777877797780778177827783778477857786778777887789779077917792779377947795779677977798779978007801780278037804780578067807780878097810781178127813781478157816781778187819782078217822782378247825782678277828782978307831783278337834783578367837783878397840784178427843784478457846784778487849785078517852785378547855785678577858785978607861786278637864786578667867786878697870787178727873787478757876787778787879788078817882788378847885788678877888788978907891789278937894789578967897789878997900790179027903790479057906790779087909791079117912791379147915791679177918791979207921792279237924792579267927792879297930793179327933793479357936793779387939794079417942794379447945794679477948794979507951795279537954795579567957795879597960796179627963796479657966796779687969797079717972797379747975797679777978797979807981798279837984798579867987798879897990799179927993799479957996799779987999800080018002800380048005800680078008800980108011801280138014801580168017801880198020802180228023802480258026802780288029803080318032803380348035803680378038803980408041804280438044804580468047804880498050805180528053805480558056805780588059806080618062806380648065806680678068806980708071807280738074807580768077807880798080808180828083808480858086808780888089809080918092809380948095809680978098809981008101810281038104810581068107810881098110811181128113811481158116811781188119812081218122812381248125812681278128812981308131813281338134813581368137813881398140814181428143814481458146814781488149815081518152815381548155815681578158815981608161816281638164816581668167816881698170817181728173817481758176817781788179818081818182818381848185818681878188818981908191819281938194819581968197819881998200820182028203820482058206820782088209821082118212821382148215821682178218821982208221822282238224822582268227822882298230823182328233823482358236823782388239824082418242824382448245824682478248824982508251825282538254825582568257825882598260826182628263826482658266826782688269827082718272827382748275827682778278827982808281828282838284828582868287828882898290829182928293829482958296829782988299830083018302830383048305830683078308830983108311831283138314831583168317831883198320832183228323832483258326832783288329833083318332833383348335833683378338833983408341834283438344834583468347834883498350835183528353835483558356835783588359836083618362836383648365836683678368836983708371837283738374837583768377837883798380838183828383838483858386838783888389839083918392839383948395839683978398839984008401840284038404840584068407840884098410841184128413841484158416841784188419842084218422842384248425842684278428842984308431843284338434843584368437843884398440844184428443844484458446844784488449845084518452845384548455845684578458845984608461846284638464846584668467846884698470847184728473847484758476847784788479848084818482848384848485848684878488848984908491849284938494849584968497849884998500850185028503850485058506850785088509851085118512851385148515851685178518851985208521852285238524852585268527852885298530853185328533853485358536853785388539854085418542854385448545854685478548854985508551855285538554
  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/pci_ids.h>
  17. #include <linux/if_ether.h>
  18. #include <net/mac80211.h>
  19. #include <brcm_hw_ids.h>
  20. #include <aiutils.h>
  21. #include <chipcommon.h>
  22. #include "rate.h"
  23. #include "scb.h"
  24. #include "phy/phy_hal.h"
  25. #include "channel.h"
  26. #include "antsel.h"
  27. #include "stf.h"
  28. #include "ampdu.h"
  29. #include "mac80211_if.h"
  30. #include "ucode_loader.h"
  31. #include "main.h"
  32. #include "soc.h"
  33. /*
  34. * Indication for txflowcontrol that all priority bits in
  35. * TXQ_STOP_FOR_PRIOFC_MASK are to be considered.
  36. */
  37. #define ALLPRIO -1
  38. /* watchdog timer, in unit of ms */
  39. #define TIMER_INTERVAL_WATCHDOG 1000
  40. /* radio monitor timer, in unit of ms */
  41. #define TIMER_INTERVAL_RADIOCHK 800
  42. /* beacon interval, in unit of 1024TU */
  43. #define BEACON_INTERVAL_DEFAULT 100
  44. /* n-mode support capability */
  45. /* 2x2 includes both 1x1 & 2x2 devices
  46. * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
  47. * control it independently
  48. */
  49. #define WL_11N_2x2 1
  50. #define WL_11N_3x3 3
  51. #define WL_11N_4x4 4
  52. #define EDCF_ACI_MASK 0x60
  53. #define EDCF_ACI_SHIFT 5
  54. #define EDCF_ECWMIN_MASK 0x0f
  55. #define EDCF_ECWMAX_SHIFT 4
  56. #define EDCF_AIFSN_MASK 0x0f
  57. #define EDCF_AIFSN_MAX 15
  58. #define EDCF_ECWMAX_MASK 0xf0
  59. #define EDCF_AC_BE_TXOP_STA 0x0000
  60. #define EDCF_AC_BK_TXOP_STA 0x0000
  61. #define EDCF_AC_VO_ACI_STA 0x62
  62. #define EDCF_AC_VO_ECW_STA 0x32
  63. #define EDCF_AC_VI_ACI_STA 0x42
  64. #define EDCF_AC_VI_ECW_STA 0x43
  65. #define EDCF_AC_BK_ECW_STA 0xA4
  66. #define EDCF_AC_VI_TXOP_STA 0x005e
  67. #define EDCF_AC_VO_TXOP_STA 0x002f
  68. #define EDCF_AC_BE_ACI_STA 0x03
  69. #define EDCF_AC_BE_ECW_STA 0xA4
  70. #define EDCF_AC_BK_ACI_STA 0x27
  71. #define EDCF_AC_VO_TXOP_AP 0x002f
  72. #define EDCF_TXOP2USEC(txop) ((txop) << 5)
  73. #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
  74. #define APHY_SYMBOL_TIME 4
  75. #define APHY_PREAMBLE_TIME 16
  76. #define APHY_SIGNAL_TIME 4
  77. #define APHY_SIFS_TIME 16
  78. #define APHY_SERVICE_NBITS 16
  79. #define APHY_TAIL_NBITS 6
  80. #define BPHY_SIFS_TIME 10
  81. #define BPHY_PLCP_SHORT_TIME 96
  82. #define PREN_PREAMBLE 24
  83. #define PREN_MM_EXT 12
  84. #define PREN_PREAMBLE_EXT 4
  85. #define DOT11_MAC_HDR_LEN 24
  86. #define DOT11_ACK_LEN 10
  87. #define DOT11_BA_LEN 4
  88. #define DOT11_OFDM_SIGNAL_EXTENSION 6
  89. #define DOT11_MIN_FRAG_LEN 256
  90. #define DOT11_RTS_LEN 16
  91. #define DOT11_CTS_LEN 10
  92. #define DOT11_BA_BITMAP_LEN 128
  93. #define DOT11_MIN_BEACON_PERIOD 1
  94. #define DOT11_MAX_BEACON_PERIOD 0xFFFF
  95. #define DOT11_MAXNUMFRAGS 16
  96. #define DOT11_MAX_FRAG_LEN 2346
  97. #define BPHY_PLCP_TIME 192
  98. #define RIFS_11N_TIME 2
  99. #define AC_BE 0
  100. #define AC_BK 1
  101. #define AC_VI 2
  102. #define AC_VO 3
  103. /* length of the BCN template area */
  104. #define BCN_TMPL_LEN 512
  105. /* brcms_bss_info flag bit values */
  106. #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
  107. /* chip rx buffer offset */
  108. #define BRCMS_HWRXOFF 38
  109. /* rfdisable delay timer 500 ms, runs of ALP clock */
  110. #define RFDISABLE_DEFAULT 10000000
  111. #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
  112. /* precedences numbers for wlc queues. These are twice as may levels as
  113. * 802.1D priorities.
  114. * Odd numbers are used for HI priority traffic at same precedence levels
  115. * These constants are used ONLY by wlc_prio2prec_map. Do not use them
  116. * elsewhere.
  117. */
  118. #define _BRCMS_PREC_NONE 0 /* None = - */
  119. #define _BRCMS_PREC_BK 2 /* BK - Background */
  120. #define _BRCMS_PREC_BE 4 /* BE - Best-effort */
  121. #define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
  122. #define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
  123. #define _BRCMS_PREC_VI 10 /* Vi - Video */
  124. #define _BRCMS_PREC_VO 12 /* Vo - Voice */
  125. #define _BRCMS_PREC_NC 14 /* NC - Network Control */
  126. /* synthpu_dly times in us */
  127. #define SYNTHPU_DLY_APHY_US 3700
  128. #define SYNTHPU_DLY_BPHY_US 1050
  129. #define SYNTHPU_DLY_NPHY_US 2048
  130. #define SYNTHPU_DLY_LPPHY_US 300
  131. #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
  132. /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
  133. #define EDCF_SHORT_S 0
  134. #define EDCF_SFB_S 4
  135. #define EDCF_LONG_S 8
  136. #define EDCF_LFB_S 12
  137. #define EDCF_SHORT_M BITFIELD_MASK(4)
  138. #define EDCF_SFB_M BITFIELD_MASK(4)
  139. #define EDCF_LONG_M BITFIELD_MASK(4)
  140. #define EDCF_LFB_M BITFIELD_MASK(4)
  141. #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
  142. #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
  143. #define RETRY_LONG_DEF 4 /* Default Long retry count */
  144. #define RETRY_SHORT_FB 3 /* Short count for fb rate */
  145. #define RETRY_LONG_FB 2 /* Long count for fb rate */
  146. #define APHY_CWMIN 15
  147. #define PHY_CWMAX 1023
  148. #define EDCF_AIFSN_MIN 1
  149. #define FRAGNUM_MASK 0xF
  150. #define APHY_SLOT_TIME 9
  151. #define BPHY_SLOT_TIME 20
  152. #define WL_SPURAVOID_OFF 0
  153. #define WL_SPURAVOID_ON1 1
  154. #define WL_SPURAVOID_ON2 2
  155. /* invalid core flags, use the saved coreflags */
  156. #define BRCMS_USE_COREFLAGS 0xffffffff
  157. /* values for PLCPHdr_override */
  158. #define BRCMS_PLCP_AUTO -1
  159. #define BRCMS_PLCP_SHORT 0
  160. #define BRCMS_PLCP_LONG 1
  161. /* values for g_protection_override and n_protection_override */
  162. #define BRCMS_PROTECTION_AUTO -1
  163. #define BRCMS_PROTECTION_OFF 0
  164. #define BRCMS_PROTECTION_ON 1
  165. #define BRCMS_PROTECTION_MMHDR_ONLY 2
  166. #define BRCMS_PROTECTION_CTS_ONLY 3
  167. /* values for g_protection_control and n_protection_control */
  168. #define BRCMS_PROTECTION_CTL_OFF 0
  169. #define BRCMS_PROTECTION_CTL_LOCAL 1
  170. #define BRCMS_PROTECTION_CTL_OVERLAP 2
  171. /* values for n_protection */
  172. #define BRCMS_N_PROTECTION_OFF 0
  173. #define BRCMS_N_PROTECTION_OPTIONAL 1
  174. #define BRCMS_N_PROTECTION_20IN40 2
  175. #define BRCMS_N_PROTECTION_MIXEDMODE 3
  176. /* values for band specific 40MHz capabilities */
  177. #define BRCMS_N_BW_20ALL 0
  178. #define BRCMS_N_BW_40ALL 1
  179. #define BRCMS_N_BW_20IN2G_40IN5G 2
  180. /* bitflags for SGI support (sgi_rx iovar) */
  181. #define BRCMS_N_SGI_20 0x01
  182. #define BRCMS_N_SGI_40 0x02
  183. /* defines used by the nrate iovar */
  184. /* MSC in use,indicates b0-6 holds an mcs */
  185. #define NRATE_MCS_INUSE 0x00000080
  186. /* rate/mcs value */
  187. #define NRATE_RATE_MASK 0x0000007f
  188. /* stf mode mask: siso, cdd, stbc, sdm */
  189. #define NRATE_STF_MASK 0x0000ff00
  190. /* stf mode shift */
  191. #define NRATE_STF_SHIFT 8
  192. /* bit indicate to override mcs only */
  193. #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
  194. #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
  195. #define NRATE_SGI_SHIFT 23 /* sgi mode */
  196. #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
  197. #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
  198. #define NRATE_STF_SISO 0 /* stf mode SISO */
  199. #define NRATE_STF_CDD 1 /* stf mode CDD */
  200. #define NRATE_STF_STBC 2 /* stf mode STBC */
  201. #define NRATE_STF_SDM 3 /* stf mode SDM */
  202. #define MAX_DMA_SEGS 4
  203. /* Max # of entries in Tx FIFO based on 4kb page size */
  204. #define NTXD 256
  205. /* Max # of entries in Rx FIFO based on 4kb page size */
  206. #define NRXD 256
  207. /* try to keep this # rbufs posted to the chip */
  208. #define NRXBUFPOST 32
  209. /* data msg txq hiwat mark */
  210. #define BRCMS_DATAHIWAT 50
  211. /* max # frames to process in brcms_c_recv() */
  212. #define RXBND 8
  213. /* max # tx status to process in wlc_txstatus() */
  214. #define TXSBND 8
  215. /* brcmu_format_flags() bit description structure */
  216. struct brcms_c_bit_desc {
  217. u32 bit;
  218. const char *name;
  219. };
  220. /*
  221. * The following table lists the buffer memory allocated to xmt fifos in HW.
  222. * the size is in units of 256bytes(one block), total size is HW dependent
  223. * ucode has default fifo partition, sw can overwrite if necessary
  224. *
  225. * This is documented in twiki under the topic UcodeTxFifo. Please ensure
  226. * the twiki is updated before making changes.
  227. */
  228. /* Starting corerev for the fifo size table */
  229. #define XMTFIFOTBL_STARTREV 20
  230. struct d11init {
  231. __le16 addr;
  232. __le16 size;
  233. __le32 value;
  234. };
  235. struct edcf_acparam {
  236. u8 ACI;
  237. u8 ECW;
  238. u16 TXOP;
  239. } __packed;
  240. const u8 prio2fifo[NUMPRIO] = {
  241. TX_AC_BE_FIFO, /* 0 BE AC_BE Best Effort */
  242. TX_AC_BK_FIFO, /* 1 BK AC_BK Background */
  243. TX_AC_BK_FIFO, /* 2 -- AC_BK Background */
  244. TX_AC_BE_FIFO, /* 3 EE AC_BE Best Effort */
  245. TX_AC_VI_FIFO, /* 4 CL AC_VI Video */
  246. TX_AC_VI_FIFO, /* 5 VI AC_VI Video */
  247. TX_AC_VO_FIFO, /* 6 VO AC_VO Voice */
  248. TX_AC_VO_FIFO /* 7 NC AC_VO Voice */
  249. };
  250. /* debug/trace */
  251. uint brcm_msg_level =
  252. #if defined(BCMDBG)
  253. LOG_ERROR_VAL;
  254. #else
  255. 0;
  256. #endif /* BCMDBG */
  257. /* TX FIFO number to WME/802.1E Access Category */
  258. static const u8 wme_fifo2ac[] = { AC_BK, AC_BE, AC_VI, AC_VO, AC_BE, AC_BE };
  259. /* WME/802.1E Access Category to TX FIFO number */
  260. static const u8 wme_ac2fifo[] = { 1, 0, 2, 3 };
  261. /* 802.1D Priority to precedence queue mapping */
  262. const u8 wlc_prio2prec_map[] = {
  263. _BRCMS_PREC_BE, /* 0 BE - Best-effort */
  264. _BRCMS_PREC_BK, /* 1 BK - Background */
  265. _BRCMS_PREC_NONE, /* 2 None = - */
  266. _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */
  267. _BRCMS_PREC_CL, /* 4 CL - Controlled Load */
  268. _BRCMS_PREC_VI, /* 5 Vi - Video */
  269. _BRCMS_PREC_VO, /* 6 Vo - Voice */
  270. _BRCMS_PREC_NC, /* 7 NC - Network Control */
  271. };
  272. static const u16 xmtfifo_sz[][NFIFO] = {
  273. /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
  274. {20, 192, 192, 21, 17, 5},
  275. /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
  276. {9, 58, 22, 14, 14, 5},
  277. /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
  278. {20, 192, 192, 21, 17, 5},
  279. /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
  280. {20, 192, 192, 21, 17, 5},
  281. /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
  282. {9, 58, 22, 14, 14, 5},
  283. };
  284. #ifdef BCMDBG
  285. static const char * const fifo_names[] = {
  286. "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
  287. #else
  288. static const char fifo_names[6][0];
  289. #endif
  290. #ifdef BCMDBG
  291. /* pointer to most recently allocated wl/wlc */
  292. static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
  293. #endif
  294. /* Find basic rate for a given rate */
  295. static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
  296. {
  297. if (is_mcs_rate(rspec))
  298. return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
  299. .leg_ofdm];
  300. return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
  301. }
  302. static u16 frametype(u32 rspec, u8 mimoframe)
  303. {
  304. if (is_mcs_rate(rspec))
  305. return mimoframe;
  306. return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
  307. }
  308. /* currently the best mechanism for determining SIFS is the band in use */
  309. static u16 get_sifs(struct brcms_band *band)
  310. {
  311. return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
  312. BPHY_SIFS_TIME;
  313. }
  314. /*
  315. * Detect Card removed.
  316. * Even checking an sbconfig register read will not false trigger when the core
  317. * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
  318. * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
  319. * reg with fixed 0/1 pattern (some platforms return all 0).
  320. * If clocks are present, call the sb routine which will figure out if the
  321. * device is removed.
  322. */
  323. static bool brcms_deviceremoved(struct brcms_c_info *wlc)
  324. {
  325. if (!wlc->hw->clk)
  326. return ai_deviceremoved(wlc->hw->sih);
  327. return (R_REG(&wlc->hw->regs->maccontrol) &
  328. (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
  329. }
  330. /* sum the individual fifo tx pending packet counts */
  331. static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
  332. {
  333. return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
  334. wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
  335. }
  336. static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
  337. {
  338. return wlc->pub->_nbands > 1 && !wlc->bandlocked;
  339. }
  340. static int brcms_chspec_bw(u16 chanspec)
  341. {
  342. if (CHSPEC_IS40(chanspec))
  343. return BRCMS_40_MHZ;
  344. if (CHSPEC_IS20(chanspec))
  345. return BRCMS_20_MHZ;
  346. return BRCMS_10_MHZ;
  347. }
  348. static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
  349. {
  350. if (cfg == NULL)
  351. return;
  352. kfree(cfg->current_bss);
  353. kfree(cfg);
  354. }
  355. static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
  356. {
  357. if (wlc == NULL)
  358. return;
  359. brcms_c_bsscfg_mfree(wlc->bsscfg);
  360. kfree(wlc->pub);
  361. kfree(wlc->modulecb);
  362. kfree(wlc->default_bss);
  363. kfree(wlc->protection);
  364. kfree(wlc->stf);
  365. kfree(wlc->bandstate[0]);
  366. kfree(wlc->corestate->macstat_snapshot);
  367. kfree(wlc->corestate);
  368. kfree(wlc->hw->bandstate[0]);
  369. kfree(wlc->hw);
  370. /* free the wlc */
  371. kfree(wlc);
  372. wlc = NULL;
  373. }
  374. static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
  375. {
  376. struct brcms_bss_cfg *cfg;
  377. cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
  378. if (cfg == NULL)
  379. goto fail;
  380. cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  381. if (cfg->current_bss == NULL)
  382. goto fail;
  383. return cfg;
  384. fail:
  385. brcms_c_bsscfg_mfree(cfg);
  386. return NULL;
  387. }
  388. static struct brcms_c_info *
  389. brcms_c_attach_malloc(uint unit, uint *err, uint devid)
  390. {
  391. struct brcms_c_info *wlc;
  392. wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
  393. if (wlc == NULL) {
  394. *err = 1002;
  395. goto fail;
  396. }
  397. /* allocate struct brcms_c_pub state structure */
  398. wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
  399. if (wlc->pub == NULL) {
  400. *err = 1003;
  401. goto fail;
  402. }
  403. wlc->pub->wlc = wlc;
  404. /* allocate struct brcms_hardware state structure */
  405. wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
  406. if (wlc->hw == NULL) {
  407. *err = 1005;
  408. goto fail;
  409. }
  410. wlc->hw->wlc = wlc;
  411. wlc->hw->bandstate[0] =
  412. kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
  413. if (wlc->hw->bandstate[0] == NULL) {
  414. *err = 1006;
  415. goto fail;
  416. } else {
  417. int i;
  418. for (i = 1; i < MAXBANDS; i++)
  419. wlc->hw->bandstate[i] = (struct brcms_hw_band *)
  420. ((unsigned long)wlc->hw->bandstate[0] +
  421. (sizeof(struct brcms_hw_band) * i));
  422. }
  423. wlc->modulecb =
  424. kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
  425. if (wlc->modulecb == NULL) {
  426. *err = 1009;
  427. goto fail;
  428. }
  429. wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
  430. if (wlc->default_bss == NULL) {
  431. *err = 1010;
  432. goto fail;
  433. }
  434. wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
  435. if (wlc->bsscfg == NULL) {
  436. *err = 1011;
  437. goto fail;
  438. }
  439. wlc->protection = kzalloc(sizeof(struct brcms_protection),
  440. GFP_ATOMIC);
  441. if (wlc->protection == NULL) {
  442. *err = 1016;
  443. goto fail;
  444. }
  445. wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
  446. if (wlc->stf == NULL) {
  447. *err = 1017;
  448. goto fail;
  449. }
  450. wlc->bandstate[0] =
  451. kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
  452. if (wlc->bandstate[0] == NULL) {
  453. *err = 1025;
  454. goto fail;
  455. } else {
  456. int i;
  457. for (i = 1; i < MAXBANDS; i++)
  458. wlc->bandstate[i] = (struct brcms_band *)
  459. ((unsigned long)wlc->bandstate[0]
  460. + (sizeof(struct brcms_band)*i));
  461. }
  462. wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
  463. if (wlc->corestate == NULL) {
  464. *err = 1026;
  465. goto fail;
  466. }
  467. wlc->corestate->macstat_snapshot =
  468. kzalloc(sizeof(struct macstat), GFP_ATOMIC);
  469. if (wlc->corestate->macstat_snapshot == NULL) {
  470. *err = 1027;
  471. goto fail;
  472. }
  473. return wlc;
  474. fail:
  475. brcms_c_detach_mfree(wlc);
  476. return NULL;
  477. }
  478. /*
  479. * Update the slot timing for standard 11b/g (20us slots)
  480. * or shortslot 11g (9us slots)
  481. * The PSM needs to be suspended for this call.
  482. */
  483. static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
  484. bool shortslot)
  485. {
  486. struct d11regs __iomem *regs;
  487. regs = wlc_hw->regs;
  488. if (shortslot) {
  489. /* 11g short slot: 11a timing */
  490. W_REG(&regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
  491. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
  492. } else {
  493. /* 11g long slot: 11b timing */
  494. W_REG(&regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
  495. brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
  496. }
  497. }
  498. /*
  499. * calculate frame duration of a given rate and length, return
  500. * time in usec unit
  501. */
  502. static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
  503. u8 preamble_type, uint mac_len)
  504. {
  505. uint nsyms, dur = 0, Ndps, kNdps;
  506. uint rate = rspec2rate(ratespec);
  507. if (rate == 0) {
  508. wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
  509. wlc->pub->unit);
  510. rate = BRCM_RATE_1M;
  511. }
  512. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
  513. wlc->pub->unit, ratespec, preamble_type, mac_len);
  514. if (is_mcs_rate(ratespec)) {
  515. uint mcs = ratespec & RSPEC_RATE_MASK;
  516. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  517. dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  518. if (preamble_type == BRCMS_MM_PREAMBLE)
  519. dur += PREN_MM_EXT;
  520. /* 1000Ndbps = kbps * 4 */
  521. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  522. rspec_issgi(ratespec)) * 4;
  523. if (rspec_stc(ratespec) == 0)
  524. nsyms =
  525. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  526. APHY_TAIL_NBITS) * 1000, kNdps);
  527. else
  528. /* STBC needs to have even number of symbols */
  529. nsyms =
  530. 2 *
  531. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  532. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  533. dur += APHY_SYMBOL_TIME * nsyms;
  534. if (wlc->band->bandtype == BRCM_BAND_2G)
  535. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  536. } else if (is_ofdm_rate(rate)) {
  537. dur = APHY_PREAMBLE_TIME;
  538. dur += APHY_SIGNAL_TIME;
  539. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  540. Ndps = rate * 2;
  541. /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
  542. nsyms =
  543. CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
  544. Ndps);
  545. dur += APHY_SYMBOL_TIME * nsyms;
  546. if (wlc->band->bandtype == BRCM_BAND_2G)
  547. dur += DOT11_OFDM_SIGNAL_EXTENSION;
  548. } else {
  549. /*
  550. * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
  551. * will divide out
  552. */
  553. mac_len = mac_len * 8 * 2;
  554. /* calc ceiling of bits/rate = microseconds of air time */
  555. dur = (mac_len + rate - 1) / rate;
  556. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  557. dur += BPHY_PLCP_SHORT_TIME;
  558. else
  559. dur += BPHY_PLCP_TIME;
  560. }
  561. return dur;
  562. }
  563. static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
  564. const struct d11init *inits)
  565. {
  566. int i;
  567. u8 __iomem *base;
  568. u8 __iomem *addr;
  569. u16 size;
  570. u32 value;
  571. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  572. base = (u8 __iomem *)wlc_hw->regs;
  573. for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
  574. size = le16_to_cpu(inits[i].size);
  575. addr = base + le16_to_cpu(inits[i].addr);
  576. value = le32_to_cpu(inits[i].value);
  577. if (size == 2)
  578. W_REG((u16 __iomem *)addr, value);
  579. else if (size == 4)
  580. W_REG((u32 __iomem *)addr, value);
  581. else
  582. break;
  583. }
  584. }
  585. static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
  586. {
  587. u8 idx;
  588. u16 addr[] = {
  589. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  590. M_HOST_FLAGS5
  591. };
  592. for (idx = 0; idx < MHFMAX; idx++)
  593. brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
  594. }
  595. static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
  596. {
  597. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  598. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  599. /* init microcode host flags */
  600. brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
  601. /* do band-specific ucode IHR, SHM, and SCR inits */
  602. if (D11REV_IS(wlc_hw->corerev, 23)) {
  603. if (BRCMS_ISNPHY(wlc_hw->band))
  604. brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
  605. else
  606. wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
  607. " %d\n", __func__, wlc_hw->unit,
  608. wlc_hw->corerev);
  609. } else {
  610. if (D11REV_IS(wlc_hw->corerev, 24)) {
  611. if (BRCMS_ISLCNPHY(wlc_hw->band))
  612. brcms_c_write_inits(wlc_hw,
  613. ucode->d11lcn0bsinitvals24);
  614. else
  615. wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
  616. " core rev %d\n", __func__,
  617. wlc_hw->unit, wlc_hw->corerev);
  618. } else {
  619. wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
  620. __func__, wlc_hw->unit, wlc_hw->corerev);
  621. }
  622. }
  623. }
  624. static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
  625. {
  626. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
  627. wlc_hw->phyclk = clk;
  628. if (OFF == clk) { /* clear gmode bit, put phy into reset */
  629. ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
  630. (SICF_PRST | SICF_FGC));
  631. udelay(1);
  632. ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
  633. udelay(1);
  634. } else { /* take phy out of reset */
  635. ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
  636. udelay(1);
  637. ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
  638. udelay(1);
  639. }
  640. }
  641. /* low-level band switch utility routine */
  642. static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
  643. {
  644. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  645. bandunit);
  646. wlc_hw->band = wlc_hw->bandstate[bandunit];
  647. /*
  648. * BMAC_NOTE:
  649. * until we eliminate need for wlc->band refs in low level code
  650. */
  651. wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
  652. /* set gmode core flag */
  653. if (wlc_hw->sbclk && !wlc_hw->noreset)
  654. ai_core_cflags(wlc_hw->sih, SICF_GMODE,
  655. ((bandunit == 0) ? SICF_GMODE : 0));
  656. }
  657. /* switch to new band but leave it inactive */
  658. static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
  659. {
  660. struct brcms_hardware *wlc_hw = wlc->hw;
  661. u32 macintmask;
  662. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  663. WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
  664. /* disable interrupts */
  665. macintmask = brcms_intrsoff(wlc->wl);
  666. /* radio off */
  667. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  668. brcms_b_core_phy_clk(wlc_hw, OFF);
  669. brcms_c_setxband(wlc_hw, bandunit);
  670. return macintmask;
  671. }
  672. /* process an individual struct tx_status */
  673. static bool
  674. brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
  675. {
  676. struct sk_buff *p;
  677. uint queue;
  678. struct d11txh *txh;
  679. struct scb *scb = NULL;
  680. bool free_pdu;
  681. int tx_rts, tx_frame_count, tx_rts_count;
  682. uint totlen, supr_status;
  683. bool lastframe;
  684. struct ieee80211_hdr *h;
  685. u16 mcl;
  686. struct ieee80211_tx_info *tx_info;
  687. struct ieee80211_tx_rate *txrate;
  688. int i;
  689. /* discard intermediate indications for ucode with one legitimate case:
  690. * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
  691. * but the subsequent tx of DATA failed. so it will start rts/cts
  692. * from the beginning (resetting the rts transmission count)
  693. */
  694. if (!(txs->status & TX_STATUS_AMPDU)
  695. && (txs->status & TX_STATUS_INTERMEDIATE)) {
  696. wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
  697. __func__);
  698. return false;
  699. }
  700. queue = txs->frameid & TXFID_QUEUE_MASK;
  701. if (queue >= NFIFO) {
  702. p = NULL;
  703. goto fatal;
  704. }
  705. p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
  706. if (p == NULL)
  707. goto fatal;
  708. txh = (struct d11txh *) (p->data);
  709. mcl = le16_to_cpu(txh->MacTxControlLow);
  710. if (txs->phyerr) {
  711. if (brcm_msg_level & LOG_ERROR_VAL) {
  712. wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
  713. txs->phyerr, txh->MainRates);
  714. brcms_c_print_txdesc(txh);
  715. }
  716. brcms_c_print_txstatus(txs);
  717. }
  718. if (txs->frameid != le16_to_cpu(txh->TxFrameID))
  719. goto fatal;
  720. tx_info = IEEE80211_SKB_CB(p);
  721. h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
  722. if (tx_info->control.sta)
  723. scb = &wlc->pri_scb;
  724. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  725. brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
  726. return false;
  727. }
  728. supr_status = txs->status & TX_STATUS_SUPR_MASK;
  729. if (supr_status == TX_STATUS_SUPR_BADCH)
  730. BCMMSG(wlc->wiphy,
  731. "%s: Pkt tx suppressed, possibly channel %d\n",
  732. __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
  733. tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
  734. tx_frame_count =
  735. (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
  736. tx_rts_count =
  737. (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
  738. lastframe = !ieee80211_has_morefrags(h->frame_control);
  739. if (!lastframe) {
  740. wiphy_err(wlc->wiphy, "Not last frame!\n");
  741. } else {
  742. /*
  743. * Set information to be consumed by Minstrel ht.
  744. *
  745. * The "fallback limit" is the number of tx attempts a given
  746. * MPDU is sent at the "primary" rate. Tx attempts beyond that
  747. * limit are sent at the "secondary" rate.
  748. * A 'short frame' does not exceed RTS treshold.
  749. */
  750. u16 sfbl, /* Short Frame Rate Fallback Limit */
  751. lfbl, /* Long Frame Rate Fallback Limit */
  752. fbl;
  753. if (queue < AC_COUNT) {
  754. sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  755. EDCF_SFB);
  756. lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
  757. EDCF_LFB);
  758. } else {
  759. sfbl = wlc->SFBL;
  760. lfbl = wlc->LFBL;
  761. }
  762. txrate = tx_info->status.rates;
  763. if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
  764. fbl = lfbl;
  765. else
  766. fbl = sfbl;
  767. ieee80211_tx_info_clear_status(tx_info);
  768. if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
  769. /*
  770. * rate selection requested a fallback rate
  771. * and we used it
  772. */
  773. txrate[0].count = fbl;
  774. txrate[1].count = tx_frame_count - fbl;
  775. } else {
  776. /*
  777. * rate selection did not request fallback rate, or
  778. * we didn't need it
  779. */
  780. txrate[0].count = tx_frame_count;
  781. /*
  782. * rc80211_minstrel.c:minstrel_tx_status() expects
  783. * unused rates to be marked with idx = -1
  784. */
  785. txrate[1].idx = -1;
  786. txrate[1].count = 0;
  787. }
  788. /* clear the rest of the rates */
  789. for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
  790. txrate[i].idx = -1;
  791. txrate[i].count = 0;
  792. }
  793. if (txs->status & TX_STATUS_ACK_RCV)
  794. tx_info->flags |= IEEE80211_TX_STAT_ACK;
  795. }
  796. totlen = brcmu_pkttotlen(p);
  797. free_pdu = true;
  798. brcms_c_txfifo_complete(wlc, queue, 1);
  799. if (lastframe) {
  800. p->next = NULL;
  801. p->prev = NULL;
  802. /* remove PLCP & Broadcom tx descriptor header */
  803. skb_pull(p, D11_PHY_HDR_LEN);
  804. skb_pull(p, D11_TXH_LEN);
  805. ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
  806. } else {
  807. wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
  808. "tx_status\n", __func__);
  809. }
  810. return false;
  811. fatal:
  812. if (p)
  813. brcmu_pkt_buf_free_skb(p);
  814. return true;
  815. }
  816. /* process tx completion events in BMAC
  817. * Return true if more tx status need to be processed. false otherwise.
  818. */
  819. static bool
  820. brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
  821. {
  822. bool morepending = false;
  823. struct brcms_c_info *wlc = wlc_hw->wlc;
  824. struct d11regs __iomem *regs;
  825. struct tx_status txstatus, *txs;
  826. u32 s1, s2;
  827. uint n = 0;
  828. /*
  829. * Param 'max_tx_num' indicates max. # tx status to process before
  830. * break out.
  831. */
  832. uint max_tx_num = bound ? TXSBND : -1;
  833. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  834. txs = &txstatus;
  835. regs = wlc_hw->regs;
  836. *fatal = false;
  837. while (!(*fatal)
  838. && (s1 = R_REG(&regs->frmtxstatus)) & TXS_V) {
  839. if (s1 == 0xffffffff) {
  840. wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
  841. wlc_hw->unit, __func__);
  842. return morepending;
  843. }
  844. s2 = R_REG(&regs->frmtxstatus2);
  845. txs->status = s1 & TXS_STATUS_MASK;
  846. txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
  847. txs->sequence = s2 & TXS_SEQ_MASK;
  848. txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
  849. txs->lasttxtime = 0;
  850. *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
  851. /* !give others some time to run! */
  852. if (++n >= max_tx_num)
  853. break;
  854. }
  855. if (*fatal)
  856. return 0;
  857. if (n >= max_tx_num)
  858. morepending = true;
  859. if (!pktq_empty(&wlc->pkt_queue->q))
  860. brcms_c_send_q(wlc);
  861. return morepending;
  862. }
  863. static void brcms_c_tbtt(struct brcms_c_info *wlc)
  864. {
  865. if (!wlc->bsscfg->BSS)
  866. /*
  867. * DirFrmQ is now valid...defer setting until end
  868. * of ATIM window
  869. */
  870. wlc->qvalid |= MCMD_DIRFRMQVAL;
  871. }
  872. /* set initial host flags value */
  873. static void
  874. brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
  875. {
  876. struct brcms_hardware *wlc_hw = wlc->hw;
  877. memset(mhfs, 0, MHFMAX * sizeof(u16));
  878. mhfs[MHF2] |= mhf2_init;
  879. /* prohibit use of slowclock on multifunction boards */
  880. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  881. mhfs[MHF1] |= MHF1_FORCEFASTCLK;
  882. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
  883. mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
  884. mhfs[MHF1] |= MHF1_IQSWAP_WAR;
  885. }
  886. }
  887. static struct dma64regs __iomem *
  888. dmareg(struct brcms_hardware *hw, uint direction, uint fifonum)
  889. {
  890. if (direction == DMA_TX)
  891. return &(hw->regs->fifo64regs[fifonum].dmaxmt);
  892. return &(hw->regs->fifo64regs[fifonum].dmarcv);
  893. }
  894. static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
  895. {
  896. uint i;
  897. char name[8];
  898. /*
  899. * ucode host flag 2 needed for pio mode, independent of band and fifo
  900. */
  901. u16 pio_mhf2 = 0;
  902. struct brcms_hardware *wlc_hw = wlc->hw;
  903. uint unit = wlc_hw->unit;
  904. struct wiphy *wiphy = wlc->wiphy;
  905. /* name and offsets for dma_attach */
  906. snprintf(name, sizeof(name), "wl%d", unit);
  907. if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
  908. int dma_attach_err = 0;
  909. /*
  910. * FIFO 0
  911. * TX: TX_AC_BK_FIFO (TX AC Background data packets)
  912. * RX: RX_FIFO (RX data packets)
  913. */
  914. wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
  915. (wme ? dmareg(wlc_hw, DMA_TX, 0) :
  916. NULL), dmareg(wlc_hw, DMA_RX, 0),
  917. (wme ? NTXD : 0), NRXD,
  918. RXBUFSZ, -1, NRXBUFPOST,
  919. BRCMS_HWRXOFF, &brcm_msg_level);
  920. dma_attach_err |= (NULL == wlc_hw->di[0]);
  921. /*
  922. * FIFO 1
  923. * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
  924. * (legacy) TX_DATA_FIFO (TX data packets)
  925. * RX: UNUSED
  926. */
  927. wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
  928. dmareg(wlc_hw, DMA_TX, 1), NULL,
  929. NTXD, 0, 0, -1, 0, 0,
  930. &brcm_msg_level);
  931. dma_attach_err |= (NULL == wlc_hw->di[1]);
  932. /*
  933. * FIFO 2
  934. * TX: TX_AC_VI_FIFO (TX AC Video data packets)
  935. * RX: UNUSED
  936. */
  937. wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
  938. dmareg(wlc_hw, DMA_TX, 2), NULL,
  939. NTXD, 0, 0, -1, 0, 0,
  940. &brcm_msg_level);
  941. dma_attach_err |= (NULL == wlc_hw->di[2]);
  942. /*
  943. * FIFO 3
  944. * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
  945. * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
  946. */
  947. wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
  948. dmareg(wlc_hw, DMA_TX, 3),
  949. NULL, NTXD, 0, 0, -1,
  950. 0, 0, &brcm_msg_level);
  951. dma_attach_err |= (NULL == wlc_hw->di[3]);
  952. /* Cleaner to leave this as if with AP defined */
  953. if (dma_attach_err) {
  954. wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
  955. "\n", unit);
  956. return false;
  957. }
  958. /* get pointer to dma engine tx flow control variable */
  959. for (i = 0; i < NFIFO; i++)
  960. if (wlc_hw->di[i])
  961. wlc_hw->txavail[i] =
  962. (uint *) dma_getvar(wlc_hw->di[i],
  963. "&txavail");
  964. }
  965. /* initial ucode host flags */
  966. brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
  967. return true;
  968. }
  969. static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
  970. {
  971. uint j;
  972. for (j = 0; j < NFIFO; j++) {
  973. if (wlc_hw->di[j]) {
  974. dma_detach(wlc_hw->di[j]);
  975. wlc_hw->di[j] = NULL;
  976. }
  977. }
  978. }
  979. /*
  980. * Initialize brcms_c_info default values ...
  981. * may get overrides later in this function
  982. * BMAC_NOTES, move low out and resolve the dangling ones
  983. */
  984. static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
  985. {
  986. struct brcms_c_info *wlc = wlc_hw->wlc;
  987. /* set default sw macintmask value */
  988. wlc->defmacintmask = DEF_MACINTMASK;
  989. /* various 802.11g modes */
  990. wlc_hw->shortslot = false;
  991. wlc_hw->SFBL = RETRY_SHORT_FB;
  992. wlc_hw->LFBL = RETRY_LONG_FB;
  993. /* default mac retry limits */
  994. wlc_hw->SRL = RETRY_SHORT_DEF;
  995. wlc_hw->LRL = RETRY_LONG_DEF;
  996. wlc_hw->chanspec = ch20mhz_chspec(1);
  997. }
  998. static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
  999. {
  1000. /* delay before first read of ucode state */
  1001. udelay(40);
  1002. /* wait until ucode is no longer asleep */
  1003. SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
  1004. DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
  1005. }
  1006. /* control chip clock to save power, enable dynamic clock or force fast clock */
  1007. static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, uint mode)
  1008. {
  1009. if (wlc_hw->sih->cccaps & CC_CAP_PMU) {
  1010. /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
  1011. * on backplane, but mac core will still run on ALP(not HT) when
  1012. * it enters powersave mode, which means the FCA bit may not be
  1013. * set. Should wakeup mac if driver wants it to run on HT.
  1014. */
  1015. if (wlc_hw->clk) {
  1016. if (mode == CLK_FAST) {
  1017. OR_REG(&wlc_hw->regs->clk_ctl_st,
  1018. CCS_FORCEHT);
  1019. udelay(64);
  1020. SPINWAIT(((R_REG
  1021. (&wlc_hw->regs->
  1022. clk_ctl_st) & CCS_HTAVAIL) == 0),
  1023. PMU_MAX_TRANSITION_DLY);
  1024. WARN_ON(!(R_REG
  1025. (&wlc_hw->regs->
  1026. clk_ctl_st) & CCS_HTAVAIL));
  1027. } else {
  1028. if ((wlc_hw->sih->pmurev == 0) &&
  1029. (R_REG
  1030. (&wlc_hw->regs->
  1031. clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
  1032. SPINWAIT(((R_REG
  1033. (&wlc_hw->regs->
  1034. clk_ctl_st) & CCS_HTAVAIL)
  1035. == 0),
  1036. PMU_MAX_TRANSITION_DLY);
  1037. AND_REG(&wlc_hw->regs->clk_ctl_st,
  1038. ~CCS_FORCEHT);
  1039. }
  1040. }
  1041. wlc_hw->forcefastclk = (mode == CLK_FAST);
  1042. } else {
  1043. /* old chips w/o PMU, force HT through cc,
  1044. * then use FCA to verify mac is running fast clock
  1045. */
  1046. wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
  1047. /* check fast clock is available (if core is not in reset) */
  1048. if (wlc_hw->forcefastclk && wlc_hw->clk)
  1049. WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
  1050. SISF_FCLKA));
  1051. /*
  1052. * keep the ucode wake bit on if forcefastclk is on since we
  1053. * do not want ucode to put us back to slow clock when it dozes
  1054. * for PM mode. Code below matches the wake override bit with
  1055. * current forcefastclk state. Only setting bit in wake_override
  1056. * instead of waking ucode immediately since old code had this
  1057. * behavior. Older code set wlc->forcefastclk but only had the
  1058. * wake happen if the wakup_ucode work (protected by an up
  1059. * check) was executed just below.
  1060. */
  1061. if (wlc_hw->forcefastclk)
  1062. mboolset(wlc_hw->wake_override,
  1063. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1064. else
  1065. mboolclr(wlc_hw->wake_override,
  1066. BRCMS_WAKE_OVERRIDE_FORCEFAST);
  1067. }
  1068. }
  1069. /* set or clear ucode host flag bits
  1070. * it has an optimization for no-change write
  1071. * it only writes through shared memory when the core has clock;
  1072. * pre-CLK changes should use wlc_write_mhf to get around the optimization
  1073. *
  1074. *
  1075. * bands values are: BRCM_BAND_AUTO <--- Current band only
  1076. * BRCM_BAND_5G <--- 5G band only
  1077. * BRCM_BAND_2G <--- 2G band only
  1078. * BRCM_BAND_ALL <--- All bands
  1079. */
  1080. void
  1081. brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
  1082. int bands)
  1083. {
  1084. u16 save;
  1085. u16 addr[MHFMAX] = {
  1086. M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
  1087. M_HOST_FLAGS5
  1088. };
  1089. struct brcms_hw_band *band;
  1090. if ((val & ~mask) || idx >= MHFMAX)
  1091. return; /* error condition */
  1092. switch (bands) {
  1093. /* Current band only or all bands,
  1094. * then set the band to current band
  1095. */
  1096. case BRCM_BAND_AUTO:
  1097. case BRCM_BAND_ALL:
  1098. band = wlc_hw->band;
  1099. break;
  1100. case BRCM_BAND_5G:
  1101. band = wlc_hw->bandstate[BAND_5G_INDEX];
  1102. break;
  1103. case BRCM_BAND_2G:
  1104. band = wlc_hw->bandstate[BAND_2G_INDEX];
  1105. break;
  1106. default:
  1107. band = NULL; /* error condition */
  1108. }
  1109. if (band) {
  1110. save = band->mhfs[idx];
  1111. band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
  1112. /* optimization: only write through if changed, and
  1113. * changed band is the current band
  1114. */
  1115. if (wlc_hw->clk && (band->mhfs[idx] != save)
  1116. && (band == wlc_hw->band))
  1117. brcms_b_write_shm(wlc_hw, addr[idx],
  1118. (u16) band->mhfs[idx]);
  1119. }
  1120. if (bands == BRCM_BAND_ALL) {
  1121. wlc_hw->bandstate[0]->mhfs[idx] =
  1122. (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
  1123. wlc_hw->bandstate[1]->mhfs[idx] =
  1124. (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
  1125. }
  1126. }
  1127. /* set the maccontrol register to desired reset state and
  1128. * initialize the sw cache of the register
  1129. */
  1130. static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
  1131. {
  1132. /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
  1133. wlc_hw->maccontrol = 0;
  1134. wlc_hw->suspended_fifos = 0;
  1135. wlc_hw->wake_override = 0;
  1136. wlc_hw->mute_override = 0;
  1137. brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
  1138. }
  1139. /*
  1140. * write the software state of maccontrol and
  1141. * overrides to the maccontrol register
  1142. */
  1143. static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
  1144. {
  1145. u32 maccontrol = wlc_hw->maccontrol;
  1146. /* OR in the wake bit if overridden */
  1147. if (wlc_hw->wake_override)
  1148. maccontrol |= MCTL_WAKE;
  1149. /* set AP and INFRA bits for mute if needed */
  1150. if (wlc_hw->mute_override) {
  1151. maccontrol &= ~(MCTL_AP);
  1152. maccontrol |= MCTL_INFRA;
  1153. }
  1154. W_REG(&wlc_hw->regs->maccontrol, maccontrol);
  1155. }
  1156. /* set or clear maccontrol bits */
  1157. void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
  1158. {
  1159. u32 maccontrol;
  1160. u32 new_maccontrol;
  1161. if (val & ~mask)
  1162. return; /* error condition */
  1163. maccontrol = wlc_hw->maccontrol;
  1164. new_maccontrol = (maccontrol & ~mask) | val;
  1165. /* if the new maccontrol value is the same as the old, nothing to do */
  1166. if (new_maccontrol == maccontrol)
  1167. return;
  1168. /* something changed, cache the new value */
  1169. wlc_hw->maccontrol = new_maccontrol;
  1170. /* write the new values with overrides applied */
  1171. brcms_c_mctrl_write(wlc_hw);
  1172. }
  1173. void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
  1174. u32 override_bit)
  1175. {
  1176. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
  1177. mboolset(wlc_hw->wake_override, override_bit);
  1178. return;
  1179. }
  1180. mboolset(wlc_hw->wake_override, override_bit);
  1181. brcms_c_mctrl_write(wlc_hw);
  1182. brcms_b_wait_for_wake(wlc_hw);
  1183. }
  1184. void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
  1185. u32 override_bit)
  1186. {
  1187. mboolclr(wlc_hw->wake_override, override_bit);
  1188. if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
  1189. return;
  1190. brcms_c_mctrl_write(wlc_hw);
  1191. }
  1192. /* When driver needs ucode to stop beaconing, it has to make sure that
  1193. * MCTL_AP is clear and MCTL_INFRA is set
  1194. * Mode MCTL_AP MCTL_INFRA
  1195. * AP 1 1
  1196. * STA 0 1 <--- This will ensure no beacons
  1197. * IBSS 0 0
  1198. */
  1199. static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
  1200. {
  1201. wlc_hw->mute_override = 1;
  1202. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1203. * override, then there is no change to write
  1204. */
  1205. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1206. return;
  1207. brcms_c_mctrl_write(wlc_hw);
  1208. }
  1209. /* Clear the override on AP and INFRA bits */
  1210. static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
  1211. {
  1212. if (wlc_hw->mute_override == 0)
  1213. return;
  1214. wlc_hw->mute_override = 0;
  1215. /* if maccontrol already has AP == 0 and INFRA == 1 without this
  1216. * override, then there is no change to write
  1217. */
  1218. if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
  1219. return;
  1220. brcms_c_mctrl_write(wlc_hw);
  1221. }
  1222. /*
  1223. * Write a MAC address to the given match reg offset in the RXE match engine.
  1224. */
  1225. static void
  1226. brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
  1227. const u8 *addr)
  1228. {
  1229. struct d11regs __iomem *regs;
  1230. u16 mac_l;
  1231. u16 mac_m;
  1232. u16 mac_h;
  1233. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
  1234. wlc_hw->unit);
  1235. regs = wlc_hw->regs;
  1236. mac_l = addr[0] | (addr[1] << 8);
  1237. mac_m = addr[2] | (addr[3] << 8);
  1238. mac_h = addr[4] | (addr[5] << 8);
  1239. /* enter the MAC addr into the RXE match registers */
  1240. W_REG(&regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
  1241. W_REG(&regs->rcm_mat_data, mac_l);
  1242. W_REG(&regs->rcm_mat_data, mac_m);
  1243. W_REG(&regs->rcm_mat_data, mac_h);
  1244. }
  1245. void
  1246. brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
  1247. void *buf)
  1248. {
  1249. struct d11regs __iomem *regs;
  1250. u32 word;
  1251. __le32 word_le;
  1252. __be32 word_be;
  1253. bool be_bit;
  1254. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1255. regs = wlc_hw->regs;
  1256. W_REG(&regs->tplatewrptr, offset);
  1257. /* if MCTL_BIGEND bit set in mac control register,
  1258. * the chip swaps data in fifo, as well as data in
  1259. * template ram
  1260. */
  1261. be_bit = (R_REG(&regs->maccontrol) & MCTL_BIGEND) != 0;
  1262. while (len > 0) {
  1263. memcpy(&word, buf, sizeof(u32));
  1264. if (be_bit) {
  1265. word_be = cpu_to_be32(word);
  1266. word = *(u32 *)&word_be;
  1267. } else {
  1268. word_le = cpu_to_le32(word);
  1269. word = *(u32 *)&word_le;
  1270. }
  1271. W_REG(&regs->tplatewrdata, word);
  1272. buf = (u8 *) buf + sizeof(u32);
  1273. len -= sizeof(u32);
  1274. }
  1275. }
  1276. static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
  1277. {
  1278. wlc_hw->band->CWmin = newmin;
  1279. W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
  1280. (void)R_REG(&wlc_hw->regs->objaddr);
  1281. W_REG(&wlc_hw->regs->objdata, newmin);
  1282. }
  1283. static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
  1284. {
  1285. wlc_hw->band->CWmax = newmax;
  1286. W_REG(&wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
  1287. (void)R_REG(&wlc_hw->regs->objaddr);
  1288. W_REG(&wlc_hw->regs->objdata, newmax);
  1289. }
  1290. void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
  1291. {
  1292. bool fastclk;
  1293. /* request FAST clock if not on */
  1294. fastclk = wlc_hw->forcefastclk;
  1295. if (!fastclk)
  1296. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  1297. wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
  1298. brcms_b_phy_reset(wlc_hw);
  1299. wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
  1300. /* restore the clk */
  1301. if (!fastclk)
  1302. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  1303. }
  1304. static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
  1305. {
  1306. u16 v;
  1307. struct brcms_c_info *wlc = wlc_hw->wlc;
  1308. /* update SYNTHPU_DLY */
  1309. if (BRCMS_ISLCNPHY(wlc->band))
  1310. v = SYNTHPU_DLY_LPPHY_US;
  1311. else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
  1312. v = SYNTHPU_DLY_NPHY_US;
  1313. else
  1314. v = SYNTHPU_DLY_BPHY_US;
  1315. brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
  1316. }
  1317. static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
  1318. {
  1319. u16 phyctl;
  1320. u16 phytxant = wlc_hw->bmac_phytxant;
  1321. u16 mask = PHY_TXC_ANT_MASK;
  1322. /* set the Probe Response frame phy control word */
  1323. phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
  1324. phyctl = (phyctl & ~mask) | phytxant;
  1325. brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
  1326. /* set the Response (ACK/CTS) frame phy control word */
  1327. phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
  1328. phyctl = (phyctl & ~mask) | phytxant;
  1329. brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
  1330. }
  1331. static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
  1332. u8 rate)
  1333. {
  1334. uint i;
  1335. u8 plcp_rate = 0;
  1336. struct plcp_signal_rate_lookup {
  1337. u8 rate;
  1338. u8 signal_rate;
  1339. };
  1340. /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
  1341. const struct plcp_signal_rate_lookup rate_lookup[] = {
  1342. {BRCM_RATE_6M, 0xB},
  1343. {BRCM_RATE_9M, 0xF},
  1344. {BRCM_RATE_12M, 0xA},
  1345. {BRCM_RATE_18M, 0xE},
  1346. {BRCM_RATE_24M, 0x9},
  1347. {BRCM_RATE_36M, 0xD},
  1348. {BRCM_RATE_48M, 0x8},
  1349. {BRCM_RATE_54M, 0xC}
  1350. };
  1351. for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
  1352. if (rate == rate_lookup[i].rate) {
  1353. plcp_rate = rate_lookup[i].signal_rate;
  1354. break;
  1355. }
  1356. }
  1357. /* Find the SHM pointer to the rate table entry by looking in the
  1358. * Direct-map Table
  1359. */
  1360. return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
  1361. }
  1362. static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
  1363. {
  1364. u8 rate;
  1365. u8 rates[8] = {
  1366. BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
  1367. BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
  1368. };
  1369. u16 entry_ptr;
  1370. u16 pctl1;
  1371. uint i;
  1372. if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
  1373. return;
  1374. /* walk the phy rate table and update the entries */
  1375. for (i = 0; i < ARRAY_SIZE(rates); i++) {
  1376. rate = rates[i];
  1377. entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
  1378. /* read the SHM Rate Table entry OFDM PCTL1 values */
  1379. pctl1 =
  1380. brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
  1381. /* modify the value */
  1382. pctl1 &= ~PHY_TXC1_MODE_MASK;
  1383. pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
  1384. /* Update the SHM Rate Table entry OFDM PCTL1 values */
  1385. brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
  1386. pctl1);
  1387. }
  1388. }
  1389. /* band-specific init */
  1390. static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
  1391. {
  1392. struct brcms_hardware *wlc_hw = wlc->hw;
  1393. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  1394. wlc_hw->band->bandunit);
  1395. brcms_c_ucode_bsinit(wlc_hw);
  1396. wlc_phy_init(wlc_hw->band->pi, chanspec);
  1397. brcms_c_ucode_txant_set(wlc_hw);
  1398. /*
  1399. * cwmin is band-specific, update hardware
  1400. * with value for current band
  1401. */
  1402. brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
  1403. brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
  1404. brcms_b_update_slot_timing(wlc_hw,
  1405. wlc_hw->band->bandtype == BRCM_BAND_5G ?
  1406. true : wlc_hw->shortslot);
  1407. /* write phytype and phyvers */
  1408. brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
  1409. brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
  1410. /*
  1411. * initialize the txphyctl1 rate table since
  1412. * shmem is shared between bands
  1413. */
  1414. brcms_upd_ofdm_pctl1_table(wlc_hw);
  1415. brcms_b_upd_synthpu(wlc_hw);
  1416. }
  1417. /* Perform a soft reset of the PHY PLL */
  1418. void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
  1419. {
  1420. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1421. ai_corereg(wlc_hw->sih, SI_CC_IDX,
  1422. offsetof(struct chipcregs, chipcontrol_addr), ~0, 0);
  1423. udelay(1);
  1424. ai_corereg(wlc_hw->sih, SI_CC_IDX,
  1425. offsetof(struct chipcregs, chipcontrol_data), 0x4, 0);
  1426. udelay(1);
  1427. ai_corereg(wlc_hw->sih, SI_CC_IDX,
  1428. offsetof(struct chipcregs, chipcontrol_data), 0x4, 4);
  1429. udelay(1);
  1430. ai_corereg(wlc_hw->sih, SI_CC_IDX,
  1431. offsetof(struct chipcregs, chipcontrol_data), 0x4, 0);
  1432. udelay(1);
  1433. }
  1434. /* light way to turn on phy clock without reset for NPHY only
  1435. * refer to brcms_b_core_phy_clk for full version
  1436. */
  1437. void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
  1438. {
  1439. /* support(necessary for NPHY and HYPHY) only */
  1440. if (!BRCMS_ISNPHY(wlc_hw->band))
  1441. return;
  1442. if (ON == clk)
  1443. ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
  1444. else
  1445. ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
  1446. }
  1447. void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
  1448. {
  1449. if (ON == clk)
  1450. ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
  1451. else
  1452. ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
  1453. }
  1454. void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
  1455. {
  1456. struct brcms_phy_pub *pih = wlc_hw->band->pi;
  1457. u32 phy_bw_clkbits;
  1458. bool phy_in_reset = false;
  1459. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1460. if (pih == NULL)
  1461. return;
  1462. phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
  1463. /* Specific reset sequence required for NPHY rev 3 and 4 */
  1464. if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
  1465. NREV_LE(wlc_hw->band->phyrev, 4)) {
  1466. /* Set the PHY bandwidth */
  1467. ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
  1468. udelay(1);
  1469. /* Perform a soft reset of the PHY PLL */
  1470. brcms_b_core_phypll_reset(wlc_hw);
  1471. /* reset the PHY */
  1472. ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
  1473. (SICF_PRST | SICF_PCLKE));
  1474. phy_in_reset = true;
  1475. } else {
  1476. ai_core_cflags(wlc_hw->sih,
  1477. (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
  1478. (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
  1479. }
  1480. udelay(2);
  1481. brcms_b_core_phy_clk(wlc_hw, ON);
  1482. if (pih)
  1483. wlc_phy_anacore(pih, ON);
  1484. }
  1485. /* switch to and initialize new band */
  1486. static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
  1487. u16 chanspec) {
  1488. struct brcms_c_info *wlc = wlc_hw->wlc;
  1489. u32 macintmask;
  1490. /* Enable the d11 core before accessing it */
  1491. if (!ai_iscoreup(wlc_hw->sih)) {
  1492. ai_core_reset(wlc_hw->sih, 0, 0);
  1493. brcms_c_mctrl_reset(wlc_hw);
  1494. }
  1495. macintmask = brcms_c_setband_inact(wlc, bandunit);
  1496. if (!wlc_hw->up)
  1497. return;
  1498. brcms_b_core_phy_clk(wlc_hw, ON);
  1499. /* band-specific initializations */
  1500. brcms_b_bsinit(wlc, chanspec);
  1501. /*
  1502. * If there are any pending software interrupt bits,
  1503. * then replace these with a harmless nonzero value
  1504. * so brcms_c_dpc() will re-enable interrupts when done.
  1505. */
  1506. if (wlc->macintstatus)
  1507. wlc->macintstatus = MI_DMAINT;
  1508. /* restore macintmask */
  1509. brcms_intrsrestore(wlc->wl, macintmask);
  1510. /* ucode should still be suspended.. */
  1511. WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
  1512. }
  1513. static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
  1514. {
  1515. /* reject unsupported corerev */
  1516. if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
  1517. wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
  1518. wlc_hw->corerev);
  1519. return false;
  1520. }
  1521. return true;
  1522. }
  1523. /* Validate some board info parameters */
  1524. static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
  1525. {
  1526. uint boardrev = wlc_hw->boardrev;
  1527. /* 4 bits each for board type, major, minor, and tiny version */
  1528. uint brt = (boardrev & 0xf000) >> 12;
  1529. uint b0 = (boardrev & 0xf00) >> 8;
  1530. uint b1 = (boardrev & 0xf0) >> 4;
  1531. uint b2 = boardrev & 0xf;
  1532. /* voards from other vendors are always considered valid */
  1533. if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
  1534. return true;
  1535. /* do some boardrev sanity checks when boardvendor is Broadcom */
  1536. if (boardrev == 0)
  1537. return false;
  1538. if (boardrev <= 0xff)
  1539. return true;
  1540. if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
  1541. || (b2 > 9))
  1542. return false;
  1543. return true;
  1544. }
  1545. static char *brcms_c_get_macaddr(struct brcms_hardware *wlc_hw)
  1546. {
  1547. enum brcms_srom_id var_id = BRCMS_SROM_MACADDR;
  1548. char *macaddr;
  1549. /* If macaddr exists, use it (Sromrev4, CIS, ...). */
  1550. macaddr = getvar(wlc_hw->sih, var_id);
  1551. if (macaddr != NULL)
  1552. return macaddr;
  1553. if (wlc_hw->_nbands > 1)
  1554. var_id = BRCMS_SROM_ET1MACADDR;
  1555. else
  1556. var_id = BRCMS_SROM_IL0MACADDR;
  1557. macaddr = getvar(wlc_hw->sih, var_id);
  1558. if (macaddr == NULL)
  1559. wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
  1560. "getvar(%d) not found\n", wlc_hw->unit, var_id);
  1561. return macaddr;
  1562. }
  1563. /* power both the pll and external oscillator on/off */
  1564. static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
  1565. {
  1566. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
  1567. /*
  1568. * dont power down if plldown is false or
  1569. * we must poll hw radio disable
  1570. */
  1571. if (!want && wlc_hw->pllreq)
  1572. return;
  1573. if (wlc_hw->sih)
  1574. ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
  1575. wlc_hw->sbclk = want;
  1576. if (!wlc_hw->sbclk) {
  1577. wlc_hw->clk = false;
  1578. if (wlc_hw->band && wlc_hw->band->pi)
  1579. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  1580. }
  1581. }
  1582. /*
  1583. * Return true if radio is disabled, otherwise false.
  1584. * hw radio disable signal is an external pin, users activate it asynchronously
  1585. * this function could be called when driver is down and w/o clock
  1586. * it operates on different registers depending on corerev and boardflag.
  1587. */
  1588. static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
  1589. {
  1590. bool v, clk, xtal;
  1591. u32 resetbits = 0, flags = 0;
  1592. xtal = wlc_hw->sbclk;
  1593. if (!xtal)
  1594. brcms_b_xtal(wlc_hw, ON);
  1595. /* may need to take core out of reset first */
  1596. clk = wlc_hw->clk;
  1597. if (!clk) {
  1598. /*
  1599. * mac no longer enables phyclk automatically when driver
  1600. * accesses phyreg throughput mac. This can be skipped since
  1601. * only mac reg is accessed below
  1602. */
  1603. flags |= SICF_PCLKE;
  1604. /*
  1605. * AI chip doesn't restore bar0win2 on
  1606. * hibernation/resume, need sw fixup
  1607. */
  1608. if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
  1609. (wlc_hw->sih->chip == BCM43225_CHIP_ID))
  1610. wlc_hw->regs = (struct d11regs __iomem *)
  1611. ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
  1612. ai_core_reset(wlc_hw->sih, flags, resetbits);
  1613. brcms_c_mctrl_reset(wlc_hw);
  1614. }
  1615. v = ((R_REG(&wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
  1616. /* put core back into reset */
  1617. if (!clk)
  1618. ai_core_disable(wlc_hw->sih, 0);
  1619. if (!xtal)
  1620. brcms_b_xtal(wlc_hw, OFF);
  1621. return v;
  1622. }
  1623. static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
  1624. {
  1625. struct dma_pub *di = wlc_hw->di[fifo];
  1626. return dma_rxreset(di);
  1627. }
  1628. /* d11 core reset
  1629. * ensure fask clock during reset
  1630. * reset dma
  1631. * reset d11(out of reset)
  1632. * reset phy(out of reset)
  1633. * clear software macintstatus for fresh new start
  1634. * one testing hack wlc_hw->noreset will bypass the d11/phy reset
  1635. */
  1636. void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
  1637. {
  1638. struct d11regs __iomem *regs;
  1639. uint i;
  1640. bool fastclk;
  1641. u32 resetbits = 0;
  1642. if (flags == BRCMS_USE_COREFLAGS)
  1643. flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
  1644. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1645. regs = wlc_hw->regs;
  1646. /* request FAST clock if not on */
  1647. fastclk = wlc_hw->forcefastclk;
  1648. if (!fastclk)
  1649. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  1650. /* reset the dma engines except first time thru */
  1651. if (ai_iscoreup(wlc_hw->sih)) {
  1652. for (i = 0; i < NFIFO; i++)
  1653. if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
  1654. wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
  1655. "dma_txreset[%d]: cannot stop dma\n",
  1656. wlc_hw->unit, __func__, i);
  1657. if ((wlc_hw->di[RX_FIFO])
  1658. && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
  1659. wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
  1660. "[%d]: cannot stop dma\n",
  1661. wlc_hw->unit, __func__, RX_FIFO);
  1662. }
  1663. /* if noreset, just stop the psm and return */
  1664. if (wlc_hw->noreset) {
  1665. wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
  1666. brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
  1667. return;
  1668. }
  1669. /*
  1670. * mac no longer enables phyclk automatically when driver accesses
  1671. * phyreg throughput mac, AND phy_reset is skipped at early stage when
  1672. * band->pi is invalid. need to enable PHY CLK
  1673. */
  1674. flags |= SICF_PCLKE;
  1675. /*
  1676. * reset the core
  1677. * In chips with PMU, the fastclk request goes through d11 core
  1678. * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
  1679. *
  1680. * This adds some delay and we can optimize it by also requesting
  1681. * fastclk through chipcommon during this period if necessary. But
  1682. * that has to work coordinate with other driver like mips/arm since
  1683. * they may touch chipcommon as well.
  1684. */
  1685. wlc_hw->clk = false;
  1686. ai_core_reset(wlc_hw->sih, flags, resetbits);
  1687. wlc_hw->clk = true;
  1688. if (wlc_hw->band && wlc_hw->band->pi)
  1689. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
  1690. brcms_c_mctrl_reset(wlc_hw);
  1691. if (wlc_hw->sih->cccaps & CC_CAP_PMU)
  1692. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  1693. brcms_b_phy_reset(wlc_hw);
  1694. /* turn on PHY_PLL */
  1695. brcms_b_core_phypll_ctl(wlc_hw, true);
  1696. /* clear sw intstatus */
  1697. wlc_hw->wlc->macintstatus = 0;
  1698. /* restore the clk setting */
  1699. if (!fastclk)
  1700. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  1701. }
  1702. /* txfifo sizes needs to be modified(increased) since the newer cores
  1703. * have more memory.
  1704. */
  1705. static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
  1706. {
  1707. struct d11regs __iomem *regs = wlc_hw->regs;
  1708. u16 fifo_nu;
  1709. u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
  1710. u16 txfifo_def, txfifo_def1;
  1711. u16 txfifo_cmd;
  1712. /* tx fifos start at TXFIFO_START_BLK from the Base address */
  1713. txfifo_startblk = TXFIFO_START_BLK;
  1714. /* sequence of operations: reset fifo, set fifo size, reset fifo */
  1715. for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
  1716. txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
  1717. txfifo_def = (txfifo_startblk & 0xff) |
  1718. (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
  1719. txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
  1720. ((((txfifo_endblk -
  1721. 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
  1722. txfifo_cmd =
  1723. TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
  1724. W_REG(&regs->xmtfifocmd, txfifo_cmd);
  1725. W_REG(&regs->xmtfifodef, txfifo_def);
  1726. W_REG(&regs->xmtfifodef1, txfifo_def1);
  1727. W_REG(&regs->xmtfifocmd, txfifo_cmd);
  1728. txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
  1729. }
  1730. /*
  1731. * need to propagate to shm location to be in sync since ucode/hw won't
  1732. * do this
  1733. */
  1734. brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
  1735. wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
  1736. brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
  1737. wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
  1738. brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
  1739. ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
  1740. xmtfifo_sz[TX_AC_BK_FIFO]));
  1741. brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
  1742. ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
  1743. xmtfifo_sz[TX_BCMC_FIFO]));
  1744. }
  1745. /* This function is used for changing the tsf frac register
  1746. * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
  1747. * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
  1748. * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
  1749. * HTPHY Formula is 2^26/freq(MHz) e.g.
  1750. * For spuron2 - 126MHz -> 2^26/126 = 532610.0
  1751. * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
  1752. * For spuron: 123MHz -> 2^26/123 = 545600.5
  1753. * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
  1754. * For spur off: 120MHz -> 2^26/120 = 559240.5
  1755. * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
  1756. */
  1757. void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
  1758. {
  1759. struct d11regs __iomem *regs = wlc_hw->regs;
  1760. if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
  1761. (wlc_hw->sih->chip == BCM43225_CHIP_ID)) {
  1762. if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
  1763. W_REG(&regs->tsf_clk_frac_l, 0x2082);
  1764. W_REG(&regs->tsf_clk_frac_h, 0x8);
  1765. } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
  1766. W_REG(&regs->tsf_clk_frac_l, 0x5341);
  1767. W_REG(&regs->tsf_clk_frac_h, 0x8);
  1768. } else { /* 120Mhz */
  1769. W_REG(&regs->tsf_clk_frac_l, 0x8889);
  1770. W_REG(&regs->tsf_clk_frac_h, 0x8);
  1771. }
  1772. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1773. if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
  1774. W_REG(&regs->tsf_clk_frac_l, 0x7CE0);
  1775. W_REG(&regs->tsf_clk_frac_h, 0xC);
  1776. } else { /* 80Mhz */
  1777. W_REG(&regs->tsf_clk_frac_l, 0xCCCD);
  1778. W_REG(&regs->tsf_clk_frac_h, 0xC);
  1779. }
  1780. }
  1781. }
  1782. /* Initialize GPIOs that are controlled by D11 core */
  1783. static void brcms_c_gpio_init(struct brcms_c_info *wlc)
  1784. {
  1785. struct brcms_hardware *wlc_hw = wlc->hw;
  1786. struct d11regs __iomem *regs;
  1787. u32 gc, gm;
  1788. regs = wlc_hw->regs;
  1789. /* use GPIO select 0 to get all gpio signals from the gpio out reg */
  1790. brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
  1791. /*
  1792. * Common GPIO setup:
  1793. * G0 = LED 0 = WLAN Activity
  1794. * G1 = LED 1 = WLAN 2.4 GHz Radio State
  1795. * G2 = LED 2 = WLAN 5 GHz Radio State
  1796. * G4 = radio disable input (HI enabled, LO disabled)
  1797. */
  1798. gc = gm = 0;
  1799. /* Allocate GPIOs for mimo antenna diversity feature */
  1800. if (wlc_hw->antsel_type == ANTSEL_2x3) {
  1801. /* Enable antenna diversity, use 2x3 mode */
  1802. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1803. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1804. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
  1805. MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
  1806. /* init superswitch control */
  1807. wlc_phy_antsel_init(wlc_hw->band->pi, false);
  1808. } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
  1809. gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
  1810. /*
  1811. * The board itself is powered by these GPIOs
  1812. * (when not sending pattern) so set them high
  1813. */
  1814. OR_REG(&regs->psm_gpio_oe,
  1815. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1816. OR_REG(&regs->psm_gpio_out,
  1817. (BOARD_GPIO_12 | BOARD_GPIO_13));
  1818. /* Enable antenna diversity, use 2x4 mode */
  1819. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
  1820. MHF3_ANTSEL_EN, BRCM_BAND_ALL);
  1821. brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
  1822. BRCM_BAND_ALL);
  1823. /* Configure the desired clock to be 4Mhz */
  1824. brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
  1825. ANTSEL_CLKDIV_4MHZ);
  1826. }
  1827. /*
  1828. * gpio 9 controls the PA. ucode is responsible
  1829. * for wiggling out and oe
  1830. */
  1831. if (wlc_hw->boardflags & BFL_PACTRL)
  1832. gm |= gc |= BOARD_GPIO_PACTRL;
  1833. /* apply to gpiocontrol register */
  1834. ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
  1835. }
  1836. static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
  1837. const __le32 ucode[], const size_t nbytes)
  1838. {
  1839. struct d11regs __iomem *regs = wlc_hw->regs;
  1840. uint i;
  1841. uint count;
  1842. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  1843. count = (nbytes / sizeof(u32));
  1844. W_REG(&regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
  1845. (void)R_REG(&regs->objaddr);
  1846. for (i = 0; i < count; i++)
  1847. W_REG(&regs->objdata, le32_to_cpu(ucode[i]));
  1848. }
  1849. static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
  1850. {
  1851. struct brcms_c_info *wlc;
  1852. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  1853. wlc = wlc_hw->wlc;
  1854. if (wlc_hw->ucode_loaded)
  1855. return;
  1856. if (D11REV_IS(wlc_hw->corerev, 23)) {
  1857. if (BRCMS_ISNPHY(wlc_hw->band)) {
  1858. brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
  1859. ucode->bcm43xx_16_mimosz);
  1860. wlc_hw->ucode_loaded = true;
  1861. } else
  1862. wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
  1863. "corerev %d\n",
  1864. __func__, wlc_hw->unit, wlc_hw->corerev);
  1865. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  1866. if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  1867. brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
  1868. ucode->bcm43xx_24_lcnsz);
  1869. wlc_hw->ucode_loaded = true;
  1870. } else {
  1871. wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
  1872. "corerev %d\n",
  1873. __func__, wlc_hw->unit, wlc_hw->corerev);
  1874. }
  1875. }
  1876. }
  1877. void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
  1878. {
  1879. /* update sw state */
  1880. wlc_hw->bmac_phytxant = phytxant;
  1881. /* push to ucode if up */
  1882. if (!wlc_hw->up)
  1883. return;
  1884. brcms_c_ucode_txant_set(wlc_hw);
  1885. }
  1886. u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
  1887. {
  1888. return (u16) wlc_hw->wlc->stf->txant;
  1889. }
  1890. void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
  1891. {
  1892. wlc_hw->antsel_type = antsel_type;
  1893. /* Update the antsel type for phy module to use */
  1894. wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
  1895. }
  1896. static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
  1897. {
  1898. bool fatal = false;
  1899. uint unit;
  1900. uint intstatus, idx;
  1901. struct d11regs __iomem *regs = wlc_hw->regs;
  1902. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  1903. unit = wlc_hw->unit;
  1904. for (idx = 0; idx < NFIFO; idx++) {
  1905. /* read intstatus register and ignore any non-error bits */
  1906. intstatus =
  1907. R_REG(&regs->intctrlregs[idx].intstatus) & I_ERRORS;
  1908. if (!intstatus)
  1909. continue;
  1910. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
  1911. unit, idx, intstatus);
  1912. if (intstatus & I_RO) {
  1913. wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
  1914. "overflow\n", unit, idx);
  1915. fatal = true;
  1916. }
  1917. if (intstatus & I_PC) {
  1918. wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
  1919. unit, idx);
  1920. fatal = true;
  1921. }
  1922. if (intstatus & I_PD) {
  1923. wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
  1924. idx);
  1925. fatal = true;
  1926. }
  1927. if (intstatus & I_DE) {
  1928. wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
  1929. "error\n", unit, idx);
  1930. fatal = true;
  1931. }
  1932. if (intstatus & I_RU)
  1933. wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
  1934. "underflow\n", idx, unit);
  1935. if (intstatus & I_XU) {
  1936. wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
  1937. "underflow\n", idx, unit);
  1938. fatal = true;
  1939. }
  1940. if (fatal) {
  1941. brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
  1942. break;
  1943. } else
  1944. W_REG(&regs->intctrlregs[idx].intstatus,
  1945. intstatus);
  1946. }
  1947. }
  1948. void brcms_c_intrson(struct brcms_c_info *wlc)
  1949. {
  1950. struct brcms_hardware *wlc_hw = wlc->hw;
  1951. wlc->macintmask = wlc->defmacintmask;
  1952. W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
  1953. }
  1954. /*
  1955. * callback for siutils.c, which has only wlc handler, no wl they both check
  1956. * up, not only because there is no need to off/restore d11 interrupt but also
  1957. * because per-port code may require sync with valid interrupt.
  1958. */
  1959. static u32 brcms_c_wlintrsoff(struct brcms_c_info *wlc)
  1960. {
  1961. if (!wlc->hw->up)
  1962. return 0;
  1963. return brcms_intrsoff(wlc->wl);
  1964. }
  1965. static void brcms_c_wlintrsrestore(struct brcms_c_info *wlc, u32 macintmask)
  1966. {
  1967. if (!wlc->hw->up)
  1968. return;
  1969. brcms_intrsrestore(wlc->wl, macintmask);
  1970. }
  1971. u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
  1972. {
  1973. struct brcms_hardware *wlc_hw = wlc->hw;
  1974. u32 macintmask;
  1975. if (!wlc_hw->clk)
  1976. return 0;
  1977. macintmask = wlc->macintmask; /* isr can still happen */
  1978. W_REG(&wlc_hw->regs->macintmask, 0);
  1979. (void)R_REG(&wlc_hw->regs->macintmask); /* sync readback */
  1980. udelay(1); /* ensure int line is no longer driven */
  1981. wlc->macintmask = 0;
  1982. /* return previous macintmask; resolve race between us and our isr */
  1983. return wlc->macintstatus ? 0 : macintmask;
  1984. }
  1985. void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
  1986. {
  1987. struct brcms_hardware *wlc_hw = wlc->hw;
  1988. if (!wlc_hw->clk)
  1989. return;
  1990. wlc->macintmask = macintmask;
  1991. W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
  1992. }
  1993. /* assumes that the d11 MAC is enabled */
  1994. static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
  1995. uint tx_fifo)
  1996. {
  1997. u8 fifo = 1 << tx_fifo;
  1998. /* Two clients of this code, 11h Quiet period and scanning. */
  1999. /* only suspend if not already suspended */
  2000. if ((wlc_hw->suspended_fifos & fifo) == fifo)
  2001. return;
  2002. /* force the core awake only if not already */
  2003. if (wlc_hw->suspended_fifos == 0)
  2004. brcms_c_ucode_wake_override_set(wlc_hw,
  2005. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2006. wlc_hw->suspended_fifos |= fifo;
  2007. if (wlc_hw->di[tx_fifo]) {
  2008. /*
  2009. * Suspending AMPDU transmissions in the middle can cause
  2010. * underflow which may result in mismatch between ucode and
  2011. * driver so suspend the mac before suspending the FIFO
  2012. */
  2013. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2014. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  2015. dma_txsuspend(wlc_hw->di[tx_fifo]);
  2016. if (BRCMS_PHY_11N_CAP(wlc_hw->band))
  2017. brcms_c_enable_mac(wlc_hw->wlc);
  2018. }
  2019. }
  2020. static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
  2021. uint tx_fifo)
  2022. {
  2023. /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
  2024. * but need to be done here for PIO otherwise the watchdog will catch
  2025. * the inconsistency and fire
  2026. */
  2027. /* Two clients of this code, 11h Quiet period and scanning. */
  2028. if (wlc_hw->di[tx_fifo])
  2029. dma_txresume(wlc_hw->di[tx_fifo]);
  2030. /* allow core to sleep again */
  2031. if (wlc_hw->suspended_fifos == 0)
  2032. return;
  2033. else {
  2034. wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
  2035. if (wlc_hw->suspended_fifos == 0)
  2036. brcms_c_ucode_wake_override_clear(wlc_hw,
  2037. BRCMS_WAKE_OVERRIDE_TXFIFO);
  2038. }
  2039. }
  2040. /* precondition: requires the mac core to be enabled */
  2041. static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
  2042. {
  2043. static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
  2044. if (mute_tx) {
  2045. /* suspend tx fifos */
  2046. brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
  2047. brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
  2048. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
  2049. brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
  2050. /* zero the address match register so we do not send ACKs */
  2051. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
  2052. null_ether_addr);
  2053. } else {
  2054. /* resume tx fifos */
  2055. brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
  2056. brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
  2057. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
  2058. brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
  2059. /* Restore address */
  2060. brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
  2061. wlc_hw->etheraddr);
  2062. }
  2063. wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
  2064. if (mute_tx)
  2065. brcms_c_ucode_mute_override_set(wlc_hw);
  2066. else
  2067. brcms_c_ucode_mute_override_clear(wlc_hw);
  2068. }
  2069. void
  2070. brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
  2071. {
  2072. brcms_b_mute(wlc->hw, mute_tx);
  2073. }
  2074. /*
  2075. * Read and clear macintmask and macintstatus and intstatus registers.
  2076. * This routine should be called with interrupts off
  2077. * Return:
  2078. * -1 if brcms_deviceremoved(wlc) evaluates to true;
  2079. * 0 if the interrupt is not for us, or we are in some special cases;
  2080. * device interrupt status bits otherwise.
  2081. */
  2082. static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
  2083. {
  2084. struct brcms_hardware *wlc_hw = wlc->hw;
  2085. struct d11regs __iomem *regs = wlc_hw->regs;
  2086. u32 macintstatus;
  2087. /* macintstatus includes a DMA interrupt summary bit */
  2088. macintstatus = R_REG(&regs->macintstatus);
  2089. BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
  2090. macintstatus);
  2091. /* detect cardbus removed, in power down(suspend) and in reset */
  2092. if (brcms_deviceremoved(wlc))
  2093. return -1;
  2094. /* brcms_deviceremoved() succeeds even when the core is still resetting,
  2095. * handle that case here.
  2096. */
  2097. if (macintstatus == 0xffffffff)
  2098. return 0;
  2099. /* defer unsolicited interrupts */
  2100. macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
  2101. /* if not for us */
  2102. if (macintstatus == 0)
  2103. return 0;
  2104. /* interrupts are already turned off for CFE build
  2105. * Caution: For CFE Turning off the interrupts again has some undesired
  2106. * consequences
  2107. */
  2108. /* turn off the interrupts */
  2109. W_REG(&regs->macintmask, 0);
  2110. (void)R_REG(&regs->macintmask); /* sync readback */
  2111. wlc->macintmask = 0;
  2112. /* clear device interrupts */
  2113. W_REG(&regs->macintstatus, macintstatus);
  2114. /* MI_DMAINT is indication of non-zero intstatus */
  2115. if (macintstatus & MI_DMAINT)
  2116. /*
  2117. * only fifo interrupt enabled is I_RI in
  2118. * RX_FIFO. If MI_DMAINT is set, assume it
  2119. * is set and clear the interrupt.
  2120. */
  2121. W_REG(&regs->intctrlregs[RX_FIFO].intstatus,
  2122. DEF_RXINTMASK);
  2123. return macintstatus;
  2124. }
  2125. /* Update wlc->macintstatus and wlc->intstatus[]. */
  2126. /* Return true if they are updated successfully. false otherwise */
  2127. bool brcms_c_intrsupd(struct brcms_c_info *wlc)
  2128. {
  2129. u32 macintstatus;
  2130. /* read and clear macintstatus and intstatus registers */
  2131. macintstatus = wlc_intstatus(wlc, false);
  2132. /* device is removed */
  2133. if (macintstatus == 0xffffffff)
  2134. return false;
  2135. /* update interrupt status in software */
  2136. wlc->macintstatus |= macintstatus;
  2137. return true;
  2138. }
  2139. /*
  2140. * First-level interrupt processing.
  2141. * Return true if this was our interrupt, false otherwise.
  2142. * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
  2143. * false otherwise.
  2144. */
  2145. bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
  2146. {
  2147. struct brcms_hardware *wlc_hw = wlc->hw;
  2148. u32 macintstatus;
  2149. *wantdpc = false;
  2150. if (!wlc_hw->up || !wlc->macintmask)
  2151. return false;
  2152. /* read and clear macintstatus and intstatus registers */
  2153. macintstatus = wlc_intstatus(wlc, true);
  2154. if (macintstatus == 0xffffffff)
  2155. wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
  2156. " path\n");
  2157. /* it is not for us */
  2158. if (macintstatus == 0)
  2159. return false;
  2160. *wantdpc = true;
  2161. /* save interrupt status bits */
  2162. wlc->macintstatus = macintstatus;
  2163. return true;
  2164. }
  2165. void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
  2166. {
  2167. struct brcms_hardware *wlc_hw = wlc->hw;
  2168. struct d11regs __iomem *regs = wlc_hw->regs;
  2169. u32 mc, mi;
  2170. struct wiphy *wiphy = wlc->wiphy;
  2171. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  2172. wlc_hw->band->bandunit);
  2173. /*
  2174. * Track overlapping suspend requests
  2175. */
  2176. wlc_hw->mac_suspend_depth++;
  2177. if (wlc_hw->mac_suspend_depth > 1)
  2178. return;
  2179. /* force the core awake */
  2180. brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2181. mc = R_REG(&regs->maccontrol);
  2182. if (mc == 0xffffffff) {
  2183. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2184. __func__);
  2185. brcms_down(wlc->wl);
  2186. return;
  2187. }
  2188. WARN_ON(mc & MCTL_PSM_JMP_0);
  2189. WARN_ON(!(mc & MCTL_PSM_RUN));
  2190. WARN_ON(!(mc & MCTL_EN_MAC));
  2191. mi = R_REG(&regs->macintstatus);
  2192. if (mi == 0xffffffff) {
  2193. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2194. __func__);
  2195. brcms_down(wlc->wl);
  2196. return;
  2197. }
  2198. WARN_ON(mi & MI_MACSSPNDD);
  2199. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
  2200. SPINWAIT(!(R_REG(&regs->macintstatus) & MI_MACSSPNDD),
  2201. BRCMS_MAX_MAC_SUSPEND);
  2202. if (!(R_REG(&regs->macintstatus) & MI_MACSSPNDD)) {
  2203. wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
  2204. " and MI_MACSSPNDD is still not on.\n",
  2205. wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
  2206. wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
  2207. "psm_brc 0x%04x\n", wlc_hw->unit,
  2208. R_REG(&regs->psmdebug),
  2209. R_REG(&regs->phydebug),
  2210. R_REG(&regs->psm_brc));
  2211. }
  2212. mc = R_REG(&regs->maccontrol);
  2213. if (mc == 0xffffffff) {
  2214. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  2215. __func__);
  2216. brcms_down(wlc->wl);
  2217. return;
  2218. }
  2219. WARN_ON(mc & MCTL_PSM_JMP_0);
  2220. WARN_ON(!(mc & MCTL_PSM_RUN));
  2221. WARN_ON(mc & MCTL_EN_MAC);
  2222. }
  2223. void brcms_c_enable_mac(struct brcms_c_info *wlc)
  2224. {
  2225. struct brcms_hardware *wlc_hw = wlc->hw;
  2226. struct d11regs __iomem *regs = wlc_hw->regs;
  2227. u32 mc, mi;
  2228. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
  2229. wlc->band->bandunit);
  2230. /*
  2231. * Track overlapping suspend requests
  2232. */
  2233. wlc_hw->mac_suspend_depth--;
  2234. if (wlc_hw->mac_suspend_depth > 0)
  2235. return;
  2236. mc = R_REG(&regs->maccontrol);
  2237. WARN_ON(mc & MCTL_PSM_JMP_0);
  2238. WARN_ON(mc & MCTL_EN_MAC);
  2239. WARN_ON(!(mc & MCTL_PSM_RUN));
  2240. brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
  2241. W_REG(&regs->macintstatus, MI_MACSSPNDD);
  2242. mc = R_REG(&regs->maccontrol);
  2243. WARN_ON(mc & MCTL_PSM_JMP_0);
  2244. WARN_ON(!(mc & MCTL_EN_MAC));
  2245. WARN_ON(!(mc & MCTL_PSM_RUN));
  2246. mi = R_REG(&regs->macintstatus);
  2247. WARN_ON(mi & MI_MACSSPNDD);
  2248. brcms_c_ucode_wake_override_clear(wlc_hw,
  2249. BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2250. }
  2251. void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
  2252. {
  2253. wlc_hw->hw_stf_ss_opmode = stf_mode;
  2254. if (wlc_hw->clk)
  2255. brcms_upd_ofdm_pctl1_table(wlc_hw);
  2256. }
  2257. static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
  2258. {
  2259. struct d11regs __iomem *regs;
  2260. u32 w, val;
  2261. struct wiphy *wiphy = wlc_hw->wlc->wiphy;
  2262. BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
  2263. regs = wlc_hw->regs;
  2264. /* Validate dchip register access */
  2265. W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
  2266. (void)R_REG(&regs->objaddr);
  2267. w = R_REG(&regs->objdata);
  2268. /* Can we write and read back a 32bit register? */
  2269. W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
  2270. (void)R_REG(&regs->objaddr);
  2271. W_REG(&regs->objdata, (u32) 0xaa5555aa);
  2272. W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
  2273. (void)R_REG(&regs->objaddr);
  2274. val = R_REG(&regs->objdata);
  2275. if (val != (u32) 0xaa5555aa) {
  2276. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2277. "expected 0xaa5555aa\n", wlc_hw->unit, val);
  2278. return false;
  2279. }
  2280. W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
  2281. (void)R_REG(&regs->objaddr);
  2282. W_REG(&regs->objdata, (u32) 0x55aaaa55);
  2283. W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
  2284. (void)R_REG(&regs->objaddr);
  2285. val = R_REG(&regs->objdata);
  2286. if (val != (u32) 0x55aaaa55) {
  2287. wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
  2288. "expected 0x55aaaa55\n", wlc_hw->unit, val);
  2289. return false;
  2290. }
  2291. W_REG(&regs->objaddr, OBJADDR_SHM_SEL | 0);
  2292. (void)R_REG(&regs->objaddr);
  2293. W_REG(&regs->objdata, w);
  2294. /* clear CFPStart */
  2295. W_REG(&regs->tsf_cfpstart, 0);
  2296. w = R_REG(&regs->maccontrol);
  2297. if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
  2298. (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
  2299. wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
  2300. "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
  2301. (MCTL_IHR_EN | MCTL_WAKE),
  2302. (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
  2303. return false;
  2304. }
  2305. return true;
  2306. }
  2307. #define PHYPLL_WAIT_US 100000
  2308. void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
  2309. {
  2310. struct d11regs __iomem *regs;
  2311. u32 tmp;
  2312. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2313. tmp = 0;
  2314. regs = wlc_hw->regs;
  2315. if (on) {
  2316. if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
  2317. OR_REG(&regs->clk_ctl_st,
  2318. (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
  2319. CCS_ERSRC_REQ_PHYPLL));
  2320. SPINWAIT((R_REG(&regs->clk_ctl_st) &
  2321. (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
  2322. PHYPLL_WAIT_US);
  2323. tmp = R_REG(&regs->clk_ctl_st);
  2324. if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
  2325. (CCS_ERSRC_AVAIL_HT))
  2326. wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
  2327. " PLL failed\n", __func__);
  2328. } else {
  2329. OR_REG(&regs->clk_ctl_st,
  2330. (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
  2331. SPINWAIT((R_REG(&regs->clk_ctl_st) &
  2332. (CCS_ERSRC_AVAIL_D11PLL |
  2333. CCS_ERSRC_AVAIL_PHYPLL)) !=
  2334. (CCS_ERSRC_AVAIL_D11PLL |
  2335. CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
  2336. tmp = R_REG(&regs->clk_ctl_st);
  2337. if ((tmp &
  2338. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2339. !=
  2340. (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
  2341. wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
  2342. "PHY PLL failed\n", __func__);
  2343. }
  2344. } else {
  2345. /*
  2346. * Since the PLL may be shared, other cores can still
  2347. * be requesting it; so we'll deassert the request but
  2348. * not wait for status to comply.
  2349. */
  2350. AND_REG(&regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
  2351. tmp = R_REG(&regs->clk_ctl_st);
  2352. }
  2353. }
  2354. static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
  2355. {
  2356. bool dev_gone;
  2357. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2358. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  2359. if (dev_gone)
  2360. return;
  2361. if (wlc_hw->noreset)
  2362. return;
  2363. /* radio off */
  2364. wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
  2365. /* turn off analog core */
  2366. wlc_phy_anacore(wlc_hw->band->pi, OFF);
  2367. /* turn off PHYPLL to save power */
  2368. brcms_b_core_phypll_ctl(wlc_hw, false);
  2369. wlc_hw->clk = false;
  2370. ai_core_disable(wlc_hw->sih, 0);
  2371. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  2372. }
  2373. static void brcms_c_flushqueues(struct brcms_c_info *wlc)
  2374. {
  2375. struct brcms_hardware *wlc_hw = wlc->hw;
  2376. uint i;
  2377. /* free any posted tx packets */
  2378. for (i = 0; i < NFIFO; i++)
  2379. if (wlc_hw->di[i]) {
  2380. dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
  2381. wlc->core->txpktpend[i] = 0;
  2382. BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
  2383. }
  2384. /* free any posted rx packets */
  2385. dma_rxreclaim(wlc_hw->di[RX_FIFO]);
  2386. }
  2387. static u16
  2388. brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
  2389. {
  2390. struct d11regs __iomem *regs = wlc_hw->regs;
  2391. u16 __iomem *objdata_lo = (u16 __iomem *)&regs->objdata;
  2392. u16 __iomem *objdata_hi = objdata_lo + 1;
  2393. u16 v;
  2394. W_REG(&regs->objaddr, sel | (offset >> 2));
  2395. (void)R_REG(&regs->objaddr);
  2396. if (offset & 2)
  2397. v = R_REG(objdata_hi);
  2398. else
  2399. v = R_REG(objdata_lo);
  2400. return v;
  2401. }
  2402. static void
  2403. brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
  2404. u32 sel)
  2405. {
  2406. struct d11regs __iomem *regs = wlc_hw->regs;
  2407. u16 __iomem *objdata_lo = (u16 __iomem *)&regs->objdata;
  2408. u16 __iomem *objdata_hi = objdata_lo + 1;
  2409. W_REG(&regs->objaddr, sel | (offset >> 2));
  2410. (void)R_REG(&regs->objaddr);
  2411. if (offset & 2)
  2412. W_REG(objdata_hi, v);
  2413. else
  2414. W_REG(objdata_lo, v);
  2415. }
  2416. /*
  2417. * Read a single u16 from shared memory.
  2418. * SHM 'offset' needs to be an even address
  2419. */
  2420. u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
  2421. {
  2422. return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
  2423. }
  2424. /*
  2425. * Write a single u16 to shared memory.
  2426. * SHM 'offset' needs to be an even address
  2427. */
  2428. void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
  2429. {
  2430. brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
  2431. }
  2432. /*
  2433. * Copy a buffer to shared memory of specified type .
  2434. * SHM 'offset' needs to be an even address and
  2435. * Buffer length 'len' must be an even number of bytes
  2436. * 'sel' selects the type of memory
  2437. */
  2438. void
  2439. brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
  2440. const void *buf, int len, u32 sel)
  2441. {
  2442. u16 v;
  2443. const u8 *p = (const u8 *)buf;
  2444. int i;
  2445. if (len <= 0 || (offset & 1) || (len & 1))
  2446. return;
  2447. for (i = 0; i < len; i += 2) {
  2448. v = p[i] | (p[i + 1] << 8);
  2449. brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
  2450. }
  2451. }
  2452. /*
  2453. * Copy a piece of shared memory of specified type to a buffer .
  2454. * SHM 'offset' needs to be an even address and
  2455. * Buffer length 'len' must be an even number of bytes
  2456. * 'sel' selects the type of memory
  2457. */
  2458. void
  2459. brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
  2460. int len, u32 sel)
  2461. {
  2462. u16 v;
  2463. u8 *p = (u8 *) buf;
  2464. int i;
  2465. if (len <= 0 || (offset & 1) || (len & 1))
  2466. return;
  2467. for (i = 0; i < len; i += 2) {
  2468. v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
  2469. p[i] = v & 0xFF;
  2470. p[i + 1] = (v >> 8) & 0xFF;
  2471. }
  2472. }
  2473. /* Copy a buffer to shared memory.
  2474. * SHM 'offset' needs to be an even address and
  2475. * Buffer length 'len' must be an even number of bytes
  2476. */
  2477. static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
  2478. const void *buf, int len)
  2479. {
  2480. brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
  2481. }
  2482. static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
  2483. u16 SRL, u16 LRL)
  2484. {
  2485. wlc_hw->SRL = SRL;
  2486. wlc_hw->LRL = LRL;
  2487. /* write retry limit to SCR, shouldn't need to suspend */
  2488. if (wlc_hw->up) {
  2489. W_REG(&wlc_hw->regs->objaddr,
  2490. OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2491. (void)R_REG(&wlc_hw->regs->objaddr);
  2492. W_REG(&wlc_hw->regs->objdata, wlc_hw->SRL);
  2493. W_REG(&wlc_hw->regs->objaddr,
  2494. OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2495. (void)R_REG(&wlc_hw->regs->objaddr);
  2496. W_REG(&wlc_hw->regs->objdata, wlc_hw->LRL);
  2497. }
  2498. }
  2499. static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
  2500. {
  2501. if (set) {
  2502. if (mboolisset(wlc_hw->pllreq, req_bit))
  2503. return;
  2504. mboolset(wlc_hw->pllreq, req_bit);
  2505. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2506. if (!wlc_hw->sbclk)
  2507. brcms_b_xtal(wlc_hw, ON);
  2508. }
  2509. } else {
  2510. if (!mboolisset(wlc_hw->pllreq, req_bit))
  2511. return;
  2512. mboolclr(wlc_hw->pllreq, req_bit);
  2513. if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
  2514. if (wlc_hw->sbclk)
  2515. brcms_b_xtal(wlc_hw, OFF);
  2516. }
  2517. }
  2518. }
  2519. static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
  2520. {
  2521. wlc_hw->antsel_avail = antsel_avail;
  2522. }
  2523. /*
  2524. * conditions under which the PM bit should be set in outgoing frames
  2525. * and STAY_AWAKE is meaningful
  2526. */
  2527. static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
  2528. {
  2529. struct brcms_bss_cfg *cfg = wlc->bsscfg;
  2530. /* disallow PS when one of the following global conditions meets */
  2531. if (!wlc->pub->associated)
  2532. return false;
  2533. /* disallow PS when one of these meets when not scanning */
  2534. if (wlc->monitor)
  2535. return false;
  2536. if (cfg->associated) {
  2537. /*
  2538. * disallow PS when one of the following
  2539. * bsscfg specific conditions meets
  2540. */
  2541. if (!cfg->BSS)
  2542. return false;
  2543. return false;
  2544. }
  2545. return true;
  2546. }
  2547. static void brcms_c_statsupd(struct brcms_c_info *wlc)
  2548. {
  2549. int i;
  2550. struct macstat macstats;
  2551. #ifdef BCMDBG
  2552. u16 delta;
  2553. u16 rxf0ovfl;
  2554. u16 txfunfl[NFIFO];
  2555. #endif /* BCMDBG */
  2556. /* if driver down, make no sense to update stats */
  2557. if (!wlc->pub->up)
  2558. return;
  2559. #ifdef BCMDBG
  2560. /* save last rx fifo 0 overflow count */
  2561. rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
  2562. /* save last tx fifo underflow count */
  2563. for (i = 0; i < NFIFO; i++)
  2564. txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
  2565. #endif /* BCMDBG */
  2566. /* Read mac stats from contiguous shared memory */
  2567. brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
  2568. sizeof(struct macstat), OBJADDR_SHM_SEL);
  2569. #ifdef BCMDBG
  2570. /* check for rx fifo 0 overflow */
  2571. delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
  2572. if (delta)
  2573. wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
  2574. wlc->pub->unit, delta);
  2575. /* check for tx fifo underflows */
  2576. for (i = 0; i < NFIFO; i++) {
  2577. delta =
  2578. (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
  2579. txfunfl[i]);
  2580. if (delta)
  2581. wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
  2582. "\n", wlc->pub->unit, delta, i);
  2583. }
  2584. #endif /* BCMDBG */
  2585. /* merge counters from dma module */
  2586. for (i = 0; i < NFIFO; i++) {
  2587. if (wlc->hw->di[i])
  2588. dma_counterreset(wlc->hw->di[i]);
  2589. }
  2590. }
  2591. static void brcms_b_reset(struct brcms_hardware *wlc_hw)
  2592. {
  2593. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2594. /* reset the core */
  2595. if (!brcms_deviceremoved(wlc_hw->wlc))
  2596. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  2597. /* purge the dma rings */
  2598. brcms_c_flushqueues(wlc_hw->wlc);
  2599. }
  2600. void brcms_c_reset(struct brcms_c_info *wlc)
  2601. {
  2602. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  2603. /* slurp up hw mac counters before core reset */
  2604. brcms_c_statsupd(wlc);
  2605. /* reset our snapshot of macstat counters */
  2606. memset((char *)wlc->core->macstat_snapshot, 0,
  2607. sizeof(struct macstat));
  2608. brcms_b_reset(wlc->hw);
  2609. }
  2610. /* Return the channel the driver should initialize during brcms_c_init.
  2611. * the channel may have to be changed from the currently configured channel
  2612. * if other configurations are in conflict (bandlocked, 11n mode disabled,
  2613. * invalid channel for current country, etc.)
  2614. */
  2615. static u16 brcms_c_init_chanspec(struct brcms_c_info *wlc)
  2616. {
  2617. u16 chanspec =
  2618. 1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
  2619. WL_CHANSPEC_BAND_2G;
  2620. return chanspec;
  2621. }
  2622. void brcms_c_init_scb(struct scb *scb)
  2623. {
  2624. int i;
  2625. memset(scb, 0, sizeof(struct scb));
  2626. scb->flags = SCB_WMECAP | SCB_HTCAP;
  2627. for (i = 0; i < NUMPRIO; i++) {
  2628. scb->seqnum[i] = 0;
  2629. scb->seqctl[i] = 0xFFFF;
  2630. }
  2631. scb->seqctl_nonqos = 0xFFFF;
  2632. scb->magic = SCB_MAGIC;
  2633. }
  2634. /* d11 core init
  2635. * reset PSM
  2636. * download ucode/PCM
  2637. * let ucode run to suspended
  2638. * download ucode inits
  2639. * config other core registers
  2640. * init dma
  2641. */
  2642. static void brcms_b_coreinit(struct brcms_c_info *wlc)
  2643. {
  2644. struct brcms_hardware *wlc_hw = wlc->hw;
  2645. struct d11regs __iomem *regs;
  2646. u32 sflags;
  2647. uint bcnint_us;
  2648. uint i = 0;
  2649. bool fifosz_fixup = false;
  2650. int err = 0;
  2651. u16 buf[NFIFO];
  2652. struct wiphy *wiphy = wlc->wiphy;
  2653. struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
  2654. regs = wlc_hw->regs;
  2655. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2656. /* reset PSM */
  2657. brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
  2658. brcms_ucode_download(wlc_hw);
  2659. /*
  2660. * FIFOSZ fixup. driver wants to controls the fifo allocation.
  2661. */
  2662. fifosz_fixup = true;
  2663. /* let the PSM run to the suspended state, set mode to BSS STA */
  2664. W_REG(&regs->macintstatus, -1);
  2665. brcms_b_mctrl(wlc_hw, ~0,
  2666. (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
  2667. /* wait for ucode to self-suspend after auto-init */
  2668. SPINWAIT(((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0),
  2669. 1000 * 1000);
  2670. if ((R_REG(&regs->macintstatus) & MI_MACSSPNDD) == 0)
  2671. wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
  2672. "suspend!\n", wlc_hw->unit);
  2673. brcms_c_gpio_init(wlc);
  2674. sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
  2675. if (D11REV_IS(wlc_hw->corerev, 23)) {
  2676. if (BRCMS_ISNPHY(wlc_hw->band))
  2677. brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
  2678. else
  2679. wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
  2680. " %d\n", __func__, wlc_hw->unit,
  2681. wlc_hw->corerev);
  2682. } else if (D11REV_IS(wlc_hw->corerev, 24)) {
  2683. if (BRCMS_ISLCNPHY(wlc_hw->band))
  2684. brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
  2685. else
  2686. wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
  2687. " %d\n", __func__, wlc_hw->unit,
  2688. wlc_hw->corerev);
  2689. } else {
  2690. wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
  2691. __func__, wlc_hw->unit, wlc_hw->corerev);
  2692. }
  2693. /* For old ucode, txfifo sizes needs to be modified(increased) */
  2694. if (fifosz_fixup == true)
  2695. brcms_b_corerev_fifofixup(wlc_hw);
  2696. /* check txfifo allocations match between ucode and driver */
  2697. buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
  2698. if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
  2699. i = TX_AC_BE_FIFO;
  2700. err = -1;
  2701. }
  2702. buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
  2703. if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
  2704. i = TX_AC_VI_FIFO;
  2705. err = -1;
  2706. }
  2707. buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
  2708. buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
  2709. buf[TX_AC_BK_FIFO] &= 0xff;
  2710. if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
  2711. i = TX_AC_BK_FIFO;
  2712. err = -1;
  2713. }
  2714. if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
  2715. i = TX_AC_VO_FIFO;
  2716. err = -1;
  2717. }
  2718. buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
  2719. buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
  2720. buf[TX_BCMC_FIFO] &= 0xff;
  2721. if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
  2722. i = TX_BCMC_FIFO;
  2723. err = -1;
  2724. }
  2725. if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
  2726. i = TX_ATIM_FIFO;
  2727. err = -1;
  2728. }
  2729. if (err != 0)
  2730. wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
  2731. " driver size %d index %d\n", buf[i],
  2732. wlc_hw->xmtfifo_sz[i], i);
  2733. /* make sure we can still talk to the mac */
  2734. WARN_ON(R_REG(&regs->maccontrol) == 0xffffffff);
  2735. /* band-specific inits done by wlc_bsinit() */
  2736. /* Set up frame burst size and antenna swap threshold init values */
  2737. brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
  2738. brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
  2739. /* enable one rx interrupt per received frame */
  2740. W_REG(&regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
  2741. /* set the station mode (BSS STA) */
  2742. brcms_b_mctrl(wlc_hw,
  2743. (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
  2744. (MCTL_INFRA | MCTL_DISCARD_PMQ));
  2745. /* set up Beacon interval */
  2746. bcnint_us = 0x8000 << 10;
  2747. W_REG(&regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
  2748. W_REG(&regs->tsf_cfpstart, bcnint_us);
  2749. W_REG(&regs->macintstatus, MI_GP1);
  2750. /* write interrupt mask */
  2751. W_REG(&regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
  2752. /* allow the MAC to control the PHY clock (dynamic on/off) */
  2753. brcms_b_macphyclk_set(wlc_hw, ON);
  2754. /* program dynamic clock control fast powerup delay register */
  2755. wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
  2756. W_REG(&regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
  2757. /* tell the ucode the corerev */
  2758. brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
  2759. /* tell the ucode MAC capabilities */
  2760. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
  2761. (u16) (wlc_hw->machwcap & 0xffff));
  2762. brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
  2763. (u16) ((wlc_hw->
  2764. machwcap >> 16) & 0xffff));
  2765. /* write retry limits to SCR, this done after PSM init */
  2766. W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
  2767. (void)R_REG(&regs->objaddr);
  2768. W_REG(&regs->objdata, wlc_hw->SRL);
  2769. W_REG(&regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
  2770. (void)R_REG(&regs->objaddr);
  2771. W_REG(&regs->objdata, wlc_hw->LRL);
  2772. /* write rate fallback retry limits */
  2773. brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
  2774. brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
  2775. AND_REG(&regs->ifs_ctl, 0x0FFF);
  2776. W_REG(&regs->ifs_aifsn, EDCF_AIFSN_MIN);
  2777. /* init the tx dma engines */
  2778. for (i = 0; i < NFIFO; i++) {
  2779. if (wlc_hw->di[i])
  2780. dma_txinit(wlc_hw->di[i]);
  2781. }
  2782. /* init the rx dma engine(s) and post receive buffers */
  2783. dma_rxinit(wlc_hw->di[RX_FIFO]);
  2784. dma_rxfill(wlc_hw->di[RX_FIFO]);
  2785. }
  2786. void
  2787. static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
  2788. u32 macintmask;
  2789. bool fastclk;
  2790. struct brcms_c_info *wlc = wlc_hw->wlc;
  2791. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  2792. /* request FAST clock if not on */
  2793. fastclk = wlc_hw->forcefastclk;
  2794. if (!fastclk)
  2795. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  2796. /* disable interrupts */
  2797. macintmask = brcms_intrsoff(wlc->wl);
  2798. /* set up the specified band and chanspec */
  2799. brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
  2800. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  2801. /* do one-time phy inits and calibration */
  2802. wlc_phy_cal_init(wlc_hw->band->pi);
  2803. /* core-specific initialization */
  2804. brcms_b_coreinit(wlc);
  2805. /* band-specific inits */
  2806. brcms_b_bsinit(wlc, chanspec);
  2807. /* restore macintmask */
  2808. brcms_intrsrestore(wlc->wl, macintmask);
  2809. /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
  2810. * is suspended and brcms_c_enable_mac() will clear this override bit.
  2811. */
  2812. mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
  2813. /*
  2814. * initialize mac_suspend_depth to 1 to match ucode
  2815. * initial suspended state
  2816. */
  2817. wlc_hw->mac_suspend_depth = 1;
  2818. /* restore the clk */
  2819. if (!fastclk)
  2820. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  2821. }
  2822. static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
  2823. u16 chanspec)
  2824. {
  2825. /* Save our copy of the chanspec */
  2826. wlc->chanspec = chanspec;
  2827. /* Set the chanspec and power limits for this locale */
  2828. brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
  2829. if (wlc->stf->ss_algosel_auto)
  2830. brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
  2831. chanspec);
  2832. brcms_c_stf_ss_update(wlc, wlc->band);
  2833. }
  2834. static void
  2835. brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
  2836. {
  2837. brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
  2838. wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
  2839. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  2840. brcms_chspec_bw(wlc->default_bss->chanspec),
  2841. wlc->stf->txstreams);
  2842. }
  2843. /* derive wlc->band->basic_rate[] table from 'rateset' */
  2844. static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
  2845. struct brcms_c_rateset *rateset)
  2846. {
  2847. u8 rate;
  2848. u8 mandatory;
  2849. u8 cck_basic = 0;
  2850. u8 ofdm_basic = 0;
  2851. u8 *br = wlc->band->basic_rate;
  2852. uint i;
  2853. /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
  2854. memset(br, 0, BRCM_MAXRATE + 1);
  2855. /* For each basic rate in the rates list, make an entry in the
  2856. * best basic lookup.
  2857. */
  2858. for (i = 0; i < rateset->count; i++) {
  2859. /* only make an entry for a basic rate */
  2860. if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
  2861. continue;
  2862. /* mask off basic bit */
  2863. rate = (rateset->rates[i] & BRCMS_RATE_MASK);
  2864. if (rate > BRCM_MAXRATE) {
  2865. wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
  2866. "invalid rate 0x%X in rate set\n",
  2867. rateset->rates[i]);
  2868. continue;
  2869. }
  2870. br[rate] = rate;
  2871. }
  2872. /* The rate lookup table now has non-zero entries for each
  2873. * basic rate, equal to the basic rate: br[basicN] = basicN
  2874. *
  2875. * To look up the best basic rate corresponding to any
  2876. * particular rate, code can use the basic_rate table
  2877. * like this
  2878. *
  2879. * basic_rate = wlc->band->basic_rate[tx_rate]
  2880. *
  2881. * Make sure there is a best basic rate entry for
  2882. * every rate by walking up the table from low rates
  2883. * to high, filling in holes in the lookup table
  2884. */
  2885. for (i = 0; i < wlc->band->hw_rateset.count; i++) {
  2886. rate = wlc->band->hw_rateset.rates[i];
  2887. if (br[rate] != 0) {
  2888. /* This rate is a basic rate.
  2889. * Keep track of the best basic rate so far by
  2890. * modulation type.
  2891. */
  2892. if (is_ofdm_rate(rate))
  2893. ofdm_basic = rate;
  2894. else
  2895. cck_basic = rate;
  2896. continue;
  2897. }
  2898. /* This rate is not a basic rate so figure out the
  2899. * best basic rate less than this rate and fill in
  2900. * the hole in the table
  2901. */
  2902. br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
  2903. if (br[rate] != 0)
  2904. continue;
  2905. if (is_ofdm_rate(rate)) {
  2906. /*
  2907. * In 11g and 11a, the OFDM mandatory rates
  2908. * are 6, 12, and 24 Mbps
  2909. */
  2910. if (rate >= BRCM_RATE_24M)
  2911. mandatory = BRCM_RATE_24M;
  2912. else if (rate >= BRCM_RATE_12M)
  2913. mandatory = BRCM_RATE_12M;
  2914. else
  2915. mandatory = BRCM_RATE_6M;
  2916. } else {
  2917. /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
  2918. mandatory = rate;
  2919. }
  2920. br[rate] = mandatory;
  2921. }
  2922. }
  2923. static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
  2924. u16 chanspec)
  2925. {
  2926. struct brcms_c_rateset default_rateset;
  2927. uint parkband;
  2928. uint i, band_order[2];
  2929. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  2930. /*
  2931. * We might have been bandlocked during down and the chip
  2932. * power-cycled (hibernate). Figure out the right band to park on
  2933. */
  2934. if (wlc->bandlocked || wlc->pub->_nbands == 1) {
  2935. /* updated in brcms_c_bandlock() */
  2936. parkband = wlc->band->bandunit;
  2937. band_order[0] = band_order[1] = parkband;
  2938. } else {
  2939. /* park on the band of the specified chanspec */
  2940. parkband = chspec_bandunit(chanspec);
  2941. /* order so that parkband initialize last */
  2942. band_order[0] = parkband ^ 1;
  2943. band_order[1] = parkband;
  2944. }
  2945. /* make each band operational, software state init */
  2946. for (i = 0; i < wlc->pub->_nbands; i++) {
  2947. uint j = band_order[i];
  2948. wlc->band = wlc->bandstate[j];
  2949. brcms_default_rateset(wlc, &default_rateset);
  2950. /* fill in hw_rate */
  2951. brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
  2952. false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  2953. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  2954. /* init basic rate lookup */
  2955. brcms_c_rate_lookup_init(wlc, &default_rateset);
  2956. }
  2957. /* sync up phy/radio chanspec */
  2958. brcms_c_set_phy_chanspec(wlc, chanspec);
  2959. }
  2960. static void brcms_c_mac_bcn_promisc(struct brcms_c_info *wlc)
  2961. {
  2962. if (wlc->bcnmisc_monitor)
  2963. brcms_b_mctrl(wlc->hw, MCTL_BCNS_PROMISC, MCTL_BCNS_PROMISC);
  2964. else
  2965. brcms_b_mctrl(wlc->hw, MCTL_BCNS_PROMISC, 0);
  2966. }
  2967. void brcms_c_mac_bcn_promisc_change(struct brcms_c_info *wlc, bool promisc)
  2968. {
  2969. wlc->bcnmisc_monitor = promisc;
  2970. brcms_c_mac_bcn_promisc(wlc);
  2971. }
  2972. /* set or clear maccontrol bits MCTL_PROMISC and MCTL_KEEPCONTROL */
  2973. static void brcms_c_mac_promisc(struct brcms_c_info *wlc)
  2974. {
  2975. u32 promisc_bits = 0;
  2976. /*
  2977. * promiscuous mode just sets MCTL_PROMISC
  2978. * Note: APs get all BSS traffic without the need to set
  2979. * the MCTL_PROMISC bit since all BSS data traffic is
  2980. * directed at the AP
  2981. */
  2982. if (wlc->pub->promisc)
  2983. promisc_bits |= MCTL_PROMISC;
  2984. /* monitor mode needs both MCTL_PROMISC and MCTL_KEEPCONTROL
  2985. * Note: monitor mode also needs MCTL_BCNS_PROMISC, but that is
  2986. * handled in brcms_c_mac_bcn_promisc()
  2987. */
  2988. if (wlc->monitor)
  2989. promisc_bits |= MCTL_PROMISC | MCTL_KEEPCONTROL;
  2990. brcms_b_mctrl(wlc->hw, MCTL_PROMISC | MCTL_KEEPCONTROL, promisc_bits);
  2991. }
  2992. /*
  2993. * ucode, hwmac update
  2994. * Channel dependent updates for ucode and hw
  2995. */
  2996. static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
  2997. {
  2998. /* enable or disable any active IBSSs depending on whether or not
  2999. * we are on the home channel
  3000. */
  3001. if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
  3002. if (wlc->pub->associated) {
  3003. /*
  3004. * BMAC_NOTE: This is something that should be fixed
  3005. * in ucode inits. I think that the ucode inits set
  3006. * up the bcn templates and shm values with a bogus
  3007. * beacon. This should not be done in the inits. If
  3008. * ucode needs to set up a beacon for testing, the
  3009. * test routines should write it down, not expect the
  3010. * inits to populate a bogus beacon.
  3011. */
  3012. if (BRCMS_PHY_11N_CAP(wlc->band))
  3013. brcms_b_write_shm(wlc->hw,
  3014. M_BCN_TXTSF_OFFSET, 0);
  3015. }
  3016. } else {
  3017. /* disable an active IBSS if we are not on the home channel */
  3018. }
  3019. /* update the various promisc bits */
  3020. brcms_c_mac_bcn_promisc(wlc);
  3021. brcms_c_mac_promisc(wlc);
  3022. }
  3023. static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
  3024. u8 basic_rate)
  3025. {
  3026. u8 phy_rate, index;
  3027. u8 basic_phy_rate, basic_index;
  3028. u16 dir_table, basic_table;
  3029. u16 basic_ptr;
  3030. /* Shared memory address for the table we are reading */
  3031. dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
  3032. /* Shared memory address for the table we are writing */
  3033. basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
  3034. /*
  3035. * for a given rate, the LS-nibble of the PLCP SIGNAL field is
  3036. * the index into the rate table.
  3037. */
  3038. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  3039. basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
  3040. index = phy_rate & 0xf;
  3041. basic_index = basic_phy_rate & 0xf;
  3042. /* Find the SHM pointer to the ACK rate entry by looking in the
  3043. * Direct-map Table
  3044. */
  3045. basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
  3046. /* Update the SHM BSS-basic-rate-set mapping table with the pointer
  3047. * to the correct basic rate for the given incoming rate
  3048. */
  3049. brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
  3050. }
  3051. static const struct brcms_c_rateset *
  3052. brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
  3053. {
  3054. const struct brcms_c_rateset *rs_dflt;
  3055. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  3056. if (wlc->band->bandtype == BRCM_BAND_5G)
  3057. rs_dflt = &ofdm_mimo_rates;
  3058. else
  3059. rs_dflt = &cck_ofdm_mimo_rates;
  3060. } else if (wlc->band->gmode)
  3061. rs_dflt = &cck_ofdm_rates;
  3062. else
  3063. rs_dflt = &cck_rates;
  3064. return rs_dflt;
  3065. }
  3066. static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
  3067. {
  3068. const struct brcms_c_rateset *rs_dflt;
  3069. struct brcms_c_rateset rs;
  3070. u8 rate, basic_rate;
  3071. uint i;
  3072. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  3073. brcms_c_rateset_copy(rs_dflt, &rs);
  3074. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  3075. /* walk the phy rate table and update SHM basic rate lookup table */
  3076. for (i = 0; i < rs.count; i++) {
  3077. rate = rs.rates[i] & BRCMS_RATE_MASK;
  3078. /* for a given rate brcms_basic_rate returns the rate at
  3079. * which a response ACK/CTS should be sent.
  3080. */
  3081. basic_rate = brcms_basic_rate(wlc, rate);
  3082. if (basic_rate == 0)
  3083. /* This should only happen if we are using a
  3084. * restricted rateset.
  3085. */
  3086. basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
  3087. brcms_c_write_rate_shm(wlc, rate, basic_rate);
  3088. }
  3089. }
  3090. /* band-specific init */
  3091. static void brcms_c_bsinit(struct brcms_c_info *wlc)
  3092. {
  3093. BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
  3094. wlc->pub->unit, wlc->band->bandunit);
  3095. /* write ucode ACK/CTS rate table */
  3096. brcms_c_set_ratetable(wlc);
  3097. /* update some band specific mac configuration */
  3098. brcms_c_ucode_mac_upd(wlc);
  3099. /* init antenna selection */
  3100. brcms_c_antsel_init(wlc->asi);
  3101. }
  3102. /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
  3103. static int
  3104. brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
  3105. bool writeToShm)
  3106. {
  3107. int idle_busy_ratio_x_16 = 0;
  3108. uint offset =
  3109. isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
  3110. M_TX_IDLE_BUSY_RATIO_X_16_CCK;
  3111. if (duty_cycle > 100 || duty_cycle < 0) {
  3112. wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
  3113. wlc->pub->unit);
  3114. return -EINVAL;
  3115. }
  3116. if (duty_cycle)
  3117. idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
  3118. /* Only write to shared memory when wl is up */
  3119. if (writeToShm)
  3120. brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
  3121. if (isOFDM)
  3122. wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
  3123. else
  3124. wlc->tx_duty_cycle_cck = (u16) duty_cycle;
  3125. return 0;
  3126. }
  3127. /*
  3128. * Initialize the base precedence map for dequeueing
  3129. * from txq based on WME settings
  3130. */
  3131. static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
  3132. {
  3133. wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
  3134. memset(wlc->fifo2prec_map, 0, NFIFO * sizeof(u16));
  3135. wlc->fifo2prec_map[TX_AC_BK_FIFO] = BRCMS_PREC_BMP_AC_BK;
  3136. wlc->fifo2prec_map[TX_AC_BE_FIFO] = BRCMS_PREC_BMP_AC_BE;
  3137. wlc->fifo2prec_map[TX_AC_VI_FIFO] = BRCMS_PREC_BMP_AC_VI;
  3138. wlc->fifo2prec_map[TX_AC_VO_FIFO] = BRCMS_PREC_BMP_AC_VO;
  3139. }
  3140. static void
  3141. brcms_c_txflowcontrol_signal(struct brcms_c_info *wlc,
  3142. struct brcms_txq_info *qi, bool on, int prio)
  3143. {
  3144. /* transmit flowcontrol is not yet implemented */
  3145. }
  3146. static void brcms_c_txflowcontrol_reset(struct brcms_c_info *wlc)
  3147. {
  3148. struct brcms_txq_info *qi;
  3149. for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
  3150. if (qi->stopped) {
  3151. brcms_c_txflowcontrol_signal(wlc, qi, OFF, ALLPRIO);
  3152. qi->stopped = 0;
  3153. }
  3154. }
  3155. }
  3156. /* push sw hps and wake state through hardware */
  3157. static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
  3158. {
  3159. u32 v1, v2;
  3160. bool hps;
  3161. bool awake_before;
  3162. hps = brcms_c_ps_allowed(wlc);
  3163. BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
  3164. v1 = R_REG(&wlc->regs->maccontrol);
  3165. v2 = MCTL_WAKE;
  3166. if (hps)
  3167. v2 |= MCTL_HPS;
  3168. brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
  3169. awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
  3170. if (!awake_before)
  3171. brcms_b_wait_for_wake(wlc->hw);
  3172. }
  3173. /*
  3174. * Write this BSS config's MAC address to core.
  3175. * Updates RXE match engine.
  3176. */
  3177. static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
  3178. {
  3179. int err = 0;
  3180. struct brcms_c_info *wlc = bsscfg->wlc;
  3181. /* enter the MAC addr into the RXE match registers */
  3182. brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
  3183. brcms_c_ampdu_macaddr_upd(wlc);
  3184. return err;
  3185. }
  3186. /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
  3187. * Updates RXE match engine.
  3188. */
  3189. static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
  3190. {
  3191. /* we need to update BSSID in RXE match registers */
  3192. brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
  3193. }
  3194. static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
  3195. {
  3196. wlc_hw->shortslot = shortslot;
  3197. if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
  3198. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  3199. brcms_b_update_slot_timing(wlc_hw, shortslot);
  3200. brcms_c_enable_mac(wlc_hw->wlc);
  3201. }
  3202. }
  3203. /*
  3204. * Suspend the the MAC and update the slot timing
  3205. * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
  3206. */
  3207. static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
  3208. {
  3209. /* use the override if it is set */
  3210. if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
  3211. shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
  3212. if (wlc->shortslot == shortslot)
  3213. return;
  3214. wlc->shortslot = shortslot;
  3215. brcms_b_set_shortslot(wlc->hw, shortslot);
  3216. }
  3217. static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3218. {
  3219. if (wlc->home_chanspec != chanspec) {
  3220. wlc->home_chanspec = chanspec;
  3221. if (wlc->bsscfg->associated)
  3222. wlc->bsscfg->current_bss->chanspec = chanspec;
  3223. }
  3224. }
  3225. void
  3226. brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
  3227. bool mute_tx, struct txpwr_limits *txpwr)
  3228. {
  3229. uint bandunit;
  3230. BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
  3231. wlc_hw->chanspec = chanspec;
  3232. /* Switch bands if necessary */
  3233. if (wlc_hw->_nbands > 1) {
  3234. bandunit = chspec_bandunit(chanspec);
  3235. if (wlc_hw->band->bandunit != bandunit) {
  3236. /* brcms_b_setband disables other bandunit,
  3237. * use light band switch if not up yet
  3238. */
  3239. if (wlc_hw->up) {
  3240. wlc_phy_chanspec_radio_set(wlc_hw->
  3241. bandstate[bandunit]->
  3242. pi, chanspec);
  3243. brcms_b_setband(wlc_hw, bandunit, chanspec);
  3244. } else {
  3245. brcms_c_setxband(wlc_hw, bandunit);
  3246. }
  3247. }
  3248. }
  3249. wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
  3250. if (!wlc_hw->up) {
  3251. if (wlc_hw->clk)
  3252. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
  3253. chanspec);
  3254. wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
  3255. } else {
  3256. wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
  3257. wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
  3258. /* Update muting of the channel */
  3259. brcms_b_mute(wlc_hw, mute_tx);
  3260. }
  3261. }
  3262. /* switch to and initialize new band */
  3263. static void brcms_c_setband(struct brcms_c_info *wlc,
  3264. uint bandunit)
  3265. {
  3266. wlc->band = wlc->bandstate[bandunit];
  3267. if (!wlc->pub->up)
  3268. return;
  3269. /* wait for at least one beacon before entering sleeping state */
  3270. brcms_c_set_ps_ctrl(wlc);
  3271. /* band-specific initializations */
  3272. brcms_c_bsinit(wlc);
  3273. }
  3274. static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
  3275. {
  3276. uint bandunit;
  3277. bool switchband = false;
  3278. u16 old_chanspec = wlc->chanspec;
  3279. if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
  3280. wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
  3281. wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
  3282. return;
  3283. }
  3284. /* Switch bands if necessary */
  3285. if (wlc->pub->_nbands > 1) {
  3286. bandunit = chspec_bandunit(chanspec);
  3287. if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
  3288. switchband = true;
  3289. if (wlc->bandlocked) {
  3290. wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
  3291. "band is locked!\n",
  3292. wlc->pub->unit, __func__,
  3293. CHSPEC_CHANNEL(chanspec));
  3294. return;
  3295. }
  3296. /*
  3297. * should the setband call come after the
  3298. * brcms_b_chanspec() ? if the setband updates
  3299. * (brcms_c_bsinit) use low level calls to inspect and
  3300. * set state, the state inspected may be from the wrong
  3301. * band, or the following brcms_b_set_chanspec() may
  3302. * undo the work.
  3303. */
  3304. brcms_c_setband(wlc, bandunit);
  3305. }
  3306. }
  3307. /* sync up phy/radio chanspec */
  3308. brcms_c_set_phy_chanspec(wlc, chanspec);
  3309. /* init antenna selection */
  3310. if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
  3311. brcms_c_antsel_init(wlc->asi);
  3312. /* Fix the hardware rateset based on bw.
  3313. * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
  3314. */
  3315. brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
  3316. wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
  3317. }
  3318. /* update some mac configuration since chanspec changed */
  3319. brcms_c_ucode_mac_upd(wlc);
  3320. }
  3321. /*
  3322. * This function changes the phytxctl for beacon based on current
  3323. * beacon ratespec AND txant setting as per this table:
  3324. * ratespec CCK ant = wlc->stf->txant
  3325. * OFDM ant = 3
  3326. */
  3327. void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
  3328. u32 bcn_rspec)
  3329. {
  3330. u16 phyctl;
  3331. u16 phytxant = wlc->stf->phytxant;
  3332. u16 mask = PHY_TXC_ANT_MASK;
  3333. /* for non-siso rates or default setting, use the available chains */
  3334. if (BRCMS_PHY_11N_CAP(wlc->band))
  3335. phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
  3336. phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
  3337. phyctl = (phyctl & ~mask) | phytxant;
  3338. brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
  3339. }
  3340. /*
  3341. * centralized protection config change function to simplify debugging, no
  3342. * consistency checking this should be called only on changes to avoid overhead
  3343. * in periodic function
  3344. */
  3345. void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
  3346. {
  3347. BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
  3348. switch (idx) {
  3349. case BRCMS_PROT_G_SPEC:
  3350. wlc->protection->_g = (bool) val;
  3351. break;
  3352. case BRCMS_PROT_G_OVR:
  3353. wlc->protection->g_override = (s8) val;
  3354. break;
  3355. case BRCMS_PROT_G_USER:
  3356. wlc->protection->gmode_user = (u8) val;
  3357. break;
  3358. case BRCMS_PROT_OVERLAP:
  3359. wlc->protection->overlap = (s8) val;
  3360. break;
  3361. case BRCMS_PROT_N_USER:
  3362. wlc->protection->nmode_user = (s8) val;
  3363. break;
  3364. case BRCMS_PROT_N_CFG:
  3365. wlc->protection->n_cfg = (s8) val;
  3366. break;
  3367. case BRCMS_PROT_N_CFG_OVR:
  3368. wlc->protection->n_cfg_override = (s8) val;
  3369. break;
  3370. case BRCMS_PROT_N_NONGF:
  3371. wlc->protection->nongf = (bool) val;
  3372. break;
  3373. case BRCMS_PROT_N_NONGF_OVR:
  3374. wlc->protection->nongf_override = (s8) val;
  3375. break;
  3376. case BRCMS_PROT_N_PAM_OVR:
  3377. wlc->protection->n_pam_override = (s8) val;
  3378. break;
  3379. case BRCMS_PROT_N_OBSS:
  3380. wlc->protection->n_obss = (bool) val;
  3381. break;
  3382. default:
  3383. break;
  3384. }
  3385. }
  3386. static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
  3387. {
  3388. if (wlc->pub->up) {
  3389. brcms_c_update_beacon(wlc);
  3390. brcms_c_update_probe_resp(wlc, true);
  3391. }
  3392. }
  3393. static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
  3394. {
  3395. wlc->stf->ldpc = val;
  3396. if (wlc->pub->up) {
  3397. brcms_c_update_beacon(wlc);
  3398. brcms_c_update_probe_resp(wlc, true);
  3399. wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
  3400. }
  3401. }
  3402. void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
  3403. const struct ieee80211_tx_queue_params *params,
  3404. bool suspend)
  3405. {
  3406. int i;
  3407. struct shm_acparams acp_shm;
  3408. u16 *shm_entry;
  3409. /* Only apply params if the core is out of reset and has clocks */
  3410. if (!wlc->clk) {
  3411. wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
  3412. __func__);
  3413. return;
  3414. }
  3415. memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
  3416. /* fill in shm ac params struct */
  3417. acp_shm.txop = params->txop;
  3418. /* convert from units of 32us to us for ucode */
  3419. wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
  3420. EDCF_TXOP2USEC(acp_shm.txop);
  3421. acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
  3422. if (aci == AC_VI && acp_shm.txop == 0
  3423. && acp_shm.aifs < EDCF_AIFSN_MAX)
  3424. acp_shm.aifs++;
  3425. if (acp_shm.aifs < EDCF_AIFSN_MIN
  3426. || acp_shm.aifs > EDCF_AIFSN_MAX) {
  3427. wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
  3428. "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
  3429. } else {
  3430. acp_shm.cwmin = params->cw_min;
  3431. acp_shm.cwmax = params->cw_max;
  3432. acp_shm.cwcur = acp_shm.cwmin;
  3433. acp_shm.bslots =
  3434. R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
  3435. acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
  3436. /* Indicate the new params to the ucode */
  3437. acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
  3438. wme_ac2fifo[aci] *
  3439. M_EDCF_QLEN +
  3440. M_EDCF_STATUS_OFF));
  3441. acp_shm.status |= WME_STATUS_NEWAC;
  3442. /* Fill in shm acparam table */
  3443. shm_entry = (u16 *) &acp_shm;
  3444. for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
  3445. brcms_b_write_shm(wlc->hw,
  3446. M_EDCF_QINFO +
  3447. wme_ac2fifo[aci] * M_EDCF_QLEN + i,
  3448. *shm_entry++);
  3449. }
  3450. if (suspend) {
  3451. brcms_c_suspend_mac_and_wait(wlc);
  3452. brcms_c_enable_mac(wlc);
  3453. }
  3454. }
  3455. static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
  3456. {
  3457. u16 aci;
  3458. int i_ac;
  3459. struct ieee80211_tx_queue_params txq_pars;
  3460. static const struct edcf_acparam default_edcf_acparams[] = {
  3461. {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
  3462. {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
  3463. {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
  3464. {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
  3465. }; /* ucode needs these parameters during its initialization */
  3466. const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
  3467. for (i_ac = 0; i_ac < AC_COUNT; i_ac++, edcf_acp++) {
  3468. /* find out which ac this set of params applies to */
  3469. aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
  3470. /* fill in shm ac params struct */
  3471. txq_pars.txop = edcf_acp->TXOP;
  3472. txq_pars.aifs = edcf_acp->ACI;
  3473. /* CWmin = 2^(ECWmin) - 1 */
  3474. txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
  3475. /* CWmax = 2^(ECWmax) - 1 */
  3476. txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
  3477. >> EDCF_ECWMAX_SHIFT);
  3478. brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
  3479. }
  3480. if (suspend) {
  3481. brcms_c_suspend_mac_and_wait(wlc);
  3482. brcms_c_enable_mac(wlc);
  3483. }
  3484. }
  3485. static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
  3486. {
  3487. /* Don't start the timer if HWRADIO feature is disabled */
  3488. if (wlc->radio_monitor)
  3489. return;
  3490. wlc->radio_monitor = true;
  3491. brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
  3492. brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
  3493. }
  3494. static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
  3495. {
  3496. if (!wlc->radio_monitor)
  3497. return true;
  3498. wlc->radio_monitor = false;
  3499. brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
  3500. return brcms_del_timer(wlc->radio_timer);
  3501. }
  3502. /* read hwdisable state and propagate to wlc flag */
  3503. static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
  3504. {
  3505. if (wlc->pub->hw_off)
  3506. return;
  3507. if (brcms_b_radio_read_hwdisabled(wlc->hw))
  3508. mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3509. else
  3510. mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
  3511. }
  3512. /* update hwradio status and return it */
  3513. bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
  3514. {
  3515. brcms_c_radio_hwdisable_upd(wlc);
  3516. return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
  3517. true : false;
  3518. }
  3519. /* periodical query hw radio button while driver is "down" */
  3520. static void brcms_c_radio_timer(void *arg)
  3521. {
  3522. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3523. if (brcms_deviceremoved(wlc)) {
  3524. wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
  3525. __func__);
  3526. brcms_down(wlc->wl);
  3527. return;
  3528. }
  3529. brcms_c_radio_hwdisable_upd(wlc);
  3530. }
  3531. /* common low-level watchdog code */
  3532. static void brcms_b_watchdog(void *arg)
  3533. {
  3534. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3535. struct brcms_hardware *wlc_hw = wlc->hw;
  3536. BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
  3537. if (!wlc_hw->up)
  3538. return;
  3539. /* increment second count */
  3540. wlc_hw->now++;
  3541. /* Check for FIFO error interrupts */
  3542. brcms_b_fifoerrors(wlc_hw);
  3543. /* make sure RX dma has buffers */
  3544. dma_rxfill(wlc->hw->di[RX_FIFO]);
  3545. wlc_phy_watchdog(wlc_hw->band->pi);
  3546. }
  3547. /* common watchdog code */
  3548. static void brcms_c_watchdog(void *arg)
  3549. {
  3550. struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
  3551. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  3552. if (!wlc->pub->up)
  3553. return;
  3554. if (brcms_deviceremoved(wlc)) {
  3555. wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
  3556. __func__);
  3557. brcms_down(wlc->wl);
  3558. return;
  3559. }
  3560. /* increment second count */
  3561. wlc->pub->now++;
  3562. brcms_c_radio_hwdisable_upd(wlc);
  3563. /* if radio is disable, driver may be down, quit here */
  3564. if (wlc->pub->radio_disabled)
  3565. return;
  3566. brcms_b_watchdog(wlc);
  3567. /*
  3568. * occasionally sample mac stat counters to
  3569. * detect 16-bit counter wrap
  3570. */
  3571. if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
  3572. brcms_c_statsupd(wlc);
  3573. if (BRCMS_ISNPHY(wlc->band) &&
  3574. ((wlc->pub->now - wlc->tempsense_lasttime) >=
  3575. BRCMS_TEMPSENSE_PERIOD)) {
  3576. wlc->tempsense_lasttime = wlc->pub->now;
  3577. brcms_c_tempsense_upd(wlc);
  3578. }
  3579. }
  3580. static void brcms_c_watchdog_by_timer(void *arg)
  3581. {
  3582. brcms_c_watchdog(arg);
  3583. }
  3584. static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
  3585. {
  3586. wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
  3587. wlc, "watchdog");
  3588. if (!wlc->wdtimer) {
  3589. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
  3590. "failed\n", unit);
  3591. goto fail;
  3592. }
  3593. wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
  3594. wlc, "radio");
  3595. if (!wlc->radio_timer) {
  3596. wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
  3597. "failed\n", unit);
  3598. goto fail;
  3599. }
  3600. return true;
  3601. fail:
  3602. return false;
  3603. }
  3604. /*
  3605. * Initialize brcms_c_info default values ...
  3606. * may get overrides later in this function
  3607. */
  3608. static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
  3609. {
  3610. int i;
  3611. /* Save our copy of the chanspec */
  3612. wlc->chanspec = ch20mhz_chspec(1);
  3613. /* various 802.11g modes */
  3614. wlc->shortslot = false;
  3615. wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
  3616. brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
  3617. brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
  3618. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
  3619. BRCMS_PROTECTION_AUTO);
  3620. brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
  3621. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
  3622. BRCMS_PROTECTION_AUTO);
  3623. brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
  3624. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
  3625. brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
  3626. BRCMS_PROTECTION_CTL_OVERLAP);
  3627. /* 802.11g draft 4.0 NonERP elt advertisement */
  3628. wlc->include_legacy_erp = true;
  3629. wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
  3630. wlc->stf->txant = ANT_TX_DEF;
  3631. wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
  3632. wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
  3633. for (i = 0; i < NFIFO; i++)
  3634. wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
  3635. wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
  3636. /* default rate fallback retry limits */
  3637. wlc->SFBL = RETRY_SHORT_FB;
  3638. wlc->LFBL = RETRY_LONG_FB;
  3639. /* default mac retry limits */
  3640. wlc->SRL = RETRY_SHORT_DEF;
  3641. wlc->LRL = RETRY_LONG_DEF;
  3642. /* WME QoS mode is Auto by default */
  3643. wlc->pub->_ampdu = AMPDU_AGG_HOST;
  3644. wlc->pub->bcmerror = 0;
  3645. }
  3646. static uint brcms_c_attach_module(struct brcms_c_info *wlc)
  3647. {
  3648. uint err = 0;
  3649. uint unit;
  3650. unit = wlc->pub->unit;
  3651. wlc->asi = brcms_c_antsel_attach(wlc);
  3652. if (wlc->asi == NULL) {
  3653. wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
  3654. "failed\n", unit);
  3655. err = 44;
  3656. goto fail;
  3657. }
  3658. wlc->ampdu = brcms_c_ampdu_attach(wlc);
  3659. if (wlc->ampdu == NULL) {
  3660. wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
  3661. "failed\n", unit);
  3662. err = 50;
  3663. goto fail;
  3664. }
  3665. if ((brcms_c_stf_attach(wlc) != 0)) {
  3666. wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
  3667. "failed\n", unit);
  3668. err = 68;
  3669. goto fail;
  3670. }
  3671. fail:
  3672. return err;
  3673. }
  3674. struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
  3675. {
  3676. return wlc->pub;
  3677. }
  3678. /* low level attach
  3679. * run backplane attach, init nvram
  3680. * run phy attach
  3681. * initialize software state for each core and band
  3682. * put the whole chip in reset(driver down state), no clock
  3683. */
  3684. static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
  3685. uint unit, bool piomode, void __iomem *regsva,
  3686. struct pci_dev *btparam)
  3687. {
  3688. struct brcms_hardware *wlc_hw;
  3689. struct d11regs __iomem *regs;
  3690. char *macaddr = NULL;
  3691. uint err = 0;
  3692. uint j;
  3693. bool wme = false;
  3694. struct shared_phy_params sha_params;
  3695. struct wiphy *wiphy = wlc->wiphy;
  3696. BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
  3697. device);
  3698. wme = true;
  3699. wlc_hw = wlc->hw;
  3700. wlc_hw->wlc = wlc;
  3701. wlc_hw->unit = unit;
  3702. wlc_hw->band = wlc_hw->bandstate[0];
  3703. wlc_hw->_piomode = piomode;
  3704. /* populate struct brcms_hardware with default values */
  3705. brcms_b_info_init(wlc_hw);
  3706. /*
  3707. * Do the hardware portion of the attach. Also initialize software
  3708. * state that depends on the particular hardware we are running.
  3709. */
  3710. wlc_hw->sih = ai_attach(regsva, btparam);
  3711. if (wlc_hw->sih == NULL) {
  3712. wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
  3713. unit);
  3714. err = 11;
  3715. goto fail;
  3716. }
  3717. /* verify again the device is supported */
  3718. if (!brcms_c_chipmatch(vendor, device)) {
  3719. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
  3720. "vendor/device (0x%x/0x%x)\n",
  3721. unit, vendor, device);
  3722. err = 12;
  3723. goto fail;
  3724. }
  3725. wlc_hw->vendorid = vendor;
  3726. wlc_hw->deviceid = device;
  3727. /* set bar0 window to point at D11 core */
  3728. wlc_hw->regs = (struct d11regs __iomem *)
  3729. ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
  3730. wlc_hw->corerev = ai_corerev(wlc_hw->sih);
  3731. regs = wlc_hw->regs;
  3732. wlc->regs = wlc_hw->regs;
  3733. /* validate chip, chiprev and corerev */
  3734. if (!brcms_c_isgoodchip(wlc_hw)) {
  3735. err = 13;
  3736. goto fail;
  3737. }
  3738. /* initialize power control registers */
  3739. ai_clkctl_init(wlc_hw->sih);
  3740. /* request fastclock and force fastclock for the rest of attach
  3741. * bring the d11 core out of reset.
  3742. * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
  3743. * is still false; But it will be called again inside wlc_corereset,
  3744. * after d11 is out of reset.
  3745. */
  3746. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  3747. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  3748. if (!brcms_b_validate_chip_access(wlc_hw)) {
  3749. wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
  3750. "failed\n", unit);
  3751. err = 14;
  3752. goto fail;
  3753. }
  3754. /* get the board rev, used just below */
  3755. j = getintvar(wlc_hw->sih, BRCMS_SROM_BOARDREV);
  3756. /* promote srom boardrev of 0xFF to 1 */
  3757. if (j == BOARDREV_PROMOTABLE)
  3758. j = BOARDREV_PROMOTED;
  3759. wlc_hw->boardrev = (u16) j;
  3760. if (!brcms_c_validboardtype(wlc_hw)) {
  3761. wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
  3762. "board type (0x%x)" " or revision level (0x%x)\n",
  3763. unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
  3764. err = 15;
  3765. goto fail;
  3766. }
  3767. wlc_hw->sromrev = (u8) getintvar(wlc_hw->sih, BRCMS_SROM_REV);
  3768. wlc_hw->boardflags = (u32) getintvar(wlc_hw->sih,
  3769. BRCMS_SROM_BOARDFLAGS);
  3770. wlc_hw->boardflags2 = (u32) getintvar(wlc_hw->sih,
  3771. BRCMS_SROM_BOARDFLAGS2);
  3772. if (wlc_hw->boardflags & BFL_NOPLLDOWN)
  3773. brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
  3774. /* check device id(srom, nvram etc.) to set bands */
  3775. if (wlc_hw->deviceid == BCM43224_D11N_ID ||
  3776. wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
  3777. /* Dualband boards */
  3778. wlc_hw->_nbands = 2;
  3779. else
  3780. wlc_hw->_nbands = 1;
  3781. if ((wlc_hw->sih->chip == BCM43225_CHIP_ID))
  3782. wlc_hw->_nbands = 1;
  3783. /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
  3784. * unconditionally does the init of these values
  3785. */
  3786. wlc->vendorid = wlc_hw->vendorid;
  3787. wlc->deviceid = wlc_hw->deviceid;
  3788. wlc->pub->sih = wlc_hw->sih;
  3789. wlc->pub->corerev = wlc_hw->corerev;
  3790. wlc->pub->sromrev = wlc_hw->sromrev;
  3791. wlc->pub->boardrev = wlc_hw->boardrev;
  3792. wlc->pub->boardflags = wlc_hw->boardflags;
  3793. wlc->pub->boardflags2 = wlc_hw->boardflags2;
  3794. wlc->pub->_nbands = wlc_hw->_nbands;
  3795. wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
  3796. if (wlc_hw->physhim == NULL) {
  3797. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
  3798. "failed\n", unit);
  3799. err = 25;
  3800. goto fail;
  3801. }
  3802. /* pass all the parameters to wlc_phy_shared_attach in one struct */
  3803. sha_params.sih = wlc_hw->sih;
  3804. sha_params.physhim = wlc_hw->physhim;
  3805. sha_params.unit = unit;
  3806. sha_params.corerev = wlc_hw->corerev;
  3807. sha_params.vid = wlc_hw->vendorid;
  3808. sha_params.did = wlc_hw->deviceid;
  3809. sha_params.chip = wlc_hw->sih->chip;
  3810. sha_params.chiprev = wlc_hw->sih->chiprev;
  3811. sha_params.chippkg = wlc_hw->sih->chippkg;
  3812. sha_params.sromrev = wlc_hw->sromrev;
  3813. sha_params.boardtype = wlc_hw->sih->boardtype;
  3814. sha_params.boardrev = wlc_hw->boardrev;
  3815. sha_params.boardvendor = wlc_hw->sih->boardvendor;
  3816. sha_params.boardflags = wlc_hw->boardflags;
  3817. sha_params.boardflags2 = wlc_hw->boardflags2;
  3818. sha_params.buscorerev = wlc_hw->sih->buscorerev;
  3819. /* alloc and save pointer to shared phy state area */
  3820. wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
  3821. if (!wlc_hw->phy_sh) {
  3822. err = 16;
  3823. goto fail;
  3824. }
  3825. /* initialize software state for each core and band */
  3826. for (j = 0; j < wlc_hw->_nbands; j++) {
  3827. /*
  3828. * band0 is always 2.4Ghz
  3829. * band1, if present, is 5Ghz
  3830. */
  3831. brcms_c_setxband(wlc_hw, j);
  3832. wlc_hw->band->bandunit = j;
  3833. wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3834. wlc->band->bandunit = j;
  3835. wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
  3836. wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
  3837. wlc_hw->machwcap = R_REG(&regs->machwcap);
  3838. wlc_hw->machwcap_backup = wlc_hw->machwcap;
  3839. /* init tx fifo size */
  3840. wlc_hw->xmtfifo_sz =
  3841. xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
  3842. /* Get a phy for this band */
  3843. wlc_hw->band->pi =
  3844. wlc_phy_attach(wlc_hw->phy_sh, regs,
  3845. wlc_hw->band->bandtype,
  3846. wlc->wiphy);
  3847. if (wlc_hw->band->pi == NULL) {
  3848. wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
  3849. "attach failed\n", unit);
  3850. err = 17;
  3851. goto fail;
  3852. }
  3853. wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
  3854. wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
  3855. &wlc_hw->band->phyrev,
  3856. &wlc_hw->band->radioid,
  3857. &wlc_hw->band->radiorev);
  3858. wlc_hw->band->abgphy_encore =
  3859. wlc_phy_get_encore(wlc_hw->band->pi);
  3860. wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
  3861. wlc_hw->band->core_flags =
  3862. wlc_phy_get_coreflags(wlc_hw->band->pi);
  3863. /* verify good phy_type & supported phy revision */
  3864. if (BRCMS_ISNPHY(wlc_hw->band)) {
  3865. if (NCONF_HAS(wlc_hw->band->phyrev))
  3866. goto good_phy;
  3867. else
  3868. goto bad_phy;
  3869. } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
  3870. if (LCNCONF_HAS(wlc_hw->band->phyrev))
  3871. goto good_phy;
  3872. else
  3873. goto bad_phy;
  3874. } else {
  3875. bad_phy:
  3876. wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
  3877. "phy type/rev (%d/%d)\n", unit,
  3878. wlc_hw->band->phytype, wlc_hw->band->phyrev);
  3879. err = 18;
  3880. goto fail;
  3881. }
  3882. good_phy:
  3883. /*
  3884. * BMAC_NOTE: wlc->band->pi should not be set below and should
  3885. * be done in the high level attach. However we can not make
  3886. * that change until all low level access is changed to
  3887. * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
  3888. * keeping wlc_hw->band->pi as well for incremental update of
  3889. * low level fns, and cut over low only init when all fns
  3890. * updated.
  3891. */
  3892. wlc->band->pi = wlc_hw->band->pi;
  3893. wlc->band->phytype = wlc_hw->band->phytype;
  3894. wlc->band->phyrev = wlc_hw->band->phyrev;
  3895. wlc->band->radioid = wlc_hw->band->radioid;
  3896. wlc->band->radiorev = wlc_hw->band->radiorev;
  3897. /* default contention windows size limits */
  3898. wlc_hw->band->CWmin = APHY_CWMIN;
  3899. wlc_hw->band->CWmax = PHY_CWMAX;
  3900. if (!brcms_b_attach_dmapio(wlc, j, wme)) {
  3901. err = 19;
  3902. goto fail;
  3903. }
  3904. }
  3905. /* disable core to match driver "down" state */
  3906. brcms_c_coredisable(wlc_hw);
  3907. /* Match driver "down" state */
  3908. ai_pci_down(wlc_hw->sih);
  3909. /* register sb interrupt callback functions */
  3910. ai_register_intr_callback(wlc_hw->sih, (void *)brcms_c_wlintrsoff,
  3911. (void *)brcms_c_wlintrsrestore, NULL, wlc);
  3912. /* turn off pll and xtal to match driver "down" state */
  3913. brcms_b_xtal(wlc_hw, OFF);
  3914. /* *******************************************************************
  3915. * The hardware is in the DOWN state at this point. D11 core
  3916. * or cores are in reset with clocks off, and the board PLLs
  3917. * are off if possible.
  3918. *
  3919. * Beyond this point, wlc->sbclk == false and chip registers
  3920. * should not be touched.
  3921. *********************************************************************
  3922. */
  3923. /* init etheraddr state variables */
  3924. macaddr = brcms_c_get_macaddr(wlc_hw);
  3925. if (macaddr == NULL) {
  3926. wiphy_err(wiphy, "wl%d: brcms_b_attach: macaddr not found\n",
  3927. unit);
  3928. err = 21;
  3929. goto fail;
  3930. }
  3931. if (!mac_pton(macaddr, wlc_hw->etheraddr) ||
  3932. is_broadcast_ether_addr(wlc_hw->etheraddr) ||
  3933. is_zero_ether_addr(wlc_hw->etheraddr)) {
  3934. wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr %s\n",
  3935. unit, macaddr);
  3936. err = 22;
  3937. goto fail;
  3938. }
  3939. BCMMSG(wlc->wiphy,
  3940. "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
  3941. wlc_hw->deviceid, wlc_hw->_nbands,
  3942. wlc_hw->sih->boardtype, macaddr);
  3943. return err;
  3944. fail:
  3945. wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
  3946. err);
  3947. return err;
  3948. }
  3949. static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
  3950. {
  3951. uint unit;
  3952. unit = wlc->pub->unit;
  3953. if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
  3954. /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
  3955. wlc->band->antgain = 8;
  3956. } else if (wlc->band->antgain == -1) {
  3957. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3958. " srom, using 2dB\n", unit, __func__);
  3959. wlc->band->antgain = 8;
  3960. } else {
  3961. s8 gain, fract;
  3962. /* Older sroms specified gain in whole dbm only. In order
  3963. * be able to specify qdbm granularity and remain backward
  3964. * compatible the whole dbms are now encoded in only
  3965. * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
  3966. * 6 bit signed number ranges from -32 - 31.
  3967. *
  3968. * Examples:
  3969. * 0x1 = 1 db,
  3970. * 0xc1 = 1.75 db (1 + 3 quarters),
  3971. * 0x3f = -1 (-1 + 0 quarters),
  3972. * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
  3973. * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
  3974. */
  3975. gain = wlc->band->antgain & 0x3f;
  3976. gain <<= 2; /* Sign extend */
  3977. gain >>= 2;
  3978. fract = (wlc->band->antgain & 0xc0) >> 6;
  3979. wlc->band->antgain = 4 * gain + fract;
  3980. }
  3981. }
  3982. static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
  3983. {
  3984. int aa;
  3985. uint unit;
  3986. int bandtype;
  3987. struct si_pub *sih = wlc->hw->sih;
  3988. unit = wlc->pub->unit;
  3989. bandtype = wlc->band->bandtype;
  3990. /* get antennas available */
  3991. if (bandtype == BRCM_BAND_5G)
  3992. aa = (s8) getintvar(sih, BRCMS_SROM_AA5G);
  3993. else
  3994. aa = (s8) getintvar(sih, BRCMS_SROM_AA2G);
  3995. if ((aa < 1) || (aa > 15)) {
  3996. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
  3997. " srom (0x%x), using 3\n", unit, __func__, aa);
  3998. aa = 3;
  3999. }
  4000. /* reset the defaults if we have a single antenna */
  4001. if (aa == 1) {
  4002. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
  4003. wlc->stf->txant = ANT_TX_FORCE_0;
  4004. } else if (aa == 2) {
  4005. wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
  4006. wlc->stf->txant = ANT_TX_FORCE_1;
  4007. } else {
  4008. }
  4009. /* Compute Antenna Gain */
  4010. if (bandtype == BRCM_BAND_5G)
  4011. wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG1);
  4012. else
  4013. wlc->band->antgain = (s8) getintvar(sih, BRCMS_SROM_AG0);
  4014. brcms_c_attach_antgain_init(wlc);
  4015. return true;
  4016. }
  4017. static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
  4018. {
  4019. u16 chanspec;
  4020. struct brcms_band *band;
  4021. struct brcms_bss_info *bi = wlc->default_bss;
  4022. /* init default and target BSS with some sane initial values */
  4023. memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
  4024. bi->beacon_period = BEACON_INTERVAL_DEFAULT;
  4025. /* fill the default channel as the first valid channel
  4026. * starting from the 2G channels
  4027. */
  4028. chanspec = ch20mhz_chspec(1);
  4029. wlc->home_chanspec = bi->chanspec = chanspec;
  4030. /* find the band of our default channel */
  4031. band = wlc->band;
  4032. if (wlc->pub->_nbands > 1 &&
  4033. band->bandunit != chspec_bandunit(chanspec))
  4034. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  4035. /* init bss rates to the band specific default rate set */
  4036. brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
  4037. band->bandtype, false, BRCMS_RATE_MASK_FULL,
  4038. (bool) (wlc->pub->_n_enab & SUPPORT_11N),
  4039. brcms_chspec_bw(chanspec), wlc->stf->txstreams);
  4040. if (wlc->pub->_n_enab & SUPPORT_11N)
  4041. bi->flags |= BRCMS_BSS_HT;
  4042. }
  4043. static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
  4044. {
  4045. struct brcms_txq_info *qi, *p;
  4046. qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
  4047. if (qi != NULL) {
  4048. /*
  4049. * Have enough room for control packets along with HI watermark
  4050. * Also, add room to txq for total psq packets if all the SCBs
  4051. * leave PS mode. The watermark for flowcontrol to OS packets
  4052. * will remain the same
  4053. */
  4054. brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
  4055. 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
  4056. /* add this queue to the the global list */
  4057. p = wlc->tx_queues;
  4058. if (p == NULL) {
  4059. wlc->tx_queues = qi;
  4060. } else {
  4061. while (p->next != NULL)
  4062. p = p->next;
  4063. p->next = qi;
  4064. }
  4065. }
  4066. return qi;
  4067. }
  4068. static void brcms_c_txq_free(struct brcms_c_info *wlc,
  4069. struct brcms_txq_info *qi)
  4070. {
  4071. struct brcms_txq_info *p;
  4072. if (qi == NULL)
  4073. return;
  4074. /* remove the queue from the linked list */
  4075. p = wlc->tx_queues;
  4076. if (p == qi)
  4077. wlc->tx_queues = p->next;
  4078. else {
  4079. while (p != NULL && p->next != qi)
  4080. p = p->next;
  4081. if (p != NULL)
  4082. p->next = p->next->next;
  4083. }
  4084. kfree(qi);
  4085. }
  4086. static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
  4087. {
  4088. uint i;
  4089. struct brcms_band *band;
  4090. for (i = 0; i < wlc->pub->_nbands; i++) {
  4091. band = wlc->bandstate[i];
  4092. if (band->bandtype == BRCM_BAND_5G) {
  4093. if ((bwcap == BRCMS_N_BW_40ALL)
  4094. || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
  4095. band->mimo_cap_40 = true;
  4096. else
  4097. band->mimo_cap_40 = false;
  4098. } else {
  4099. if (bwcap == BRCMS_N_BW_40ALL)
  4100. band->mimo_cap_40 = true;
  4101. else
  4102. band->mimo_cap_40 = false;
  4103. }
  4104. }
  4105. }
  4106. static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
  4107. {
  4108. /* free timer state */
  4109. if (wlc->wdtimer) {
  4110. brcms_free_timer(wlc->wdtimer);
  4111. wlc->wdtimer = NULL;
  4112. }
  4113. if (wlc->radio_timer) {
  4114. brcms_free_timer(wlc->radio_timer);
  4115. wlc->radio_timer = NULL;
  4116. }
  4117. }
  4118. static void brcms_c_detach_module(struct brcms_c_info *wlc)
  4119. {
  4120. if (wlc->asi) {
  4121. brcms_c_antsel_detach(wlc->asi);
  4122. wlc->asi = NULL;
  4123. }
  4124. if (wlc->ampdu) {
  4125. brcms_c_ampdu_detach(wlc->ampdu);
  4126. wlc->ampdu = NULL;
  4127. }
  4128. brcms_c_stf_detach(wlc);
  4129. }
  4130. /*
  4131. * low level detach
  4132. */
  4133. static int brcms_b_detach(struct brcms_c_info *wlc)
  4134. {
  4135. uint i;
  4136. struct brcms_hw_band *band;
  4137. struct brcms_hardware *wlc_hw = wlc->hw;
  4138. int callbacks;
  4139. callbacks = 0;
  4140. if (wlc_hw->sih) {
  4141. /*
  4142. * detach interrupt sync mechanism since interrupt is disabled
  4143. * and per-port interrupt object may has been freed. this must
  4144. * be done before sb core switch
  4145. */
  4146. ai_deregister_intr_callback(wlc_hw->sih);
  4147. ai_pci_sleep(wlc_hw->sih);
  4148. }
  4149. brcms_b_detach_dmapio(wlc_hw);
  4150. band = wlc_hw->band;
  4151. for (i = 0; i < wlc_hw->_nbands; i++) {
  4152. if (band->pi) {
  4153. /* Detach this band's phy */
  4154. wlc_phy_detach(band->pi);
  4155. band->pi = NULL;
  4156. }
  4157. band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
  4158. }
  4159. /* Free shared phy state */
  4160. kfree(wlc_hw->phy_sh);
  4161. wlc_phy_shim_detach(wlc_hw->physhim);
  4162. if (wlc_hw->sih) {
  4163. ai_detach(wlc_hw->sih);
  4164. wlc_hw->sih = NULL;
  4165. }
  4166. return callbacks;
  4167. }
  4168. /*
  4169. * Return a count of the number of driver callbacks still pending.
  4170. *
  4171. * General policy is that brcms_c_detach can only dealloc/free software states.
  4172. * It can NOT touch hardware registers since the d11core may be in reset and
  4173. * clock may not be available.
  4174. * One exception is sb register access, which is possible if crystal is turned
  4175. * on after "down" state, driver should avoid software timer with the exception
  4176. * of radio_monitor.
  4177. */
  4178. uint brcms_c_detach(struct brcms_c_info *wlc)
  4179. {
  4180. uint callbacks = 0;
  4181. if (wlc == NULL)
  4182. return 0;
  4183. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  4184. callbacks += brcms_b_detach(wlc);
  4185. /* delete software timers */
  4186. if (!brcms_c_radio_monitor_stop(wlc))
  4187. callbacks++;
  4188. brcms_c_channel_mgr_detach(wlc->cmi);
  4189. brcms_c_timers_deinit(wlc);
  4190. brcms_c_detach_module(wlc);
  4191. while (wlc->tx_queues != NULL)
  4192. brcms_c_txq_free(wlc, wlc->tx_queues);
  4193. brcms_c_detach_mfree(wlc);
  4194. return callbacks;
  4195. }
  4196. /* update state that depends on the current value of "ap" */
  4197. static void brcms_c_ap_upd(struct brcms_c_info *wlc)
  4198. {
  4199. /* STA-BSS; short capable */
  4200. wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
  4201. }
  4202. /* Initialize just the hardware when coming out of POR or S3/S5 system states */
  4203. static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
  4204. {
  4205. if (wlc_hw->wlc->pub->hw_up)
  4206. return;
  4207. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4208. /*
  4209. * Enable pll and xtal, initialize the power control registers,
  4210. * and force fastclock for the remainder of brcms_c_up().
  4211. */
  4212. brcms_b_xtal(wlc_hw, ON);
  4213. ai_clkctl_init(wlc_hw->sih);
  4214. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  4215. ai_pci_fixcfg(wlc_hw->sih);
  4216. /*
  4217. * AI chip doesn't restore bar0win2 on
  4218. * hibernation/resume, need sw fixup
  4219. */
  4220. if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
  4221. (wlc_hw->sih->chip == BCM43225_CHIP_ID))
  4222. wlc_hw->regs = (struct d11regs __iomem *)
  4223. ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
  4224. /*
  4225. * Inform phy that a POR reset has occurred so
  4226. * it does a complete phy init
  4227. */
  4228. wlc_phy_por_inform(wlc_hw->band->pi);
  4229. wlc_hw->ucode_loaded = false;
  4230. wlc_hw->wlc->pub->hw_up = true;
  4231. if ((wlc_hw->boardflags & BFL_FEM)
  4232. && (wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
  4233. if (!
  4234. (wlc_hw->boardrev >= 0x1250
  4235. && (wlc_hw->boardflags & BFL_FEM_BT)))
  4236. ai_epa_4313war(wlc_hw->sih);
  4237. }
  4238. }
  4239. static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
  4240. {
  4241. uint coremask;
  4242. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4243. /*
  4244. * Enable pll and xtal, initialize the power control registers,
  4245. * and force fastclock for the remainder of brcms_c_up().
  4246. */
  4247. brcms_b_xtal(wlc_hw, ON);
  4248. ai_clkctl_init(wlc_hw->sih);
  4249. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  4250. /*
  4251. * Configure pci/pcmcia here instead of in brcms_c_attach()
  4252. * to allow mfg hotswap: down, hotswap (chip power cycle), up.
  4253. */
  4254. coremask = (1 << wlc_hw->wlc->core->coreidx);
  4255. ai_pci_setup(wlc_hw->sih, coremask);
  4256. /*
  4257. * Need to read the hwradio status here to cover the case where the
  4258. * system is loaded with the hw radio disabled. We do not want to
  4259. * bring the driver up in this case.
  4260. */
  4261. if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
  4262. /* put SB PCI in down state again */
  4263. ai_pci_down(wlc_hw->sih);
  4264. brcms_b_xtal(wlc_hw, OFF);
  4265. return -ENOMEDIUM;
  4266. }
  4267. ai_pci_up(wlc_hw->sih);
  4268. /* reset the d11 core */
  4269. brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
  4270. return 0;
  4271. }
  4272. static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
  4273. {
  4274. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4275. wlc_hw->up = true;
  4276. wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
  4277. /* FULLY enable dynamic power control and d11 core interrupt */
  4278. brcms_b_clkctl_clk(wlc_hw, CLK_DYNAMIC);
  4279. brcms_intrson(wlc_hw->wlc->wl);
  4280. return 0;
  4281. }
  4282. /*
  4283. * Write WME tunable parameters for retransmit/max rate
  4284. * from wlc struct to ucode
  4285. */
  4286. static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
  4287. {
  4288. int ac;
  4289. /* Need clock to do this */
  4290. if (!wlc->clk)
  4291. return;
  4292. for (ac = 0; ac < AC_COUNT; ac++)
  4293. brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
  4294. wlc->wme_retries[ac]);
  4295. }
  4296. /* make interface operational */
  4297. int brcms_c_up(struct brcms_c_info *wlc)
  4298. {
  4299. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  4300. /* HW is turned off so don't try to access it */
  4301. if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
  4302. return -ENOMEDIUM;
  4303. if (!wlc->pub->hw_up) {
  4304. brcms_b_hw_up(wlc->hw);
  4305. wlc->pub->hw_up = true;
  4306. }
  4307. if ((wlc->pub->boardflags & BFL_FEM)
  4308. && (wlc->pub->sih->chip == BCM4313_CHIP_ID)) {
  4309. if (wlc->pub->boardrev >= 0x1250
  4310. && (wlc->pub->boardflags & BFL_FEM_BT))
  4311. brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
  4312. MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
  4313. else
  4314. brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
  4315. MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
  4316. }
  4317. /*
  4318. * Need to read the hwradio status here to cover the case where the
  4319. * system is loaded with the hw radio disabled. We do not want to bring
  4320. * the driver up in this case. If radio is disabled, abort up, lower
  4321. * power, start radio timer and return 0(for NDIS) don't call
  4322. * radio_update to avoid looping brcms_c_up.
  4323. *
  4324. * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
  4325. */
  4326. if (!wlc->pub->radio_disabled) {
  4327. int status = brcms_b_up_prep(wlc->hw);
  4328. if (status == -ENOMEDIUM) {
  4329. if (!mboolisset
  4330. (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
  4331. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  4332. mboolset(wlc->pub->radio_disabled,
  4333. WL_RADIO_HW_DISABLE);
  4334. if (bsscfg->enable && bsscfg->BSS)
  4335. wiphy_err(wlc->wiphy, "wl%d: up"
  4336. ": rfdisable -> "
  4337. "bsscfg_disable()\n",
  4338. wlc->pub->unit);
  4339. }
  4340. }
  4341. }
  4342. if (wlc->pub->radio_disabled) {
  4343. brcms_c_radio_monitor_start(wlc);
  4344. return 0;
  4345. }
  4346. /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
  4347. wlc->clk = true;
  4348. brcms_c_radio_monitor_stop(wlc);
  4349. /* Set EDCF hostflags */
  4350. brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
  4351. brcms_init(wlc->wl);
  4352. wlc->pub->up = true;
  4353. if (wlc->bandinit_pending) {
  4354. brcms_c_suspend_mac_and_wait(wlc);
  4355. brcms_c_set_chanspec(wlc, wlc->default_bss->chanspec);
  4356. wlc->bandinit_pending = false;
  4357. brcms_c_enable_mac(wlc);
  4358. }
  4359. brcms_b_up_finish(wlc->hw);
  4360. /* Program the TX wme params with the current settings */
  4361. brcms_c_wme_retries_write(wlc);
  4362. /* start one second watchdog timer */
  4363. brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
  4364. wlc->WDarmed = true;
  4365. /* ensure antenna config is up to date */
  4366. brcms_c_stf_phy_txant_upd(wlc);
  4367. /* ensure LDPC config is in sync */
  4368. brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
  4369. return 0;
  4370. }
  4371. static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
  4372. {
  4373. uint callbacks = 0;
  4374. return callbacks;
  4375. }
  4376. static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
  4377. {
  4378. bool dev_gone;
  4379. uint callbacks = 0;
  4380. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4381. if (!wlc_hw->up)
  4382. return callbacks;
  4383. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4384. /* disable interrupts */
  4385. if (dev_gone)
  4386. wlc_hw->wlc->macintmask = 0;
  4387. else {
  4388. /* now disable interrupts */
  4389. brcms_intrsoff(wlc_hw->wlc->wl);
  4390. /* ensure we're running on the pll clock again */
  4391. brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
  4392. }
  4393. /* down phy at the last of this stage */
  4394. callbacks += wlc_phy_down(wlc_hw->band->pi);
  4395. return callbacks;
  4396. }
  4397. static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
  4398. {
  4399. uint callbacks = 0;
  4400. bool dev_gone;
  4401. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  4402. if (!wlc_hw->up)
  4403. return callbacks;
  4404. wlc_hw->up = false;
  4405. wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
  4406. dev_gone = brcms_deviceremoved(wlc_hw->wlc);
  4407. if (dev_gone) {
  4408. wlc_hw->sbclk = false;
  4409. wlc_hw->clk = false;
  4410. wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
  4411. /* reclaim any posted packets */
  4412. brcms_c_flushqueues(wlc_hw->wlc);
  4413. } else {
  4414. /* Reset and disable the core */
  4415. if (ai_iscoreup(wlc_hw->sih)) {
  4416. if (R_REG(&wlc_hw->regs->maccontrol) &
  4417. MCTL_EN_MAC)
  4418. brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
  4419. callbacks += brcms_reset(wlc_hw->wlc->wl);
  4420. brcms_c_coredisable(wlc_hw);
  4421. }
  4422. /* turn off primary xtal and pll */
  4423. if (!wlc_hw->noreset) {
  4424. ai_pci_down(wlc_hw->sih);
  4425. brcms_b_xtal(wlc_hw, OFF);
  4426. }
  4427. }
  4428. return callbacks;
  4429. }
  4430. /*
  4431. * Mark the interface nonoperational, stop the software mechanisms,
  4432. * disable the hardware, free any transient buffer state.
  4433. * Return a count of the number of driver callbacks still pending.
  4434. */
  4435. uint brcms_c_down(struct brcms_c_info *wlc)
  4436. {
  4437. uint callbacks = 0;
  4438. int i;
  4439. bool dev_gone = false;
  4440. struct brcms_txq_info *qi;
  4441. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  4442. /* check if we are already in the going down path */
  4443. if (wlc->going_down) {
  4444. wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
  4445. "\n", wlc->pub->unit, __func__);
  4446. return 0;
  4447. }
  4448. if (!wlc->pub->up)
  4449. return callbacks;
  4450. wlc->going_down = true;
  4451. callbacks += brcms_b_bmac_down_prep(wlc->hw);
  4452. dev_gone = brcms_deviceremoved(wlc);
  4453. /* Call any registered down handlers */
  4454. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4455. if (wlc->modulecb[i].down_fn)
  4456. callbacks +=
  4457. wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
  4458. }
  4459. /* cancel the watchdog timer */
  4460. if (wlc->WDarmed) {
  4461. if (!brcms_del_timer(wlc->wdtimer))
  4462. callbacks++;
  4463. wlc->WDarmed = false;
  4464. }
  4465. /* cancel all other timers */
  4466. callbacks += brcms_c_down_del_timer(wlc);
  4467. wlc->pub->up = false;
  4468. wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
  4469. /* clear txq flow control */
  4470. brcms_c_txflowcontrol_reset(wlc);
  4471. /* flush tx queues */
  4472. for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
  4473. brcmu_pktq_flush(&qi->q, true, NULL, NULL);
  4474. callbacks += brcms_b_down_finish(wlc->hw);
  4475. /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
  4476. wlc->clk = false;
  4477. wlc->going_down = false;
  4478. return callbacks;
  4479. }
  4480. /* Set the current gmode configuration */
  4481. int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
  4482. {
  4483. int ret = 0;
  4484. uint i;
  4485. struct brcms_c_rateset rs;
  4486. /* Default to 54g Auto */
  4487. /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
  4488. s8 shortslot = BRCMS_SHORTSLOT_AUTO;
  4489. bool shortslot_restrict = false; /* Restrict association to stations
  4490. * that support shortslot
  4491. */
  4492. bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
  4493. /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
  4494. int preamble = BRCMS_PLCP_LONG;
  4495. bool preamble_restrict = false; /* Restrict association to stations
  4496. * that support short preambles
  4497. */
  4498. struct brcms_band *band;
  4499. /* if N-support is enabled, allow Gmode set as long as requested
  4500. * Gmode is not GMODE_LEGACY_B
  4501. */
  4502. if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
  4503. return -ENOTSUPP;
  4504. /* verify that we are dealing with 2G band and grab the band pointer */
  4505. if (wlc->band->bandtype == BRCM_BAND_2G)
  4506. band = wlc->band;
  4507. else if ((wlc->pub->_nbands > 1) &&
  4508. (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
  4509. band = wlc->bandstate[OTHERBANDUNIT(wlc)];
  4510. else
  4511. return -EINVAL;
  4512. /* Legacy or bust when no OFDM is supported by regulatory */
  4513. if ((brcms_c_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
  4514. BRCMS_NO_OFDM) && (gmode != GMODE_LEGACY_B))
  4515. return -EINVAL;
  4516. /* update configuration value */
  4517. if (config == true)
  4518. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
  4519. /* Clear rateset override */
  4520. memset(&rs, 0, sizeof(struct brcms_c_rateset));
  4521. switch (gmode) {
  4522. case GMODE_LEGACY_B:
  4523. shortslot = BRCMS_SHORTSLOT_OFF;
  4524. brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
  4525. break;
  4526. case GMODE_LRS:
  4527. break;
  4528. case GMODE_AUTO:
  4529. /* Accept defaults */
  4530. break;
  4531. case GMODE_ONLY:
  4532. ofdm_basic = true;
  4533. preamble = BRCMS_PLCP_SHORT;
  4534. preamble_restrict = true;
  4535. break;
  4536. case GMODE_PERFORMANCE:
  4537. shortslot = BRCMS_SHORTSLOT_ON;
  4538. shortslot_restrict = true;
  4539. ofdm_basic = true;
  4540. preamble = BRCMS_PLCP_SHORT;
  4541. preamble_restrict = true;
  4542. break;
  4543. default:
  4544. /* Error */
  4545. wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
  4546. wlc->pub->unit, __func__, gmode);
  4547. return -ENOTSUPP;
  4548. }
  4549. band->gmode = gmode;
  4550. wlc->shortslot_override = shortslot;
  4551. /* Use the default 11g rateset */
  4552. if (!rs.count)
  4553. brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
  4554. if (ofdm_basic) {
  4555. for (i = 0; i < rs.count; i++) {
  4556. if (rs.rates[i] == BRCM_RATE_6M
  4557. || rs.rates[i] == BRCM_RATE_12M
  4558. || rs.rates[i] == BRCM_RATE_24M)
  4559. rs.rates[i] |= BRCMS_RATE_FLAG;
  4560. }
  4561. }
  4562. /* Set default bss rateset */
  4563. wlc->default_bss->rateset.count = rs.count;
  4564. memcpy(wlc->default_bss->rateset.rates, rs.rates,
  4565. sizeof(wlc->default_bss->rateset.rates));
  4566. return ret;
  4567. }
  4568. int brcms_c_set_nmode(struct brcms_c_info *wlc)
  4569. {
  4570. uint i;
  4571. s32 nmode = AUTO;
  4572. if (wlc->stf->txstreams == WL_11N_3x3)
  4573. nmode = WL_11N_3x3;
  4574. else
  4575. nmode = WL_11N_2x2;
  4576. /* force GMODE_AUTO if NMODE is ON */
  4577. brcms_c_set_gmode(wlc, GMODE_AUTO, true);
  4578. if (nmode == WL_11N_3x3)
  4579. wlc->pub->_n_enab = SUPPORT_HT;
  4580. else
  4581. wlc->pub->_n_enab = SUPPORT_11N;
  4582. wlc->default_bss->flags |= BRCMS_BSS_HT;
  4583. /* add the mcs rates to the default and hw ratesets */
  4584. brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
  4585. wlc->stf->txstreams);
  4586. for (i = 0; i < wlc->pub->_nbands; i++)
  4587. memcpy(wlc->bandstate[i]->hw_rateset.mcs,
  4588. wlc->default_bss->rateset.mcs, MCSSET_LEN);
  4589. return 0;
  4590. }
  4591. static int
  4592. brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
  4593. struct brcms_c_rateset *rs_arg)
  4594. {
  4595. struct brcms_c_rateset rs, new;
  4596. uint bandunit;
  4597. memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
  4598. /* check for bad count value */
  4599. if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
  4600. return -EINVAL;
  4601. /* try the current band */
  4602. bandunit = wlc->band->bandunit;
  4603. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4604. if (brcms_c_rate_hwrs_filter_sort_validate
  4605. (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
  4606. wlc->stf->txstreams))
  4607. goto good;
  4608. /* try the other band */
  4609. if (brcms_is_mband_unlocked(wlc)) {
  4610. bandunit = OTHERBANDUNIT(wlc);
  4611. memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
  4612. if (brcms_c_rate_hwrs_filter_sort_validate(&new,
  4613. &wlc->
  4614. bandstate[bandunit]->
  4615. hw_rateset, true,
  4616. wlc->stf->txstreams))
  4617. goto good;
  4618. }
  4619. return -EBADE;
  4620. good:
  4621. /* apply new rateset */
  4622. memcpy(&wlc->default_bss->rateset, &new,
  4623. sizeof(struct brcms_c_rateset));
  4624. memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
  4625. sizeof(struct brcms_c_rateset));
  4626. return 0;
  4627. }
  4628. static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
  4629. {
  4630. u8 r;
  4631. bool war = false;
  4632. if (wlc->bsscfg->associated)
  4633. r = wlc->bsscfg->current_bss->rateset.rates[0];
  4634. else
  4635. r = wlc->default_bss->rateset.rates[0];
  4636. wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
  4637. }
  4638. int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
  4639. {
  4640. u16 chspec = ch20mhz_chspec(channel);
  4641. if (channel < 0 || channel > MAXCHANNEL)
  4642. return -EINVAL;
  4643. if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
  4644. return -EINVAL;
  4645. if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
  4646. if (wlc->band->bandunit != chspec_bandunit(chspec))
  4647. wlc->bandinit_pending = true;
  4648. else
  4649. wlc->bandinit_pending = false;
  4650. }
  4651. wlc->default_bss->chanspec = chspec;
  4652. /* brcms_c_BSSinit() will sanitize the rateset before
  4653. * using it.. */
  4654. if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
  4655. brcms_c_set_home_chanspec(wlc, chspec);
  4656. brcms_c_suspend_mac_and_wait(wlc);
  4657. brcms_c_set_chanspec(wlc, chspec);
  4658. brcms_c_enable_mac(wlc);
  4659. }
  4660. return 0;
  4661. }
  4662. int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
  4663. {
  4664. int ac;
  4665. if (srl < 1 || srl > RETRY_SHORT_MAX ||
  4666. lrl < 1 || lrl > RETRY_SHORT_MAX)
  4667. return -EINVAL;
  4668. wlc->SRL = srl;
  4669. wlc->LRL = lrl;
  4670. brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
  4671. for (ac = 0; ac < AC_COUNT; ac++) {
  4672. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4673. EDCF_SHORT, wlc->SRL);
  4674. wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
  4675. EDCF_LONG, wlc->LRL);
  4676. }
  4677. brcms_c_wme_retries_write(wlc);
  4678. return 0;
  4679. }
  4680. void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
  4681. struct brcm_rateset *currs)
  4682. {
  4683. struct brcms_c_rateset *rs;
  4684. if (wlc->pub->associated)
  4685. rs = &wlc->bsscfg->current_bss->rateset;
  4686. else
  4687. rs = &wlc->default_bss->rateset;
  4688. /* Copy only legacy rateset section */
  4689. currs->count = rs->count;
  4690. memcpy(&currs->rates, &rs->rates, rs->count);
  4691. }
  4692. int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
  4693. {
  4694. struct brcms_c_rateset internal_rs;
  4695. int bcmerror;
  4696. if (rs->count > BRCMS_NUMRATES)
  4697. return -ENOBUFS;
  4698. memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
  4699. /* Copy only legacy rateset section */
  4700. internal_rs.count = rs->count;
  4701. memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
  4702. /* merge rateset coming in with the current mcsset */
  4703. if (wlc->pub->_n_enab & SUPPORT_11N) {
  4704. struct brcms_bss_info *mcsset_bss;
  4705. if (wlc->bsscfg->associated)
  4706. mcsset_bss = wlc->bsscfg->current_bss;
  4707. else
  4708. mcsset_bss = wlc->default_bss;
  4709. memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
  4710. MCSSET_LEN);
  4711. }
  4712. bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
  4713. if (!bcmerror)
  4714. brcms_c_ofdm_rateset_war(wlc);
  4715. return bcmerror;
  4716. }
  4717. int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
  4718. {
  4719. if (period < DOT11_MIN_BEACON_PERIOD ||
  4720. period > DOT11_MAX_BEACON_PERIOD)
  4721. return -EINVAL;
  4722. wlc->default_bss->beacon_period = period;
  4723. return 0;
  4724. }
  4725. u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
  4726. {
  4727. return wlc->band->phytype;
  4728. }
  4729. void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
  4730. {
  4731. wlc->shortslot_override = sslot_override;
  4732. /*
  4733. * shortslot is an 11g feature, so no more work if we are
  4734. * currently on the 5G band
  4735. */
  4736. if (wlc->band->bandtype == BRCM_BAND_5G)
  4737. return;
  4738. if (wlc->pub->up && wlc->pub->associated) {
  4739. /* let watchdog or beacon processing update shortslot */
  4740. } else if (wlc->pub->up) {
  4741. /* unassociated shortslot is off */
  4742. brcms_c_switch_shortslot(wlc, false);
  4743. } else {
  4744. /* driver is down, so just update the brcms_c_info
  4745. * value */
  4746. if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
  4747. wlc->shortslot = false;
  4748. else
  4749. wlc->shortslot =
  4750. (wlc->shortslot_override ==
  4751. BRCMS_SHORTSLOT_ON);
  4752. }
  4753. }
  4754. /*
  4755. * register watchdog and down handlers.
  4756. */
  4757. int brcms_c_module_register(struct brcms_pub *pub,
  4758. const char *name, struct brcms_info *hdl,
  4759. int (*d_fn)(void *handle))
  4760. {
  4761. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4762. int i;
  4763. /* find an empty entry and just add, no duplication check! */
  4764. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4765. if (wlc->modulecb[i].name[0] == '\0') {
  4766. strncpy(wlc->modulecb[i].name, name,
  4767. sizeof(wlc->modulecb[i].name) - 1);
  4768. wlc->modulecb[i].hdl = hdl;
  4769. wlc->modulecb[i].down_fn = d_fn;
  4770. return 0;
  4771. }
  4772. }
  4773. return -ENOSR;
  4774. }
  4775. /* unregister module callbacks */
  4776. int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
  4777. struct brcms_info *hdl)
  4778. {
  4779. struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
  4780. int i;
  4781. if (wlc == NULL)
  4782. return -ENODATA;
  4783. for (i = 0; i < BRCMS_MAXMODULES; i++) {
  4784. if (!strcmp(wlc->modulecb[i].name, name) &&
  4785. (wlc->modulecb[i].hdl == hdl)) {
  4786. memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
  4787. return 0;
  4788. }
  4789. }
  4790. /* table not found! */
  4791. return -ENODATA;
  4792. }
  4793. #ifdef BCMDBG
  4794. static const char * const supr_reason[] = {
  4795. "None", "PMQ Entry", "Flush request",
  4796. "Previous frag failure", "Channel mismatch",
  4797. "Lifetime Expiry", "Underflow"
  4798. };
  4799. static void brcms_c_print_txs_status(u16 s)
  4800. {
  4801. printk(KERN_DEBUG "[15:12] %d frame attempts\n",
  4802. (s & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT);
  4803. printk(KERN_DEBUG " [11:8] %d rts attempts\n",
  4804. (s & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT);
  4805. printk(KERN_DEBUG " [7] %d PM mode indicated\n",
  4806. ((s & TX_STATUS_PMINDCTD) ? 1 : 0));
  4807. printk(KERN_DEBUG " [6] %d intermediate status\n",
  4808. ((s & TX_STATUS_INTERMEDIATE) ? 1 : 0));
  4809. printk(KERN_DEBUG " [5] %d AMPDU\n",
  4810. (s & TX_STATUS_AMPDU) ? 1 : 0);
  4811. printk(KERN_DEBUG " [4:2] %d Frame Suppressed Reason (%s)\n",
  4812. ((s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT),
  4813. supr_reason[(s & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT]);
  4814. printk(KERN_DEBUG " [1] %d acked\n",
  4815. ((s & TX_STATUS_ACK_RCV) ? 1 : 0));
  4816. }
  4817. #endif /* BCMDBG */
  4818. void brcms_c_print_txstatus(struct tx_status *txs)
  4819. {
  4820. #if defined(BCMDBG)
  4821. u16 s = txs->status;
  4822. u16 ackphyrxsh = txs->ackphyrxsh;
  4823. printk(KERN_DEBUG "\ntxpkt (MPDU) Complete\n");
  4824. printk(KERN_DEBUG "FrameID: %04x ", txs->frameid);
  4825. printk(KERN_DEBUG "TxStatus: %04x", s);
  4826. printk(KERN_DEBUG "\n");
  4827. brcms_c_print_txs_status(s);
  4828. printk(KERN_DEBUG "LastTxTime: %04x ", txs->lasttxtime);
  4829. printk(KERN_DEBUG "Seq: %04x ", txs->sequence);
  4830. printk(KERN_DEBUG "PHYTxStatus: %04x ", txs->phyerr);
  4831. printk(KERN_DEBUG "RxAckRSSI: %04x ",
  4832. (ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT);
  4833. printk(KERN_DEBUG "RxAckSQ: %04x",
  4834. (ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
  4835. printk(KERN_DEBUG "\n");
  4836. #endif /* defined(BCMDBG) */
  4837. }
  4838. bool brcms_c_chipmatch(u16 vendor, u16 device)
  4839. {
  4840. if (vendor != PCI_VENDOR_ID_BROADCOM) {
  4841. pr_err("chipmatch: unknown vendor id %04x\n", vendor);
  4842. return false;
  4843. }
  4844. if (device == BCM43224_D11N_ID_VEN1)
  4845. return true;
  4846. if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
  4847. return true;
  4848. if (device == BCM4313_D11N2G_ID)
  4849. return true;
  4850. if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
  4851. return true;
  4852. pr_err("chipmatch: unknown device id %04x\n", device);
  4853. return false;
  4854. }
  4855. #if defined(BCMDBG)
  4856. void brcms_c_print_txdesc(struct d11txh *txh)
  4857. {
  4858. u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
  4859. u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
  4860. u16 mfc = le16_to_cpu(txh->MacFrameControl);
  4861. u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
  4862. u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
  4863. u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
  4864. u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
  4865. u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
  4866. u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
  4867. u16 mainrates = le16_to_cpu(txh->MainRates);
  4868. u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
  4869. u8 *iv = txh->IV;
  4870. u8 *ra = txh->TxFrameRA;
  4871. u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
  4872. u8 *rtspfb = txh->RTSPLCPFallback;
  4873. u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
  4874. u8 *fragpfb = txh->FragPLCPFallback;
  4875. u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
  4876. u16 mmodelen = le16_to_cpu(txh->MModeLen);
  4877. u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
  4878. u16 tfid = le16_to_cpu(txh->TxFrameID);
  4879. u16 txs = le16_to_cpu(txh->TxStatus);
  4880. u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
  4881. u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
  4882. u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
  4883. u16 mmbyte = le16_to_cpu(txh->MinMBytes);
  4884. u8 *rtsph = txh->RTSPhyHeader;
  4885. struct ieee80211_rts rts = txh->rts_frame;
  4886. /* add plcp header along with txh descriptor */
  4887. printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
  4888. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  4889. txh, sizeof(struct d11txh) + 48);
  4890. printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
  4891. printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
  4892. printk(KERN_DEBUG "FC: %04x ", mfc);
  4893. printk(KERN_DEBUG "FES Time: %04x\n", tfest);
  4894. printk(KERN_DEBUG "PhyCtl: %04x%s ", ptcw,
  4895. (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
  4896. printk(KERN_DEBUG "PhyCtl_1: %04x ", ptcw_1);
  4897. printk(KERN_DEBUG "PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
  4898. printk(KERN_DEBUG "PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
  4899. printk(KERN_DEBUG "PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
  4900. printk(KERN_DEBUG "MainRates: %04x ", mainrates);
  4901. printk(KERN_DEBUG "XtraFrameTypes: %04x ", xtraft);
  4902. printk(KERN_DEBUG "\n");
  4903. print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
  4904. print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
  4905. ra, sizeof(txh->TxFrameRA));
  4906. printk(KERN_DEBUG "Fb FES Time: %04x ", tfestfb);
  4907. print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
  4908. rtspfb, sizeof(txh->RTSPLCPFallback));
  4909. printk(KERN_DEBUG "RTS DUR: %04x ", rtsdfb);
  4910. print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
  4911. fragpfb, sizeof(txh->FragPLCPFallback));
  4912. printk(KERN_DEBUG "DUR: %04x", fragdfb);
  4913. printk(KERN_DEBUG "\n");
  4914. printk(KERN_DEBUG "MModeLen: %04x ", mmodelen);
  4915. printk(KERN_DEBUG "MModeFbrLen: %04x\n", mmodefbrlen);
  4916. printk(KERN_DEBUG "FrameID: %04x\n", tfid);
  4917. printk(KERN_DEBUG "TxStatus: %04x\n", txs);
  4918. printk(KERN_DEBUG "MaxNumMpdu: %04x\n", mnmpdu);
  4919. printk(KERN_DEBUG "MaxAggbyte: %04x\n", mabyte);
  4920. printk(KERN_DEBUG "MaxAggbyte_fb: %04x\n", mabyte_f);
  4921. printk(KERN_DEBUG "MinByte: %04x\n", mmbyte);
  4922. print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
  4923. rtsph, sizeof(txh->RTSPhyHeader));
  4924. print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
  4925. (u8 *)&rts, sizeof(txh->rts_frame));
  4926. printk(KERN_DEBUG "\n");
  4927. }
  4928. #endif /* defined(BCMDBG) */
  4929. #if defined(BCMDBG)
  4930. static int
  4931. brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
  4932. int len)
  4933. {
  4934. int i;
  4935. char *p = buf;
  4936. char hexstr[16];
  4937. int slen = 0, nlen = 0;
  4938. u32 bit;
  4939. const char *name;
  4940. if (len < 2 || !buf)
  4941. return 0;
  4942. buf[0] = '\0';
  4943. for (i = 0; flags != 0; i++) {
  4944. bit = bd[i].bit;
  4945. name = bd[i].name;
  4946. if (bit == 0 && flags != 0) {
  4947. /* print any unnamed bits */
  4948. snprintf(hexstr, 16, "0x%X", flags);
  4949. name = hexstr;
  4950. flags = 0; /* exit loop */
  4951. } else if ((flags & bit) == 0)
  4952. continue;
  4953. flags &= ~bit;
  4954. nlen = strlen(name);
  4955. slen += nlen;
  4956. /* count btwn flag space */
  4957. if (flags != 0)
  4958. slen += 1;
  4959. /* need NULL char as well */
  4960. if (len <= slen)
  4961. break;
  4962. /* copy NULL char but don't count it */
  4963. strncpy(p, name, nlen + 1);
  4964. p += nlen;
  4965. /* copy btwn flag space and NULL char */
  4966. if (flags != 0)
  4967. p += snprintf(p, 2, " ");
  4968. len -= slen;
  4969. }
  4970. /* indicate the str was too short */
  4971. if (flags != 0) {
  4972. if (len < 2)
  4973. p -= 2 - len; /* overwrite last char */
  4974. p += snprintf(p, 2, ">");
  4975. }
  4976. return (int)(p - buf);
  4977. }
  4978. #endif /* defined(BCMDBG) */
  4979. #if defined(BCMDBG)
  4980. void brcms_c_print_rxh(struct d11rxhdr *rxh)
  4981. {
  4982. u16 len = rxh->RxFrameSize;
  4983. u16 phystatus_0 = rxh->PhyRxStatus_0;
  4984. u16 phystatus_1 = rxh->PhyRxStatus_1;
  4985. u16 phystatus_2 = rxh->PhyRxStatus_2;
  4986. u16 phystatus_3 = rxh->PhyRxStatus_3;
  4987. u16 macstatus1 = rxh->RxStatus1;
  4988. u16 macstatus2 = rxh->RxStatus2;
  4989. char flagstr[64];
  4990. char lenbuf[20];
  4991. static const struct brcms_c_bit_desc macstat_flags[] = {
  4992. {RXS_FCSERR, "FCSErr"},
  4993. {RXS_RESPFRAMETX, "Reply"},
  4994. {RXS_PBPRES, "PADDING"},
  4995. {RXS_DECATMPT, "DeCr"},
  4996. {RXS_DECERR, "DeCrErr"},
  4997. {RXS_BCNSENT, "Bcn"},
  4998. {0, NULL}
  4999. };
  5000. printk(KERN_DEBUG "Raw RxDesc:\n");
  5001. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh,
  5002. sizeof(struct d11rxhdr));
  5003. brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
  5004. snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
  5005. printk(KERN_DEBUG "RxFrameSize: %6s (%d)%s\n", lenbuf, len,
  5006. (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
  5007. printk(KERN_DEBUG "RxPHYStatus: %04x %04x %04x %04x\n",
  5008. phystatus_0, phystatus_1, phystatus_2, phystatus_3);
  5009. printk(KERN_DEBUG "RxMACStatus: %x %s\n", macstatus1, flagstr);
  5010. printk(KERN_DEBUG "RXMACaggtype: %x\n",
  5011. (macstatus2 & RXS_AGGTYPE_MASK));
  5012. printk(KERN_DEBUG "RxTSFTime: %04x\n", rxh->RxTSFTime);
  5013. }
  5014. #endif /* defined(BCMDBG) */
  5015. u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
  5016. {
  5017. u16 table_ptr;
  5018. u8 phy_rate, index;
  5019. /* get the phy specific rate encoding for the PLCP SIGNAL field */
  5020. if (is_ofdm_rate(rate))
  5021. table_ptr = M_RT_DIRMAP_A;
  5022. else
  5023. table_ptr = M_RT_DIRMAP_B;
  5024. /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
  5025. * the index into the rate table.
  5026. */
  5027. phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
  5028. index = phy_rate & 0xf;
  5029. /* Find the SHM pointer to the rate table entry by looking in the
  5030. * Direct-map Table
  5031. */
  5032. return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
  5033. }
  5034. static bool
  5035. brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
  5036. struct sk_buff *pkt, int prec, bool head)
  5037. {
  5038. struct sk_buff *p;
  5039. int eprec = -1; /* precedence to evict from */
  5040. /* Determine precedence from which to evict packet, if any */
  5041. if (pktq_pfull(q, prec))
  5042. eprec = prec;
  5043. else if (pktq_full(q)) {
  5044. p = brcmu_pktq_peek_tail(q, &eprec);
  5045. if (eprec > prec) {
  5046. wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
  5047. "\n", __func__, eprec, prec);
  5048. return false;
  5049. }
  5050. }
  5051. /* Evict if needed */
  5052. if (eprec >= 0) {
  5053. bool discard_oldest;
  5054. discard_oldest = ac_bitmap_tst(0, eprec);
  5055. /* Refuse newer packet unless configured to discard oldest */
  5056. if (eprec == prec && !discard_oldest) {
  5057. wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
  5058. "\n", __func__, prec);
  5059. return false;
  5060. }
  5061. /* Evict packet according to discard policy */
  5062. p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
  5063. brcmu_pktq_pdeq_tail(q, eprec);
  5064. brcmu_pkt_buf_free_skb(p);
  5065. }
  5066. /* Enqueue */
  5067. if (head)
  5068. p = brcmu_pktq_penq_head(q, prec, pkt);
  5069. else
  5070. p = brcmu_pktq_penq(q, prec, pkt);
  5071. return true;
  5072. }
  5073. /*
  5074. * Attempts to queue a packet onto a multiple-precedence queue,
  5075. * if necessary evicting a lower precedence packet from the queue.
  5076. *
  5077. * 'prec' is the precedence number that has already been mapped
  5078. * from the packet priority.
  5079. *
  5080. * Returns true if packet consumed (queued), false if not.
  5081. */
  5082. static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
  5083. struct sk_buff *pkt, int prec)
  5084. {
  5085. return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
  5086. }
  5087. void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
  5088. struct sk_buff *sdu, uint prec)
  5089. {
  5090. struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */
  5091. struct pktq *q = &qi->q;
  5092. int prio;
  5093. prio = sdu->priority;
  5094. if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
  5095. /*
  5096. * we might hit this condtion in case
  5097. * packet flooding from mac80211 stack
  5098. */
  5099. brcmu_pkt_buf_free_skb(sdu);
  5100. }
  5101. }
  5102. /*
  5103. * bcmc_fid_generate:
  5104. * Generate frame ID for a BCMC packet. The frag field is not used
  5105. * for MC frames so is used as part of the sequence number.
  5106. */
  5107. static inline u16
  5108. bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
  5109. struct d11txh *txh)
  5110. {
  5111. u16 frameid;
  5112. frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
  5113. TXFID_QUEUE_MASK);
  5114. frameid |=
  5115. (((wlc->
  5116. mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  5117. TX_BCMC_FIFO;
  5118. return frameid;
  5119. }
  5120. static uint
  5121. brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
  5122. u8 preamble_type)
  5123. {
  5124. uint dur = 0;
  5125. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
  5126. wlc->pub->unit, rspec, preamble_type);
  5127. /*
  5128. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  5129. * is less than or equal to the rate of the immediately previous
  5130. * frame in the FES
  5131. */
  5132. rspec = brcms_basic_rate(wlc, rspec);
  5133. /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
  5134. dur =
  5135. brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  5136. (DOT11_ACK_LEN + FCS_LEN));
  5137. return dur;
  5138. }
  5139. static uint
  5140. brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
  5141. u8 preamble_type)
  5142. {
  5143. BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
  5144. wlc->pub->unit, rspec, preamble_type);
  5145. return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
  5146. }
  5147. static uint
  5148. brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
  5149. u8 preamble_type)
  5150. {
  5151. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
  5152. "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
  5153. /*
  5154. * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
  5155. * is less than or equal to the rate of the immediately previous
  5156. * frame in the FES
  5157. */
  5158. rspec = brcms_basic_rate(wlc, rspec);
  5159. /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
  5160. return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
  5161. (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
  5162. FCS_LEN));
  5163. }
  5164. /* brcms_c_compute_frame_dur()
  5165. *
  5166. * Calculate the 802.11 MAC header DUR field for MPDU
  5167. * DUR for a single frame = 1 SIFS + 1 ACK
  5168. * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
  5169. *
  5170. * rate MPDU rate in unit of 500kbps
  5171. * next_frag_len next MPDU length in bytes
  5172. * preamble_type use short/GF or long/MM PLCP header
  5173. */
  5174. static u16
  5175. brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
  5176. u8 preamble_type, uint next_frag_len)
  5177. {
  5178. u16 dur, sifs;
  5179. sifs = get_sifs(wlc->band);
  5180. dur = sifs;
  5181. dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
  5182. if (next_frag_len) {
  5183. /* Double the current DUR to get 2 SIFS + 2 ACKs */
  5184. dur *= 2;
  5185. /* add another SIFS and the frag time */
  5186. dur += sifs;
  5187. dur +=
  5188. (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
  5189. next_frag_len);
  5190. }
  5191. return dur;
  5192. }
  5193. /* The opposite of brcms_c_calc_frame_time */
  5194. static uint
  5195. brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
  5196. u8 preamble_type, uint dur)
  5197. {
  5198. uint nsyms, mac_len, Ndps, kNdps;
  5199. uint rate = rspec2rate(ratespec);
  5200. BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
  5201. wlc->pub->unit, ratespec, preamble_type, dur);
  5202. if (is_mcs_rate(ratespec)) {
  5203. uint mcs = ratespec & RSPEC_RATE_MASK;
  5204. int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
  5205. dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
  5206. /* payload calculation matches that of regular ofdm */
  5207. if (wlc->band->bandtype == BRCM_BAND_2G)
  5208. dur -= DOT11_OFDM_SIGNAL_EXTENSION;
  5209. /* kNdbps = kbps * 4 */
  5210. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  5211. rspec_issgi(ratespec)) * 4;
  5212. nsyms = dur / APHY_SYMBOL_TIME;
  5213. mac_len =
  5214. ((nsyms * kNdps) -
  5215. ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
  5216. } else if (is_ofdm_rate(ratespec)) {
  5217. dur -= APHY_PREAMBLE_TIME;
  5218. dur -= APHY_SIGNAL_TIME;
  5219. /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
  5220. Ndps = rate * 2;
  5221. nsyms = dur / APHY_SYMBOL_TIME;
  5222. mac_len =
  5223. ((nsyms * Ndps) -
  5224. (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
  5225. } else {
  5226. if (preamble_type & BRCMS_SHORT_PREAMBLE)
  5227. dur -= BPHY_PLCP_SHORT_TIME;
  5228. else
  5229. dur -= BPHY_PLCP_TIME;
  5230. mac_len = dur * rate;
  5231. /* divide out factor of 2 in rate (1/2 mbps) */
  5232. mac_len = mac_len / 8 / 2;
  5233. }
  5234. return mac_len;
  5235. }
  5236. /*
  5237. * Return true if the specified rate is supported by the specified band.
  5238. * BRCM_BAND_AUTO indicates the current band.
  5239. */
  5240. static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
  5241. bool verbose)
  5242. {
  5243. struct brcms_c_rateset *hw_rateset;
  5244. uint i;
  5245. if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
  5246. hw_rateset = &wlc->band->hw_rateset;
  5247. else if (wlc->pub->_nbands > 1)
  5248. hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
  5249. else
  5250. /* other band specified and we are a single band device */
  5251. return false;
  5252. /* check if this is a mimo rate */
  5253. if (is_mcs_rate(rspec)) {
  5254. if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
  5255. goto error;
  5256. return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
  5257. }
  5258. for (i = 0; i < hw_rateset->count; i++)
  5259. if (hw_rateset->rates[i] == rspec2rate(rspec))
  5260. return true;
  5261. error:
  5262. if (verbose)
  5263. wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
  5264. "not in hw_rateset\n", wlc->pub->unit, rspec);
  5265. return false;
  5266. }
  5267. static u32
  5268. mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
  5269. u32 int_val)
  5270. {
  5271. u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
  5272. u8 rate = int_val & NRATE_RATE_MASK;
  5273. u32 rspec;
  5274. bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
  5275. bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
  5276. bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
  5277. == NRATE_OVERRIDE_MCS_ONLY);
  5278. int bcmerror = 0;
  5279. if (!ismcs)
  5280. return (u32) rate;
  5281. /* validate the combination of rate/mcs/stf is allowed */
  5282. if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
  5283. /* mcs only allowed when nmode */
  5284. if (stf > PHY_TXC1_MODE_SDM) {
  5285. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
  5286. wlc->pub->unit, __func__);
  5287. bcmerror = -EINVAL;
  5288. goto done;
  5289. }
  5290. /* mcs 32 is a special case, DUP mode 40 only */
  5291. if (rate == 32) {
  5292. if (!CHSPEC_IS40(wlc->home_chanspec) ||
  5293. ((stf != PHY_TXC1_MODE_SISO)
  5294. && (stf != PHY_TXC1_MODE_CDD))) {
  5295. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
  5296. "32\n", wlc->pub->unit, __func__);
  5297. bcmerror = -EINVAL;
  5298. goto done;
  5299. }
  5300. /* mcs > 7 must use stf SDM */
  5301. } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
  5302. /* mcs > 7 must use stf SDM */
  5303. if (stf != PHY_TXC1_MODE_SDM) {
  5304. BCMMSG(wlc->wiphy, "wl%d: enabling "
  5305. "SDM mode for mcs %d\n",
  5306. wlc->pub->unit, rate);
  5307. stf = PHY_TXC1_MODE_SDM;
  5308. }
  5309. } else {
  5310. /*
  5311. * MCS 0-7 may use SISO, CDD, and for
  5312. * phy_rev >= 3 STBC
  5313. */
  5314. if ((stf > PHY_TXC1_MODE_STBC) ||
  5315. (!BRCMS_STBC_CAP_PHY(wlc)
  5316. && (stf == PHY_TXC1_MODE_STBC))) {
  5317. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
  5318. "\n", wlc->pub->unit, __func__);
  5319. bcmerror = -EINVAL;
  5320. goto done;
  5321. }
  5322. }
  5323. } else if (is_ofdm_rate(rate)) {
  5324. if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
  5325. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
  5326. wlc->pub->unit, __func__);
  5327. bcmerror = -EINVAL;
  5328. goto done;
  5329. }
  5330. } else if (is_cck_rate(rate)) {
  5331. if ((cur_band->bandtype != BRCM_BAND_2G)
  5332. || (stf != PHY_TXC1_MODE_SISO)) {
  5333. wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
  5334. wlc->pub->unit, __func__);
  5335. bcmerror = -EINVAL;
  5336. goto done;
  5337. }
  5338. } else {
  5339. wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
  5340. wlc->pub->unit, __func__);
  5341. bcmerror = -EINVAL;
  5342. goto done;
  5343. }
  5344. /* make sure multiple antennae are available for non-siso rates */
  5345. if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
  5346. wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
  5347. "request\n", wlc->pub->unit, __func__);
  5348. bcmerror = -EINVAL;
  5349. goto done;
  5350. }
  5351. rspec = rate;
  5352. if (ismcs) {
  5353. rspec |= RSPEC_MIMORATE;
  5354. /* For STBC populate the STC field of the ratespec */
  5355. if (stf == PHY_TXC1_MODE_STBC) {
  5356. u8 stc;
  5357. stc = 1; /* Nss for single stream is always 1 */
  5358. rspec |= (stc << RSPEC_STC_SHIFT);
  5359. }
  5360. }
  5361. rspec |= (stf << RSPEC_STF_SHIFT);
  5362. if (override_mcs_only)
  5363. rspec |= RSPEC_OVERRIDE_MCS_ONLY;
  5364. if (issgi)
  5365. rspec |= RSPEC_SHORT_GI;
  5366. if ((rate != 0)
  5367. && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
  5368. return rate;
  5369. return rspec;
  5370. done:
  5371. return rate;
  5372. }
  5373. /*
  5374. * Compute PLCP, but only requires actual rate and length of pkt.
  5375. * Rate is given in the driver standard multiple of 500 kbps.
  5376. * le is set for 11 Mbps rate if necessary.
  5377. * Broken out for PRQ.
  5378. */
  5379. static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
  5380. uint length, u8 *plcp)
  5381. {
  5382. u16 usec = 0;
  5383. u8 le = 0;
  5384. switch (rate_500) {
  5385. case BRCM_RATE_1M:
  5386. usec = length << 3;
  5387. break;
  5388. case BRCM_RATE_2M:
  5389. usec = length << 2;
  5390. break;
  5391. case BRCM_RATE_5M5:
  5392. usec = (length << 4) / 11;
  5393. if ((length << 4) - (usec * 11) > 0)
  5394. usec++;
  5395. break;
  5396. case BRCM_RATE_11M:
  5397. usec = (length << 3) / 11;
  5398. if ((length << 3) - (usec * 11) > 0) {
  5399. usec++;
  5400. if ((usec * 11) - (length << 3) >= 8)
  5401. le = D11B_PLCP_SIGNAL_LE;
  5402. }
  5403. break;
  5404. default:
  5405. wiphy_err(wlc->wiphy,
  5406. "brcms_c_cck_plcp_set: unsupported rate %d\n",
  5407. rate_500);
  5408. rate_500 = BRCM_RATE_1M;
  5409. usec = length << 3;
  5410. break;
  5411. }
  5412. /* PLCP signal byte */
  5413. plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
  5414. /* PLCP service byte */
  5415. plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
  5416. /* PLCP length u16, little endian */
  5417. plcp[2] = usec & 0xff;
  5418. plcp[3] = (usec >> 8) & 0xff;
  5419. /* PLCP CRC16 */
  5420. plcp[4] = 0;
  5421. plcp[5] = 0;
  5422. }
  5423. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5424. static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
  5425. {
  5426. u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
  5427. plcp[0] = mcs;
  5428. if (rspec_is40mhz(rspec) || (mcs == 32))
  5429. plcp[0] |= MIMO_PLCP_40MHZ;
  5430. BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
  5431. plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
  5432. plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
  5433. plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
  5434. plcp[5] = 0;
  5435. }
  5436. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5437. static void
  5438. brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
  5439. {
  5440. u8 rate_signal;
  5441. u32 tmp = 0;
  5442. int rate = rspec2rate(rspec);
  5443. /*
  5444. * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
  5445. * transmitted first
  5446. */
  5447. rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
  5448. memset(plcp, 0, D11_PHY_HDR_LEN);
  5449. D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
  5450. tmp = (length & 0xfff) << 5;
  5451. plcp[2] |= (tmp >> 16) & 0xff;
  5452. plcp[1] |= (tmp >> 8) & 0xff;
  5453. plcp[0] |= tmp & 0xff;
  5454. }
  5455. /* Rate: 802.11 rate code, length: PSDU length in octets */
  5456. static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
  5457. uint length, u8 *plcp)
  5458. {
  5459. int rate = rspec2rate(rspec);
  5460. brcms_c_cck_plcp_set(wlc, rate, length, plcp);
  5461. }
  5462. static void
  5463. brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
  5464. uint length, u8 *plcp)
  5465. {
  5466. if (is_mcs_rate(rspec))
  5467. brcms_c_compute_mimo_plcp(rspec, length, plcp);
  5468. else if (is_ofdm_rate(rspec))
  5469. brcms_c_compute_ofdm_plcp(rspec, length, plcp);
  5470. else
  5471. brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
  5472. }
  5473. /* brcms_c_compute_rtscts_dur()
  5474. *
  5475. * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
  5476. * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
  5477. * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
  5478. *
  5479. * cts cts-to-self or rts/cts
  5480. * rts_rate rts or cts rate in unit of 500kbps
  5481. * rate next MPDU rate in unit of 500kbps
  5482. * frame_len next MPDU frame length in bytes
  5483. */
  5484. u16
  5485. brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
  5486. u32 rts_rate,
  5487. u32 frame_rate, u8 rts_preamble_type,
  5488. u8 frame_preamble_type, uint frame_len, bool ba)
  5489. {
  5490. u16 dur, sifs;
  5491. sifs = get_sifs(wlc->band);
  5492. if (!cts_only) {
  5493. /* RTS/CTS */
  5494. dur = 3 * sifs;
  5495. dur +=
  5496. (u16) brcms_c_calc_cts_time(wlc, rts_rate,
  5497. rts_preamble_type);
  5498. } else {
  5499. /* CTS-TO-SELF */
  5500. dur = 2 * sifs;
  5501. }
  5502. dur +=
  5503. (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
  5504. frame_len);
  5505. if (ba)
  5506. dur +=
  5507. (u16) brcms_c_calc_ba_time(wlc, frame_rate,
  5508. BRCMS_SHORT_PREAMBLE);
  5509. else
  5510. dur +=
  5511. (u16) brcms_c_calc_ack_time(wlc, frame_rate,
  5512. frame_preamble_type);
  5513. return dur;
  5514. }
  5515. static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
  5516. {
  5517. u16 phyctl1 = 0;
  5518. u16 bw;
  5519. if (BRCMS_ISLCNPHY(wlc->band)) {
  5520. bw = PHY_TXC1_BW_20MHZ;
  5521. } else {
  5522. bw = rspec_get_bw(rspec);
  5523. /* 10Mhz is not supported yet */
  5524. if (bw < PHY_TXC1_BW_20MHZ) {
  5525. wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
  5526. "not supported yet, set to 20L\n", bw);
  5527. bw = PHY_TXC1_BW_20MHZ;
  5528. }
  5529. }
  5530. if (is_mcs_rate(rspec)) {
  5531. uint mcs = rspec & RSPEC_RATE_MASK;
  5532. /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
  5533. phyctl1 = rspec_phytxbyte2(rspec);
  5534. /* set the upper byte of phyctl1 */
  5535. phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
  5536. } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
  5537. && !BRCMS_ISSSLPNPHY(wlc->band)) {
  5538. /*
  5539. * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
  5540. * Data Rate. Eventually MIMOPHY would also be converted to
  5541. * this format
  5542. */
  5543. /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
  5544. phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5545. } else { /* legacy OFDM/CCK */
  5546. s16 phycfg;
  5547. /* get the phyctl byte from rate phycfg table */
  5548. phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
  5549. if (phycfg == -1) {
  5550. wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
  5551. "legacy OFDM/CCK rate\n");
  5552. phycfg = 0;
  5553. }
  5554. /* set the upper byte of phyctl1 */
  5555. phyctl1 =
  5556. (bw | (phycfg << 8) |
  5557. (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
  5558. }
  5559. return phyctl1;
  5560. }
  5561. /*
  5562. * Add struct d11txh, struct cck_phy_hdr.
  5563. *
  5564. * 'p' data must start with 802.11 MAC header
  5565. * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
  5566. *
  5567. * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
  5568. *
  5569. */
  5570. static u16
  5571. brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
  5572. struct sk_buff *p, struct scb *scb, uint frag,
  5573. uint nfrags, uint queue, uint next_frag_len)
  5574. {
  5575. struct ieee80211_hdr *h;
  5576. struct d11txh *txh;
  5577. u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
  5578. int len, phylen, rts_phylen;
  5579. u16 mch, phyctl, xfts, mainrates;
  5580. u16 seq = 0, mcl = 0, status = 0, frameid = 0;
  5581. u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5582. u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
  5583. bool use_rts = false;
  5584. bool use_cts = false;
  5585. bool use_rifs = false;
  5586. bool short_preamble[2] = { false, false };
  5587. u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5588. u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
  5589. u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
  5590. struct ieee80211_rts *rts = NULL;
  5591. bool qos;
  5592. uint ac;
  5593. bool hwtkmic = false;
  5594. u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
  5595. #define ANTCFG_NONE 0xFF
  5596. u8 antcfg = ANTCFG_NONE;
  5597. u8 fbantcfg = ANTCFG_NONE;
  5598. uint phyctl1_stf = 0;
  5599. u16 durid = 0;
  5600. struct ieee80211_tx_rate *txrate[2];
  5601. int k;
  5602. struct ieee80211_tx_info *tx_info;
  5603. bool is_mcs;
  5604. u16 mimo_txbw;
  5605. u8 mimo_preamble_type;
  5606. /* locate 802.11 MAC header */
  5607. h = (struct ieee80211_hdr *)(p->data);
  5608. qos = ieee80211_is_data_qos(h->frame_control);
  5609. /* compute length of frame in bytes for use in PLCP computations */
  5610. len = brcmu_pkttotlen(p);
  5611. phylen = len + FCS_LEN;
  5612. /* Get tx_info */
  5613. tx_info = IEEE80211_SKB_CB(p);
  5614. /* add PLCP */
  5615. plcp = skb_push(p, D11_PHY_HDR_LEN);
  5616. /* add Broadcom tx descriptor header */
  5617. txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
  5618. memset(txh, 0, D11_TXH_LEN);
  5619. /* setup frameid */
  5620. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  5621. /* non-AP STA should never use BCMC queue */
  5622. if (queue == TX_BCMC_FIFO) {
  5623. wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
  5624. "TX_BCMC!\n", wlc->pub->unit, __func__);
  5625. frameid = bcmc_fid_generate(wlc, NULL, txh);
  5626. } else {
  5627. /* Increment the counter for first fragment */
  5628. if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  5629. scb->seqnum[p->priority]++;
  5630. /* extract fragment number from frame first */
  5631. seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
  5632. seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
  5633. h->seq_ctrl = cpu_to_le16(seq);
  5634. frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
  5635. (queue & TXFID_QUEUE_MASK);
  5636. }
  5637. }
  5638. frameid |= queue & TXFID_QUEUE_MASK;
  5639. /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
  5640. if (ieee80211_is_beacon(h->frame_control))
  5641. mcl |= TXC_IGNOREPMQ;
  5642. txrate[0] = tx_info->control.rates;
  5643. txrate[1] = txrate[0] + 1;
  5644. /*
  5645. * if rate control algorithm didn't give us a fallback
  5646. * rate, use the primary rate
  5647. */
  5648. if (txrate[1]->idx < 0)
  5649. txrate[1] = txrate[0];
  5650. for (k = 0; k < hw->max_rates; k++) {
  5651. is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
  5652. if (!is_mcs) {
  5653. if ((txrate[k]->idx >= 0)
  5654. && (txrate[k]->idx <
  5655. hw->wiphy->bands[tx_info->band]->n_bitrates)) {
  5656. rspec[k] =
  5657. hw->wiphy->bands[tx_info->band]->
  5658. bitrates[txrate[k]->idx].hw_value;
  5659. short_preamble[k] =
  5660. txrate[k]->
  5661. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
  5662. true : false;
  5663. } else {
  5664. rspec[k] = BRCM_RATE_1M;
  5665. }
  5666. } else {
  5667. rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
  5668. NRATE_MCS_INUSE | txrate[k]->idx);
  5669. }
  5670. /*
  5671. * Currently only support same setting for primay and
  5672. * fallback rates. Unify flags for each rate into a
  5673. * single value for the frame
  5674. */
  5675. use_rts |=
  5676. txrate[k]->
  5677. flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
  5678. use_cts |=
  5679. txrate[k]->
  5680. flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
  5681. /*
  5682. * (1) RATE:
  5683. * determine and validate primary rate
  5684. * and fallback rates
  5685. */
  5686. if (!rspec_active(rspec[k])) {
  5687. rspec[k] = BRCM_RATE_1M;
  5688. } else {
  5689. if (!is_multicast_ether_addr(h->addr1)) {
  5690. /* set tx antenna config */
  5691. brcms_c_antsel_antcfg_get(wlc->asi, false,
  5692. false, 0, 0, &antcfg, &fbantcfg);
  5693. }
  5694. }
  5695. }
  5696. phyctl1_stf = wlc->stf->ss_opmode;
  5697. if (wlc->pub->_n_enab & SUPPORT_11N) {
  5698. for (k = 0; k < hw->max_rates; k++) {
  5699. /*
  5700. * apply siso/cdd to single stream mcs's or ofdm
  5701. * if rspec is auto selected
  5702. */
  5703. if (((is_mcs_rate(rspec[k]) &&
  5704. is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
  5705. is_ofdm_rate(rspec[k]))
  5706. && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
  5707. || !(rspec[k] & RSPEC_OVERRIDE))) {
  5708. rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
  5709. /* For SISO MCS use STBC if possible */
  5710. if (is_mcs_rate(rspec[k])
  5711. && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
  5712. u8 stc;
  5713. /* Nss for single stream is always 1 */
  5714. stc = 1;
  5715. rspec[k] |= (PHY_TXC1_MODE_STBC <<
  5716. RSPEC_STF_SHIFT) |
  5717. (stc << RSPEC_STC_SHIFT);
  5718. } else
  5719. rspec[k] |=
  5720. (phyctl1_stf << RSPEC_STF_SHIFT);
  5721. }
  5722. /*
  5723. * Is the phy configured to use 40MHZ frames? If
  5724. * so then pick the desired txbw
  5725. */
  5726. if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
  5727. /* default txbw is 20in40 SB */
  5728. mimo_ctlchbw = mimo_txbw =
  5729. CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
  5730. wlc->band->pi))
  5731. ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
  5732. if (is_mcs_rate(rspec[k])) {
  5733. /* mcs 32 must be 40b/w DUP */
  5734. if ((rspec[k] & RSPEC_RATE_MASK)
  5735. == 32) {
  5736. mimo_txbw =
  5737. PHY_TXC1_BW_40MHZ_DUP;
  5738. /* use override */
  5739. } else if (wlc->mimo_40txbw != AUTO)
  5740. mimo_txbw = wlc->mimo_40txbw;
  5741. /* else check if dst is using 40 Mhz */
  5742. else if (scb->flags & SCB_IS40)
  5743. mimo_txbw = PHY_TXC1_BW_40MHZ;
  5744. } else if (is_ofdm_rate(rspec[k])) {
  5745. if (wlc->ofdm_40txbw != AUTO)
  5746. mimo_txbw = wlc->ofdm_40txbw;
  5747. } else if (wlc->cck_40txbw != AUTO) {
  5748. mimo_txbw = wlc->cck_40txbw;
  5749. }
  5750. } else {
  5751. /*
  5752. * mcs32 is 40 b/w only.
  5753. * This is possible for probe packets on
  5754. * a STA during SCAN
  5755. */
  5756. if ((rspec[k] & RSPEC_RATE_MASK) == 32)
  5757. /* mcs 0 */
  5758. rspec[k] = RSPEC_MIMORATE;
  5759. mimo_txbw = PHY_TXC1_BW_20MHZ;
  5760. }
  5761. /* Set channel width */
  5762. rspec[k] &= ~RSPEC_BW_MASK;
  5763. if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
  5764. rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
  5765. else
  5766. rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  5767. /* Disable short GI, not supported yet */
  5768. rspec[k] &= ~RSPEC_SHORT_GI;
  5769. mimo_preamble_type = BRCMS_MM_PREAMBLE;
  5770. if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
  5771. mimo_preamble_type = BRCMS_GF_PREAMBLE;
  5772. if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
  5773. && (!is_mcs_rate(rspec[k]))) {
  5774. wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
  5775. "RC_MCS != is_mcs_rate(rspec)\n",
  5776. wlc->pub->unit, __func__);
  5777. }
  5778. if (is_mcs_rate(rspec[k])) {
  5779. preamble_type[k] = mimo_preamble_type;
  5780. /*
  5781. * if SGI is selected, then forced mm
  5782. * for single stream
  5783. */
  5784. if ((rspec[k] & RSPEC_SHORT_GI)
  5785. && is_single_stream(rspec[k] &
  5786. RSPEC_RATE_MASK))
  5787. preamble_type[k] = BRCMS_MM_PREAMBLE;
  5788. }
  5789. /* should be better conditionalized */
  5790. if (!is_mcs_rate(rspec[0])
  5791. && (tx_info->control.rates[0].
  5792. flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
  5793. preamble_type[k] = BRCMS_SHORT_PREAMBLE;
  5794. }
  5795. } else {
  5796. for (k = 0; k < hw->max_rates; k++) {
  5797. /* Set ctrlchbw as 20Mhz */
  5798. rspec[k] &= ~RSPEC_BW_MASK;
  5799. rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
  5800. /* for nphy, stf of ofdm frames must follow policies */
  5801. if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
  5802. rspec[k] &= ~RSPEC_STF_MASK;
  5803. rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
  5804. }
  5805. }
  5806. }
  5807. /* Reset these for use with AMPDU's */
  5808. txrate[0]->count = 0;
  5809. txrate[1]->count = 0;
  5810. /* (2) PROTECTION, may change rspec */
  5811. if ((ieee80211_is_data(h->frame_control) ||
  5812. ieee80211_is_mgmt(h->frame_control)) &&
  5813. (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
  5814. use_rts = true;
  5815. /* (3) PLCP: determine PLCP header and MAC duration,
  5816. * fill struct d11txh */
  5817. brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
  5818. brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
  5819. memcpy(&txh->FragPLCPFallback,
  5820. plcp_fallback, sizeof(txh->FragPLCPFallback));
  5821. /* Length field now put in CCK FBR CRC field */
  5822. if (is_cck_rate(rspec[1])) {
  5823. txh->FragPLCPFallback[4] = phylen & 0xff;
  5824. txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
  5825. }
  5826. /* MIMO-RATE: need validation ?? */
  5827. mainrates = is_ofdm_rate(rspec[0]) ?
  5828. D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
  5829. plcp[0];
  5830. /* DUR field for main rate */
  5831. if (!ieee80211_is_pspoll(h->frame_control) &&
  5832. !is_multicast_ether_addr(h->addr1) && !use_rifs) {
  5833. durid =
  5834. brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
  5835. next_frag_len);
  5836. h->duration_id = cpu_to_le16(durid);
  5837. } else if (use_rifs) {
  5838. /* NAV protect to end of next max packet size */
  5839. durid =
  5840. (u16) brcms_c_calc_frame_time(wlc, rspec[0],
  5841. preamble_type[0],
  5842. DOT11_MAX_FRAG_LEN);
  5843. durid += RIFS_11N_TIME;
  5844. h->duration_id = cpu_to_le16(durid);
  5845. }
  5846. /* DUR field for fallback rate */
  5847. if (ieee80211_is_pspoll(h->frame_control))
  5848. txh->FragDurFallback = h->duration_id;
  5849. else if (is_multicast_ether_addr(h->addr1) || use_rifs)
  5850. txh->FragDurFallback = 0;
  5851. else {
  5852. durid = brcms_c_compute_frame_dur(wlc, rspec[1],
  5853. preamble_type[1], next_frag_len);
  5854. txh->FragDurFallback = cpu_to_le16(durid);
  5855. }
  5856. /* (4) MAC-HDR: MacTxControlLow */
  5857. if (frag == 0)
  5858. mcl |= TXC_STARTMSDU;
  5859. if (!is_multicast_ether_addr(h->addr1))
  5860. mcl |= TXC_IMMEDACK;
  5861. if (wlc->band->bandtype == BRCM_BAND_5G)
  5862. mcl |= TXC_FREQBAND_5G;
  5863. if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
  5864. mcl |= TXC_BW_40;
  5865. /* set AMIC bit if using hardware TKIP MIC */
  5866. if (hwtkmic)
  5867. mcl |= TXC_AMIC;
  5868. txh->MacTxControlLow = cpu_to_le16(mcl);
  5869. /* MacTxControlHigh */
  5870. mch = 0;
  5871. /* Set fallback rate preamble type */
  5872. if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
  5873. (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
  5874. if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
  5875. mch |= TXC_PREAMBLE_DATA_FB_SHORT;
  5876. }
  5877. /* MacFrameControl */
  5878. memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
  5879. txh->TxFesTimeNormal = cpu_to_le16(0);
  5880. txh->TxFesTimeFallback = cpu_to_le16(0);
  5881. /* TxFrameRA */
  5882. memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
  5883. /* TxFrameID */
  5884. txh->TxFrameID = cpu_to_le16(frameid);
  5885. /*
  5886. * TxStatus, Note the case of recreating the first frag of a suppressed
  5887. * frame then we may need to reset the retry cnt's via the status reg
  5888. */
  5889. txh->TxStatus = cpu_to_le16(status);
  5890. /*
  5891. * extra fields for ucode AMPDU aggregation, the new fields are added to
  5892. * the END of previous structure so that it's compatible in driver.
  5893. */
  5894. txh->MaxNMpdus = cpu_to_le16(0);
  5895. txh->MaxABytes_MRT = cpu_to_le16(0);
  5896. txh->MaxABytes_FBR = cpu_to_le16(0);
  5897. txh->MinMBytes = cpu_to_le16(0);
  5898. /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
  5899. * furnish struct d11txh */
  5900. /* RTS PLCP header and RTS frame */
  5901. if (use_rts || use_cts) {
  5902. if (use_rts && use_cts)
  5903. use_cts = false;
  5904. for (k = 0; k < 2; k++) {
  5905. rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
  5906. false,
  5907. mimo_ctlchbw);
  5908. }
  5909. if (!is_ofdm_rate(rts_rspec[0]) &&
  5910. !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
  5911. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5912. rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
  5913. mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
  5914. }
  5915. if (!is_ofdm_rate(rts_rspec[1]) &&
  5916. !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
  5917. (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
  5918. rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
  5919. mch |= TXC_PREAMBLE_RTS_FB_SHORT;
  5920. }
  5921. /* RTS/CTS additions to MacTxControlLow */
  5922. if (use_cts) {
  5923. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
  5924. } else {
  5925. txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
  5926. txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
  5927. }
  5928. /* RTS PLCP header */
  5929. rts_plcp = txh->RTSPhyHeader;
  5930. if (use_cts)
  5931. rts_phylen = DOT11_CTS_LEN + FCS_LEN;
  5932. else
  5933. rts_phylen = DOT11_RTS_LEN + FCS_LEN;
  5934. brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
  5935. /* fallback rate version of RTS PLCP header */
  5936. brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
  5937. rts_plcp_fallback);
  5938. memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
  5939. sizeof(txh->RTSPLCPFallback));
  5940. /* RTS frame fields... */
  5941. rts = (struct ieee80211_rts *)&txh->rts_frame;
  5942. durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
  5943. rspec[0], rts_preamble_type[0],
  5944. preamble_type[0], phylen, false);
  5945. rts->duration = cpu_to_le16(durid);
  5946. /* fallback rate version of RTS DUR field */
  5947. durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
  5948. rts_rspec[1], rspec[1],
  5949. rts_preamble_type[1],
  5950. preamble_type[1], phylen, false);
  5951. txh->RTSDurFallback = cpu_to_le16(durid);
  5952. if (use_cts) {
  5953. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5954. IEEE80211_STYPE_CTS);
  5955. memcpy(&rts->ra, &h->addr2, ETH_ALEN);
  5956. } else {
  5957. rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
  5958. IEEE80211_STYPE_RTS);
  5959. memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
  5960. }
  5961. /* mainrate
  5962. * low 8 bits: main frag rate/mcs,
  5963. * high 8 bits: rts/cts rate/mcs
  5964. */
  5965. mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
  5966. D11A_PHY_HDR_GRATE(
  5967. (struct ofdm_phy_hdr *) rts_plcp) :
  5968. rts_plcp[0]) << 8;
  5969. } else {
  5970. memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
  5971. memset((char *)&txh->rts_frame, 0,
  5972. sizeof(struct ieee80211_rts));
  5973. memset((char *)txh->RTSPLCPFallback, 0,
  5974. sizeof(txh->RTSPLCPFallback));
  5975. txh->RTSDurFallback = 0;
  5976. }
  5977. #ifdef SUPPORT_40MHZ
  5978. /* add null delimiter count */
  5979. if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
  5980. txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
  5981. brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
  5982. #endif
  5983. /*
  5984. * Now that RTS/RTS FB preamble types are updated, write
  5985. * the final value
  5986. */
  5987. txh->MacTxControlHigh = cpu_to_le16(mch);
  5988. /*
  5989. * MainRates (both the rts and frag plcp rates have
  5990. * been calculated now)
  5991. */
  5992. txh->MainRates = cpu_to_le16(mainrates);
  5993. /* XtraFrameTypes */
  5994. xfts = frametype(rspec[1], wlc->mimoft);
  5995. xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
  5996. xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
  5997. xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
  5998. XFTS_CHANNEL_SHIFT;
  5999. txh->XtraFrameTypes = cpu_to_le16(xfts);
  6000. /* PhyTxControlWord */
  6001. phyctl = frametype(rspec[0], wlc->mimoft);
  6002. if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
  6003. (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
  6004. if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
  6005. phyctl |= PHY_TXC_SHORT_HDR;
  6006. }
  6007. /* phytxant is properly bit shifted */
  6008. phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
  6009. txh->PhyTxControlWord = cpu_to_le16(phyctl);
  6010. /* PhyTxControlWord_1 */
  6011. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  6012. u16 phyctl1 = 0;
  6013. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
  6014. txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
  6015. phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
  6016. txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
  6017. if (use_rts || use_cts) {
  6018. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
  6019. txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
  6020. phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
  6021. txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
  6022. }
  6023. /*
  6024. * For mcs frames, if mixedmode(overloaded with long preamble)
  6025. * is going to be set, fill in non-zero MModeLen and/or
  6026. * MModeFbrLen it will be unnecessary if they are separated
  6027. */
  6028. if (is_mcs_rate(rspec[0]) &&
  6029. (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
  6030. u16 mmodelen =
  6031. brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
  6032. txh->MModeLen = cpu_to_le16(mmodelen);
  6033. }
  6034. if (is_mcs_rate(rspec[1]) &&
  6035. (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
  6036. u16 mmodefbrlen =
  6037. brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
  6038. txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
  6039. }
  6040. }
  6041. ac = skb_get_queue_mapping(p);
  6042. if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
  6043. uint frag_dur, dur, dur_fallback;
  6044. /* WME: Update TXOP threshold */
  6045. if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
  6046. frag_dur =
  6047. brcms_c_calc_frame_time(wlc, rspec[0],
  6048. preamble_type[0], phylen);
  6049. if (rts) {
  6050. /* 1 RTS or CTS-to-self frame */
  6051. dur =
  6052. brcms_c_calc_cts_time(wlc, rts_rspec[0],
  6053. rts_preamble_type[0]);
  6054. dur_fallback =
  6055. brcms_c_calc_cts_time(wlc, rts_rspec[1],
  6056. rts_preamble_type[1]);
  6057. /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
  6058. dur += le16_to_cpu(rts->duration);
  6059. dur_fallback +=
  6060. le16_to_cpu(txh->RTSDurFallback);
  6061. } else if (use_rifs) {
  6062. dur = frag_dur;
  6063. dur_fallback = 0;
  6064. } else {
  6065. /* frame + SIFS + ACK */
  6066. dur = frag_dur;
  6067. dur +=
  6068. brcms_c_compute_frame_dur(wlc, rspec[0],
  6069. preamble_type[0], 0);
  6070. dur_fallback =
  6071. brcms_c_calc_frame_time(wlc, rspec[1],
  6072. preamble_type[1],
  6073. phylen);
  6074. dur_fallback +=
  6075. brcms_c_compute_frame_dur(wlc, rspec[1],
  6076. preamble_type[1], 0);
  6077. }
  6078. /* NEED to set TxFesTimeNormal (hard) */
  6079. txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
  6080. /*
  6081. * NEED to set fallback rate version of
  6082. * TxFesTimeNormal (hard)
  6083. */
  6084. txh->TxFesTimeFallback =
  6085. cpu_to_le16((u16) dur_fallback);
  6086. /*
  6087. * update txop byte threshold (txop minus intraframe
  6088. * overhead)
  6089. */
  6090. if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
  6091. uint newfragthresh;
  6092. newfragthresh =
  6093. brcms_c_calc_frame_len(wlc,
  6094. rspec[0], preamble_type[0],
  6095. (wlc->edcf_txop[ac] -
  6096. (dur - frag_dur)));
  6097. /* range bound the fragthreshold */
  6098. if (newfragthresh < DOT11_MIN_FRAG_LEN)
  6099. newfragthresh =
  6100. DOT11_MIN_FRAG_LEN;
  6101. else if (newfragthresh >
  6102. wlc->usr_fragthresh)
  6103. newfragthresh =
  6104. wlc->usr_fragthresh;
  6105. /* update the fragthresh and do txc update */
  6106. if (wlc->fragthresh[queue] !=
  6107. (u16) newfragthresh)
  6108. wlc->fragthresh[queue] =
  6109. (u16) newfragthresh;
  6110. } else {
  6111. wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
  6112. "for rate %d\n",
  6113. wlc->pub->unit, fifo_names[queue],
  6114. rspec2rate(rspec[0]));
  6115. }
  6116. if (dur > wlc->edcf_txop[ac])
  6117. wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
  6118. "exceeded phylen %d/%d dur %d/%d\n",
  6119. wlc->pub->unit, __func__,
  6120. fifo_names[queue],
  6121. phylen, wlc->fragthresh[queue],
  6122. dur, wlc->edcf_txop[ac]);
  6123. }
  6124. }
  6125. return 0;
  6126. }
  6127. void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
  6128. struct ieee80211_hw *hw)
  6129. {
  6130. u8 prio;
  6131. uint fifo;
  6132. struct scb *scb = &wlc->pri_scb;
  6133. struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
  6134. /*
  6135. * 802.11 standard requires management traffic
  6136. * to go at highest priority
  6137. */
  6138. prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
  6139. MAXPRIO;
  6140. fifo = prio2fifo[prio];
  6141. if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
  6142. return;
  6143. brcms_c_txq_enq(wlc, scb, sdu, BRCMS_PRIO_TO_PREC(prio));
  6144. brcms_c_send_q(wlc);
  6145. }
  6146. void brcms_c_send_q(struct brcms_c_info *wlc)
  6147. {
  6148. struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
  6149. int prec;
  6150. u16 prec_map;
  6151. int err = 0, i, count;
  6152. uint fifo;
  6153. struct brcms_txq_info *qi = wlc->pkt_queue;
  6154. struct pktq *q = &qi->q;
  6155. struct ieee80211_tx_info *tx_info;
  6156. prec_map = wlc->tx_prec_map;
  6157. /* Send all the enq'd pkts that we can.
  6158. * Dequeue packets with precedence with empty HW fifo only
  6159. */
  6160. while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
  6161. tx_info = IEEE80211_SKB_CB(pkt[0]);
  6162. if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
  6163. err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec);
  6164. } else {
  6165. count = 1;
  6166. err = brcms_c_prep_pdu(wlc, pkt[0], &fifo);
  6167. if (!err) {
  6168. for (i = 0; i < count; i++)
  6169. brcms_c_txfifo(wlc, fifo, pkt[i], true,
  6170. 1);
  6171. }
  6172. }
  6173. if (err == -EBUSY) {
  6174. brcmu_pktq_penq_head(q, prec, pkt[0]);
  6175. /*
  6176. * If send failed due to any other reason than a
  6177. * change in HW FIFO condition, quit. Otherwise,
  6178. * read the new prec_map!
  6179. */
  6180. if (prec_map == wlc->tx_prec_map)
  6181. break;
  6182. prec_map = wlc->tx_prec_map;
  6183. }
  6184. }
  6185. }
  6186. void
  6187. brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p,
  6188. bool commit, s8 txpktpend)
  6189. {
  6190. u16 frameid = INVALIDFID;
  6191. struct d11txh *txh;
  6192. txh = (struct d11txh *) (p->data);
  6193. /* When a BC/MC frame is being committed to the BCMC fifo
  6194. * via DMA (NOT PIO), update ucode or BSS info as appropriate.
  6195. */
  6196. if (fifo == TX_BCMC_FIFO)
  6197. frameid = le16_to_cpu(txh->TxFrameID);
  6198. /*
  6199. * Bump up pending count for if not using rpc. If rpc is
  6200. * used, this will be handled in brcms_b_txfifo()
  6201. */
  6202. if (commit) {
  6203. wlc->core->txpktpend[fifo] += txpktpend;
  6204. BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
  6205. txpktpend, wlc->core->txpktpend[fifo]);
  6206. }
  6207. /* Commit BCMC sequence number in the SHM frame ID location */
  6208. if (frameid != INVALIDFID) {
  6209. /*
  6210. * To inform the ucode of the last mcast frame posted
  6211. * so that it can clear moredata bit
  6212. */
  6213. brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
  6214. }
  6215. if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0)
  6216. wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
  6217. }
  6218. u32
  6219. brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
  6220. bool use_rspec, u16 mimo_ctlchbw)
  6221. {
  6222. u32 rts_rspec = 0;
  6223. if (use_rspec)
  6224. /* use frame rate as rts rate */
  6225. rts_rspec = rspec;
  6226. else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
  6227. /* Use 11Mbps as the g protection RTS target rate and fallback.
  6228. * Use the brcms_basic_rate() lookup to find the best basic rate
  6229. * under the target in case 11 Mbps is not Basic.
  6230. * 6 and 9 Mbps are not usually selected by rate selection, but
  6231. * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
  6232. * is more robust.
  6233. */
  6234. rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
  6235. else
  6236. /* calculate RTS rate and fallback rate based on the frame rate
  6237. * RTS must be sent at a basic rate since it is a
  6238. * control frame, sec 9.6 of 802.11 spec
  6239. */
  6240. rts_rspec = brcms_basic_rate(wlc, rspec);
  6241. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  6242. /* set rts txbw to correct side band */
  6243. rts_rspec &= ~RSPEC_BW_MASK;
  6244. /*
  6245. * if rspec/rspec_fallback is 40MHz, then send RTS on both
  6246. * 20MHz channel (DUP), otherwise send RTS on control channel
  6247. */
  6248. if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
  6249. rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
  6250. else
  6251. rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
  6252. /* pick siso/cdd as default for ofdm */
  6253. if (is_ofdm_rate(rts_rspec)) {
  6254. rts_rspec &= ~RSPEC_STF_MASK;
  6255. rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
  6256. }
  6257. }
  6258. return rts_rspec;
  6259. }
  6260. void
  6261. brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo, s8 txpktpend)
  6262. {
  6263. wlc->core->txpktpend[fifo] -= txpktpend;
  6264. BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
  6265. wlc->core->txpktpend[fifo]);
  6266. /* There is more room; mark precedences related to this FIFO sendable */
  6267. wlc->tx_prec_map |= wlc->fifo2prec_map[fifo];
  6268. /* figure out which bsscfg is being worked on... */
  6269. }
  6270. /* Update beacon listen interval in shared memory */
  6271. static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
  6272. {
  6273. /* wake up every DTIM is the default */
  6274. if (wlc->bcn_li_dtim == 1)
  6275. brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
  6276. else
  6277. brcms_b_write_shm(wlc->hw, M_BCN_LI,
  6278. (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
  6279. }
  6280. static void
  6281. brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
  6282. u32 *tsf_h_ptr)
  6283. {
  6284. struct d11regs __iomem *regs = wlc_hw->regs;
  6285. /* read the tsf timer low, then high to get an atomic read */
  6286. *tsf_l_ptr = R_REG(&regs->tsf_timerlow);
  6287. *tsf_h_ptr = R_REG(&regs->tsf_timerhigh);
  6288. }
  6289. /*
  6290. * recover 64bit TSF value from the 16bit TSF value in the rx header
  6291. * given the assumption that the TSF passed in header is within 65ms
  6292. * of the current tsf.
  6293. *
  6294. * 6 5 4 4 3 2 1
  6295. * 3.......6.......8.......0.......2.......4.......6.......8......0
  6296. * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
  6297. *
  6298. * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
  6299. * tsf_l is filled in by brcms_b_recv, which is done earlier in the
  6300. * receive call sequence after rx interrupt. Only the higher 16 bits
  6301. * are used. Finally, the tsf_h is read from the tsf register.
  6302. */
  6303. static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
  6304. struct d11rxhdr *rxh)
  6305. {
  6306. u32 tsf_h, tsf_l;
  6307. u16 rx_tsf_0_15, rx_tsf_16_31;
  6308. brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
  6309. rx_tsf_16_31 = (u16)(tsf_l >> 16);
  6310. rx_tsf_0_15 = rxh->RxTSFTime;
  6311. /*
  6312. * a greater tsf time indicates the low 16 bits of
  6313. * tsf_l wrapped, so decrement the high 16 bits.
  6314. */
  6315. if ((u16)tsf_l < rx_tsf_0_15) {
  6316. rx_tsf_16_31 -= 1;
  6317. if (rx_tsf_16_31 == 0xffff)
  6318. tsf_h -= 1;
  6319. }
  6320. return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
  6321. }
  6322. static void
  6323. prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  6324. struct sk_buff *p,
  6325. struct ieee80211_rx_status *rx_status)
  6326. {
  6327. int preamble;
  6328. int channel;
  6329. u32 rspec;
  6330. unsigned char *plcp;
  6331. /* fill in TSF and flag its presence */
  6332. rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
  6333. rx_status->flag |= RX_FLAG_MACTIME_MPDU;
  6334. channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
  6335. if (channel > 14) {
  6336. rx_status->band = IEEE80211_BAND_5GHZ;
  6337. rx_status->freq = ieee80211_ofdm_chan_to_freq(
  6338. WF_CHAN_FACTOR_5_G/2, channel);
  6339. } else {
  6340. rx_status->band = IEEE80211_BAND_2GHZ;
  6341. rx_status->freq = ieee80211_dsss_chan_to_freq(channel);
  6342. }
  6343. rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
  6344. /* noise */
  6345. /* qual */
  6346. rx_status->antenna =
  6347. (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
  6348. plcp = p->data;
  6349. rspec = brcms_c_compute_rspec(rxh, plcp);
  6350. if (is_mcs_rate(rspec)) {
  6351. rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
  6352. rx_status->flag |= RX_FLAG_HT;
  6353. if (rspec_is40mhz(rspec))
  6354. rx_status->flag |= RX_FLAG_40MHZ;
  6355. } else {
  6356. switch (rspec2rate(rspec)) {
  6357. case BRCM_RATE_1M:
  6358. rx_status->rate_idx = 0;
  6359. break;
  6360. case BRCM_RATE_2M:
  6361. rx_status->rate_idx = 1;
  6362. break;
  6363. case BRCM_RATE_5M5:
  6364. rx_status->rate_idx = 2;
  6365. break;
  6366. case BRCM_RATE_11M:
  6367. rx_status->rate_idx = 3;
  6368. break;
  6369. case BRCM_RATE_6M:
  6370. rx_status->rate_idx = 4;
  6371. break;
  6372. case BRCM_RATE_9M:
  6373. rx_status->rate_idx = 5;
  6374. break;
  6375. case BRCM_RATE_12M:
  6376. rx_status->rate_idx = 6;
  6377. break;
  6378. case BRCM_RATE_18M:
  6379. rx_status->rate_idx = 7;
  6380. break;
  6381. case BRCM_RATE_24M:
  6382. rx_status->rate_idx = 8;
  6383. break;
  6384. case BRCM_RATE_36M:
  6385. rx_status->rate_idx = 9;
  6386. break;
  6387. case BRCM_RATE_48M:
  6388. rx_status->rate_idx = 10;
  6389. break;
  6390. case BRCM_RATE_54M:
  6391. rx_status->rate_idx = 11;
  6392. break;
  6393. default:
  6394. wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
  6395. }
  6396. /*
  6397. * For 5GHz, we should decrease the index as it is
  6398. * a subset of the 2.4G rates. See bitrates field
  6399. * of brcms_band_5GHz_nphy (in mac80211_if.c).
  6400. */
  6401. if (rx_status->band == IEEE80211_BAND_5GHZ)
  6402. rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
  6403. /* Determine short preamble and rate_idx */
  6404. preamble = 0;
  6405. if (is_cck_rate(rspec)) {
  6406. if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
  6407. rx_status->flag |= RX_FLAG_SHORTPRE;
  6408. } else if (is_ofdm_rate(rspec)) {
  6409. rx_status->flag |= RX_FLAG_SHORTPRE;
  6410. } else {
  6411. wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
  6412. __func__);
  6413. }
  6414. }
  6415. if (plcp3_issgi(plcp[3]))
  6416. rx_status->flag |= RX_FLAG_SHORT_GI;
  6417. if (rxh->RxStatus1 & RXS_DECERR) {
  6418. rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
  6419. wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
  6420. __func__);
  6421. }
  6422. if (rxh->RxStatus1 & RXS_FCSERR) {
  6423. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  6424. wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
  6425. __func__);
  6426. }
  6427. }
  6428. static void
  6429. brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
  6430. struct sk_buff *p)
  6431. {
  6432. int len_mpdu;
  6433. struct ieee80211_rx_status rx_status;
  6434. memset(&rx_status, 0, sizeof(rx_status));
  6435. prep_mac80211_status(wlc, rxh, p, &rx_status);
  6436. /* mac header+body length, exclude CRC and plcp header */
  6437. len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
  6438. skb_pull(p, D11_PHY_HDR_LEN);
  6439. __skb_trim(p, len_mpdu);
  6440. memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
  6441. ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
  6442. }
  6443. /* calculate frame duration for Mixed-mode L-SIG spoofing, return
  6444. * number of bytes goes in the length field
  6445. *
  6446. * Formula given by HT PHY Spec v 1.13
  6447. * len = 3(nsyms + nstream + 3) - 3
  6448. */
  6449. u16
  6450. brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
  6451. uint mac_len)
  6452. {
  6453. uint nsyms, len = 0, kNdps;
  6454. BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
  6455. wlc->pub->unit, rspec2rate(ratespec), mac_len);
  6456. if (is_mcs_rate(ratespec)) {
  6457. uint mcs = ratespec & RSPEC_RATE_MASK;
  6458. int tot_streams = (mcs_2_txstreams(mcs) + 1) +
  6459. rspec_stc(ratespec);
  6460. /*
  6461. * the payload duration calculation matches that
  6462. * of regular ofdm
  6463. */
  6464. /* 1000Ndbps = kbps * 4 */
  6465. kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
  6466. rspec_issgi(ratespec)) * 4;
  6467. if (rspec_stc(ratespec) == 0)
  6468. nsyms =
  6469. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6470. APHY_TAIL_NBITS) * 1000, kNdps);
  6471. else
  6472. /* STBC needs to have even number of symbols */
  6473. nsyms =
  6474. 2 *
  6475. CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
  6476. APHY_TAIL_NBITS) * 1000, 2 * kNdps);
  6477. /* (+3) account for HT-SIG(2) and HT-STF(1) */
  6478. nsyms += (tot_streams + 3);
  6479. /*
  6480. * 3 bytes/symbol @ legacy 6Mbps rate
  6481. * (-3) excluding service bits and tail bits
  6482. */
  6483. len = (3 * nsyms) - 3;
  6484. }
  6485. return (u16) len;
  6486. }
  6487. static void
  6488. brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
  6489. {
  6490. const struct brcms_c_rateset *rs_dflt;
  6491. struct brcms_c_rateset rs;
  6492. u8 rate;
  6493. u16 entry_ptr;
  6494. u8 plcp[D11_PHY_HDR_LEN];
  6495. u16 dur, sifs;
  6496. uint i;
  6497. sifs = get_sifs(wlc->band);
  6498. rs_dflt = brcms_c_rateset_get_hwrs(wlc);
  6499. brcms_c_rateset_copy(rs_dflt, &rs);
  6500. brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
  6501. /*
  6502. * walk the phy rate table and update MAC core SHM
  6503. * basic rate table entries
  6504. */
  6505. for (i = 0; i < rs.count; i++) {
  6506. rate = rs.rates[i] & BRCMS_RATE_MASK;
  6507. entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
  6508. /* Calculate the Probe Response PLCP for the given rate */
  6509. brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
  6510. /*
  6511. * Calculate the duration of the Probe Response
  6512. * frame plus SIFS for the MAC
  6513. */
  6514. dur = (u16) brcms_c_calc_frame_time(wlc, rate,
  6515. BRCMS_LONG_PREAMBLE, frame_len);
  6516. dur += sifs;
  6517. /* Update the SHM Rate Table entry Probe Response values */
  6518. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
  6519. (u16) (plcp[0] + (plcp[1] << 8)));
  6520. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
  6521. (u16) (plcp[2] + (plcp[3] << 8)));
  6522. brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
  6523. }
  6524. }
  6525. /* Max buffering needed for beacon template/prb resp template is 142 bytes.
  6526. *
  6527. * PLCP header is 6 bytes.
  6528. * 802.11 A3 header is 24 bytes.
  6529. * Max beacon frame body template length is 112 bytes.
  6530. * Max probe resp frame body template length is 110 bytes.
  6531. *
  6532. * *len on input contains the max length of the packet available.
  6533. *
  6534. * The *len value is set to the number of bytes in buf used, and starts
  6535. * with the PLCP and included up to, but not including, the 4 byte FCS.
  6536. */
  6537. static void
  6538. brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
  6539. u32 bcn_rspec,
  6540. struct brcms_bss_cfg *cfg, u16 *buf, int *len)
  6541. {
  6542. static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
  6543. struct cck_phy_hdr *plcp;
  6544. struct ieee80211_mgmt *h;
  6545. int hdr_len, body_len;
  6546. hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
  6547. /* calc buffer size provided for frame body */
  6548. body_len = *len - hdr_len;
  6549. /* return actual size */
  6550. *len = hdr_len + body_len;
  6551. /* format PHY and MAC headers */
  6552. memset((char *)buf, 0, hdr_len);
  6553. plcp = (struct cck_phy_hdr *) buf;
  6554. /*
  6555. * PLCP for Probe Response frames are filled in from
  6556. * core's rate table
  6557. */
  6558. if (type == IEEE80211_STYPE_BEACON)
  6559. /* fill in PLCP */
  6560. brcms_c_compute_plcp(wlc, bcn_rspec,
  6561. (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
  6562. (u8 *) plcp);
  6563. /* "Regular" and 16 MBSS but not for 4 MBSS */
  6564. /* Update the phytxctl for the beacon based on the rspec */
  6565. brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
  6566. h = (struct ieee80211_mgmt *)&plcp[1];
  6567. /* fill in 802.11 header */
  6568. h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
  6569. /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
  6570. /* A1 filled in by MAC for prb resp, broadcast for bcn */
  6571. if (type == IEEE80211_STYPE_BEACON)
  6572. memcpy(&h->da, &ether_bcast, ETH_ALEN);
  6573. memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
  6574. memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
  6575. /* SEQ filled in by MAC */
  6576. }
  6577. int brcms_c_get_header_len(void)
  6578. {
  6579. return TXOFF;
  6580. }
  6581. /*
  6582. * Update all beacons for the system.
  6583. */
  6584. void brcms_c_update_beacon(struct brcms_c_info *wlc)
  6585. {
  6586. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6587. if (bsscfg->up && !bsscfg->BSS)
  6588. /* Clear the soft intmask */
  6589. wlc->defmacintmask &= ~MI_BCNTPL;
  6590. }
  6591. /* Write ssid into shared memory */
  6592. static void
  6593. brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
  6594. {
  6595. u8 *ssidptr = cfg->SSID;
  6596. u16 base = M_SSID;
  6597. u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
  6598. /* padding the ssid with zero and copy it into shm */
  6599. memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
  6600. memcpy(ssidbuf, ssidptr, cfg->SSID_len);
  6601. brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
  6602. brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
  6603. }
  6604. static void
  6605. brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
  6606. struct brcms_bss_cfg *cfg,
  6607. bool suspend)
  6608. {
  6609. u16 prb_resp[BCN_TMPL_LEN / 2];
  6610. int len = BCN_TMPL_LEN;
  6611. /*
  6612. * write the probe response to hardware, or save in
  6613. * the config structure
  6614. */
  6615. /* create the probe response template */
  6616. brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
  6617. cfg, prb_resp, &len);
  6618. if (suspend)
  6619. brcms_c_suspend_mac_and_wait(wlc);
  6620. /* write the probe response into the template region */
  6621. brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
  6622. (len + 3) & ~3, prb_resp);
  6623. /* write the length of the probe response frame (+PLCP/-FCS) */
  6624. brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
  6625. /* write the SSID and SSID length */
  6626. brcms_c_shm_ssid_upd(wlc, cfg);
  6627. /*
  6628. * Write PLCP headers and durations for probe response frames
  6629. * at all rates. Use the actual frame length covered by the
  6630. * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
  6631. * by subtracting the PLCP len and adding the FCS.
  6632. */
  6633. len += (-D11_PHY_HDR_LEN + FCS_LEN);
  6634. brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
  6635. if (suspend)
  6636. brcms_c_enable_mac(wlc);
  6637. }
  6638. void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
  6639. {
  6640. struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
  6641. /* update AP or IBSS probe responses */
  6642. if (bsscfg->up && !bsscfg->BSS)
  6643. brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
  6644. }
  6645. /* prepares pdu for transmission. returns BCM error codes */
  6646. int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop)
  6647. {
  6648. uint fifo;
  6649. struct d11txh *txh;
  6650. struct ieee80211_hdr *h;
  6651. struct scb *scb;
  6652. txh = (struct d11txh *) (pdu->data);
  6653. h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
  6654. /* get the pkt queue info. This was put at brcms_c_sendctl or
  6655. * brcms_c_send for PDU */
  6656. fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
  6657. scb = NULL;
  6658. *fifop = fifo;
  6659. /* return if insufficient dma resources */
  6660. if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) {
  6661. /* Mark precedences related to this FIFO, unsendable */
  6662. /* A fifo is full. Clear precedences related to that FIFO */
  6663. wlc->tx_prec_map &= ~(wlc->fifo2prec_map[fifo]);
  6664. return -EBUSY;
  6665. }
  6666. return 0;
  6667. }
  6668. int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
  6669. uint *blocks)
  6670. {
  6671. if (fifo >= NFIFO)
  6672. return -EINVAL;
  6673. *blocks = wlc_hw->xmtfifo_sz[fifo];
  6674. return 0;
  6675. }
  6676. void
  6677. brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
  6678. const u8 *addr)
  6679. {
  6680. brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
  6681. if (match_reg_offset == RCM_BSSID_OFFSET)
  6682. memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
  6683. }
  6684. /*
  6685. * Flag 'scan in progress' to withhold dynamic phy calibration
  6686. */
  6687. void brcms_c_scan_start(struct brcms_c_info *wlc)
  6688. {
  6689. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
  6690. }
  6691. void brcms_c_scan_stop(struct brcms_c_info *wlc)
  6692. {
  6693. wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
  6694. }
  6695. void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
  6696. {
  6697. wlc->pub->associated = state;
  6698. wlc->bsscfg->associated = state;
  6699. }
  6700. /*
  6701. * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
  6702. * AMPDU traffic, packets pending in hardware have to be invalidated so that
  6703. * when later on hardware releases them, they can be handled appropriately.
  6704. */
  6705. void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
  6706. struct ieee80211_sta *sta,
  6707. void (*dma_callback_fn))
  6708. {
  6709. struct dma_pub *dmah;
  6710. int i;
  6711. for (i = 0; i < NFIFO; i++) {
  6712. dmah = hw->di[i];
  6713. if (dmah != NULL)
  6714. dma_walk_packets(dmah, dma_callback_fn, sta);
  6715. }
  6716. }
  6717. int brcms_c_get_curband(struct brcms_c_info *wlc)
  6718. {
  6719. return wlc->band->bandunit;
  6720. }
  6721. void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
  6722. {
  6723. /* flush packet queue when requested */
  6724. if (drop)
  6725. brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
  6726. /* wait for queue and DMA fifos to run dry */
  6727. while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0)
  6728. brcms_msleep(wlc->wl, 1);
  6729. }
  6730. void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
  6731. {
  6732. wlc->bcn_li_bcn = interval;
  6733. if (wlc->pub->up)
  6734. brcms_c_bcn_li_upd(wlc);
  6735. }
  6736. int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
  6737. {
  6738. uint qdbm;
  6739. /* Remove override bit and clip to max qdbm value */
  6740. qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
  6741. return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
  6742. }
  6743. int brcms_c_get_tx_power(struct brcms_c_info *wlc)
  6744. {
  6745. uint qdbm;
  6746. bool override;
  6747. wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
  6748. /* Return qdbm units */
  6749. return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
  6750. }
  6751. /* Process received frames */
  6752. /*
  6753. * Return true if more frames need to be processed. false otherwise.
  6754. * Param 'bound' indicates max. # frames to process before break out.
  6755. */
  6756. static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
  6757. {
  6758. struct d11rxhdr *rxh;
  6759. struct ieee80211_hdr *h;
  6760. uint len;
  6761. bool is_amsdu;
  6762. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  6763. /* frame starts with rxhdr */
  6764. rxh = (struct d11rxhdr *) (p->data);
  6765. /* strip off rxhdr */
  6766. skb_pull(p, BRCMS_HWRXOFF);
  6767. /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
  6768. if (rxh->RxStatus1 & RXS_PBPRES) {
  6769. if (p->len < 2) {
  6770. wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
  6771. "len %d\n", wlc->pub->unit, p->len);
  6772. goto toss;
  6773. }
  6774. skb_pull(p, 2);
  6775. }
  6776. h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
  6777. len = p->len;
  6778. if (rxh->RxStatus1 & RXS_FCSERR) {
  6779. if (wlc->pub->mac80211_state & MAC80211_PROMISC_BCNS) {
  6780. wiphy_err(wlc->wiphy, "FCSERR while scanning******* -"
  6781. " tossing\n");
  6782. goto toss;
  6783. } else {
  6784. wiphy_err(wlc->wiphy, "RCSERR!!!\n");
  6785. goto toss;
  6786. }
  6787. }
  6788. /* check received pkt has at least frame control field */
  6789. if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
  6790. goto toss;
  6791. /* not supporting A-MSDU */
  6792. is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
  6793. if (is_amsdu)
  6794. goto toss;
  6795. brcms_c_recvctl(wlc, rxh, p);
  6796. return;
  6797. toss:
  6798. brcmu_pkt_buf_free_skb(p);
  6799. }
  6800. /* Process received frames */
  6801. /*
  6802. * Return true if more frames need to be processed. false otherwise.
  6803. * Param 'bound' indicates max. # frames to process before break out.
  6804. */
  6805. static bool
  6806. brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
  6807. {
  6808. struct sk_buff *p;
  6809. struct sk_buff *next = NULL;
  6810. struct sk_buff_head recv_frames;
  6811. uint n = 0;
  6812. uint bound_limit = bound ? RXBND : -1;
  6813. BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
  6814. skb_queue_head_init(&recv_frames);
  6815. /* gather received frames */
  6816. while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
  6817. /* !give others some time to run! */
  6818. if (++n >= bound_limit)
  6819. break;
  6820. }
  6821. /* post more rbufs */
  6822. dma_rxfill(wlc_hw->di[fifo]);
  6823. /* process each frame */
  6824. skb_queue_walk_safe(&recv_frames, p, next) {
  6825. struct d11rxhdr_le *rxh_le;
  6826. struct d11rxhdr *rxh;
  6827. skb_unlink(p, &recv_frames);
  6828. rxh_le = (struct d11rxhdr_le *)p->data;
  6829. rxh = (struct d11rxhdr *)p->data;
  6830. /* fixup rx header endianness */
  6831. rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
  6832. rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
  6833. rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
  6834. rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
  6835. rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
  6836. rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
  6837. rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
  6838. rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
  6839. rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
  6840. rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
  6841. rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
  6842. brcms_c_recv(wlc_hw->wlc, p);
  6843. }
  6844. return n >= bound_limit;
  6845. }
  6846. /* second-level interrupt processing
  6847. * Return true if another dpc needs to be re-scheduled. false otherwise.
  6848. * Param 'bounded' indicates if applicable loops should be bounded.
  6849. */
  6850. bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
  6851. {
  6852. u32 macintstatus;
  6853. struct brcms_hardware *wlc_hw = wlc->hw;
  6854. struct d11regs __iomem *regs = wlc_hw->regs;
  6855. struct wiphy *wiphy = wlc->wiphy;
  6856. if (brcms_deviceremoved(wlc)) {
  6857. wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
  6858. __func__);
  6859. brcms_down(wlc->wl);
  6860. return false;
  6861. }
  6862. /* grab and clear the saved software intstatus bits */
  6863. macintstatus = wlc->macintstatus;
  6864. wlc->macintstatus = 0;
  6865. BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
  6866. wlc_hw->unit, macintstatus);
  6867. WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
  6868. /* tx status */
  6869. if (macintstatus & MI_TFS) {
  6870. bool fatal;
  6871. if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
  6872. wlc->macintstatus |= MI_TFS;
  6873. if (fatal) {
  6874. wiphy_err(wiphy, "MI_TFS: fatal\n");
  6875. goto fatal;
  6876. }
  6877. }
  6878. if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
  6879. brcms_c_tbtt(wlc);
  6880. /* ATIM window end */
  6881. if (macintstatus & MI_ATIMWINEND) {
  6882. BCMMSG(wlc->wiphy, "end of ATIM window\n");
  6883. OR_REG(&regs->maccommand, wlc->qvalid);
  6884. wlc->qvalid = 0;
  6885. }
  6886. /*
  6887. * received data or control frame, MI_DMAINT is
  6888. * indication of RX_FIFO interrupt
  6889. */
  6890. if (macintstatus & MI_DMAINT)
  6891. if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
  6892. wlc->macintstatus |= MI_DMAINT;
  6893. /* noise sample collected */
  6894. if (macintstatus & MI_BG_NOISE)
  6895. wlc_phy_noise_sample_intr(wlc_hw->band->pi);
  6896. if (macintstatus & MI_GP0) {
  6897. wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
  6898. "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
  6899. printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
  6900. __func__, wlc_hw->sih->chip,
  6901. wlc_hw->sih->chiprev);
  6902. brcms_fatal_error(wlc_hw->wlc->wl);
  6903. }
  6904. /* gptimer timeout */
  6905. if (macintstatus & MI_TO)
  6906. W_REG(&regs->gptimer, 0);
  6907. if (macintstatus & MI_RFDISABLE) {
  6908. BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
  6909. " RF Disable Input\n", wlc_hw->unit);
  6910. brcms_rfkill_set_hw_state(wlc->wl);
  6911. }
  6912. /* send any enq'd tx packets. Just makes sure to jump start tx */
  6913. if (!pktq_empty(&wlc->pkt_queue->q))
  6914. brcms_c_send_q(wlc);
  6915. /* it isn't done and needs to be resched if macintstatus is non-zero */
  6916. return wlc->macintstatus != 0;
  6917. fatal:
  6918. brcms_fatal_error(wlc_hw->wlc->wl);
  6919. return wlc->macintstatus != 0;
  6920. }
  6921. void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
  6922. {
  6923. struct d11regs __iomem *regs;
  6924. u16 chanspec;
  6925. BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
  6926. regs = wlc->regs;
  6927. /*
  6928. * This will happen if a big-hammer was executed. In
  6929. * that case, we want to go back to the channel that
  6930. * we were on and not new channel
  6931. */
  6932. if (wlc->pub->associated)
  6933. chanspec = wlc->home_chanspec;
  6934. else
  6935. chanspec = brcms_c_init_chanspec(wlc);
  6936. brcms_b_init(wlc->hw, chanspec);
  6937. /* update beacon listen interval */
  6938. brcms_c_bcn_li_upd(wlc);
  6939. /* write ethernet address to core */
  6940. brcms_c_set_mac(wlc->bsscfg);
  6941. brcms_c_set_bssid(wlc->bsscfg);
  6942. /* Update tsf_cfprep if associated and up */
  6943. if (wlc->pub->associated && wlc->bsscfg->up) {
  6944. u32 bi;
  6945. /* get beacon period and convert to uS */
  6946. bi = wlc->bsscfg->current_bss->beacon_period << 10;
  6947. /*
  6948. * update since init path would reset
  6949. * to default value
  6950. */
  6951. W_REG(&regs->tsf_cfprep,
  6952. (bi << CFPREP_CBI_SHIFT));
  6953. /* Update maccontrol PM related bits */
  6954. brcms_c_set_ps_ctrl(wlc);
  6955. }
  6956. brcms_c_bandinit_ordered(wlc, chanspec);
  6957. /* init probe response timeout */
  6958. brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
  6959. /* init max burst txop (framebursting) */
  6960. brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
  6961. (wlc->
  6962. _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
  6963. /* initialize maximum allowed duty cycle */
  6964. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
  6965. brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
  6966. /*
  6967. * Update some shared memory locations related to
  6968. * max AMPDU size allowed to received
  6969. */
  6970. brcms_c_ampdu_shm_upd(wlc->ampdu);
  6971. /* band-specific inits */
  6972. brcms_c_bsinit(wlc);
  6973. /* Enable EDCF mode (while the MAC is suspended) */
  6974. OR_REG(&regs->ifs_ctl, IFS_USEEDCF);
  6975. brcms_c_edcf_setparams(wlc, false);
  6976. /* Init precedence maps for empty FIFOs */
  6977. brcms_c_tx_prec_map_init(wlc);
  6978. /* read the ucode version if we have not yet done so */
  6979. if (wlc->ucode_rev == 0) {
  6980. wlc->ucode_rev =
  6981. brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
  6982. wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
  6983. }
  6984. /* ..now really unleash hell (allow the MAC out of suspend) */
  6985. brcms_c_enable_mac(wlc);
  6986. /* suspend the tx fifos and mute the phy for preism cac time */
  6987. if (mute_tx)
  6988. brcms_b_mute(wlc->hw, true);
  6989. /* clear tx flow control */
  6990. brcms_c_txflowcontrol_reset(wlc);
  6991. /* enable the RF Disable Delay timer */
  6992. W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
  6993. /*
  6994. * Initialize WME parameters; if they haven't been set by some other
  6995. * mechanism (IOVar, etc) then read them from the hardware.
  6996. */
  6997. if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
  6998. /* Uninitialized; read from HW */
  6999. int ac;
  7000. for (ac = 0; ac < AC_COUNT; ac++)
  7001. wlc->wme_retries[ac] =
  7002. brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
  7003. }
  7004. }
  7005. /*
  7006. * The common driver entry routine. Error codes should be unique
  7007. */
  7008. struct brcms_c_info *
  7009. brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
  7010. bool piomode, void __iomem *regsva, struct pci_dev *btparam,
  7011. uint *perr)
  7012. {
  7013. struct brcms_c_info *wlc;
  7014. uint err = 0;
  7015. uint i, j;
  7016. struct brcms_pub *pub;
  7017. /* allocate struct brcms_c_info state and its substructures */
  7018. wlc = (struct brcms_c_info *) brcms_c_attach_malloc(unit, &err, device);
  7019. if (wlc == NULL)
  7020. goto fail;
  7021. wlc->wiphy = wl->wiphy;
  7022. pub = wlc->pub;
  7023. #if defined(BCMDBG)
  7024. wlc_info_dbg = wlc;
  7025. #endif
  7026. wlc->band = wlc->bandstate[0];
  7027. wlc->core = wlc->corestate;
  7028. wlc->wl = wl;
  7029. pub->unit = unit;
  7030. pub->_piomode = piomode;
  7031. wlc->bandinit_pending = false;
  7032. /* populate struct brcms_c_info with default values */
  7033. brcms_c_info_init(wlc, unit);
  7034. /* update sta/ap related parameters */
  7035. brcms_c_ap_upd(wlc);
  7036. /*
  7037. * low level attach steps(all hw accesses go
  7038. * inside, no more in rest of the attach)
  7039. */
  7040. err = brcms_b_attach(wlc, vendor, device, unit, piomode, regsva,
  7041. btparam);
  7042. if (err)
  7043. goto fail;
  7044. brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
  7045. pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
  7046. /* disable allowed duty cycle */
  7047. wlc->tx_duty_cycle_ofdm = 0;
  7048. wlc->tx_duty_cycle_cck = 0;
  7049. brcms_c_stf_phy_chain_calc(wlc);
  7050. /* txchain 1: txant 0, txchain 2: txant 1 */
  7051. if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
  7052. wlc->stf->txant = wlc->stf->hw_txchain - 1;
  7053. /* push to BMAC driver */
  7054. wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
  7055. wlc->stf->hw_rxchain);
  7056. /* pull up some info resulting from the low attach */
  7057. for (i = 0; i < NFIFO; i++)
  7058. wlc->core->txavail[i] = wlc->hw->txavail[i];
  7059. memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  7060. memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
  7061. for (j = 0; j < wlc->pub->_nbands; j++) {
  7062. wlc->band = wlc->bandstate[j];
  7063. if (!brcms_c_attach_stf_ant_init(wlc)) {
  7064. err = 24;
  7065. goto fail;
  7066. }
  7067. /* default contention windows size limits */
  7068. wlc->band->CWmin = APHY_CWMIN;
  7069. wlc->band->CWmax = PHY_CWMAX;
  7070. /* init gmode value */
  7071. if (wlc->band->bandtype == BRCM_BAND_2G) {
  7072. wlc->band->gmode = GMODE_AUTO;
  7073. brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
  7074. wlc->band->gmode);
  7075. }
  7076. /* init _n_enab supported mode */
  7077. if (BRCMS_PHY_11N_CAP(wlc->band)) {
  7078. pub->_n_enab = SUPPORT_11N;
  7079. brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
  7080. ((pub->_n_enab ==
  7081. SUPPORT_11N) ? WL_11N_2x2 :
  7082. WL_11N_3x3));
  7083. }
  7084. /* init per-band default rateset, depend on band->gmode */
  7085. brcms_default_rateset(wlc, &wlc->band->defrateset);
  7086. /* fill in hw_rateset */
  7087. brcms_c_rateset_filter(&wlc->band->defrateset,
  7088. &wlc->band->hw_rateset, false,
  7089. BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
  7090. (bool) (wlc->pub->_n_enab & SUPPORT_11N));
  7091. }
  7092. /*
  7093. * update antenna config due to
  7094. * wlc->stf->txant/txchain/ant_rx_ovr change
  7095. */
  7096. brcms_c_stf_phy_txant_upd(wlc);
  7097. /* attach each modules */
  7098. err = brcms_c_attach_module(wlc);
  7099. if (err != 0)
  7100. goto fail;
  7101. if (!brcms_c_timers_init(wlc, unit)) {
  7102. wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
  7103. __func__);
  7104. err = 32;
  7105. goto fail;
  7106. }
  7107. /* depend on rateset, gmode */
  7108. wlc->cmi = brcms_c_channel_mgr_attach(wlc);
  7109. if (!wlc->cmi) {
  7110. wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
  7111. "\n", unit, __func__);
  7112. err = 33;
  7113. goto fail;
  7114. }
  7115. /* init default when all parameters are ready, i.e. ->rateset */
  7116. brcms_c_bss_default_init(wlc);
  7117. /*
  7118. * Complete the wlc default state initializations..
  7119. */
  7120. /* allocate our initial queue */
  7121. wlc->pkt_queue = brcms_c_txq_alloc(wlc);
  7122. if (wlc->pkt_queue == NULL) {
  7123. wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
  7124. unit, __func__);
  7125. err = 100;
  7126. goto fail;
  7127. }
  7128. wlc->bsscfg->wlc = wlc;
  7129. wlc->mimoft = FT_HT;
  7130. wlc->mimo_40txbw = AUTO;
  7131. wlc->ofdm_40txbw = AUTO;
  7132. wlc->cck_40txbw = AUTO;
  7133. brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
  7134. /* Set default values of SGI */
  7135. if (BRCMS_SGI_CAP_PHY(wlc)) {
  7136. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  7137. BRCMS_N_SGI_40));
  7138. } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
  7139. brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
  7140. BRCMS_N_SGI_40));
  7141. } else {
  7142. brcms_c_ht_update_sgi_rx(wlc, 0);
  7143. }
  7144. brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
  7145. if (perr)
  7146. *perr = 0;
  7147. return wlc;
  7148. fail:
  7149. wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
  7150. unit, __func__, err);
  7151. if (wlc)
  7152. brcms_c_detach(wlc);
  7153. if (perr)
  7154. *perr = err;
  7155. return NULL;
  7156. }