scc_pata.c 22 KB

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  1. /*
  2. * Support for IDE interfaces on Celleb platform
  3. *
  4. * (C) Copyright 2006 TOSHIBA CORPORATION
  5. *
  6. * This code is based on drivers/ide/pci/siimage.c:
  7. * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
  8. * Copyright (C) 2003 Red Hat <alan@redhat.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License along
  21. * with this program; if not, write to the Free Software Foundation, Inc.,
  22. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23. */
  24. #include <linux/types.h>
  25. #include <linux/module.h>
  26. #include <linux/pci.h>
  27. #include <linux/delay.h>
  28. #include <linux/hdreg.h>
  29. #include <linux/ide.h>
  30. #include <linux/init.h>
  31. #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
  32. #define SCC_PATA_NAME "scc IDE"
  33. #define TDVHSEL_MASTER 0x00000001
  34. #define TDVHSEL_SLAVE 0x00000004
  35. #define MODE_JCUSFEN 0x00000080
  36. #define CCKCTRL_ATARESET 0x00040000
  37. #define CCKCTRL_BUFCNT 0x00020000
  38. #define CCKCTRL_CRST 0x00010000
  39. #define CCKCTRL_OCLKEN 0x00000100
  40. #define CCKCTRL_ATACLKOEN 0x00000002
  41. #define CCKCTRL_LCLKEN 0x00000001
  42. #define QCHCD_IOS_SS 0x00000001
  43. #define QCHSD_STPDIAG 0x00020000
  44. #define INTMASK_MSK 0xD1000012
  45. #define INTSTS_SERROR 0x80000000
  46. #define INTSTS_PRERR 0x40000000
  47. #define INTSTS_RERR 0x10000000
  48. #define INTSTS_ICERR 0x01000000
  49. #define INTSTS_BMSINT 0x00000010
  50. #define INTSTS_BMHE 0x00000008
  51. #define INTSTS_IOIRQS 0x00000004
  52. #define INTSTS_INTRQ 0x00000002
  53. #define INTSTS_ACTEINT 0x00000001
  54. #define ECMODE_VALUE 0x01
  55. static struct scc_ports {
  56. unsigned long ctl, dma;
  57. unsigned char hwif_id; /* for removing hwif from system */
  58. } scc_ports[MAX_HWIFS];
  59. /* PIO transfer mode table */
  60. /* JCHST */
  61. static unsigned long JCHSTtbl[2][7] = {
  62. {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
  63. {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
  64. };
  65. /* JCHHT */
  66. static unsigned long JCHHTtbl[2][7] = {
  67. {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
  68. {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
  69. };
  70. /* JCHCT */
  71. static unsigned long JCHCTtbl[2][7] = {
  72. {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
  73. {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
  74. };
  75. /* DMA transfer mode table */
  76. /* JCHDCTM/JCHDCTS */
  77. static unsigned long JCHDCTxtbl[2][7] = {
  78. {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
  79. {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
  80. };
  81. /* JCSTWTM/JCSTWTS */
  82. static unsigned long JCSTWTxtbl[2][7] = {
  83. {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
  84. {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
  85. };
  86. /* JCTSS */
  87. static unsigned long JCTSStbl[2][7] = {
  88. {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
  89. {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
  90. };
  91. /* JCENVT */
  92. static unsigned long JCENVTtbl[2][7] = {
  93. {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
  94. {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
  95. };
  96. /* JCACTSELS/JCACTSELM */
  97. static unsigned long JCACTSELtbl[2][7] = {
  98. {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
  99. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
  100. };
  101. static u8 scc_ide_inb(unsigned long port)
  102. {
  103. u32 data = in_be32((void*)port);
  104. return (u8)data;
  105. }
  106. static u16 scc_ide_inw(unsigned long port)
  107. {
  108. u32 data = in_be32((void*)port);
  109. return (u16)data;
  110. }
  111. static void scc_ide_insw(unsigned long port, void *addr, u32 count)
  112. {
  113. u16 *ptr = (u16 *)addr;
  114. while (count--) {
  115. *ptr++ = le16_to_cpu(in_be32((void*)port));
  116. }
  117. }
  118. static void scc_ide_insl(unsigned long port, void *addr, u32 count)
  119. {
  120. u16 *ptr = (u16 *)addr;
  121. while (count--) {
  122. *ptr++ = le16_to_cpu(in_be32((void*)port));
  123. *ptr++ = le16_to_cpu(in_be32((void*)port));
  124. }
  125. }
  126. static void scc_ide_outb(u8 addr, unsigned long port)
  127. {
  128. out_be32((void*)port, addr);
  129. }
  130. static void scc_ide_outw(u16 addr, unsigned long port)
  131. {
  132. out_be32((void*)port, addr);
  133. }
  134. static void
  135. scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
  136. {
  137. ide_hwif_t *hwif = HWIF(drive);
  138. out_be32((void*)port, addr);
  139. eieio();
  140. in_be32((void*)(hwif->dma_base + 0x01c));
  141. eieio();
  142. }
  143. static void
  144. scc_ide_outsw(unsigned long port, void *addr, u32 count)
  145. {
  146. u16 *ptr = (u16 *)addr;
  147. while (count--) {
  148. out_be32((void*)port, cpu_to_le16(*ptr++));
  149. }
  150. }
  151. static void
  152. scc_ide_outsl(unsigned long port, void *addr, u32 count)
  153. {
  154. u16 *ptr = (u16 *)addr;
  155. while (count--) {
  156. out_be32((void*)port, cpu_to_le16(*ptr++));
  157. out_be32((void*)port, cpu_to_le16(*ptr++));
  158. }
  159. }
  160. /**
  161. * scc_tune_pio - tune a drive PIO mode
  162. * @drive: drive to tune
  163. * @mode_wanted: the target operating mode
  164. *
  165. * Load the timing settings for this device mode into the
  166. * controller.
  167. */
  168. static void scc_tune_pio(ide_drive_t *drive, const u8 pio)
  169. {
  170. ide_hwif_t *hwif = HWIF(drive);
  171. struct scc_ports *ports = ide_get_hwifdata(hwif);
  172. unsigned long ctl_base = ports->ctl;
  173. unsigned long cckctrl_port = ctl_base + 0xff0;
  174. unsigned long piosht_port = ctl_base + 0x000;
  175. unsigned long pioct_port = ctl_base + 0x004;
  176. unsigned long reg;
  177. int offset;
  178. reg = in_be32((void __iomem *)cckctrl_port);
  179. if (reg & CCKCTRL_ATACLKOEN) {
  180. offset = 1; /* 133MHz */
  181. } else {
  182. offset = 0; /* 100MHz */
  183. }
  184. reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
  185. out_be32((void __iomem *)piosht_port, reg);
  186. reg = JCHCTtbl[offset][pio];
  187. out_be32((void __iomem *)pioct_port, reg);
  188. }
  189. static void scc_tuneproc(ide_drive_t *drive, u8 pio)
  190. {
  191. pio = ide_get_best_pio_mode(drive, pio, 4);
  192. scc_tune_pio(drive, pio);
  193. ide_config_drive_speed(drive, XFER_PIO_0 + pio);
  194. }
  195. /**
  196. * scc_tune_chipset - tune a drive DMA mode
  197. * @drive: Drive to set up
  198. * @xferspeed: speed we want to achieve
  199. *
  200. * Load the timing settings for this device mode into the
  201. * controller.
  202. */
  203. static int scc_tune_chipset(ide_drive_t *drive, byte xferspeed)
  204. {
  205. ide_hwif_t *hwif = HWIF(drive);
  206. u8 speed = ide_rate_filter(drive, xferspeed);
  207. struct scc_ports *ports = ide_get_hwifdata(hwif);
  208. unsigned long ctl_base = ports->ctl;
  209. unsigned long cckctrl_port = ctl_base + 0xff0;
  210. unsigned long mdmact_port = ctl_base + 0x008;
  211. unsigned long mcrcst_port = ctl_base + 0x00c;
  212. unsigned long sdmact_port = ctl_base + 0x010;
  213. unsigned long scrcst_port = ctl_base + 0x014;
  214. unsigned long udenvt_port = ctl_base + 0x018;
  215. unsigned long tdvhsel_port = ctl_base + 0x020;
  216. int is_slave = (&hwif->drives[1] == drive);
  217. int offset, idx;
  218. unsigned long reg;
  219. unsigned long jcactsel;
  220. reg = in_be32((void __iomem *)cckctrl_port);
  221. if (reg & CCKCTRL_ATACLKOEN) {
  222. offset = 1; /* 133MHz */
  223. } else {
  224. offset = 0; /* 100MHz */
  225. }
  226. switch (speed) {
  227. case XFER_UDMA_6:
  228. case XFER_UDMA_5:
  229. case XFER_UDMA_4:
  230. case XFER_UDMA_3:
  231. case XFER_UDMA_2:
  232. case XFER_UDMA_1:
  233. case XFER_UDMA_0:
  234. idx = speed - XFER_UDMA_0;
  235. break;
  236. case XFER_PIO_4:
  237. case XFER_PIO_3:
  238. case XFER_PIO_2:
  239. case XFER_PIO_1:
  240. case XFER_PIO_0:
  241. scc_tune_pio(drive, speed - XFER_PIO_0);
  242. return ide_config_drive_speed(drive, speed);
  243. default:
  244. return 1;
  245. }
  246. jcactsel = JCACTSELtbl[offset][idx];
  247. if (is_slave) {
  248. out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
  249. out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
  250. jcactsel = jcactsel << 2;
  251. out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
  252. } else {
  253. out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
  254. out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
  255. out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
  256. }
  257. reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
  258. out_be32((void __iomem *)udenvt_port, reg);
  259. return ide_config_drive_speed(drive, speed);
  260. }
  261. /**
  262. * scc_configure_drive_for_dma - set up for DMA transfers
  263. * @drive: drive we are going to set up
  264. *
  265. * Set up the drive for DMA, tune the controller and drive as
  266. * required.
  267. * If the drive isn't suitable for DMA or we hit other problems
  268. * then we will drop down to PIO and set up PIO appropriately.
  269. * (return -1)
  270. */
  271. static int scc_config_drive_for_dma(ide_drive_t *drive)
  272. {
  273. if (ide_tune_dma(drive))
  274. return 0;
  275. if (ide_use_fast_pio(drive))
  276. scc_tuneproc(drive, 255);
  277. return -1;
  278. }
  279. /**
  280. * scc_ide_dma_setup - begin a DMA phase
  281. * @drive: target device
  282. *
  283. * Build an IDE DMA PRD (IDE speak for scatter gather table)
  284. * and then set up the DMA transfer registers.
  285. *
  286. * Returns 0 on success. If a PIO fallback is required then 1
  287. * is returned.
  288. */
  289. static int scc_dma_setup(ide_drive_t *drive)
  290. {
  291. ide_hwif_t *hwif = drive->hwif;
  292. struct request *rq = HWGROUP(drive)->rq;
  293. unsigned int reading;
  294. u8 dma_stat;
  295. if (rq_data_dir(rq))
  296. reading = 0;
  297. else
  298. reading = 1 << 3;
  299. /* fall back to pio! */
  300. if (!ide_build_dmatable(drive, rq)) {
  301. ide_map_sg(drive, rq);
  302. return 1;
  303. }
  304. /* PRD table */
  305. out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
  306. /* specify r/w */
  307. out_be32((void __iomem *)hwif->dma_command, reading);
  308. /* read dma_status for INTR & ERROR flags */
  309. dma_stat = in_be32((void __iomem *)hwif->dma_status);
  310. /* clear INTR & ERROR flags */
  311. out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
  312. drive->waiting_for_dma = 1;
  313. return 0;
  314. }
  315. /**
  316. * scc_ide_dma_end - Stop DMA
  317. * @drive: IDE drive
  318. *
  319. * Check and clear INT Status register.
  320. * Then call __ide_dma_end().
  321. */
  322. static int scc_ide_dma_end(ide_drive_t * drive)
  323. {
  324. ide_hwif_t *hwif = HWIF(drive);
  325. unsigned long intsts_port = hwif->dma_base + 0x014;
  326. u32 reg;
  327. int dma_stat, data_loss = 0;
  328. static int retry = 0;
  329. /* errata A308 workaround: Step5 (check data loss) */
  330. /* We don't check non ide_disk because it is limited to UDMA4 */
  331. if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
  332. drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
  333. reg = in_be32((void __iomem *)intsts_port);
  334. if (!(reg & INTSTS_ACTEINT)) {
  335. printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
  336. drive->name);
  337. data_loss = 1;
  338. if (retry++) {
  339. struct request *rq = HWGROUP(drive)->rq;
  340. int unit;
  341. /* ERROR_RESET and drive->crc_count are needed
  342. * to reduce DMA transfer mode in retry process.
  343. */
  344. if (rq)
  345. rq->errors |= ERROR_RESET;
  346. for (unit = 0; unit < MAX_DRIVES; unit++) {
  347. ide_drive_t *drive = &hwif->drives[unit];
  348. drive->crc_count++;
  349. }
  350. }
  351. }
  352. }
  353. while (1) {
  354. reg = in_be32((void __iomem *)intsts_port);
  355. if (reg & INTSTS_SERROR) {
  356. printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
  357. out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
  358. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  359. continue;
  360. }
  361. if (reg & INTSTS_PRERR) {
  362. u32 maea0, maec0;
  363. unsigned long ctl_base = hwif->config_data;
  364. maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
  365. maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
  366. printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
  367. out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
  368. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  369. continue;
  370. }
  371. if (reg & INTSTS_RERR) {
  372. printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
  373. out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
  374. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  375. continue;
  376. }
  377. if (reg & INTSTS_ICERR) {
  378. out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
  379. printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
  380. out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
  381. continue;
  382. }
  383. if (reg & INTSTS_BMSINT) {
  384. printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
  385. out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
  386. ide_do_reset(drive);
  387. continue;
  388. }
  389. if (reg & INTSTS_BMHE) {
  390. out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
  391. continue;
  392. }
  393. if (reg & INTSTS_ACTEINT) {
  394. out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
  395. continue;
  396. }
  397. if (reg & INTSTS_IOIRQS) {
  398. out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
  399. continue;
  400. }
  401. break;
  402. }
  403. dma_stat = __ide_dma_end(drive);
  404. if (data_loss)
  405. dma_stat |= 2; /* emulate DMA error (to retry command) */
  406. return dma_stat;
  407. }
  408. /* returns 1 if dma irq issued, 0 otherwise */
  409. static int scc_dma_test_irq(ide_drive_t *drive)
  410. {
  411. ide_hwif_t *hwif = HWIF(drive);
  412. u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
  413. /* SCC errata A252,A308 workaround: Step4 */
  414. if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
  415. (int_stat & INTSTS_INTRQ))
  416. return 1;
  417. /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
  418. if (int_stat & INTSTS_IOIRQS)
  419. return 1;
  420. if (!drive->waiting_for_dma)
  421. printk(KERN_WARNING "%s: (%s) called while not waiting\n",
  422. drive->name, __FUNCTION__);
  423. return 0;
  424. }
  425. static u8 scc_udma_filter(ide_drive_t *drive)
  426. {
  427. ide_hwif_t *hwif = drive->hwif;
  428. u8 mask = hwif->ultra_mask;
  429. /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
  430. if ((drive->media != ide_disk) && (mask & 0xE0)) {
  431. printk(KERN_INFO "%s: limit %s to UDMA4\n",
  432. SCC_PATA_NAME, drive->name);
  433. mask = 0x1F;
  434. }
  435. return mask;
  436. }
  437. /**
  438. * setup_mmio_scc - map CTRL/BMID region
  439. * @dev: PCI device we are configuring
  440. * @name: device name
  441. *
  442. */
  443. static int setup_mmio_scc (struct pci_dev *dev, const char *name)
  444. {
  445. unsigned long ctl_base = pci_resource_start(dev, 0);
  446. unsigned long dma_base = pci_resource_start(dev, 1);
  447. unsigned long ctl_size = pci_resource_len(dev, 0);
  448. unsigned long dma_size = pci_resource_len(dev, 1);
  449. void __iomem *ctl_addr;
  450. void __iomem *dma_addr;
  451. int i;
  452. for (i = 0; i < MAX_HWIFS; i++) {
  453. if (scc_ports[i].ctl == 0)
  454. break;
  455. }
  456. if (i >= MAX_HWIFS)
  457. return -ENOMEM;
  458. if (!request_mem_region(ctl_base, ctl_size, name)) {
  459. printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
  460. goto fail_0;
  461. }
  462. if (!request_mem_region(dma_base, dma_size, name)) {
  463. printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
  464. goto fail_1;
  465. }
  466. if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
  467. goto fail_2;
  468. if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
  469. goto fail_3;
  470. pci_set_master(dev);
  471. scc_ports[i].ctl = (unsigned long)ctl_addr;
  472. scc_ports[i].dma = (unsigned long)dma_addr;
  473. pci_set_drvdata(dev, (void *) &scc_ports[i]);
  474. return 1;
  475. fail_3:
  476. iounmap(ctl_addr);
  477. fail_2:
  478. release_mem_region(dma_base, dma_size);
  479. fail_1:
  480. release_mem_region(ctl_base, ctl_size);
  481. fail_0:
  482. return -ENOMEM;
  483. }
  484. /**
  485. * init_setup_scc - set up an SCC PATA Controller
  486. * @dev: PCI device
  487. * @d: IDE PCI device
  488. *
  489. * Perform the initial set up for this device.
  490. */
  491. static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
  492. {
  493. unsigned long ctl_base;
  494. unsigned long dma_base;
  495. unsigned long cckctrl_port;
  496. unsigned long intmask_port;
  497. unsigned long mode_port;
  498. unsigned long ecmode_port;
  499. unsigned long dma_status_port;
  500. u32 reg = 0;
  501. struct scc_ports *ports;
  502. int rc;
  503. rc = setup_mmio_scc(dev, d->name);
  504. if (rc < 0) {
  505. return rc;
  506. }
  507. ports = pci_get_drvdata(dev);
  508. ctl_base = ports->ctl;
  509. dma_base = ports->dma;
  510. cckctrl_port = ctl_base + 0xff0;
  511. intmask_port = dma_base + 0x010;
  512. mode_port = ctl_base + 0x024;
  513. ecmode_port = ctl_base + 0xf00;
  514. dma_status_port = dma_base + 0x004;
  515. /* controller initialization */
  516. reg = 0;
  517. out_be32((void*)cckctrl_port, reg);
  518. reg |= CCKCTRL_ATACLKOEN;
  519. out_be32((void*)cckctrl_port, reg);
  520. reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
  521. out_be32((void*)cckctrl_port, reg);
  522. reg |= CCKCTRL_CRST;
  523. out_be32((void*)cckctrl_port, reg);
  524. for (;;) {
  525. reg = in_be32((void*)cckctrl_port);
  526. if (reg & CCKCTRL_CRST)
  527. break;
  528. udelay(5000);
  529. }
  530. reg |= CCKCTRL_ATARESET;
  531. out_be32((void*)cckctrl_port, reg);
  532. out_be32((void*)ecmode_port, ECMODE_VALUE);
  533. out_be32((void*)mode_port, MODE_JCUSFEN);
  534. out_be32((void*)intmask_port, INTMASK_MSK);
  535. return ide_setup_pci_device(dev, d);
  536. }
  537. /**
  538. * init_mmio_iops_scc - set up the iops for MMIO
  539. * @hwif: interface to set up
  540. *
  541. */
  542. static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
  543. {
  544. struct pci_dev *dev = hwif->pci_dev;
  545. struct scc_ports *ports = pci_get_drvdata(dev);
  546. unsigned long dma_base = ports->dma;
  547. ide_set_hwifdata(hwif, ports);
  548. hwif->INB = scc_ide_inb;
  549. hwif->INW = scc_ide_inw;
  550. hwif->INSW = scc_ide_insw;
  551. hwif->INSL = scc_ide_insl;
  552. hwif->OUTB = scc_ide_outb;
  553. hwif->OUTBSYNC = scc_ide_outbsync;
  554. hwif->OUTW = scc_ide_outw;
  555. hwif->OUTSW = scc_ide_outsw;
  556. hwif->OUTSL = scc_ide_outsl;
  557. hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
  558. hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
  559. hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
  560. hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
  561. hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
  562. hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
  563. hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
  564. hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
  565. hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
  566. hwif->irq = hwif->pci_dev->irq;
  567. hwif->dma_base = dma_base;
  568. hwif->config_data = ports->ctl;
  569. hwif->mmio = 1;
  570. }
  571. /**
  572. * init_iops_scc - set up iops
  573. * @hwif: interface to set up
  574. *
  575. * Do the basic setup for the SCC hardware interface
  576. * and then do the MMIO setup.
  577. */
  578. static void __devinit init_iops_scc(ide_hwif_t *hwif)
  579. {
  580. struct pci_dev *dev = hwif->pci_dev;
  581. hwif->hwif_data = NULL;
  582. if (pci_get_drvdata(dev) == NULL)
  583. return;
  584. init_mmio_iops_scc(hwif);
  585. }
  586. /**
  587. * init_hwif_scc - set up hwif
  588. * @hwif: interface to set up
  589. *
  590. * We do the basic set up of the interface structure. The SCC
  591. * requires several custom handlers so we override the default
  592. * ide DMA handlers appropriately.
  593. */
  594. static void __devinit init_hwif_scc(ide_hwif_t *hwif)
  595. {
  596. struct scc_ports *ports = ide_get_hwifdata(hwif);
  597. ports->hwif_id = hwif->index;
  598. hwif->dma_command = hwif->dma_base;
  599. hwif->dma_status = hwif->dma_base + 0x04;
  600. hwif->dma_prdtable = hwif->dma_base + 0x08;
  601. /* PTERADD */
  602. out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
  603. hwif->dma_setup = scc_dma_setup;
  604. hwif->ide_dma_end = scc_ide_dma_end;
  605. hwif->speedproc = scc_tune_chipset;
  606. hwif->tuneproc = scc_tuneproc;
  607. hwif->ide_dma_check = scc_config_drive_for_dma;
  608. hwif->ide_dma_test_irq = scc_dma_test_irq;
  609. hwif->udma_filter = scc_udma_filter;
  610. hwif->drives[0].autotune = IDE_TUNE_AUTO;
  611. hwif->drives[1].autotune = IDE_TUNE_AUTO;
  612. if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
  613. hwif->ultra_mask = 0x7f; /* 133MHz */
  614. } else {
  615. hwif->ultra_mask = 0x3f; /* 100MHz */
  616. }
  617. hwif->mwdma_mask = 0x00;
  618. hwif->swdma_mask = 0x00;
  619. hwif->atapi_dma = 1;
  620. /* we support 80c cable only. */
  621. hwif->cbl = ATA_CBL_PATA80;
  622. hwif->autodma = 0;
  623. if (!noautodma)
  624. hwif->autodma = 1;
  625. hwif->drives[0].autodma = hwif->autodma;
  626. hwif->drives[1].autodma = hwif->autodma;
  627. }
  628. #define DECLARE_SCC_DEV(name_str) \
  629. { \
  630. .name = name_str, \
  631. .init_setup = init_setup_scc, \
  632. .init_iops = init_iops_scc, \
  633. .init_hwif = init_hwif_scc, \
  634. .autodma = AUTODMA, \
  635. .bootable = ON_BOARD, \
  636. .host_flags = IDE_HFLAG_SINGLE, \
  637. .pio_mask = ATA_PIO4, \
  638. }
  639. static ide_pci_device_t scc_chipsets[] __devinitdata = {
  640. /* 0 */ DECLARE_SCC_DEV("sccIDE"),
  641. };
  642. /**
  643. * scc_init_one - pci layer discovery entry
  644. * @dev: PCI device
  645. * @id: ident table entry
  646. *
  647. * Called by the PCI code when it finds an SCC PATA controller.
  648. * We then use the IDE PCI generic helper to do most of the work.
  649. */
  650. static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  651. {
  652. ide_pci_device_t *d = &scc_chipsets[id->driver_data];
  653. return d->init_setup(dev, d);
  654. }
  655. /**
  656. * scc_remove - pci layer remove entry
  657. * @dev: PCI device
  658. *
  659. * Called by the PCI code when it removes an SCC PATA controller.
  660. */
  661. static void __devexit scc_remove(struct pci_dev *dev)
  662. {
  663. struct scc_ports *ports = pci_get_drvdata(dev);
  664. ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
  665. unsigned long ctl_base = pci_resource_start(dev, 0);
  666. unsigned long dma_base = pci_resource_start(dev, 1);
  667. unsigned long ctl_size = pci_resource_len(dev, 0);
  668. unsigned long dma_size = pci_resource_len(dev, 1);
  669. if (hwif->dmatable_cpu) {
  670. pci_free_consistent(hwif->pci_dev,
  671. PRD_ENTRIES * PRD_BYTES,
  672. hwif->dmatable_cpu,
  673. hwif->dmatable_dma);
  674. hwif->dmatable_cpu = NULL;
  675. }
  676. ide_unregister(hwif->index);
  677. hwif->chipset = ide_unknown;
  678. iounmap((void*)ports->dma);
  679. iounmap((void*)ports->ctl);
  680. release_mem_region(dma_base, dma_size);
  681. release_mem_region(ctl_base, ctl_size);
  682. memset(ports, 0, sizeof(*ports));
  683. }
  684. static struct pci_device_id scc_pci_tbl[] = {
  685. { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  686. { 0, },
  687. };
  688. MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
  689. static struct pci_driver driver = {
  690. .name = "SCC IDE",
  691. .id_table = scc_pci_tbl,
  692. .probe = scc_init_one,
  693. .remove = scc_remove,
  694. };
  695. static int scc_ide_init(void)
  696. {
  697. return ide_pci_register_driver(&driver);
  698. }
  699. module_init(scc_ide_init);
  700. /* -- No exit code?
  701. static void scc_ide_exit(void)
  702. {
  703. ide_pci_unregister_driver(&driver);
  704. }
  705. module_exit(scc_ide_exit);
  706. */
  707. MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
  708. MODULE_LICENSE("GPL");