smsc75xx.c 56 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/bitrev.h>
  29. #include <linux/crc16.h>
  30. #include <linux/crc32.h>
  31. #include <linux/usb/usbnet.h>
  32. #include <linux/slab.h>
  33. #include "smsc75xx.h"
  34. #define SMSC_CHIPNAME "smsc75xx"
  35. #define SMSC_DRIVER_VERSION "1.0.0"
  36. #define HS_USB_PKT_SIZE (512)
  37. #define FS_USB_PKT_SIZE (64)
  38. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  39. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  40. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  41. #define MAX_SINGLE_PACKET_SIZE (9000)
  42. #define LAN75XX_EEPROM_MAGIC (0x7500)
  43. #define EEPROM_MAC_OFFSET (0x01)
  44. #define DEFAULT_TX_CSUM_ENABLE (true)
  45. #define DEFAULT_RX_CSUM_ENABLE (true)
  46. #define DEFAULT_TSO_ENABLE (true)
  47. #define SMSC75XX_INTERNAL_PHY_ID (1)
  48. #define SMSC75XX_TX_OVERHEAD (8)
  49. #define MAX_RX_FIFO_SIZE (20 * 1024)
  50. #define MAX_TX_FIFO_SIZE (12 * 1024)
  51. #define USB_VENDOR_ID_SMSC (0x0424)
  52. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  53. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  54. #define RXW_PADDING 2
  55. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  56. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  57. #define SUSPEND_SUSPEND0 (0x01)
  58. #define SUSPEND_SUSPEND1 (0x02)
  59. #define SUSPEND_SUSPEND2 (0x04)
  60. #define SUSPEND_SUSPEND3 (0x08)
  61. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  62. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  63. struct smsc75xx_priv {
  64. struct usbnet *dev;
  65. u32 rfe_ctl;
  66. u32 wolopts;
  67. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  68. struct mutex dataport_mutex;
  69. spinlock_t rfe_ctl_lock;
  70. struct work_struct set_multicast;
  71. u8 suspend_flags;
  72. };
  73. struct usb_context {
  74. struct usb_ctrlrequest req;
  75. struct usbnet *dev;
  76. };
  77. static bool turbo_mode = true;
  78. module_param(turbo_mode, bool, 0644);
  79. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  80. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  81. u32 *data, int in_pm)
  82. {
  83. u32 buf;
  84. int ret;
  85. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  86. BUG_ON(!dev);
  87. if (!in_pm)
  88. fn = usbnet_read_cmd;
  89. else
  90. fn = usbnet_read_cmd_nopm;
  91. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  92. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  93. 0, index, &buf, 4);
  94. if (unlikely(ret < 0))
  95. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  96. index, ret);
  97. le32_to_cpus(&buf);
  98. *data = buf;
  99. return ret;
  100. }
  101. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  102. u32 data, int in_pm)
  103. {
  104. u32 buf;
  105. int ret;
  106. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  107. BUG_ON(!dev);
  108. if (!in_pm)
  109. fn = usbnet_write_cmd;
  110. else
  111. fn = usbnet_write_cmd_nopm;
  112. buf = data;
  113. cpu_to_le32s(&buf);
  114. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  115. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  116. 0, index, &buf, 4);
  117. if (unlikely(ret < 0))
  118. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  119. index, ret);
  120. return ret;
  121. }
  122. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  123. u32 *data)
  124. {
  125. return __smsc75xx_read_reg(dev, index, data, 1);
  126. }
  127. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  128. u32 data)
  129. {
  130. return __smsc75xx_write_reg(dev, index, data, 1);
  131. }
  132. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  133. u32 *data)
  134. {
  135. return __smsc75xx_read_reg(dev, index, data, 0);
  136. }
  137. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  138. u32 data)
  139. {
  140. return __smsc75xx_write_reg(dev, index, data, 0);
  141. }
  142. /* Loop until the read is completed with timeout
  143. * called with phy_mutex held */
  144. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  145. int in_pm)
  146. {
  147. unsigned long start_time = jiffies;
  148. u32 val;
  149. int ret;
  150. do {
  151. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  152. if (ret < 0) {
  153. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  154. return ret;
  155. }
  156. if (!(val & MII_ACCESS_BUSY))
  157. return 0;
  158. } while (!time_after(jiffies, start_time + HZ));
  159. return -EIO;
  160. }
  161. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  162. int in_pm)
  163. {
  164. struct usbnet *dev = netdev_priv(netdev);
  165. u32 val, addr;
  166. int ret;
  167. mutex_lock(&dev->phy_mutex);
  168. /* confirm MII not busy */
  169. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  170. if (ret < 0) {
  171. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  172. goto done;
  173. }
  174. /* set the address, index & direction (read from PHY) */
  175. phy_id &= dev->mii.phy_id_mask;
  176. idx &= dev->mii.reg_num_mask;
  177. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  178. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  179. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  180. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  181. if (ret < 0) {
  182. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  183. goto done;
  184. }
  185. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  186. if (ret < 0) {
  187. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  188. goto done;
  189. }
  190. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  191. if (ret < 0) {
  192. netdev_warn(dev->net, "Error reading MII_DATA\n");
  193. goto done;
  194. }
  195. ret = (u16)(val & 0xFFFF);
  196. done:
  197. mutex_unlock(&dev->phy_mutex);
  198. return ret;
  199. }
  200. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  201. int idx, int regval, int in_pm)
  202. {
  203. struct usbnet *dev = netdev_priv(netdev);
  204. u32 val, addr;
  205. int ret;
  206. mutex_lock(&dev->phy_mutex);
  207. /* confirm MII not busy */
  208. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  209. if (ret < 0) {
  210. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  211. goto done;
  212. }
  213. val = regval;
  214. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  215. if (ret < 0) {
  216. netdev_warn(dev->net, "Error writing MII_DATA\n");
  217. goto done;
  218. }
  219. /* set the address, index & direction (write to PHY) */
  220. phy_id &= dev->mii.phy_id_mask;
  221. idx &= dev->mii.reg_num_mask;
  222. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  223. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  224. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  225. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  226. if (ret < 0) {
  227. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  228. goto done;
  229. }
  230. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  231. if (ret < 0) {
  232. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  233. goto done;
  234. }
  235. done:
  236. mutex_unlock(&dev->phy_mutex);
  237. }
  238. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  239. int idx)
  240. {
  241. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  242. }
  243. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  244. int idx, int regval)
  245. {
  246. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  247. }
  248. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  249. {
  250. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  251. }
  252. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  253. int regval)
  254. {
  255. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  256. }
  257. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  258. {
  259. unsigned long start_time = jiffies;
  260. u32 val;
  261. int ret;
  262. do {
  263. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  264. if (ret < 0) {
  265. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  266. return ret;
  267. }
  268. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  269. break;
  270. udelay(40);
  271. } while (!time_after(jiffies, start_time + HZ));
  272. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  273. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  274. return -EIO;
  275. }
  276. return 0;
  277. }
  278. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  279. {
  280. unsigned long start_time = jiffies;
  281. u32 val;
  282. int ret;
  283. do {
  284. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  285. if (ret < 0) {
  286. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  287. return ret;
  288. }
  289. if (!(val & E2P_CMD_BUSY))
  290. return 0;
  291. udelay(40);
  292. } while (!time_after(jiffies, start_time + HZ));
  293. netdev_warn(dev->net, "EEPROM is busy\n");
  294. return -EIO;
  295. }
  296. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  297. u8 *data)
  298. {
  299. u32 val;
  300. int i, ret;
  301. BUG_ON(!dev);
  302. BUG_ON(!data);
  303. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  304. if (ret)
  305. return ret;
  306. for (i = 0; i < length; i++) {
  307. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  308. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  309. if (ret < 0) {
  310. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  311. return ret;
  312. }
  313. ret = smsc75xx_wait_eeprom(dev);
  314. if (ret < 0)
  315. return ret;
  316. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  317. if (ret < 0) {
  318. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  319. return ret;
  320. }
  321. data[i] = val & 0xFF;
  322. offset++;
  323. }
  324. return 0;
  325. }
  326. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  327. u8 *data)
  328. {
  329. u32 val;
  330. int i, ret;
  331. BUG_ON(!dev);
  332. BUG_ON(!data);
  333. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  334. if (ret)
  335. return ret;
  336. /* Issue write/erase enable command */
  337. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  338. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  339. if (ret < 0) {
  340. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  341. return ret;
  342. }
  343. ret = smsc75xx_wait_eeprom(dev);
  344. if (ret < 0)
  345. return ret;
  346. for (i = 0; i < length; i++) {
  347. /* Fill data register */
  348. val = data[i];
  349. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  350. if (ret < 0) {
  351. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  352. return ret;
  353. }
  354. /* Send "write" command */
  355. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  356. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  357. if (ret < 0) {
  358. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  359. return ret;
  360. }
  361. ret = smsc75xx_wait_eeprom(dev);
  362. if (ret < 0)
  363. return ret;
  364. offset++;
  365. }
  366. return 0;
  367. }
  368. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  369. {
  370. int i, ret;
  371. for (i = 0; i < 100; i++) {
  372. u32 dp_sel;
  373. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  374. if (ret < 0) {
  375. netdev_warn(dev->net, "Error reading DP_SEL\n");
  376. return ret;
  377. }
  378. if (dp_sel & DP_SEL_DPRDY)
  379. return 0;
  380. udelay(40);
  381. }
  382. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  383. return -EIO;
  384. }
  385. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  386. u32 length, u32 *buf)
  387. {
  388. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  389. u32 dp_sel;
  390. int i, ret;
  391. mutex_lock(&pdata->dataport_mutex);
  392. ret = smsc75xx_dataport_wait_not_busy(dev);
  393. if (ret < 0) {
  394. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  395. goto done;
  396. }
  397. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  398. if (ret < 0) {
  399. netdev_warn(dev->net, "Error reading DP_SEL\n");
  400. goto done;
  401. }
  402. dp_sel &= ~DP_SEL_RSEL;
  403. dp_sel |= ram_select;
  404. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  405. if (ret < 0) {
  406. netdev_warn(dev->net, "Error writing DP_SEL\n");
  407. goto done;
  408. }
  409. for (i = 0; i < length; i++) {
  410. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  411. if (ret < 0) {
  412. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  413. goto done;
  414. }
  415. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  416. if (ret < 0) {
  417. netdev_warn(dev->net, "Error writing DP_DATA\n");
  418. goto done;
  419. }
  420. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  421. if (ret < 0) {
  422. netdev_warn(dev->net, "Error writing DP_CMD\n");
  423. goto done;
  424. }
  425. ret = smsc75xx_dataport_wait_not_busy(dev);
  426. if (ret < 0) {
  427. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  428. goto done;
  429. }
  430. }
  431. done:
  432. mutex_unlock(&pdata->dataport_mutex);
  433. return ret;
  434. }
  435. /* returns hash bit number for given MAC address */
  436. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  437. {
  438. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  439. }
  440. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  441. {
  442. struct smsc75xx_priv *pdata =
  443. container_of(param, struct smsc75xx_priv, set_multicast);
  444. struct usbnet *dev = pdata->dev;
  445. int ret;
  446. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  447. pdata->rfe_ctl);
  448. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  449. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  450. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  451. if (ret < 0)
  452. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  453. }
  454. static void smsc75xx_set_multicast(struct net_device *netdev)
  455. {
  456. struct usbnet *dev = netdev_priv(netdev);
  457. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  458. unsigned long flags;
  459. int i;
  460. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  461. pdata->rfe_ctl &=
  462. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  463. pdata->rfe_ctl |= RFE_CTL_AB;
  464. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  465. pdata->multicast_hash_table[i] = 0;
  466. if (dev->net->flags & IFF_PROMISC) {
  467. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  468. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  469. } else if (dev->net->flags & IFF_ALLMULTI) {
  470. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  471. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  472. } else if (!netdev_mc_empty(dev->net)) {
  473. struct netdev_hw_addr *ha;
  474. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  475. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  476. netdev_for_each_mc_addr(ha, netdev) {
  477. u32 bitnum = smsc75xx_hash(ha->addr);
  478. pdata->multicast_hash_table[bitnum / 32] |=
  479. (1 << (bitnum % 32));
  480. }
  481. } else {
  482. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  483. pdata->rfe_ctl |= RFE_CTL_DPF;
  484. }
  485. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  486. /* defer register writes to a sleepable context */
  487. schedule_work(&pdata->set_multicast);
  488. }
  489. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  490. u16 lcladv, u16 rmtadv)
  491. {
  492. u32 flow = 0, fct_flow = 0;
  493. int ret;
  494. if (duplex == DUPLEX_FULL) {
  495. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  496. if (cap & FLOW_CTRL_TX) {
  497. flow = (FLOW_TX_FCEN | 0xFFFF);
  498. /* set fct_flow thresholds to 20% and 80% */
  499. fct_flow = (8 << 8) | 32;
  500. }
  501. if (cap & FLOW_CTRL_RX)
  502. flow |= FLOW_RX_FCEN;
  503. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  504. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  505. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  506. } else {
  507. netif_dbg(dev, link, dev->net, "half duplex\n");
  508. }
  509. ret = smsc75xx_write_reg(dev, FLOW, flow);
  510. if (ret < 0) {
  511. netdev_warn(dev->net, "Error writing FLOW\n");
  512. return ret;
  513. }
  514. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  515. if (ret < 0) {
  516. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  517. return ret;
  518. }
  519. return 0;
  520. }
  521. static int smsc75xx_link_reset(struct usbnet *dev)
  522. {
  523. struct mii_if_info *mii = &dev->mii;
  524. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  525. u16 lcladv, rmtadv;
  526. int ret;
  527. /* write to clear phy interrupt status */
  528. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  529. PHY_INT_SRC_CLEAR_ALL);
  530. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  531. if (ret < 0) {
  532. netdev_warn(dev->net, "Error writing INT_STS\n");
  533. return ret;
  534. }
  535. mii_check_media(mii, 1, 1);
  536. mii_ethtool_gset(&dev->mii, &ecmd);
  537. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  538. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  539. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  540. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  541. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  542. }
  543. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  544. {
  545. u32 intdata;
  546. if (urb->actual_length != 4) {
  547. netdev_warn(dev->net, "unexpected urb length %d\n",
  548. urb->actual_length);
  549. return;
  550. }
  551. memcpy(&intdata, urb->transfer_buffer, 4);
  552. le32_to_cpus(&intdata);
  553. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  554. if (intdata & INT_ENP_PHY_INT)
  555. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  556. else
  557. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  558. intdata);
  559. }
  560. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  561. {
  562. return MAX_EEPROM_SIZE;
  563. }
  564. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  565. struct ethtool_eeprom *ee, u8 *data)
  566. {
  567. struct usbnet *dev = netdev_priv(netdev);
  568. ee->magic = LAN75XX_EEPROM_MAGIC;
  569. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  570. }
  571. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  572. struct ethtool_eeprom *ee, u8 *data)
  573. {
  574. struct usbnet *dev = netdev_priv(netdev);
  575. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  576. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  577. ee->magic);
  578. return -EINVAL;
  579. }
  580. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  581. }
  582. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  583. struct ethtool_wolinfo *wolinfo)
  584. {
  585. struct usbnet *dev = netdev_priv(net);
  586. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  587. wolinfo->supported = SUPPORTED_WAKE;
  588. wolinfo->wolopts = pdata->wolopts;
  589. }
  590. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  591. struct ethtool_wolinfo *wolinfo)
  592. {
  593. struct usbnet *dev = netdev_priv(net);
  594. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  595. int ret;
  596. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  597. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  598. if (ret < 0)
  599. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  600. return ret;
  601. }
  602. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  603. .get_link = usbnet_get_link,
  604. .nway_reset = usbnet_nway_reset,
  605. .get_drvinfo = usbnet_get_drvinfo,
  606. .get_msglevel = usbnet_get_msglevel,
  607. .set_msglevel = usbnet_set_msglevel,
  608. .get_settings = usbnet_get_settings,
  609. .set_settings = usbnet_set_settings,
  610. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  611. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  612. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  613. .get_wol = smsc75xx_ethtool_get_wol,
  614. .set_wol = smsc75xx_ethtool_set_wol,
  615. };
  616. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  617. {
  618. struct usbnet *dev = netdev_priv(netdev);
  619. if (!netif_running(netdev))
  620. return -EINVAL;
  621. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  622. }
  623. static void smsc75xx_init_mac_address(struct usbnet *dev)
  624. {
  625. /* try reading mac address from EEPROM */
  626. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  627. dev->net->dev_addr) == 0) {
  628. if (is_valid_ether_addr(dev->net->dev_addr)) {
  629. /* eeprom values are valid so use them */
  630. netif_dbg(dev, ifup, dev->net,
  631. "MAC address read from EEPROM\n");
  632. return;
  633. }
  634. }
  635. /* no eeprom, or eeprom values are invalid. generate random MAC */
  636. eth_hw_addr_random(dev->net);
  637. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  638. }
  639. static int smsc75xx_set_mac_address(struct usbnet *dev)
  640. {
  641. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  642. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  643. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  644. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  645. if (ret < 0) {
  646. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  647. return ret;
  648. }
  649. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  650. if (ret < 0) {
  651. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  652. return ret;
  653. }
  654. addr_hi |= ADDR_FILTX_FB_VALID;
  655. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  656. if (ret < 0) {
  657. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  658. return ret;
  659. }
  660. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  661. if (ret < 0)
  662. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  663. return ret;
  664. }
  665. static int smsc75xx_phy_initialize(struct usbnet *dev)
  666. {
  667. int bmcr, ret, timeout = 0;
  668. /* Initialize MII structure */
  669. dev->mii.dev = dev->net;
  670. dev->mii.mdio_read = smsc75xx_mdio_read;
  671. dev->mii.mdio_write = smsc75xx_mdio_write;
  672. dev->mii.phy_id_mask = 0x1f;
  673. dev->mii.reg_num_mask = 0x1f;
  674. dev->mii.supports_gmii = 1;
  675. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  676. /* reset phy and wait for reset to complete */
  677. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  678. do {
  679. msleep(10);
  680. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  681. if (bmcr < 0) {
  682. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  683. return bmcr;
  684. }
  685. timeout++;
  686. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  687. if (timeout >= 100) {
  688. netdev_warn(dev->net, "timeout on PHY Reset\n");
  689. return -EIO;
  690. }
  691. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  692. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  693. ADVERTISE_PAUSE_ASYM);
  694. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  695. ADVERTISE_1000FULL);
  696. /* read and write to clear phy interrupt status */
  697. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  698. if (ret < 0) {
  699. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  700. return ret;
  701. }
  702. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  703. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  704. PHY_INT_MASK_DEFAULT);
  705. mii_nway_restart(&dev->mii);
  706. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  707. return 0;
  708. }
  709. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  710. {
  711. int ret = 0;
  712. u32 buf;
  713. bool rxenabled;
  714. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  715. if (ret < 0) {
  716. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  717. return ret;
  718. }
  719. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  720. if (rxenabled) {
  721. buf &= ~MAC_RX_RXEN;
  722. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  723. if (ret < 0) {
  724. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  725. return ret;
  726. }
  727. }
  728. /* add 4 to size for FCS */
  729. buf &= ~MAC_RX_MAX_SIZE;
  730. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  731. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  732. if (ret < 0) {
  733. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  734. return ret;
  735. }
  736. if (rxenabled) {
  737. buf |= MAC_RX_RXEN;
  738. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  739. if (ret < 0) {
  740. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  741. return ret;
  742. }
  743. }
  744. return 0;
  745. }
  746. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  747. {
  748. struct usbnet *dev = netdev_priv(netdev);
  749. int ret;
  750. if (new_mtu > MAX_SINGLE_PACKET_SIZE)
  751. return -EINVAL;
  752. ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
  753. if (ret < 0) {
  754. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  755. return ret;
  756. }
  757. return usbnet_change_mtu(netdev, new_mtu);
  758. }
  759. /* Enable or disable Rx checksum offload engine */
  760. static int smsc75xx_set_features(struct net_device *netdev,
  761. netdev_features_t features)
  762. {
  763. struct usbnet *dev = netdev_priv(netdev);
  764. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  765. unsigned long flags;
  766. int ret;
  767. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  768. if (features & NETIF_F_RXCSUM)
  769. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  770. else
  771. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  772. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  773. /* it's racing here! */
  774. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  775. if (ret < 0)
  776. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  777. return ret;
  778. }
  779. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  780. {
  781. int timeout = 0;
  782. do {
  783. u32 buf;
  784. int ret;
  785. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  786. if (ret < 0) {
  787. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  788. return ret;
  789. }
  790. if (buf & PMT_CTL_DEV_RDY)
  791. return 0;
  792. msleep(10);
  793. timeout++;
  794. } while (timeout < 100);
  795. netdev_warn(dev->net, "timeout waiting for device ready\n");
  796. return -EIO;
  797. }
  798. static int smsc75xx_reset(struct usbnet *dev)
  799. {
  800. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  801. u32 buf;
  802. int ret = 0, timeout;
  803. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  804. ret = smsc75xx_wait_ready(dev, 0);
  805. if (ret < 0) {
  806. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  807. return ret;
  808. }
  809. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  810. if (ret < 0) {
  811. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  812. return ret;
  813. }
  814. buf |= HW_CFG_LRST;
  815. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  816. if (ret < 0) {
  817. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  818. return ret;
  819. }
  820. timeout = 0;
  821. do {
  822. msleep(10);
  823. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  824. if (ret < 0) {
  825. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  826. return ret;
  827. }
  828. timeout++;
  829. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  830. if (timeout >= 100) {
  831. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  832. return -EIO;
  833. }
  834. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  835. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  836. if (ret < 0) {
  837. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  838. return ret;
  839. }
  840. buf |= PMT_CTL_PHY_RST;
  841. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  842. if (ret < 0) {
  843. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  844. return ret;
  845. }
  846. timeout = 0;
  847. do {
  848. msleep(10);
  849. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  850. if (ret < 0) {
  851. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  852. return ret;
  853. }
  854. timeout++;
  855. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  856. if (timeout >= 100) {
  857. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  858. return -EIO;
  859. }
  860. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  861. ret = smsc75xx_set_mac_address(dev);
  862. if (ret < 0) {
  863. netdev_warn(dev->net, "Failed to set mac address\n");
  864. return ret;
  865. }
  866. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  867. dev->net->dev_addr);
  868. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  869. if (ret < 0) {
  870. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  871. return ret;
  872. }
  873. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  874. buf);
  875. buf |= HW_CFG_BIR;
  876. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  877. if (ret < 0) {
  878. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  879. return ret;
  880. }
  881. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  882. if (ret < 0) {
  883. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  884. return ret;
  885. }
  886. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  887. buf);
  888. if (!turbo_mode) {
  889. buf = 0;
  890. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  891. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  892. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  893. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  894. } else {
  895. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  896. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  897. }
  898. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  899. (ulong)dev->rx_urb_size);
  900. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  901. if (ret < 0) {
  902. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  903. return ret;
  904. }
  905. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  906. if (ret < 0) {
  907. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  908. return ret;
  909. }
  910. netif_dbg(dev, ifup, dev->net,
  911. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  912. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  913. if (ret < 0) {
  914. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  915. return ret;
  916. }
  917. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  918. if (ret < 0) {
  919. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  920. return ret;
  921. }
  922. netif_dbg(dev, ifup, dev->net,
  923. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  924. if (turbo_mode) {
  925. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  926. if (ret < 0) {
  927. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  928. return ret;
  929. }
  930. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  931. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  932. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  933. if (ret < 0) {
  934. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  935. return ret;
  936. }
  937. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  938. if (ret < 0) {
  939. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  940. return ret;
  941. }
  942. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  943. }
  944. /* set FIFO sizes */
  945. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  946. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  947. if (ret < 0) {
  948. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  949. return ret;
  950. }
  951. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  952. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  953. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  954. if (ret < 0) {
  955. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  956. return ret;
  957. }
  958. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  959. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  960. if (ret < 0) {
  961. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  962. return ret;
  963. }
  964. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  965. if (ret < 0) {
  966. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  967. return ret;
  968. }
  969. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  970. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  971. if (ret < 0) {
  972. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  973. return ret;
  974. }
  975. /* only set default GPIO/LED settings if no EEPROM is detected */
  976. if (!(buf & E2P_CMD_LOADED)) {
  977. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  978. if (ret < 0) {
  979. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  980. return ret;
  981. }
  982. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  983. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  984. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  985. if (ret < 0) {
  986. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  987. return ret;
  988. }
  989. }
  990. ret = smsc75xx_write_reg(dev, FLOW, 0);
  991. if (ret < 0) {
  992. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  993. return ret;
  994. }
  995. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  996. if (ret < 0) {
  997. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  998. return ret;
  999. }
  1000. /* Don't need rfe_ctl_lock during initialisation */
  1001. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1002. if (ret < 0) {
  1003. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1004. return ret;
  1005. }
  1006. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1007. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1008. if (ret < 0) {
  1009. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1010. return ret;
  1011. }
  1012. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1013. if (ret < 0) {
  1014. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1015. return ret;
  1016. }
  1017. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1018. pdata->rfe_ctl);
  1019. /* Enable or disable checksum offload engines */
  1020. smsc75xx_set_features(dev->net, dev->net->features);
  1021. smsc75xx_set_multicast(dev->net);
  1022. ret = smsc75xx_phy_initialize(dev);
  1023. if (ret < 0) {
  1024. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1025. return ret;
  1026. }
  1027. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1028. if (ret < 0) {
  1029. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1030. return ret;
  1031. }
  1032. /* enable PHY interrupts */
  1033. buf |= INT_ENP_PHY_INT;
  1034. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1035. if (ret < 0) {
  1036. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1037. return ret;
  1038. }
  1039. /* allow mac to detect speed and duplex from phy */
  1040. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1041. if (ret < 0) {
  1042. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1043. return ret;
  1044. }
  1045. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1046. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1047. if (ret < 0) {
  1048. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1049. return ret;
  1050. }
  1051. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1052. if (ret < 0) {
  1053. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1054. return ret;
  1055. }
  1056. buf |= MAC_TX_TXEN;
  1057. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1058. if (ret < 0) {
  1059. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1060. return ret;
  1061. }
  1062. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1063. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1064. if (ret < 0) {
  1065. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1066. return ret;
  1067. }
  1068. buf |= FCT_TX_CTL_EN;
  1069. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1070. if (ret < 0) {
  1071. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1072. return ret;
  1073. }
  1074. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1075. ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
  1076. if (ret < 0) {
  1077. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1078. return ret;
  1079. }
  1080. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1081. if (ret < 0) {
  1082. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1083. return ret;
  1084. }
  1085. buf |= MAC_RX_RXEN;
  1086. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1087. if (ret < 0) {
  1088. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1089. return ret;
  1090. }
  1091. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1092. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1093. if (ret < 0) {
  1094. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1095. return ret;
  1096. }
  1097. buf |= FCT_RX_CTL_EN;
  1098. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1099. if (ret < 0) {
  1100. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1101. return ret;
  1102. }
  1103. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1104. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1105. return 0;
  1106. }
  1107. static const struct net_device_ops smsc75xx_netdev_ops = {
  1108. .ndo_open = usbnet_open,
  1109. .ndo_stop = usbnet_stop,
  1110. .ndo_start_xmit = usbnet_start_xmit,
  1111. .ndo_tx_timeout = usbnet_tx_timeout,
  1112. .ndo_change_mtu = smsc75xx_change_mtu,
  1113. .ndo_set_mac_address = eth_mac_addr,
  1114. .ndo_validate_addr = eth_validate_addr,
  1115. .ndo_do_ioctl = smsc75xx_ioctl,
  1116. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1117. .ndo_set_features = smsc75xx_set_features,
  1118. };
  1119. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1120. {
  1121. struct smsc75xx_priv *pdata = NULL;
  1122. int ret;
  1123. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1124. ret = usbnet_get_endpoints(dev, intf);
  1125. if (ret < 0) {
  1126. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1127. return ret;
  1128. }
  1129. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1130. GFP_KERNEL);
  1131. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1132. if (!pdata)
  1133. return -ENOMEM;
  1134. pdata->dev = dev;
  1135. spin_lock_init(&pdata->rfe_ctl_lock);
  1136. mutex_init(&pdata->dataport_mutex);
  1137. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1138. if (DEFAULT_TX_CSUM_ENABLE) {
  1139. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1140. if (DEFAULT_TSO_ENABLE)
  1141. dev->net->features |= NETIF_F_SG |
  1142. NETIF_F_TSO | NETIF_F_TSO6;
  1143. }
  1144. if (DEFAULT_RX_CSUM_ENABLE)
  1145. dev->net->features |= NETIF_F_RXCSUM;
  1146. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1147. NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
  1148. ret = smsc75xx_wait_ready(dev, 0);
  1149. if (ret < 0) {
  1150. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1151. return ret;
  1152. }
  1153. smsc75xx_init_mac_address(dev);
  1154. /* Init all registers */
  1155. ret = smsc75xx_reset(dev);
  1156. if (ret < 0) {
  1157. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1158. return ret;
  1159. }
  1160. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1161. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1162. dev->net->flags |= IFF_MULTICAST;
  1163. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1164. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1165. return 0;
  1166. }
  1167. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1168. {
  1169. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1170. if (pdata) {
  1171. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1172. kfree(pdata);
  1173. pdata = NULL;
  1174. dev->data[0] = 0;
  1175. }
  1176. }
  1177. static u16 smsc_crc(const u8 *buffer, size_t len)
  1178. {
  1179. return bitrev16(crc16(0xFFFF, buffer, len));
  1180. }
  1181. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1182. u32 wuf_mask1)
  1183. {
  1184. int cfg_base = WUF_CFGX + filter * 4;
  1185. int mask_base = WUF_MASKX + filter * 16;
  1186. int ret;
  1187. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1188. if (ret < 0) {
  1189. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1190. return ret;
  1191. }
  1192. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1193. if (ret < 0) {
  1194. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1195. return ret;
  1196. }
  1197. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1198. if (ret < 0) {
  1199. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1200. return ret;
  1201. }
  1202. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1203. if (ret < 0) {
  1204. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1205. return ret;
  1206. }
  1207. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1208. if (ret < 0) {
  1209. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1210. return ret;
  1211. }
  1212. return 0;
  1213. }
  1214. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1215. {
  1216. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1217. u32 val;
  1218. int ret;
  1219. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1220. if (ret < 0) {
  1221. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1222. return ret;
  1223. }
  1224. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1225. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1226. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1227. if (ret < 0) {
  1228. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1229. return ret;
  1230. }
  1231. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1232. return 0;
  1233. }
  1234. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1235. {
  1236. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1237. u32 val;
  1238. int ret;
  1239. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1240. if (ret < 0) {
  1241. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1242. return ret;
  1243. }
  1244. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1245. val |= PMT_CTL_SUS_MODE_1;
  1246. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1247. if (ret < 0) {
  1248. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1249. return ret;
  1250. }
  1251. /* clear wol status, enable energy detection */
  1252. val &= ~PMT_CTL_WUPS;
  1253. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1254. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1255. if (ret < 0) {
  1256. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1257. return ret;
  1258. }
  1259. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1260. return 0;
  1261. }
  1262. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1263. {
  1264. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1265. u32 val;
  1266. int ret;
  1267. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1268. if (ret < 0) {
  1269. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1270. return ret;
  1271. }
  1272. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1273. val |= PMT_CTL_SUS_MODE_2;
  1274. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1275. if (ret < 0) {
  1276. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1277. return ret;
  1278. }
  1279. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1280. return 0;
  1281. }
  1282. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1283. {
  1284. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1285. u32 val;
  1286. int ret;
  1287. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1288. if (ret < 0) {
  1289. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1290. return ret;
  1291. }
  1292. if (val & FCT_RX_CTL_RXUSED) {
  1293. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1294. return -EBUSY;
  1295. }
  1296. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1297. if (ret < 0) {
  1298. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1299. return ret;
  1300. }
  1301. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1302. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1303. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1304. if (ret < 0) {
  1305. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1306. return ret;
  1307. }
  1308. /* clear wol status */
  1309. val &= ~PMT_CTL_WUPS;
  1310. val |= PMT_CTL_WUPS_WOL;
  1311. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1312. if (ret < 0) {
  1313. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1314. return ret;
  1315. }
  1316. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1317. return 0;
  1318. }
  1319. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1320. {
  1321. struct mii_if_info *mii = &dev->mii;
  1322. int ret;
  1323. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1324. /* read to clear */
  1325. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1326. if (ret < 0) {
  1327. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1328. return ret;
  1329. }
  1330. /* enable interrupt source */
  1331. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1332. if (ret < 0) {
  1333. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1334. return ret;
  1335. }
  1336. ret |= mask;
  1337. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1338. return 0;
  1339. }
  1340. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1341. {
  1342. struct mii_if_info *mii = &dev->mii;
  1343. int ret;
  1344. /* first, a dummy read, needed to latch some MII phys */
  1345. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1346. if (ret < 0) {
  1347. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1348. return ret;
  1349. }
  1350. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1351. if (ret < 0) {
  1352. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1353. return ret;
  1354. }
  1355. return !!(ret & BMSR_LSTATUS);
  1356. }
  1357. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1358. {
  1359. int ret;
  1360. if (!netif_running(dev->net)) {
  1361. /* interface is ifconfig down so fully power down hw */
  1362. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1363. return smsc75xx_enter_suspend2(dev);
  1364. }
  1365. if (!link_up) {
  1366. /* link is down so enter EDPD mode */
  1367. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1368. /* enable PHY wakeup events for if cable is attached */
  1369. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1370. PHY_INT_MASK_ANEG_COMP);
  1371. if (ret < 0) {
  1372. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1373. return ret;
  1374. }
  1375. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1376. return smsc75xx_enter_suspend1(dev);
  1377. }
  1378. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1379. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1380. PHY_INT_MASK_LINK_DOWN);
  1381. if (ret < 0) {
  1382. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1383. return ret;
  1384. }
  1385. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1386. return smsc75xx_enter_suspend3(dev);
  1387. }
  1388. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1389. {
  1390. struct usbnet *dev = usb_get_intfdata(intf);
  1391. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1392. u32 val, link_up;
  1393. int ret;
  1394. ret = usbnet_suspend(intf, message);
  1395. if (ret < 0) {
  1396. netdev_warn(dev->net, "usbnet_suspend error\n");
  1397. return ret;
  1398. }
  1399. if (pdata->suspend_flags) {
  1400. netdev_warn(dev->net, "error during last resume\n");
  1401. pdata->suspend_flags = 0;
  1402. }
  1403. /* determine if link is up using only _nopm functions */
  1404. link_up = smsc75xx_link_ok_nopm(dev);
  1405. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1406. ret = smsc75xx_autosuspend(dev, link_up);
  1407. goto done;
  1408. }
  1409. /* if we get this far we're not autosuspending */
  1410. /* if no wol options set, or if link is down and we're not waking on
  1411. * PHY activity, enter lowest power SUSPEND2 mode
  1412. */
  1413. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1414. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1415. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1416. /* disable energy detect (link up) & wake up events */
  1417. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1418. if (ret < 0) {
  1419. netdev_warn(dev->net, "Error reading WUCSR\n");
  1420. goto done;
  1421. }
  1422. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1423. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1424. if (ret < 0) {
  1425. netdev_warn(dev->net, "Error writing WUCSR\n");
  1426. goto done;
  1427. }
  1428. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1429. if (ret < 0) {
  1430. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1431. goto done;
  1432. }
  1433. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1434. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1435. if (ret < 0) {
  1436. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1437. goto done;
  1438. }
  1439. ret = smsc75xx_enter_suspend2(dev);
  1440. goto done;
  1441. }
  1442. if (pdata->wolopts & WAKE_PHY) {
  1443. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1444. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1445. if (ret < 0) {
  1446. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1447. goto done;
  1448. }
  1449. /* if link is down then configure EDPD and enter SUSPEND1,
  1450. * otherwise enter SUSPEND0 below
  1451. */
  1452. if (!link_up) {
  1453. struct mii_if_info *mii = &dev->mii;
  1454. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1455. /* enable energy detect power-down mode */
  1456. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1457. PHY_MODE_CTRL_STS);
  1458. if (ret < 0) {
  1459. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1460. goto done;
  1461. }
  1462. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1463. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1464. PHY_MODE_CTRL_STS, ret);
  1465. /* enter SUSPEND1 mode */
  1466. ret = smsc75xx_enter_suspend1(dev);
  1467. goto done;
  1468. }
  1469. }
  1470. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1471. int i, filter = 0;
  1472. /* disable all filters */
  1473. for (i = 0; i < WUF_NUM; i++) {
  1474. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1475. if (ret < 0) {
  1476. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1477. goto done;
  1478. }
  1479. }
  1480. if (pdata->wolopts & WAKE_MCAST) {
  1481. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1482. netdev_info(dev->net, "enabling multicast detection\n");
  1483. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1484. | smsc_crc(mcast, 3);
  1485. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1486. if (ret < 0) {
  1487. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1488. goto done;
  1489. }
  1490. }
  1491. if (pdata->wolopts & WAKE_ARP) {
  1492. const u8 arp[] = {0x08, 0x06};
  1493. netdev_info(dev->net, "enabling ARP detection\n");
  1494. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1495. | smsc_crc(arp, 2);
  1496. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1497. if (ret < 0) {
  1498. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1499. goto done;
  1500. }
  1501. }
  1502. /* clear any pending pattern match packet status */
  1503. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1504. if (ret < 0) {
  1505. netdev_warn(dev->net, "Error reading WUCSR\n");
  1506. goto done;
  1507. }
  1508. val |= WUCSR_WUFR;
  1509. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1510. if (ret < 0) {
  1511. netdev_warn(dev->net, "Error writing WUCSR\n");
  1512. goto done;
  1513. }
  1514. netdev_info(dev->net, "enabling packet match detection\n");
  1515. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1516. if (ret < 0) {
  1517. netdev_warn(dev->net, "Error reading WUCSR\n");
  1518. goto done;
  1519. }
  1520. val |= WUCSR_WUEN;
  1521. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1522. if (ret < 0) {
  1523. netdev_warn(dev->net, "Error writing WUCSR\n");
  1524. goto done;
  1525. }
  1526. } else {
  1527. netdev_info(dev->net, "disabling packet match detection\n");
  1528. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1529. if (ret < 0) {
  1530. netdev_warn(dev->net, "Error reading WUCSR\n");
  1531. goto done;
  1532. }
  1533. val &= ~WUCSR_WUEN;
  1534. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1535. if (ret < 0) {
  1536. netdev_warn(dev->net, "Error writing WUCSR\n");
  1537. goto done;
  1538. }
  1539. }
  1540. /* disable magic, bcast & unicast wakeup sources */
  1541. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1542. if (ret < 0) {
  1543. netdev_warn(dev->net, "Error reading WUCSR\n");
  1544. goto done;
  1545. }
  1546. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1547. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1548. if (ret < 0) {
  1549. netdev_warn(dev->net, "Error writing WUCSR\n");
  1550. goto done;
  1551. }
  1552. if (pdata->wolopts & WAKE_PHY) {
  1553. netdev_info(dev->net, "enabling PHY wakeup\n");
  1554. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1555. if (ret < 0) {
  1556. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1557. goto done;
  1558. }
  1559. /* clear wol status, enable energy detection */
  1560. val &= ~PMT_CTL_WUPS;
  1561. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1562. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1563. if (ret < 0) {
  1564. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1565. goto done;
  1566. }
  1567. }
  1568. if (pdata->wolopts & WAKE_MAGIC) {
  1569. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1570. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1571. if (ret < 0) {
  1572. netdev_warn(dev->net, "Error reading WUCSR\n");
  1573. goto done;
  1574. }
  1575. /* clear any pending magic packet status */
  1576. val |= WUCSR_MPR | WUCSR_MPEN;
  1577. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1578. if (ret < 0) {
  1579. netdev_warn(dev->net, "Error writing WUCSR\n");
  1580. goto done;
  1581. }
  1582. }
  1583. if (pdata->wolopts & WAKE_BCAST) {
  1584. netdev_info(dev->net, "enabling broadcast detection\n");
  1585. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1586. if (ret < 0) {
  1587. netdev_warn(dev->net, "Error reading WUCSR\n");
  1588. goto done;
  1589. }
  1590. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1591. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1592. if (ret < 0) {
  1593. netdev_warn(dev->net, "Error writing WUCSR\n");
  1594. goto done;
  1595. }
  1596. }
  1597. if (pdata->wolopts & WAKE_UCAST) {
  1598. netdev_info(dev->net, "enabling unicast detection\n");
  1599. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1600. if (ret < 0) {
  1601. netdev_warn(dev->net, "Error reading WUCSR\n");
  1602. goto done;
  1603. }
  1604. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1605. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1606. if (ret < 0) {
  1607. netdev_warn(dev->net, "Error writing WUCSR\n");
  1608. goto done;
  1609. }
  1610. }
  1611. /* enable receiver to enable frame reception */
  1612. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1613. if (ret < 0) {
  1614. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1615. goto done;
  1616. }
  1617. val |= MAC_RX_RXEN;
  1618. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1619. if (ret < 0) {
  1620. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1621. goto done;
  1622. }
  1623. /* some wol options are enabled, so enter SUSPEND0 */
  1624. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1625. ret = smsc75xx_enter_suspend0(dev);
  1626. done:
  1627. if (ret)
  1628. usbnet_resume(intf);
  1629. return ret;
  1630. }
  1631. static int smsc75xx_resume(struct usb_interface *intf)
  1632. {
  1633. struct usbnet *dev = usb_get_intfdata(intf);
  1634. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1635. u8 suspend_flags = pdata->suspend_flags;
  1636. int ret;
  1637. u32 val;
  1638. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1639. /* do this first to ensure it's cleared even in error case */
  1640. pdata->suspend_flags = 0;
  1641. if (suspend_flags & SUSPEND_ALLMODES) {
  1642. /* Disable wakeup sources */
  1643. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1644. if (ret < 0) {
  1645. netdev_warn(dev->net, "Error reading WUCSR\n");
  1646. return ret;
  1647. }
  1648. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1649. | WUCSR_BCST_EN);
  1650. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1651. if (ret < 0) {
  1652. netdev_warn(dev->net, "Error writing WUCSR\n");
  1653. return ret;
  1654. }
  1655. /* clear wake-up status */
  1656. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1657. if (ret < 0) {
  1658. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1659. return ret;
  1660. }
  1661. val &= ~PMT_CTL_WOL_EN;
  1662. val |= PMT_CTL_WUPS;
  1663. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1664. if (ret < 0) {
  1665. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1666. return ret;
  1667. }
  1668. }
  1669. if (suspend_flags & SUSPEND_SUSPEND2) {
  1670. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1671. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1672. if (ret < 0) {
  1673. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1674. return ret;
  1675. }
  1676. val |= PMT_CTL_PHY_PWRUP;
  1677. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1678. if (ret < 0) {
  1679. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1680. return ret;
  1681. }
  1682. }
  1683. ret = smsc75xx_wait_ready(dev, 1);
  1684. if (ret < 0) {
  1685. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1686. return ret;
  1687. }
  1688. return usbnet_resume(intf);
  1689. }
  1690. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1691. u32 rx_cmd_a, u32 rx_cmd_b)
  1692. {
  1693. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1694. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1695. skb->ip_summed = CHECKSUM_NONE;
  1696. } else {
  1697. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1698. skb->ip_summed = CHECKSUM_COMPLETE;
  1699. }
  1700. }
  1701. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1702. {
  1703. while (skb->len > 0) {
  1704. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1705. struct sk_buff *ax_skb;
  1706. unsigned char *packet;
  1707. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1708. le32_to_cpus(&rx_cmd_a);
  1709. skb_pull(skb, 4);
  1710. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1711. le32_to_cpus(&rx_cmd_b);
  1712. skb_pull(skb, 4 + RXW_PADDING);
  1713. packet = skb->data;
  1714. /* get the packet length */
  1715. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1716. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1717. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1718. netif_dbg(dev, rx_err, dev->net,
  1719. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1720. dev->net->stats.rx_errors++;
  1721. dev->net->stats.rx_dropped++;
  1722. if (rx_cmd_a & RX_CMD_A_FCS)
  1723. dev->net->stats.rx_crc_errors++;
  1724. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1725. dev->net->stats.rx_frame_errors++;
  1726. } else {
  1727. /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
  1728. if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
  1729. netif_dbg(dev, rx_err, dev->net,
  1730. "size err rx_cmd_a=0x%08x\n",
  1731. rx_cmd_a);
  1732. return 0;
  1733. }
  1734. /* last frame in this batch */
  1735. if (skb->len == size) {
  1736. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1737. rx_cmd_b);
  1738. skb_trim(skb, skb->len - 4); /* remove fcs */
  1739. skb->truesize = size + sizeof(struct sk_buff);
  1740. return 1;
  1741. }
  1742. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1743. if (unlikely(!ax_skb)) {
  1744. netdev_warn(dev->net, "Error allocating skb\n");
  1745. return 0;
  1746. }
  1747. ax_skb->len = size;
  1748. ax_skb->data = packet;
  1749. skb_set_tail_pointer(ax_skb, size);
  1750. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1751. rx_cmd_b);
  1752. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1753. ax_skb->truesize = size + sizeof(struct sk_buff);
  1754. usbnet_skb_return(dev, ax_skb);
  1755. }
  1756. skb_pull(skb, size);
  1757. /* padding bytes before the next frame starts */
  1758. if (skb->len)
  1759. skb_pull(skb, align_count);
  1760. }
  1761. if (unlikely(skb->len < 0)) {
  1762. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1763. return 0;
  1764. }
  1765. return 1;
  1766. }
  1767. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1768. struct sk_buff *skb, gfp_t flags)
  1769. {
  1770. u32 tx_cmd_a, tx_cmd_b;
  1771. skb_linearize(skb);
  1772. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1773. struct sk_buff *skb2 =
  1774. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1775. dev_kfree_skb_any(skb);
  1776. skb = skb2;
  1777. if (!skb)
  1778. return NULL;
  1779. }
  1780. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1781. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1782. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1783. if (skb_is_gso(skb)) {
  1784. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1785. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1786. tx_cmd_a |= TX_CMD_A_LSO;
  1787. } else {
  1788. tx_cmd_b = 0;
  1789. }
  1790. skb_push(skb, 4);
  1791. cpu_to_le32s(&tx_cmd_b);
  1792. memcpy(skb->data, &tx_cmd_b, 4);
  1793. skb_push(skb, 4);
  1794. cpu_to_le32s(&tx_cmd_a);
  1795. memcpy(skb->data, &tx_cmd_a, 4);
  1796. return skb;
  1797. }
  1798. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1799. {
  1800. dev->intf->needs_remote_wakeup = on;
  1801. return 0;
  1802. }
  1803. static const struct driver_info smsc75xx_info = {
  1804. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1805. .bind = smsc75xx_bind,
  1806. .unbind = smsc75xx_unbind,
  1807. .link_reset = smsc75xx_link_reset,
  1808. .reset = smsc75xx_reset,
  1809. .rx_fixup = smsc75xx_rx_fixup,
  1810. .tx_fixup = smsc75xx_tx_fixup,
  1811. .status = smsc75xx_status,
  1812. .manage_power = smsc75xx_manage_power,
  1813. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1814. };
  1815. static const struct usb_device_id products[] = {
  1816. {
  1817. /* SMSC7500 USB Gigabit Ethernet Device */
  1818. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1819. .driver_info = (unsigned long) &smsc75xx_info,
  1820. },
  1821. {
  1822. /* SMSC7500 USB Gigabit Ethernet Device */
  1823. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1824. .driver_info = (unsigned long) &smsc75xx_info,
  1825. },
  1826. { }, /* END */
  1827. };
  1828. MODULE_DEVICE_TABLE(usb, products);
  1829. static struct usb_driver smsc75xx_driver = {
  1830. .name = SMSC_CHIPNAME,
  1831. .id_table = products,
  1832. .probe = usbnet_probe,
  1833. .suspend = smsc75xx_suspend,
  1834. .resume = smsc75xx_resume,
  1835. .reset_resume = smsc75xx_resume,
  1836. .disconnect = usbnet_disconnect,
  1837. .disable_hub_initiated_lpm = 1,
  1838. .supports_autosuspend = 1,
  1839. };
  1840. module_usb_driver(smsc75xx_driver);
  1841. MODULE_AUTHOR("Nancy Lin");
  1842. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1843. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1844. MODULE_LICENSE("GPL");