opal.h 20 KB

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  1. /*
  2. * PowerNV OPAL definitions.
  3. *
  4. * Copyright 2011 IBM Corp.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #ifndef __OPAL_H
  12. #define __OPAL_H
  13. /****** Takeover interface ********/
  14. /* PAPR H-Call used to querty the HAL existence and/or instanciate
  15. * it from within pHyp (tech preview only).
  16. *
  17. * This is exclusively used in prom_init.c
  18. */
  19. #ifndef __ASSEMBLY__
  20. struct opal_takeover_args {
  21. u64 k_image; /* r4 */
  22. u64 k_size; /* r5 */
  23. u64 k_entry; /* r6 */
  24. u64 k_entry2; /* r7 */
  25. u64 hal_addr; /* r8 */
  26. u64 rd_image; /* r9 */
  27. u64 rd_size; /* r10 */
  28. u64 rd_loc; /* r11 */
  29. };
  30. extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
  31. extern long opal_do_takeover(struct opal_takeover_args *args);
  32. struct rtas_args;
  33. extern int opal_enter_rtas(struct rtas_args *args,
  34. unsigned long data,
  35. unsigned long entry);
  36. #endif /* __ASSEMBLY__ */
  37. /****** OPAL APIs ******/
  38. /* Return codes */
  39. #define OPAL_SUCCESS 0
  40. #define OPAL_PARAMETER -1
  41. #define OPAL_BUSY -2
  42. #define OPAL_PARTIAL -3
  43. #define OPAL_CONSTRAINED -4
  44. #define OPAL_CLOSED -5
  45. #define OPAL_HARDWARE -6
  46. #define OPAL_UNSUPPORTED -7
  47. #define OPAL_PERMISSION -8
  48. #define OPAL_NO_MEM -9
  49. #define OPAL_RESOURCE -10
  50. #define OPAL_INTERNAL_ERROR -11
  51. #define OPAL_BUSY_EVENT -12
  52. #define OPAL_HARDWARE_FROZEN -13
  53. /* API Tokens (in r0) */
  54. #define OPAL_CONSOLE_WRITE 1
  55. #define OPAL_CONSOLE_READ 2
  56. #define OPAL_RTC_READ 3
  57. #define OPAL_RTC_WRITE 4
  58. #define OPAL_CEC_POWER_DOWN 5
  59. #define OPAL_CEC_REBOOT 6
  60. #define OPAL_READ_NVRAM 7
  61. #define OPAL_WRITE_NVRAM 8
  62. #define OPAL_HANDLE_INTERRUPT 9
  63. #define OPAL_POLL_EVENTS 10
  64. #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
  65. #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
  66. #define OPAL_PCI_CONFIG_READ_BYTE 13
  67. #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
  68. #define OPAL_PCI_CONFIG_READ_WORD 15
  69. #define OPAL_PCI_CONFIG_WRITE_BYTE 16
  70. #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
  71. #define OPAL_PCI_CONFIG_WRITE_WORD 18
  72. #define OPAL_SET_XIVE 19
  73. #define OPAL_GET_XIVE 20
  74. #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
  75. #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
  76. #define OPAL_PCI_EEH_FREEZE_STATUS 23
  77. #define OPAL_PCI_SHPC 24
  78. #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
  79. #define OPAL_PCI_EEH_FREEZE_CLEAR 26
  80. #define OPAL_PCI_PHB_MMIO_ENABLE 27
  81. #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
  82. #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
  83. #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
  84. #define OPAL_PCI_SET_PE 31
  85. #define OPAL_PCI_SET_PELTV 32
  86. #define OPAL_PCI_SET_MVE 33
  87. #define OPAL_PCI_SET_MVE_ENABLE 34
  88. #define OPAL_PCI_GET_XIVE_REISSUE 35
  89. #define OPAL_PCI_SET_XIVE_REISSUE 36
  90. #define OPAL_PCI_SET_XIVE_PE 37
  91. #define OPAL_GET_XIVE_SOURCE 38
  92. #define OPAL_GET_MSI_32 39
  93. #define OPAL_GET_MSI_64 40
  94. #define OPAL_START_CPU 41
  95. #define OPAL_QUERY_CPU_STATUS 42
  96. #define OPAL_WRITE_OPPANEL 43
  97. #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
  98. #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
  99. #define OPAL_PCI_RESET 49
  100. #define OPAL_PCI_GET_HUB_DIAG_DATA 50
  101. #define OPAL_PCI_GET_PHB_DIAG_DATA 51
  102. #define OPAL_PCI_FENCE_PHB 52
  103. #define OPAL_PCI_REINIT 53
  104. #define OPAL_PCI_MASK_PE_ERROR 54
  105. #define OPAL_SET_SLOT_LED_STATUS 55
  106. #define OPAL_GET_EPOW_STATUS 56
  107. #define OPAL_SET_SYSTEM_ATTENTION_LED 57
  108. #define OPAL_RESERVED1 58
  109. #define OPAL_RESERVED2 59
  110. #define OPAL_PCI_NEXT_ERROR 60
  111. #define OPAL_PCI_EEH_FREEZE_STATUS2 61
  112. #define OPAL_PCI_POLL 62
  113. #define OPAL_PCI_MSI_EOI 63
  114. #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
  115. #define OPAL_XSCOM_READ 65
  116. #define OPAL_XSCOM_WRITE 66
  117. #define OPAL_LPC_READ 67
  118. #define OPAL_LPC_WRITE 68
  119. #ifndef __ASSEMBLY__
  120. /* Other enums */
  121. enum OpalVendorApiTokens {
  122. OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
  123. };
  124. enum OpalFreezeState {
  125. OPAL_EEH_STOPPED_NOT_FROZEN = 0,
  126. OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
  127. OPAL_EEH_STOPPED_DMA_FREEZE = 2,
  128. OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
  129. OPAL_EEH_STOPPED_RESET = 4,
  130. OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
  131. OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
  132. };
  133. enum OpalEehFreezeActionToken {
  134. OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
  135. OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
  136. OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
  137. };
  138. enum OpalPciStatusToken {
  139. OPAL_EEH_NO_ERROR = 0,
  140. OPAL_EEH_IOC_ERROR = 1,
  141. OPAL_EEH_PHB_ERROR = 2,
  142. OPAL_EEH_PE_ERROR = 3,
  143. OPAL_EEH_PE_MMIO_ERROR = 4,
  144. OPAL_EEH_PE_DMA_ERROR = 5
  145. };
  146. enum OpalPciErrorSeverity {
  147. OPAL_EEH_SEV_NO_ERROR = 0,
  148. OPAL_EEH_SEV_IOC_DEAD = 1,
  149. OPAL_EEH_SEV_PHB_DEAD = 2,
  150. OPAL_EEH_SEV_PHB_FENCED = 3,
  151. OPAL_EEH_SEV_PE_ER = 4,
  152. OPAL_EEH_SEV_INF = 5
  153. };
  154. enum OpalShpcAction {
  155. OPAL_SHPC_GET_LINK_STATE = 0,
  156. OPAL_SHPC_GET_SLOT_STATE = 1
  157. };
  158. enum OpalShpcLinkState {
  159. OPAL_SHPC_LINK_DOWN = 0,
  160. OPAL_SHPC_LINK_UP = 1
  161. };
  162. enum OpalMmioWindowType {
  163. OPAL_M32_WINDOW_TYPE = 1,
  164. OPAL_M64_WINDOW_TYPE = 2,
  165. OPAL_IO_WINDOW_TYPE = 3
  166. };
  167. enum OpalShpcSlotState {
  168. OPAL_SHPC_DEV_NOT_PRESENT = 0,
  169. OPAL_SHPC_DEV_PRESENT = 1
  170. };
  171. enum OpalExceptionHandler {
  172. OPAL_MACHINE_CHECK_HANDLER = 1,
  173. OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
  174. OPAL_SOFTPATCH_HANDLER = 3
  175. };
  176. enum OpalPendingState {
  177. OPAL_EVENT_OPAL_INTERNAL = 0x1,
  178. OPAL_EVENT_NVRAM = 0x2,
  179. OPAL_EVENT_RTC = 0x4,
  180. OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
  181. OPAL_EVENT_CONSOLE_INPUT = 0x10,
  182. OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
  183. OPAL_EVENT_ERROR_LOG = 0x40,
  184. OPAL_EVENT_EPOW = 0x80,
  185. OPAL_EVENT_LED_STATUS = 0x100,
  186. OPAL_EVENT_PCI_ERROR = 0x200
  187. };
  188. /* Machine check related definitions */
  189. enum OpalMCE_Version {
  190. OpalMCE_V1 = 1,
  191. };
  192. enum OpalMCE_Severity {
  193. OpalMCE_SEV_NO_ERROR = 0,
  194. OpalMCE_SEV_WARNING = 1,
  195. OpalMCE_SEV_ERROR_SYNC = 2,
  196. OpalMCE_SEV_FATAL = 3,
  197. };
  198. enum OpalMCE_Disposition {
  199. OpalMCE_DISPOSITION_RECOVERED = 0,
  200. OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
  201. };
  202. enum OpalMCE_Initiator {
  203. OpalMCE_INITIATOR_UNKNOWN = 0,
  204. OpalMCE_INITIATOR_CPU = 1,
  205. };
  206. enum OpalMCE_ErrorType {
  207. OpalMCE_ERROR_TYPE_UNKNOWN = 0,
  208. OpalMCE_ERROR_TYPE_UE = 1,
  209. OpalMCE_ERROR_TYPE_SLB = 2,
  210. OpalMCE_ERROR_TYPE_ERAT = 3,
  211. OpalMCE_ERROR_TYPE_TLB = 4,
  212. };
  213. enum OpalMCE_UeErrorType {
  214. OpalMCE_UE_ERROR_INDETERMINATE = 0,
  215. OpalMCE_UE_ERROR_IFETCH = 1,
  216. OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
  217. OpalMCE_UE_ERROR_LOAD_STORE = 3,
  218. OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
  219. };
  220. enum OpalMCE_SlbErrorType {
  221. OpalMCE_SLB_ERROR_INDETERMINATE = 0,
  222. OpalMCE_SLB_ERROR_PARITY = 1,
  223. OpalMCE_SLB_ERROR_MULTIHIT = 2,
  224. };
  225. enum OpalMCE_EratErrorType {
  226. OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
  227. OpalMCE_ERAT_ERROR_PARITY = 1,
  228. OpalMCE_ERAT_ERROR_MULTIHIT = 2,
  229. };
  230. enum OpalMCE_TlbErrorType {
  231. OpalMCE_TLB_ERROR_INDETERMINATE = 0,
  232. OpalMCE_TLB_ERROR_PARITY = 1,
  233. OpalMCE_TLB_ERROR_MULTIHIT = 2,
  234. };
  235. enum OpalThreadStatus {
  236. OPAL_THREAD_INACTIVE = 0x0,
  237. OPAL_THREAD_STARTED = 0x1,
  238. OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
  239. };
  240. enum OpalPciBusCompare {
  241. OpalPciBusAny = 0, /* Any bus number match */
  242. OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
  243. OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
  244. OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
  245. OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
  246. OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
  247. OpalPciBusAll = 7, /* Match bus number exactly */
  248. };
  249. enum OpalDeviceCompare {
  250. OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
  251. OPAL_COMPARE_RID_DEVICE_NUMBER = 1
  252. };
  253. enum OpalFuncCompare {
  254. OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
  255. OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
  256. };
  257. enum OpalPeAction {
  258. OPAL_UNMAP_PE = 0,
  259. OPAL_MAP_PE = 1
  260. };
  261. enum OpalPeltvAction {
  262. OPAL_REMOVE_PE_FROM_DOMAIN = 0,
  263. OPAL_ADD_PE_TO_DOMAIN = 1
  264. };
  265. enum OpalMveEnableAction {
  266. OPAL_DISABLE_MVE = 0,
  267. OPAL_ENABLE_MVE = 1
  268. };
  269. enum OpalPciResetAndReinitScope {
  270. OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
  271. OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
  272. OPAL_PCI_IODA_TABLE_RESET = 6,
  273. };
  274. enum OpalPciResetState {
  275. OPAL_DEASSERT_RESET = 0,
  276. OPAL_ASSERT_RESET = 1
  277. };
  278. enum OpalPciMaskAction {
  279. OPAL_UNMASK_ERROR_TYPE = 0,
  280. OPAL_MASK_ERROR_TYPE = 1
  281. };
  282. enum OpalSlotLedType {
  283. OPAL_SLOT_LED_ID_TYPE = 0,
  284. OPAL_SLOT_LED_FAULT_TYPE = 1
  285. };
  286. enum OpalLedAction {
  287. OPAL_TURN_OFF_LED = 0,
  288. OPAL_TURN_ON_LED = 1,
  289. OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
  290. };
  291. enum OpalEpowStatus {
  292. OPAL_EPOW_NONE = 0,
  293. OPAL_EPOW_UPS = 1,
  294. OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
  295. OPAL_EPOW_OVER_INTERNAL_TEMP = 3
  296. };
  297. /*
  298. * Address cycle types for LPC accesses. These also correspond
  299. * to the content of the first cell of the "reg" property for
  300. * device nodes on the LPC bus
  301. */
  302. enum OpalLPCAddressType {
  303. OPAL_LPC_MEM = 0,
  304. OPAL_LPC_IO = 1,
  305. OPAL_LPC_FW = 2,
  306. };
  307. struct opal_machine_check_event {
  308. enum OpalMCE_Version version:8; /* 0x00 */
  309. uint8_t in_use; /* 0x01 */
  310. enum OpalMCE_Severity severity:8; /* 0x02 */
  311. enum OpalMCE_Initiator initiator:8; /* 0x03 */
  312. enum OpalMCE_ErrorType error_type:8; /* 0x04 */
  313. enum OpalMCE_Disposition disposition:8; /* 0x05 */
  314. uint8_t reserved_1[2]; /* 0x06 */
  315. uint64_t gpr3; /* 0x08 */
  316. uint64_t srr0; /* 0x10 */
  317. uint64_t srr1; /* 0x18 */
  318. union { /* 0x20 */
  319. struct {
  320. enum OpalMCE_UeErrorType ue_error_type:8;
  321. uint8_t effective_address_provided;
  322. uint8_t physical_address_provided;
  323. uint8_t reserved_1[5];
  324. uint64_t effective_address;
  325. uint64_t physical_address;
  326. uint8_t reserved_2[8];
  327. } ue_error;
  328. struct {
  329. enum OpalMCE_SlbErrorType slb_error_type:8;
  330. uint8_t effective_address_provided;
  331. uint8_t reserved_1[6];
  332. uint64_t effective_address;
  333. uint8_t reserved_2[16];
  334. } slb_error;
  335. struct {
  336. enum OpalMCE_EratErrorType erat_error_type:8;
  337. uint8_t effective_address_provided;
  338. uint8_t reserved_1[6];
  339. uint64_t effective_address;
  340. uint8_t reserved_2[16];
  341. } erat_error;
  342. struct {
  343. enum OpalMCE_TlbErrorType tlb_error_type:8;
  344. uint8_t effective_address_provided;
  345. uint8_t reserved_1[6];
  346. uint64_t effective_address;
  347. uint8_t reserved_2[16];
  348. } tlb_error;
  349. } u;
  350. };
  351. enum {
  352. OPAL_P7IOC_DIAG_TYPE_NONE = 0,
  353. OPAL_P7IOC_DIAG_TYPE_RGC = 1,
  354. OPAL_P7IOC_DIAG_TYPE_BI = 2,
  355. OPAL_P7IOC_DIAG_TYPE_CI = 3,
  356. OPAL_P7IOC_DIAG_TYPE_MISC = 4,
  357. OPAL_P7IOC_DIAG_TYPE_I2C = 5,
  358. OPAL_P7IOC_DIAG_TYPE_LAST = 6
  359. };
  360. struct OpalIoP7IOCErrorData {
  361. uint16_t type;
  362. /* GEM */
  363. uint64_t gemXfir;
  364. uint64_t gemRfir;
  365. uint64_t gemRirqfir;
  366. uint64_t gemMask;
  367. uint64_t gemRwof;
  368. /* LEM */
  369. uint64_t lemFir;
  370. uint64_t lemErrMask;
  371. uint64_t lemAction0;
  372. uint64_t lemAction1;
  373. uint64_t lemWof;
  374. union {
  375. struct OpalIoP7IOCRgcErrorData {
  376. uint64_t rgcStatus; /* 3E1C10 */
  377. uint64_t rgcLdcp; /* 3E1C18 */
  378. }rgc;
  379. struct OpalIoP7IOCBiErrorData {
  380. uint64_t biLdcp0; /* 3C0100, 3C0118 */
  381. uint64_t biLdcp1; /* 3C0108, 3C0120 */
  382. uint64_t biLdcp2; /* 3C0110, 3C0128 */
  383. uint64_t biFenceStatus; /* 3C0130, 3C0130 */
  384. uint8_t biDownbound; /* BI Downbound or Upbound */
  385. }bi;
  386. struct OpalIoP7IOCCiErrorData {
  387. uint64_t ciPortStatus; /* 3Dn008 */
  388. uint64_t ciPortLdcp; /* 3Dn010 */
  389. uint8_t ciPort; /* Index of CI port: 0/1 */
  390. }ci;
  391. };
  392. };
  393. /**
  394. * This structure defines the overlay which will be used to store PHB error
  395. * data upon request.
  396. */
  397. enum {
  398. OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
  399. };
  400. enum {
  401. OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
  402. };
  403. enum {
  404. OPAL_P7IOC_NUM_PEST_REGS = 128,
  405. };
  406. struct OpalIoPhbErrorCommon {
  407. uint32_t version;
  408. uint32_t ioType;
  409. uint32_t len;
  410. };
  411. struct OpalIoP7IOCPhbErrorData {
  412. struct OpalIoPhbErrorCommon common;
  413. uint32_t brdgCtl;
  414. // P7IOC utl regs
  415. uint32_t portStatusReg;
  416. uint32_t rootCmplxStatus;
  417. uint32_t busAgentStatus;
  418. // P7IOC cfg regs
  419. uint32_t deviceStatus;
  420. uint32_t slotStatus;
  421. uint32_t linkStatus;
  422. uint32_t devCmdStatus;
  423. uint32_t devSecStatus;
  424. // cfg AER regs
  425. uint32_t rootErrorStatus;
  426. uint32_t uncorrErrorStatus;
  427. uint32_t corrErrorStatus;
  428. uint32_t tlpHdr1;
  429. uint32_t tlpHdr2;
  430. uint32_t tlpHdr3;
  431. uint32_t tlpHdr4;
  432. uint32_t sourceId;
  433. uint32_t rsv3;
  434. // Record data about the call to allocate a buffer.
  435. uint64_t errorClass;
  436. uint64_t correlator;
  437. //P7IOC MMIO Error Regs
  438. uint64_t p7iocPlssr; // n120
  439. uint64_t p7iocCsr; // n110
  440. uint64_t lemFir; // nC00
  441. uint64_t lemErrorMask; // nC18
  442. uint64_t lemWOF; // nC40
  443. uint64_t phbErrorStatus; // nC80
  444. uint64_t phbFirstErrorStatus; // nC88
  445. uint64_t phbErrorLog0; // nCC0
  446. uint64_t phbErrorLog1; // nCC8
  447. uint64_t mmioErrorStatus; // nD00
  448. uint64_t mmioFirstErrorStatus; // nD08
  449. uint64_t mmioErrorLog0; // nD40
  450. uint64_t mmioErrorLog1; // nD48
  451. uint64_t dma0ErrorStatus; // nD80
  452. uint64_t dma0FirstErrorStatus; // nD88
  453. uint64_t dma0ErrorLog0; // nDC0
  454. uint64_t dma0ErrorLog1; // nDC8
  455. uint64_t dma1ErrorStatus; // nE00
  456. uint64_t dma1FirstErrorStatus; // nE08
  457. uint64_t dma1ErrorLog0; // nE40
  458. uint64_t dma1ErrorLog1; // nE48
  459. uint64_t pestA[OPAL_P7IOC_NUM_PEST_REGS];
  460. uint64_t pestB[OPAL_P7IOC_NUM_PEST_REGS];
  461. };
  462. typedef struct oppanel_line {
  463. const char * line;
  464. uint64_t line_len;
  465. } oppanel_line_t;
  466. /* API functions */
  467. int64_t opal_console_write(int64_t term_number, int64_t *length,
  468. const uint8_t *buffer);
  469. int64_t opal_console_read(int64_t term_number, int64_t *length,
  470. uint8_t *buffer);
  471. int64_t opal_console_write_buffer_space(int64_t term_number,
  472. int64_t *length);
  473. int64_t opal_rtc_read(uint32_t *year_month_day,
  474. uint64_t *hour_minute_second_millisecond);
  475. int64_t opal_rtc_write(uint32_t year_month_day,
  476. uint64_t hour_minute_second_millisecond);
  477. int64_t opal_cec_power_down(uint64_t request);
  478. int64_t opal_cec_reboot(void);
  479. int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
  480. int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
  481. int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
  482. int64_t opal_poll_events(uint64_t *outstanding_event_mask);
  483. int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
  484. uint64_t tce_mem_size);
  485. int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
  486. uint64_t tce_mem_size);
  487. int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
  488. uint64_t offset, uint8_t *data);
  489. int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
  490. uint64_t offset, uint16_t *data);
  491. int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
  492. uint64_t offset, uint32_t *data);
  493. int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
  494. uint64_t offset, uint8_t data);
  495. int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
  496. uint64_t offset, uint16_t data);
  497. int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
  498. uint64_t offset, uint32_t data);
  499. int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
  500. int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
  501. int64_t opal_register_exception_handler(uint64_t opal_exception,
  502. uint64_t handler_address,
  503. uint64_t glue_cache_line);
  504. int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
  505. uint8_t *freeze_state,
  506. uint16_t *pci_error_type,
  507. uint64_t *phb_status);
  508. int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
  509. uint64_t eeh_action_token);
  510. int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
  511. int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
  512. uint16_t window_num, uint16_t enable);
  513. int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
  514. uint16_t window_num,
  515. uint64_t starting_real_address,
  516. uint64_t starting_pci_address,
  517. uint16_t segment_size);
  518. int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
  519. uint16_t window_type, uint16_t window_num,
  520. uint16_t segment_num);
  521. int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
  522. uint64_t ivt_addr, uint64_t ivt_len,
  523. uint64_t reject_array_addr,
  524. uint64_t peltv_addr);
  525. int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
  526. uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
  527. uint8_t pe_action);
  528. int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
  529. uint8_t state);
  530. int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
  531. int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
  532. uint32_t state);
  533. int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
  534. uint8_t *p_bit, uint8_t *q_bit);
  535. int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
  536. uint8_t p_bit, uint8_t q_bit);
  537. int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
  538. int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
  539. uint32_t xive_num);
  540. int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
  541. int32_t *interrupt_source_number);
  542. int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
  543. uint8_t msi_range, uint32_t *msi_address,
  544. uint32_t *message_data);
  545. int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
  546. uint32_t xive_num, uint8_t msi_range,
  547. uint64_t *msi_address, uint32_t *message_data);
  548. int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
  549. int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
  550. int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
  551. int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
  552. uint16_t tce_levels, uint64_t tce_table_addr,
  553. uint64_t tce_table_size, uint64_t tce_page_size);
  554. int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
  555. uint16_t dma_window_number, uint64_t pci_start_addr,
  556. uint64_t pci_mem_size);
  557. int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
  558. int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
  559. uint64_t diag_buffer_len);
  560. int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
  561. uint64_t diag_buffer_len);
  562. int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
  563. uint64_t diag_buffer_len);
  564. int64_t opal_pci_fence_phb(uint64_t phb_id);
  565. int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
  566. int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
  567. int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
  568. int64_t opal_get_epow_status(uint64_t *status);
  569. int64_t opal_set_system_attention_led(uint8_t led_action);
  570. int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
  571. uint16_t *pci_error_type, uint16_t *severity);
  572. int64_t opal_pci_poll(uint64_t phb_id);
  573. int64_t opal_xscom_read(uint32_t gcid, uint32_t pcb_addr, uint64_t *val);
  574. int64_t opal_xscom_write(uint32_t gcid, uint32_t pcb_addr, uint64_t val);
  575. int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
  576. uint32_t addr, uint32_t data, uint32_t sz);
  577. int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
  578. uint32_t addr, uint32_t *data, uint32_t sz);
  579. /* Internal functions */
  580. extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
  581. extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
  582. extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
  583. extern void hvc_opal_init_early(void);
  584. /* Internal functions */
  585. extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
  586. int depth, void *data);
  587. extern int opal_notifier_register(struct notifier_block *nb);
  588. extern void opal_notifier_enable(void);
  589. extern void opal_notifier_disable(void);
  590. extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
  591. extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
  592. extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
  593. extern void hvc_opal_init_early(void);
  594. struct rtc_time;
  595. extern int opal_set_rtc_time(struct rtc_time *tm);
  596. extern void opal_get_rtc_time(struct rtc_time *tm);
  597. extern unsigned long opal_get_boot_time(void);
  598. extern void opal_nvram_init(void);
  599. extern int opal_machine_check(struct pt_regs *regs);
  600. extern void opal_shutdown(void);
  601. extern void opal_lpc_init(void);
  602. #endif /* __ASSEMBLY__ */
  603. #endif /* __OPAL_H */