Kconfig 7.9 KB

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  1. menu "Memory management options"
  2. config QUICKLIST
  3. def_bool y
  4. config MMU
  5. bool "Support for memory management hardware"
  6. depends on !CPU_SH2
  7. default y
  8. help
  9. Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
  10. boot on these systems, this option must not be set.
  11. On other systems (such as the SH-3 and 4) where an MMU exists,
  12. turning this off will boot the kernel on these machines with the
  13. MMU implicitly switched off.
  14. config PAGE_OFFSET
  15. hex
  16. default "0x80000000" if MMU && SUPERH32
  17. default "0x20000000" if MMU && SUPERH64
  18. default "0x00000000"
  19. config FORCE_MAX_ZONEORDER
  20. int "Maximum zone order"
  21. range 9 64 if PAGE_SIZE_16KB
  22. default "9" if PAGE_SIZE_16KB
  23. range 7 64 if PAGE_SIZE_64KB
  24. default "7" if PAGE_SIZE_64KB
  25. range 11 64
  26. default "14" if !MMU
  27. default "11"
  28. help
  29. The kernel memory allocator divides physically contiguous memory
  30. blocks into "zones", where each zone is a power of two number of
  31. pages. This option selects the largest power of two that the kernel
  32. keeps in the memory allocator. If you need to allocate very large
  33. blocks of physically contiguous memory, then you may need to
  34. increase this value.
  35. This config option is actually maximum order plus one. For example,
  36. a value of 11 means that the largest free memory block is 2^10 pages.
  37. The page size is not necessarily 4KB. Keep this in mind when
  38. choosing a value for this option.
  39. config MEMORY_START
  40. hex "Physical memory start address"
  41. default "0x08000000"
  42. ---help---
  43. Computers built with Hitachi SuperH processors always
  44. map the ROM starting at address zero. But the processor
  45. does not specify the range that RAM takes.
  46. The physical memory (RAM) start address will be automatically
  47. set to 08000000. Other platforms, such as the Solution Engine
  48. boards typically map RAM at 0C000000.
  49. Tweak this only when porting to a new machine which does not
  50. already have a defconfig. Changing it from the known correct
  51. value on any of the known systems will only lead to disaster.
  52. config MEMORY_SIZE
  53. hex "Physical memory size"
  54. default "0x04000000"
  55. help
  56. This sets the default memory size assumed by your SH kernel. It can
  57. be overridden as normal by the 'mem=' argument on the kernel command
  58. line. If unsure, consult your board specifications or just leave it
  59. as 0x04000000 which was the default value before this became
  60. configurable.
  61. # Physical addressing modes
  62. config 29BIT
  63. def_bool !32BIT
  64. depends on SUPERH32
  65. config 32BIT
  66. bool
  67. default y if CPU_SH5
  68. config PMB_ENABLE
  69. bool "Support 32-bit physical addressing through PMB"
  70. depends on MMU && EXPERIMENTAL && CPU_SH4A
  71. default y
  72. help
  73. If you say Y here, physical addressing will be extended to
  74. 32-bits through the SH-4A PMB. If this is not set, legacy
  75. 29-bit physical addressing will be used.
  76. choice
  77. prompt "PMB handling type"
  78. depends on PMB_ENABLE
  79. default PMB_FIXED
  80. config PMB
  81. bool "PMB"
  82. depends on MMU && EXPERIMENTAL && CPU_SH4A
  83. help
  84. If you say Y here, physical addressing will be extended to
  85. 32-bits through the SH-4A PMB. If this is not set, legacy
  86. 29-bit physical addressing will be used.
  87. config PMB_FIXED
  88. bool "fixed PMB"
  89. depends on MMU && EXPERIMENTAL && CPU_SH4A
  90. select 32BIT
  91. help
  92. If this option is enabled, fixed PMB mappings are inherited
  93. from the boot loader, and the kernel does not attempt dynamic
  94. management. This is the closest to legacy 29-bit physical mode,
  95. and allows systems to support up to 512MiB of system memory.
  96. endchoice
  97. config X2TLB
  98. bool "Enable extended TLB mode"
  99. depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
  100. help
  101. Selecting this option will enable the extended mode of the SH-X2
  102. TLB. For legacy SH-X behaviour and interoperability, say N. For
  103. all of the fun new features and a willingless to submit bug reports,
  104. say Y.
  105. config VSYSCALL
  106. bool "Support vsyscall page"
  107. depends on MMU && (CPU_SH3 || CPU_SH4)
  108. default y
  109. help
  110. This will enable support for the kernel mapping a vDSO page
  111. in process space, and subsequently handing down the entry point
  112. to the libc through the ELF auxiliary vector.
  113. From the kernel side this is used for the signal trampoline.
  114. For systems with an MMU that can afford to give up a page,
  115. (the default value) say Y.
  116. config NUMA
  117. bool "Non Uniform Memory Access (NUMA) Support"
  118. depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
  119. default n
  120. help
  121. Some SH systems have many various memories scattered around
  122. the address space, each with varying latencies. This enables
  123. support for these blocks by binding them to nodes and allowing
  124. memory policies to be used for prioritizing and controlling
  125. allocation behaviour.
  126. config NODES_SHIFT
  127. int
  128. default "3" if CPU_SUBTYPE_SHX3
  129. default "1"
  130. depends on NEED_MULTIPLE_NODES
  131. config ARCH_FLATMEM_ENABLE
  132. def_bool y
  133. depends on !NUMA
  134. config ARCH_SPARSEMEM_ENABLE
  135. def_bool y
  136. select SPARSEMEM_STATIC
  137. config ARCH_SPARSEMEM_DEFAULT
  138. def_bool y
  139. config MAX_ACTIVE_REGIONS
  140. int
  141. default "6" if (CPU_SUBTYPE_SHX3 && SPARSEMEM)
  142. default "2" if SPARSEMEM && (CPU_SUBTYPE_SH7722 || \
  143. CPU_SUBTYPE_SH7785)
  144. default "1"
  145. config ARCH_POPULATES_NODE_MAP
  146. def_bool y
  147. config ARCH_SELECT_MEMORY_MODEL
  148. def_bool y
  149. config ARCH_ENABLE_MEMORY_HOTPLUG
  150. def_bool y
  151. depends on SPARSEMEM && MMU
  152. config ARCH_ENABLE_MEMORY_HOTREMOVE
  153. def_bool y
  154. depends on SPARSEMEM && MMU
  155. config ARCH_MEMORY_PROBE
  156. def_bool y
  157. depends on MEMORY_HOTPLUG
  158. choice
  159. prompt "Page table layout"
  160. default PGTABLE_LEVELS_3 if X2TLB
  161. default PGTABLE_LEVELS_2
  162. config PGTABLE_LEVELS_2
  163. bool "2 Levels"
  164. help
  165. This is the default page table layout for all SuperH CPUs.
  166. config PGTABLE_LEVELS_3
  167. bool "3 Levels"
  168. depends on X2TLB
  169. help
  170. This enables a 3 level page table structure.
  171. endchoice
  172. choice
  173. prompt "Kernel page size"
  174. default PAGE_SIZE_8KB if X2TLB
  175. default PAGE_SIZE_4KB
  176. config PAGE_SIZE_4KB
  177. bool "4kB"
  178. depends on !MMU || !X2TLB || PGTABLE_LEVELS_3
  179. help
  180. This is the default page size used by all SuperH CPUs.
  181. config PAGE_SIZE_8KB
  182. bool "8kB"
  183. depends on !MMU || X2TLB
  184. help
  185. This enables 8kB pages as supported by SH-X2 and later MMUs.
  186. config PAGE_SIZE_16KB
  187. bool "16kB"
  188. depends on !MMU
  189. help
  190. This enables 16kB pages on MMU-less SH systems.
  191. config PAGE_SIZE_64KB
  192. bool "64kB"
  193. depends on !MMU || CPU_SH4 || CPU_SH5
  194. help
  195. This enables support for 64kB pages, possible on all SH-4
  196. CPUs and later.
  197. endchoice
  198. choice
  199. prompt "HugeTLB page size"
  200. depends on HUGETLB_PAGE
  201. default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
  202. default HUGETLB_PAGE_SIZE_64K
  203. config HUGETLB_PAGE_SIZE_64K
  204. bool "64kB"
  205. depends on !PAGE_SIZE_64KB
  206. config HUGETLB_PAGE_SIZE_256K
  207. bool "256kB"
  208. depends on X2TLB
  209. config HUGETLB_PAGE_SIZE_1MB
  210. bool "1MB"
  211. config HUGETLB_PAGE_SIZE_4MB
  212. bool "4MB"
  213. depends on X2TLB
  214. config HUGETLB_PAGE_SIZE_64MB
  215. bool "64MB"
  216. depends on X2TLB
  217. config HUGETLB_PAGE_SIZE_512MB
  218. bool "512MB"
  219. depends on CPU_SH5
  220. endchoice
  221. source "mm/Kconfig"
  222. config SCHED_MC
  223. bool "Multi-core scheduler support"
  224. depends on SMP
  225. default y
  226. help
  227. Multi-core scheduler support improves the CPU scheduler's decision
  228. making when dealing with multi-core CPU chips at a cost of slightly
  229. increased overhead in some places. If unsure say N here.
  230. endmenu
  231. menu "Cache configuration"
  232. config SH7705_CACHE_32KB
  233. bool "Enable 32KB cache size for SH7705"
  234. depends on CPU_SUBTYPE_SH7705
  235. default y
  236. choice
  237. prompt "Cache mode"
  238. default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4 || CPU_SH5
  239. default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
  240. config CACHE_WRITEBACK
  241. bool "Write-back"
  242. config CACHE_WRITETHROUGH
  243. bool "Write-through"
  244. help
  245. Selecting this option will configure the caches in write-through
  246. mode, as opposed to the default write-back configuration.
  247. Since there's sill some aliasing issues on SH-4, this option will
  248. unfortunately still require the majority of flushing functions to
  249. be implemented to deal with aliasing.
  250. If unsure, say N.
  251. config CACHE_OFF
  252. bool "Off"
  253. endchoice
  254. endmenu