coda.c 56 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/of.h>
  25. #include <mach/iram.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-ioctl.h>
  29. #include <media/v4l2-mem2mem.h>
  30. #include <media/videobuf2-core.h>
  31. #include <media/videobuf2-dma-contig.h>
  32. #include "coda.h"
  33. #define CODA_NAME "coda"
  34. #define CODA_MAX_INSTANCES 4
  35. #define CODA_FMO_BUF_SIZE 32
  36. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  37. #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  38. #define CODA_PARA_BUF_SIZE (10 * 1024)
  39. #define CODA_ISRAM_SIZE (2048 * 2)
  40. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  41. #define CODA_MAX_FRAMEBUFFERS 2
  42. #define MAX_W 720
  43. #define MAX_H 576
  44. #define CODA_MAX_FRAME_SIZE 0x90000
  45. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  46. #define CODA_DEFAULT_GAMMA 4096
  47. #define MIN_W 176
  48. #define MIN_H 144
  49. #define MAX_W 720
  50. #define MAX_H 576
  51. #define S_ALIGN 1 /* multiple of 2 */
  52. #define W_ALIGN 1 /* multiple of 2 */
  53. #define H_ALIGN 1 /* multiple of 2 */
  54. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  55. static int coda_debug;
  56. module_param(coda_debug, int, 0);
  57. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  58. enum {
  59. V4L2_M2M_SRC = 0,
  60. V4L2_M2M_DST = 1,
  61. };
  62. enum coda_fmt_type {
  63. CODA_FMT_ENC,
  64. CODA_FMT_RAW,
  65. };
  66. enum coda_inst_type {
  67. CODA_INST_ENCODER,
  68. CODA_INST_DECODER,
  69. };
  70. enum coda_product {
  71. CODA_DX6 = 0xf001,
  72. CODA_7541 = 0xf012,
  73. };
  74. struct coda_fmt {
  75. char *name;
  76. u32 fourcc;
  77. enum coda_fmt_type type;
  78. };
  79. struct coda_devtype {
  80. char *firmware;
  81. enum coda_product product;
  82. struct coda_fmt *formats;
  83. unsigned int num_formats;
  84. size_t workbuf_size;
  85. };
  86. /* Per-queue, driver-specific private data */
  87. struct coda_q_data {
  88. unsigned int width;
  89. unsigned int height;
  90. unsigned int sizeimage;
  91. struct coda_fmt *fmt;
  92. };
  93. struct coda_aux_buf {
  94. void *vaddr;
  95. dma_addr_t paddr;
  96. u32 size;
  97. };
  98. struct coda_dev {
  99. struct v4l2_device v4l2_dev;
  100. struct video_device vfd;
  101. struct platform_device *plat_dev;
  102. const struct coda_devtype *devtype;
  103. void __iomem *regs_base;
  104. struct clk *clk_per;
  105. struct clk *clk_ahb;
  106. struct coda_aux_buf codebuf;
  107. struct coda_aux_buf workbuf;
  108. long unsigned int iram_paddr;
  109. spinlock_t irqlock;
  110. struct mutex dev_mutex;
  111. struct v4l2_m2m_dev *m2m_dev;
  112. struct vb2_alloc_ctx *alloc_ctx;
  113. struct list_head instances;
  114. unsigned long instance_mask;
  115. struct delayed_work timeout;
  116. struct completion done;
  117. };
  118. struct coda_params {
  119. u8 rot_mode;
  120. u8 h264_intra_qp;
  121. u8 h264_inter_qp;
  122. u8 mpeg4_intra_qp;
  123. u8 mpeg4_inter_qp;
  124. u8 gop_size;
  125. int codec_mode;
  126. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  127. u32 framerate;
  128. u16 bitrate;
  129. u32 slice_max_bits;
  130. u32 slice_max_mb;
  131. };
  132. struct coda_ctx {
  133. struct coda_dev *dev;
  134. struct list_head list;
  135. int aborting;
  136. int rawstreamon;
  137. int compstreamon;
  138. u32 isequence;
  139. struct coda_q_data q_data[2];
  140. enum coda_inst_type inst_type;
  141. enum v4l2_colorspace colorspace;
  142. struct coda_params params;
  143. struct v4l2_m2m_ctx *m2m_ctx;
  144. struct v4l2_ctrl_handler ctrls;
  145. struct v4l2_fh fh;
  146. int gopcounter;
  147. char vpu_header[3][64];
  148. int vpu_header_size[3];
  149. struct coda_aux_buf parabuf;
  150. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  151. int num_internal_frames;
  152. int idx;
  153. };
  154. static u8 coda_filler_nal[] = { 0x00, 0x00, 0x00, 0x01, 0x0c,
  155. 0xff, 0xff, 0xff, 0xff, 0xff};
  156. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  157. {
  158. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  159. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  160. writel(data, dev->regs_base + reg);
  161. }
  162. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  163. {
  164. u32 data;
  165. data = readl(dev->regs_base + reg);
  166. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  167. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  168. return data;
  169. }
  170. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  171. {
  172. return coda_read(dev, CODA_REG_BIT_BUSY);
  173. }
  174. static inline int coda_is_initialized(struct coda_dev *dev)
  175. {
  176. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  177. }
  178. static int coda_wait_timeout(struct coda_dev *dev)
  179. {
  180. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  181. while (coda_isbusy(dev)) {
  182. if (time_after(jiffies, timeout))
  183. return -ETIMEDOUT;
  184. }
  185. return 0;
  186. }
  187. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  188. {
  189. struct coda_dev *dev = ctx->dev;
  190. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  191. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  192. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  193. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  194. }
  195. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  196. {
  197. struct coda_dev *dev = ctx->dev;
  198. coda_command_async(ctx, cmd);
  199. return coda_wait_timeout(dev);
  200. }
  201. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  202. enum v4l2_buf_type type)
  203. {
  204. switch (type) {
  205. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  206. return &(ctx->q_data[V4L2_M2M_SRC]);
  207. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  208. return &(ctx->q_data[V4L2_M2M_DST]);
  209. default:
  210. BUG();
  211. }
  212. return NULL;
  213. }
  214. /*
  215. * Add one array of supported formats for each version of Coda:
  216. * i.MX27 -> codadx6
  217. * i.MX51 -> coda7
  218. * i.MX6 -> coda960
  219. */
  220. static struct coda_fmt codadx6_formats[] = {
  221. {
  222. .name = "YUV 4:2:0 Planar",
  223. .fourcc = V4L2_PIX_FMT_YUV420,
  224. .type = CODA_FMT_RAW,
  225. },
  226. {
  227. .name = "H264 Encoded Stream",
  228. .fourcc = V4L2_PIX_FMT_H264,
  229. .type = CODA_FMT_ENC,
  230. },
  231. {
  232. .name = "MPEG4 Encoded Stream",
  233. .fourcc = V4L2_PIX_FMT_MPEG4,
  234. .type = CODA_FMT_ENC,
  235. },
  236. };
  237. static struct coda_fmt coda7_formats[] = {
  238. {
  239. .name = "YUV 4:2:0 Planar",
  240. .fourcc = V4L2_PIX_FMT_YUV420,
  241. .type = CODA_FMT_RAW,
  242. },
  243. {
  244. .name = "H264 Encoded Stream",
  245. .fourcc = V4L2_PIX_FMT_H264,
  246. .type = CODA_FMT_ENC,
  247. },
  248. {
  249. .name = "MPEG4 Encoded Stream",
  250. .fourcc = V4L2_PIX_FMT_MPEG4,
  251. .type = CODA_FMT_ENC,
  252. },
  253. };
  254. static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
  255. {
  256. struct coda_fmt *formats = dev->devtype->formats;
  257. int num_formats = dev->devtype->num_formats;
  258. unsigned int k;
  259. for (k = 0; k < num_formats; k++) {
  260. if (formats[k].fourcc == f->fmt.pix.pixelformat)
  261. break;
  262. }
  263. if (k == num_formats)
  264. return NULL;
  265. return &formats[k];
  266. }
  267. /*
  268. * V4L2 ioctl() operations.
  269. */
  270. static int vidioc_querycap(struct file *file, void *priv,
  271. struct v4l2_capability *cap)
  272. {
  273. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  274. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  275. strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
  276. /*
  277. * This is only a mem-to-mem video device. The capture and output
  278. * device capability flags are left only for backward compatibility
  279. * and are scheduled for removal.
  280. */
  281. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  282. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  283. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  284. return 0;
  285. }
  286. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  287. enum coda_fmt_type type)
  288. {
  289. struct coda_ctx *ctx = fh_to_ctx(priv);
  290. struct coda_dev *dev = ctx->dev;
  291. struct coda_fmt *formats = dev->devtype->formats;
  292. struct coda_fmt *fmt;
  293. int num_formats = dev->devtype->num_formats;
  294. int i, num = 0;
  295. for (i = 0; i < num_formats; i++) {
  296. if (formats[i].type == type) {
  297. if (num == f->index)
  298. break;
  299. ++num;
  300. }
  301. }
  302. if (i < num_formats) {
  303. fmt = &formats[i];
  304. strlcpy(f->description, fmt->name, sizeof(f->description));
  305. f->pixelformat = fmt->fourcc;
  306. return 0;
  307. }
  308. /* Format not found */
  309. return -EINVAL;
  310. }
  311. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  312. struct v4l2_fmtdesc *f)
  313. {
  314. return enum_fmt(priv, f, CODA_FMT_ENC);
  315. }
  316. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  317. struct v4l2_fmtdesc *f)
  318. {
  319. return enum_fmt(priv, f, CODA_FMT_RAW);
  320. }
  321. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  322. {
  323. struct vb2_queue *vq;
  324. struct coda_q_data *q_data;
  325. struct coda_ctx *ctx = fh_to_ctx(priv);
  326. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  327. if (!vq)
  328. return -EINVAL;
  329. q_data = get_q_data(ctx, f->type);
  330. f->fmt.pix.field = V4L2_FIELD_NONE;
  331. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  332. f->fmt.pix.width = q_data->width;
  333. f->fmt.pix.height = q_data->height;
  334. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  335. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  336. else /* encoded formats h.264/mpeg4 */
  337. f->fmt.pix.bytesperline = 0;
  338. f->fmt.pix.sizeimage = q_data->sizeimage;
  339. f->fmt.pix.colorspace = ctx->colorspace;
  340. return 0;
  341. }
  342. static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
  343. {
  344. enum v4l2_field field;
  345. field = f->fmt.pix.field;
  346. if (field == V4L2_FIELD_ANY)
  347. field = V4L2_FIELD_NONE;
  348. else if (V4L2_FIELD_NONE != field)
  349. return -EINVAL;
  350. /* V4L2 specification suggests the driver corrects the format struct
  351. * if any of the dimensions is unsupported */
  352. f->fmt.pix.field = field;
  353. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  354. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  355. W_ALIGN, &f->fmt.pix.height,
  356. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  357. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  358. f->fmt.pix.sizeimage = f->fmt.pix.width *
  359. f->fmt.pix.height * 3 / 2;
  360. } else { /*encoded formats h.264/mpeg4 */
  361. f->fmt.pix.bytesperline = 0;
  362. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  363. }
  364. return 0;
  365. }
  366. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  367. struct v4l2_format *f)
  368. {
  369. int ret;
  370. struct coda_fmt *fmt;
  371. struct coda_ctx *ctx = fh_to_ctx(priv);
  372. fmt = find_format(ctx->dev, f);
  373. /*
  374. * Since decoding support is not implemented yet do not allow
  375. * CODA_FMT_RAW formats in the capture interface.
  376. */
  377. if (!fmt || !(fmt->type == CODA_FMT_ENC))
  378. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  379. f->fmt.pix.colorspace = ctx->colorspace;
  380. ret = vidioc_try_fmt(ctx->dev, f);
  381. if (ret < 0)
  382. return ret;
  383. return 0;
  384. }
  385. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  386. struct v4l2_format *f)
  387. {
  388. struct coda_ctx *ctx = fh_to_ctx(priv);
  389. struct coda_fmt *fmt;
  390. int ret;
  391. fmt = find_format(ctx->dev, f);
  392. /*
  393. * Since decoding support is not implemented yet do not allow
  394. * CODA_FMT formats in the capture interface.
  395. */
  396. if (!fmt || !(fmt->type == CODA_FMT_RAW))
  397. f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
  398. if (!f->fmt.pix.colorspace)
  399. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  400. ret = vidioc_try_fmt(ctx->dev, f);
  401. if (ret < 0)
  402. return ret;
  403. return 0;
  404. }
  405. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  406. {
  407. struct coda_q_data *q_data;
  408. struct vb2_queue *vq;
  409. int ret;
  410. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  411. if (!vq)
  412. return -EINVAL;
  413. q_data = get_q_data(ctx, f->type);
  414. if (!q_data)
  415. return -EINVAL;
  416. if (vb2_is_busy(vq)) {
  417. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  418. return -EBUSY;
  419. }
  420. ret = vidioc_try_fmt(ctx->dev, f);
  421. if (ret)
  422. return ret;
  423. q_data->fmt = find_format(ctx->dev, f);
  424. q_data->width = f->fmt.pix.width;
  425. q_data->height = f->fmt.pix.height;
  426. q_data->sizeimage = f->fmt.pix.sizeimage;
  427. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  428. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  429. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  430. return 0;
  431. }
  432. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  433. struct v4l2_format *f)
  434. {
  435. int ret;
  436. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  437. if (ret)
  438. return ret;
  439. return vidioc_s_fmt(fh_to_ctx(priv), f);
  440. }
  441. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  442. struct v4l2_format *f)
  443. {
  444. struct coda_ctx *ctx = fh_to_ctx(priv);
  445. int ret;
  446. ret = vidioc_try_fmt_vid_out(file, priv, f);
  447. if (ret)
  448. return ret;
  449. ret = vidioc_s_fmt(ctx, f);
  450. if (ret)
  451. ctx->colorspace = f->fmt.pix.colorspace;
  452. return ret;
  453. }
  454. static int vidioc_reqbufs(struct file *file, void *priv,
  455. struct v4l2_requestbuffers *reqbufs)
  456. {
  457. struct coda_ctx *ctx = fh_to_ctx(priv);
  458. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  459. }
  460. static int vidioc_querybuf(struct file *file, void *priv,
  461. struct v4l2_buffer *buf)
  462. {
  463. struct coda_ctx *ctx = fh_to_ctx(priv);
  464. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  465. }
  466. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  467. {
  468. struct coda_ctx *ctx = fh_to_ctx(priv);
  469. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  470. }
  471. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  472. {
  473. struct coda_ctx *ctx = fh_to_ctx(priv);
  474. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  475. }
  476. static int vidioc_streamon(struct file *file, void *priv,
  477. enum v4l2_buf_type type)
  478. {
  479. struct coda_ctx *ctx = fh_to_ctx(priv);
  480. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  481. }
  482. static int vidioc_streamoff(struct file *file, void *priv,
  483. enum v4l2_buf_type type)
  484. {
  485. struct coda_ctx *ctx = fh_to_ctx(priv);
  486. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  487. }
  488. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  489. .vidioc_querycap = vidioc_querycap,
  490. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  491. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  492. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  493. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  494. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  495. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  496. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  497. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  498. .vidioc_reqbufs = vidioc_reqbufs,
  499. .vidioc_querybuf = vidioc_querybuf,
  500. .vidioc_qbuf = vidioc_qbuf,
  501. .vidioc_dqbuf = vidioc_dqbuf,
  502. .vidioc_streamon = vidioc_streamon,
  503. .vidioc_streamoff = vidioc_streamoff,
  504. };
  505. /*
  506. * Mem-to-mem operations.
  507. */
  508. static void coda_device_run(void *m2m_priv)
  509. {
  510. struct coda_ctx *ctx = m2m_priv;
  511. struct coda_q_data *q_data_src, *q_data_dst;
  512. struct vb2_buffer *src_buf, *dst_buf;
  513. struct coda_dev *dev = ctx->dev;
  514. int force_ipicture;
  515. int quant_param = 0;
  516. u32 picture_y, picture_cb, picture_cr;
  517. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  518. u32 dst_fourcc;
  519. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  520. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  521. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  522. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  523. dst_fourcc = q_data_dst->fmt->fourcc;
  524. src_buf->v4l2_buf.sequence = ctx->isequence;
  525. dst_buf->v4l2_buf.sequence = ctx->isequence;
  526. ctx->isequence++;
  527. /*
  528. * Workaround coda firmware BUG that only marks the first
  529. * frame as IDR. This is a problem for some decoders that can't
  530. * recover when a frame is lost.
  531. */
  532. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  533. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  534. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  535. } else {
  536. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  537. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  538. }
  539. /*
  540. * Copy headers at the beginning of the first frame for H.264 only.
  541. * In MPEG4 they are already copied by the coda.
  542. */
  543. if (src_buf->v4l2_buf.sequence == 0) {
  544. pic_stream_buffer_addr =
  545. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  546. ctx->vpu_header_size[0] +
  547. ctx->vpu_header_size[1] +
  548. ctx->vpu_header_size[2];
  549. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  550. ctx->vpu_header_size[0] -
  551. ctx->vpu_header_size[1] -
  552. ctx->vpu_header_size[2];
  553. memcpy(vb2_plane_vaddr(dst_buf, 0),
  554. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  555. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  556. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  557. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  558. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  559. ctx->vpu_header_size[2]);
  560. } else {
  561. pic_stream_buffer_addr =
  562. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  563. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  564. }
  565. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  566. force_ipicture = 1;
  567. switch (dst_fourcc) {
  568. case V4L2_PIX_FMT_H264:
  569. quant_param = ctx->params.h264_intra_qp;
  570. break;
  571. case V4L2_PIX_FMT_MPEG4:
  572. quant_param = ctx->params.mpeg4_intra_qp;
  573. break;
  574. default:
  575. v4l2_warn(&ctx->dev->v4l2_dev,
  576. "cannot set intra qp, fmt not supported\n");
  577. break;
  578. }
  579. } else {
  580. force_ipicture = 0;
  581. switch (dst_fourcc) {
  582. case V4L2_PIX_FMT_H264:
  583. quant_param = ctx->params.h264_inter_qp;
  584. break;
  585. case V4L2_PIX_FMT_MPEG4:
  586. quant_param = ctx->params.mpeg4_inter_qp;
  587. break;
  588. default:
  589. v4l2_warn(&ctx->dev->v4l2_dev,
  590. "cannot set inter qp, fmt not supported\n");
  591. break;
  592. }
  593. }
  594. /* submit */
  595. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  596. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  597. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  598. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  599. picture_cr = picture_cb + q_data_src->width / 2 *
  600. q_data_src->height / 2;
  601. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  602. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  603. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  604. coda_write(dev, force_ipicture << 1 & 0x2,
  605. CODA_CMD_ENC_PIC_OPTION);
  606. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  607. coda_write(dev, pic_stream_buffer_size / 1024,
  608. CODA_CMD_ENC_PIC_BB_SIZE);
  609. if (dev->devtype->product == CODA_7541) {
  610. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  611. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  612. CODA7_REG_BIT_AXI_SRAM_USE);
  613. }
  614. /* 1 second timeout in case CODA locks up */
  615. schedule_delayed_work(&dev->timeout, HZ);
  616. INIT_COMPLETION(dev->done);
  617. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  618. }
  619. static int coda_job_ready(void *m2m_priv)
  620. {
  621. struct coda_ctx *ctx = m2m_priv;
  622. /*
  623. * For both 'P' and 'key' frame cases 1 picture
  624. * and 1 frame are needed.
  625. */
  626. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
  627. !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  628. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  629. "not ready: not enough video buffers.\n");
  630. return 0;
  631. }
  632. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  633. "job ready\n");
  634. return 1;
  635. }
  636. static void coda_job_abort(void *priv)
  637. {
  638. struct coda_ctx *ctx = priv;
  639. struct coda_dev *dev = ctx->dev;
  640. ctx->aborting = 1;
  641. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  642. "Aborting task\n");
  643. v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
  644. }
  645. static void coda_lock(void *m2m_priv)
  646. {
  647. struct coda_ctx *ctx = m2m_priv;
  648. struct coda_dev *pcdev = ctx->dev;
  649. mutex_lock(&pcdev->dev_mutex);
  650. }
  651. static void coda_unlock(void *m2m_priv)
  652. {
  653. struct coda_ctx *ctx = m2m_priv;
  654. struct coda_dev *pcdev = ctx->dev;
  655. mutex_unlock(&pcdev->dev_mutex);
  656. }
  657. static struct v4l2_m2m_ops coda_m2m_ops = {
  658. .device_run = coda_device_run,
  659. .job_ready = coda_job_ready,
  660. .job_abort = coda_job_abort,
  661. .lock = coda_lock,
  662. .unlock = coda_unlock,
  663. };
  664. static void set_default_params(struct coda_ctx *ctx)
  665. {
  666. struct coda_dev *dev = ctx->dev;
  667. ctx->params.codec_mode = CODA_MODE_INVALID;
  668. ctx->colorspace = V4L2_COLORSPACE_REC709;
  669. ctx->params.framerate = 30;
  670. ctx->aborting = 0;
  671. /* Default formats for output and input queues */
  672. ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
  673. ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
  674. ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
  675. ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
  676. ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
  677. ctx->q_data[V4L2_M2M_DST].width = MAX_W;
  678. ctx->q_data[V4L2_M2M_DST].height = MAX_H;
  679. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  680. }
  681. /*
  682. * Queue operations
  683. */
  684. static int coda_queue_setup(struct vb2_queue *vq,
  685. const struct v4l2_format *fmt,
  686. unsigned int *nbuffers, unsigned int *nplanes,
  687. unsigned int sizes[], void *alloc_ctxs[])
  688. {
  689. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  690. struct coda_q_data *q_data;
  691. unsigned int size;
  692. q_data = get_q_data(ctx, vq->type);
  693. size = q_data->sizeimage;
  694. *nplanes = 1;
  695. sizes[0] = size;
  696. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  697. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  698. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  699. return 0;
  700. }
  701. static int coda_buf_prepare(struct vb2_buffer *vb)
  702. {
  703. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  704. struct coda_q_data *q_data;
  705. q_data = get_q_data(ctx, vb->vb2_queue->type);
  706. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  707. v4l2_warn(&ctx->dev->v4l2_dev,
  708. "%s data will not fit into plane (%lu < %lu)\n",
  709. __func__, vb2_plane_size(vb, 0),
  710. (long)q_data->sizeimage);
  711. return -EINVAL;
  712. }
  713. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  714. return 0;
  715. }
  716. static void coda_buf_queue(struct vb2_buffer *vb)
  717. {
  718. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  719. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  720. }
  721. static void coda_wait_prepare(struct vb2_queue *q)
  722. {
  723. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  724. coda_unlock(ctx);
  725. }
  726. static void coda_wait_finish(struct vb2_queue *q)
  727. {
  728. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  729. coda_lock(ctx);
  730. }
  731. static void coda_free_framebuffers(struct coda_ctx *ctx)
  732. {
  733. int i;
  734. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
  735. if (ctx->internal_frames[i].vaddr) {
  736. dma_free_coherent(&ctx->dev->plat_dev->dev,
  737. ctx->internal_frames[i].size,
  738. ctx->internal_frames[i].vaddr,
  739. ctx->internal_frames[i].paddr);
  740. ctx->internal_frames[i].vaddr = NULL;
  741. }
  742. }
  743. }
  744. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  745. {
  746. struct coda_dev *dev = ctx->dev;
  747. int height = q_data->height;
  748. int width = q_data->width;
  749. u32 *p;
  750. int i;
  751. /* Allocate frame buffers */
  752. ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
  753. for (i = 0; i < ctx->num_internal_frames; i++) {
  754. ctx->internal_frames[i].size = q_data->sizeimage;
  755. if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
  756. ctx->internal_frames[i].size += width / 2 * height / 2;
  757. ctx->internal_frames[i].vaddr = dma_alloc_coherent(
  758. &dev->plat_dev->dev, ctx->internal_frames[i].size,
  759. &ctx->internal_frames[i].paddr, GFP_KERNEL);
  760. if (!ctx->internal_frames[i].vaddr) {
  761. coda_free_framebuffers(ctx);
  762. return -ENOMEM;
  763. }
  764. }
  765. /* Register frame buffers in the parameter buffer */
  766. p = ctx->parabuf.vaddr;
  767. if (dev->devtype->product == CODA_DX6) {
  768. for (i = 0; i < ctx->num_internal_frames; i++) {
  769. p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
  770. p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
  771. p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
  772. }
  773. } else {
  774. for (i = 0; i < ctx->num_internal_frames; i += 2) {
  775. p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
  776. p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
  777. p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
  778. if (fourcc == V4L2_PIX_FMT_H264)
  779. p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
  780. if (i + 1 < ctx->num_internal_frames) {
  781. p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
  782. p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
  783. p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
  784. if (fourcc == V4L2_PIX_FMT_H264)
  785. p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
  786. }
  787. }
  788. }
  789. return 0;
  790. }
  791. static int coda_h264_padding(int size, char *p)
  792. {
  793. int size_align = size & ~0x3;
  794. int filler_size = ARRAY_SIZE(coda_filler_nal);
  795. int nal_size;
  796. int diff;
  797. diff = size - size_align;
  798. if (diff == 0)
  799. return 0;
  800. nal_size = filler_size + 2 - diff;
  801. if (nal_size > filler_size)
  802. nal_size -= 4;
  803. memcpy(p, coda_filler_nal, nal_size);
  804. /* Add rbsp stop bit and trailing at the end */
  805. *(p + nal_size - 1) = 0x80;
  806. return nal_size;
  807. }
  808. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  809. {
  810. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  811. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  812. u32 bitstream_buf, bitstream_size;
  813. struct coda_dev *dev = ctx->dev;
  814. struct coda_q_data *q_data_src, *q_data_dst;
  815. struct vb2_buffer *buf;
  816. u32 dst_fourcc;
  817. u32 value;
  818. int ret;
  819. if (count < 1)
  820. return -EINVAL;
  821. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  822. ctx->rawstreamon = 1;
  823. else
  824. ctx->compstreamon = 1;
  825. /* Don't start the coda unless both queues are on */
  826. if (!(ctx->rawstreamon & ctx->compstreamon))
  827. return 0;
  828. if (coda_isbusy(dev))
  829. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0)
  830. return -EBUSY;
  831. ctx->gopcounter = ctx->params.gop_size - 1;
  832. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  833. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  834. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  835. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  836. bitstream_size = q_data_dst->sizeimage;
  837. dst_fourcc = q_data_dst->fmt->fourcc;
  838. /* Find out whether coda must encode or decode */
  839. if (q_data_src->fmt->type == CODA_FMT_RAW &&
  840. q_data_dst->fmt->type == CODA_FMT_ENC) {
  841. ctx->inst_type = CODA_INST_ENCODER;
  842. } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
  843. q_data_dst->fmt->type == CODA_FMT_RAW) {
  844. ctx->inst_type = CODA_INST_DECODER;
  845. v4l2_err(v4l2_dev, "decoding not supported.\n");
  846. return -EINVAL;
  847. } else {
  848. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  849. return -EINVAL;
  850. }
  851. if (!coda_is_initialized(dev)) {
  852. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  853. return -EFAULT;
  854. }
  855. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  856. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
  857. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
  858. switch (dev->devtype->product) {
  859. case CODA_DX6:
  860. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  861. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  862. break;
  863. default:
  864. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  865. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  866. }
  867. if (dev->devtype->product == CODA_DX6) {
  868. /* Configure the coda */
  869. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  870. }
  871. /* Could set rotation here if needed */
  872. switch (dev->devtype->product) {
  873. case CODA_DX6:
  874. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  875. break;
  876. default:
  877. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  878. }
  879. value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  880. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  881. coda_write(dev, ctx->params.framerate,
  882. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  883. switch (dst_fourcc) {
  884. case V4L2_PIX_FMT_MPEG4:
  885. if (dev->devtype->product == CODA_DX6)
  886. ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
  887. else
  888. ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
  889. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  890. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  891. break;
  892. case V4L2_PIX_FMT_H264:
  893. if (dev->devtype->product == CODA_DX6)
  894. ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
  895. else
  896. ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
  897. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  898. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  899. break;
  900. default:
  901. v4l2_err(v4l2_dev,
  902. "dst format (0x%08x) invalid.\n", dst_fourcc);
  903. return -EINVAL;
  904. }
  905. switch (ctx->params.slice_mode) {
  906. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  907. value = 0;
  908. break;
  909. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  910. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  911. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  912. value |= 1 & CODA_SLICING_MODE_MASK;
  913. break;
  914. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  915. value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  916. value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  917. value |= 1 & CODA_SLICING_MODE_MASK;
  918. break;
  919. }
  920. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  921. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  922. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  923. if (ctx->params.bitrate) {
  924. /* Rate control enabled */
  925. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  926. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  927. } else {
  928. value = 0;
  929. }
  930. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  931. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  932. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  933. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  934. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  935. /* set default gamma */
  936. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  937. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  938. value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
  939. value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
  940. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  941. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  942. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  943. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  944. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  945. if (dev->devtype->product == CODA_DX6) {
  946. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  947. } else {
  948. coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  949. coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  950. }
  951. }
  952. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  953. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  954. return -ETIMEDOUT;
  955. }
  956. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
  957. return -EFAULT;
  958. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  959. if (ret < 0)
  960. return ret;
  961. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  962. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  963. if (dev->devtype->product != CODA_DX6) {
  964. coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  965. coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  966. coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  967. coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  968. coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  969. coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  970. }
  971. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  972. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  973. return -ETIMEDOUT;
  974. }
  975. /* Save stream headers */
  976. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  977. switch (dst_fourcc) {
  978. case V4L2_PIX_FMT_H264:
  979. /*
  980. * Get SPS in the first frame and copy it to an
  981. * intermediate buffer.
  982. */
  983. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  984. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  985. coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
  986. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  987. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  988. return -ETIMEDOUT;
  989. }
  990. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  991. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  992. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  993. ctx->vpu_header_size[0]);
  994. /*
  995. * Get PPS in the first frame and copy it to an
  996. * intermediate buffer.
  997. */
  998. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  999. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1000. coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
  1001. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1002. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1003. return -ETIMEDOUT;
  1004. }
  1005. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1006. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1007. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1008. ctx->vpu_header_size[1]);
  1009. /*
  1010. * Length of H.264 headers is variable and thus it might not be
  1011. * aligned for the coda to append the encoded frame. In that is
  1012. * the case a filler NAL must be added to header 2.
  1013. */
  1014. ctx->vpu_header_size[2] = coda_h264_padding(
  1015. (ctx->vpu_header_size[0] +
  1016. ctx->vpu_header_size[1]),
  1017. ctx->vpu_header[2]);
  1018. break;
  1019. case V4L2_PIX_FMT_MPEG4:
  1020. /*
  1021. * Get VOS in the first frame and copy it to an
  1022. * intermediate buffer
  1023. */
  1024. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1025. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1026. coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
  1027. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1028. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1029. return -ETIMEDOUT;
  1030. }
  1031. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1032. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1033. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1034. ctx->vpu_header_size[0]);
  1035. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1036. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1037. coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
  1038. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1039. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1040. return -ETIMEDOUT;
  1041. }
  1042. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1043. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1044. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1045. ctx->vpu_header_size[1]);
  1046. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1047. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1048. coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
  1049. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1050. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1051. return -ETIMEDOUT;
  1052. }
  1053. ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1054. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1055. memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
  1056. ctx->vpu_header_size[2]);
  1057. break;
  1058. default:
  1059. /* No more formats need to save headers at the moment */
  1060. break;
  1061. }
  1062. return 0;
  1063. }
  1064. static int coda_stop_streaming(struct vb2_queue *q)
  1065. {
  1066. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1067. struct coda_dev *dev = ctx->dev;
  1068. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1069. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1070. "%s: output\n", __func__);
  1071. ctx->rawstreamon = 0;
  1072. } else {
  1073. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1074. "%s: capture\n", __func__);
  1075. ctx->compstreamon = 0;
  1076. }
  1077. /* Don't stop the coda unless both queues are off */
  1078. if (ctx->rawstreamon || ctx->compstreamon)
  1079. return 0;
  1080. if (coda_isbusy(dev)) {
  1081. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0) {
  1082. v4l2_warn(&dev->v4l2_dev,
  1083. "%s: timeout, sending SEQ_END anyway\n", __func__);
  1084. }
  1085. }
  1086. cancel_delayed_work(&dev->timeout);
  1087. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1088. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1089. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1090. v4l2_err(&dev->v4l2_dev,
  1091. "CODA_COMMAND_SEQ_END failed\n");
  1092. return -ETIMEDOUT;
  1093. }
  1094. coda_free_framebuffers(ctx);
  1095. return 0;
  1096. }
  1097. static struct vb2_ops coda_qops = {
  1098. .queue_setup = coda_queue_setup,
  1099. .buf_prepare = coda_buf_prepare,
  1100. .buf_queue = coda_buf_queue,
  1101. .wait_prepare = coda_wait_prepare,
  1102. .wait_finish = coda_wait_finish,
  1103. .start_streaming = coda_start_streaming,
  1104. .stop_streaming = coda_stop_streaming,
  1105. };
  1106. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1107. {
  1108. struct coda_ctx *ctx =
  1109. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1110. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1111. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1112. switch (ctrl->id) {
  1113. case V4L2_CID_HFLIP:
  1114. if (ctrl->val)
  1115. ctx->params.rot_mode |= CODA_MIR_HOR;
  1116. else
  1117. ctx->params.rot_mode &= ~CODA_MIR_HOR;
  1118. break;
  1119. case V4L2_CID_VFLIP:
  1120. if (ctrl->val)
  1121. ctx->params.rot_mode |= CODA_MIR_VER;
  1122. else
  1123. ctx->params.rot_mode &= ~CODA_MIR_VER;
  1124. break;
  1125. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1126. ctx->params.bitrate = ctrl->val / 1000;
  1127. break;
  1128. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1129. ctx->params.gop_size = ctrl->val;
  1130. break;
  1131. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1132. ctx->params.h264_intra_qp = ctrl->val;
  1133. break;
  1134. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1135. ctx->params.h264_inter_qp = ctrl->val;
  1136. break;
  1137. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1138. ctx->params.mpeg4_intra_qp = ctrl->val;
  1139. break;
  1140. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1141. ctx->params.mpeg4_inter_qp = ctrl->val;
  1142. break;
  1143. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1144. ctx->params.slice_mode = ctrl->val;
  1145. break;
  1146. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1147. ctx->params.slice_max_mb = ctrl->val;
  1148. break;
  1149. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
  1150. ctx->params.slice_max_bits = ctrl->val * 8;
  1151. break;
  1152. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1153. break;
  1154. default:
  1155. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1156. "Invalid control, id=%d, val=%d\n",
  1157. ctrl->id, ctrl->val);
  1158. return -EINVAL;
  1159. }
  1160. return 0;
  1161. }
  1162. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1163. .s_ctrl = coda_s_ctrl,
  1164. };
  1165. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1166. {
  1167. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1168. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1169. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1170. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1171. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1172. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1173. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1174. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1175. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1176. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1177. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1178. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1179. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1180. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1181. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1182. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1183. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1184. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1185. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1186. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
  1187. V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
  1188. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1189. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1190. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1191. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
  1192. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1193. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1194. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1195. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1196. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1197. if (ctx->ctrls.error) {
  1198. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1199. ctx->ctrls.error);
  1200. return -EINVAL;
  1201. }
  1202. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1203. }
  1204. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1205. struct vb2_queue *dst_vq)
  1206. {
  1207. struct coda_ctx *ctx = priv;
  1208. int ret;
  1209. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1210. src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1211. src_vq->drv_priv = ctx;
  1212. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1213. src_vq->ops = &coda_qops;
  1214. src_vq->mem_ops = &vb2_dma_contig_memops;
  1215. ret = vb2_queue_init(src_vq);
  1216. if (ret)
  1217. return ret;
  1218. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1219. dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1220. dst_vq->drv_priv = ctx;
  1221. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1222. dst_vq->ops = &coda_qops;
  1223. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1224. return vb2_queue_init(dst_vq);
  1225. }
  1226. static int coda_next_free_instance(struct coda_dev *dev)
  1227. {
  1228. return ffz(dev->instance_mask);
  1229. }
  1230. static int coda_open(struct file *file)
  1231. {
  1232. struct coda_dev *dev = video_drvdata(file);
  1233. struct coda_ctx *ctx = NULL;
  1234. int ret = 0;
  1235. int idx;
  1236. idx = coda_next_free_instance(dev);
  1237. if (idx >= CODA_MAX_INSTANCES)
  1238. return -EBUSY;
  1239. set_bit(idx, &dev->instance_mask);
  1240. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1241. if (!ctx)
  1242. return -ENOMEM;
  1243. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1244. file->private_data = &ctx->fh;
  1245. v4l2_fh_add(&ctx->fh);
  1246. ctx->dev = dev;
  1247. ctx->idx = idx;
  1248. set_default_params(ctx);
  1249. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1250. &coda_queue_init);
  1251. if (IS_ERR(ctx->m2m_ctx)) {
  1252. int ret = PTR_ERR(ctx->m2m_ctx);
  1253. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1254. __func__, ret);
  1255. goto err;
  1256. }
  1257. ret = coda_ctrls_setup(ctx);
  1258. if (ret) {
  1259. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1260. goto err;
  1261. }
  1262. ctx->fh.ctrl_handler = &ctx->ctrls;
  1263. ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
  1264. CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
  1265. if (!ctx->parabuf.vaddr) {
  1266. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1267. ret = -ENOMEM;
  1268. goto err;
  1269. }
  1270. coda_lock(ctx);
  1271. list_add(&ctx->list, &dev->instances);
  1272. coda_unlock(ctx);
  1273. clk_prepare_enable(dev->clk_per);
  1274. clk_prepare_enable(dev->clk_ahb);
  1275. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1276. ctx->idx, ctx);
  1277. return 0;
  1278. err:
  1279. v4l2_fh_del(&ctx->fh);
  1280. v4l2_fh_exit(&ctx->fh);
  1281. kfree(ctx);
  1282. return ret;
  1283. }
  1284. static int coda_release(struct file *file)
  1285. {
  1286. struct coda_dev *dev = video_drvdata(file);
  1287. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1288. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1289. ctx);
  1290. coda_lock(ctx);
  1291. list_del(&ctx->list);
  1292. coda_unlock(ctx);
  1293. dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
  1294. ctx->parabuf.vaddr, ctx->parabuf.paddr);
  1295. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1296. v4l2_ctrl_handler_free(&ctx->ctrls);
  1297. clk_disable_unprepare(dev->clk_per);
  1298. clk_disable_unprepare(dev->clk_ahb);
  1299. v4l2_fh_del(&ctx->fh);
  1300. v4l2_fh_exit(&ctx->fh);
  1301. clear_bit(ctx->idx, &dev->instance_mask);
  1302. kfree(ctx);
  1303. return 0;
  1304. }
  1305. static unsigned int coda_poll(struct file *file,
  1306. struct poll_table_struct *wait)
  1307. {
  1308. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1309. int ret;
  1310. coda_lock(ctx);
  1311. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1312. coda_unlock(ctx);
  1313. return ret;
  1314. }
  1315. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1316. {
  1317. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1318. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1319. }
  1320. static const struct v4l2_file_operations coda_fops = {
  1321. .owner = THIS_MODULE,
  1322. .open = coda_open,
  1323. .release = coda_release,
  1324. .poll = coda_poll,
  1325. .unlocked_ioctl = video_ioctl2,
  1326. .mmap = coda_mmap,
  1327. };
  1328. static irqreturn_t coda_irq_handler(int irq, void *data)
  1329. {
  1330. struct vb2_buffer *src_buf, *dst_buf;
  1331. struct coda_dev *dev = data;
  1332. u32 wr_ptr, start_ptr;
  1333. struct coda_ctx *ctx;
  1334. cancel_delayed_work(&dev->timeout);
  1335. /* read status register to attend the IRQ */
  1336. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1337. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1338. CODA_REG_BIT_INT_CLEAR);
  1339. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1340. if (ctx == NULL) {
  1341. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1342. return IRQ_HANDLED;
  1343. }
  1344. if (ctx->aborting) {
  1345. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1346. "task has been aborted\n");
  1347. return IRQ_HANDLED;
  1348. }
  1349. if (coda_isbusy(ctx->dev)) {
  1350. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1351. "coda is still busy!!!!\n");
  1352. return IRQ_NONE;
  1353. }
  1354. complete(&dev->done);
  1355. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1356. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1357. /* Get results from the coda */
  1358. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1359. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1360. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
  1361. /* Calculate bytesused field */
  1362. if (dst_buf->v4l2_buf.sequence == 0) {
  1363. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
  1364. ctx->vpu_header_size[0] +
  1365. ctx->vpu_header_size[1] +
  1366. ctx->vpu_header_size[2];
  1367. } else {
  1368. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
  1369. }
  1370. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1371. wr_ptr - start_ptr);
  1372. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1373. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1374. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1375. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1376. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1377. } else {
  1378. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1379. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1380. }
  1381. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1382. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1383. ctx->gopcounter--;
  1384. if (ctx->gopcounter < 0)
  1385. ctx->gopcounter = ctx->params.gop_size - 1;
  1386. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1387. "job finished: encoding frame (%d) (%s)\n",
  1388. dst_buf->v4l2_buf.sequence,
  1389. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1390. "KEYFRAME" : "PFRAME");
  1391. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1392. return IRQ_HANDLED;
  1393. }
  1394. static void coda_timeout(struct work_struct *work)
  1395. {
  1396. struct coda_ctx *ctx;
  1397. struct coda_dev *dev = container_of(to_delayed_work(work),
  1398. struct coda_dev, timeout);
  1399. if (completion_done(&dev->done))
  1400. return;
  1401. complete(&dev->done);
  1402. v4l2_err(&dev->v4l2_dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1403. mutex_lock(&dev->dev_mutex);
  1404. list_for_each_entry(ctx, &dev->instances, list) {
  1405. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1406. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1407. }
  1408. mutex_unlock(&dev->dev_mutex);
  1409. }
  1410. static u32 coda_supported_firmwares[] = {
  1411. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1412. CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
  1413. };
  1414. static bool coda_firmware_supported(u32 vernum)
  1415. {
  1416. int i;
  1417. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1418. if (vernum == coda_supported_firmwares[i])
  1419. return true;
  1420. return false;
  1421. }
  1422. static char *coda_product_name(int product)
  1423. {
  1424. static char buf[9];
  1425. switch (product) {
  1426. case CODA_DX6:
  1427. return "CodaDx6";
  1428. case CODA_7541:
  1429. return "CODA7541";
  1430. default:
  1431. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1432. return buf;
  1433. }
  1434. }
  1435. static int coda_hw_init(struct coda_dev *dev)
  1436. {
  1437. u16 product, major, minor, release;
  1438. u32 data;
  1439. u16 *p;
  1440. int i;
  1441. clk_prepare_enable(dev->clk_per);
  1442. clk_prepare_enable(dev->clk_ahb);
  1443. /*
  1444. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1445. * The 16-bit chars in the code buffer are in memory access
  1446. * order, re-sort them to CODA order for register download.
  1447. * Data in this SRAM survives a reboot.
  1448. */
  1449. p = (u16 *)dev->codebuf.vaddr;
  1450. if (dev->devtype->product == CODA_DX6) {
  1451. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1452. data = CODA_DOWN_ADDRESS_SET(i) |
  1453. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1454. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1455. }
  1456. } else {
  1457. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1458. data = CODA_DOWN_ADDRESS_SET(i) |
  1459. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1460. 3 - (i % 4)]);
  1461. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1462. }
  1463. }
  1464. /* Tell the BIT where to find everything it needs */
  1465. coda_write(dev, dev->workbuf.paddr,
  1466. CODA_REG_BIT_WORK_BUF_ADDR);
  1467. coda_write(dev, dev->codebuf.paddr,
  1468. CODA_REG_BIT_CODE_BUF_ADDR);
  1469. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1470. /* Set default values */
  1471. switch (dev->devtype->product) {
  1472. case CODA_DX6:
  1473. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1474. break;
  1475. default:
  1476. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1477. }
  1478. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1479. if (dev->devtype->product != CODA_DX6)
  1480. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1481. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1482. CODA_REG_BIT_INT_ENABLE);
  1483. /* Reset VPU and start processor */
  1484. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1485. data |= CODA_REG_RESET_ENABLE;
  1486. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1487. udelay(10);
  1488. data &= ~CODA_REG_RESET_ENABLE;
  1489. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1490. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1491. /* Load firmware */
  1492. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1493. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1494. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1495. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1496. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1497. if (coda_wait_timeout(dev)) {
  1498. clk_disable_unprepare(dev->clk_per);
  1499. clk_disable_unprepare(dev->clk_ahb);
  1500. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1501. return -EIO;
  1502. }
  1503. /* Check we are compatible with the loaded firmware */
  1504. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1505. product = CODA_FIRMWARE_PRODUCT(data);
  1506. major = CODA_FIRMWARE_MAJOR(data);
  1507. minor = CODA_FIRMWARE_MINOR(data);
  1508. release = CODA_FIRMWARE_RELEASE(data);
  1509. clk_disable_unprepare(dev->clk_per);
  1510. clk_disable_unprepare(dev->clk_ahb);
  1511. if (product != dev->devtype->product) {
  1512. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1513. " Version: %u.%u.%u\n",
  1514. coda_product_name(dev->devtype->product),
  1515. coda_product_name(product), major, minor, release);
  1516. return -EINVAL;
  1517. }
  1518. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1519. coda_product_name(product));
  1520. if (coda_firmware_supported(data)) {
  1521. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1522. major, minor, release);
  1523. } else {
  1524. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1525. "%u.%u.%u\n", major, minor, release);
  1526. }
  1527. return 0;
  1528. }
  1529. static void coda_fw_callback(const struct firmware *fw, void *context)
  1530. {
  1531. struct coda_dev *dev = context;
  1532. struct platform_device *pdev = dev->plat_dev;
  1533. int ret;
  1534. if (!fw) {
  1535. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1536. return;
  1537. }
  1538. /* allocate auxiliary per-device code buffer for the BIT processor */
  1539. dev->codebuf.size = fw->size;
  1540. dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
  1541. &dev->codebuf.paddr,
  1542. GFP_KERNEL);
  1543. if (!dev->codebuf.vaddr) {
  1544. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1545. return;
  1546. }
  1547. /* Copy the whole firmware image to the code buffer */
  1548. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1549. release_firmware(fw);
  1550. ret = coda_hw_init(dev);
  1551. if (ret) {
  1552. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1553. return;
  1554. }
  1555. dev->vfd.fops = &coda_fops,
  1556. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1557. dev->vfd.release = video_device_release_empty,
  1558. dev->vfd.lock = &dev->dev_mutex;
  1559. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1560. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1561. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1562. video_set_drvdata(&dev->vfd, dev);
  1563. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1564. if (IS_ERR(dev->alloc_ctx)) {
  1565. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1566. return;
  1567. }
  1568. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1569. if (IS_ERR(dev->m2m_dev)) {
  1570. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1571. goto rel_ctx;
  1572. }
  1573. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1574. if (ret) {
  1575. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1576. goto rel_m2m;
  1577. }
  1578. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1579. dev->vfd.num);
  1580. return;
  1581. rel_m2m:
  1582. v4l2_m2m_release(dev->m2m_dev);
  1583. rel_ctx:
  1584. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1585. }
  1586. static int coda_firmware_request(struct coda_dev *dev)
  1587. {
  1588. char *fw = dev->devtype->firmware;
  1589. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1590. coda_product_name(dev->devtype->product));
  1591. return request_firmware_nowait(THIS_MODULE, true,
  1592. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1593. }
  1594. enum coda_platform {
  1595. CODA_IMX27,
  1596. CODA_IMX53,
  1597. };
  1598. static const struct coda_devtype coda_devdata[] = {
  1599. [CODA_IMX27] = {
  1600. .firmware = "v4l-codadx6-imx27.bin",
  1601. .product = CODA_DX6,
  1602. .formats = codadx6_formats,
  1603. .num_formats = ARRAY_SIZE(codadx6_formats),
  1604. },
  1605. [CODA_IMX53] = {
  1606. .firmware = "v4l-coda7541-imx53.bin",
  1607. .product = CODA_7541,
  1608. .formats = coda7_formats,
  1609. .num_formats = ARRAY_SIZE(coda7_formats),
  1610. },
  1611. };
  1612. static struct platform_device_id coda_platform_ids[] = {
  1613. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  1614. { .name = "coda-imx53", .driver_data = CODA_IMX53 },
  1615. { /* sentinel */ }
  1616. };
  1617. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  1618. #ifdef CONFIG_OF
  1619. static const struct of_device_id coda_dt_ids[] = {
  1620. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  1621. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  1622. { /* sentinel */ }
  1623. };
  1624. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  1625. #endif
  1626. static int __devinit coda_probe(struct platform_device *pdev)
  1627. {
  1628. const struct of_device_id *of_id =
  1629. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  1630. const struct platform_device_id *pdev_id;
  1631. struct coda_dev *dev;
  1632. struct resource *res;
  1633. int ret, irq;
  1634. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  1635. if (!dev) {
  1636. dev_err(&pdev->dev, "Not enough memory for %s\n",
  1637. CODA_NAME);
  1638. return -ENOMEM;
  1639. }
  1640. spin_lock_init(&dev->irqlock);
  1641. INIT_LIST_HEAD(&dev->instances);
  1642. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  1643. init_completion(&dev->done);
  1644. complete(&dev->done);
  1645. dev->plat_dev = pdev;
  1646. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  1647. if (IS_ERR(dev->clk_per)) {
  1648. dev_err(&pdev->dev, "Could not get per clock\n");
  1649. return PTR_ERR(dev->clk_per);
  1650. }
  1651. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1652. if (IS_ERR(dev->clk_ahb)) {
  1653. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1654. return PTR_ERR(dev->clk_ahb);
  1655. }
  1656. /* Get memory for physical registers */
  1657. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1658. if (res == NULL) {
  1659. dev_err(&pdev->dev, "failed to get memory region resource\n");
  1660. return -ENOENT;
  1661. }
  1662. if (devm_request_mem_region(&pdev->dev, res->start,
  1663. resource_size(res), CODA_NAME) == NULL) {
  1664. dev_err(&pdev->dev, "failed to request memory region\n");
  1665. return -ENOENT;
  1666. }
  1667. dev->regs_base = devm_ioremap(&pdev->dev, res->start,
  1668. resource_size(res));
  1669. if (!dev->regs_base) {
  1670. dev_err(&pdev->dev, "failed to ioremap address region\n");
  1671. return -ENOENT;
  1672. }
  1673. /* IRQ */
  1674. irq = platform_get_irq(pdev, 0);
  1675. if (irq < 0) {
  1676. dev_err(&pdev->dev, "failed to get irq resource\n");
  1677. return -ENOENT;
  1678. }
  1679. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  1680. 0, CODA_NAME, dev) < 0) {
  1681. dev_err(&pdev->dev, "failed to request irq\n");
  1682. return -ENOENT;
  1683. }
  1684. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1685. if (ret)
  1686. return ret;
  1687. mutex_init(&dev->dev_mutex);
  1688. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  1689. if (of_id) {
  1690. dev->devtype = of_id->data;
  1691. } else if (pdev_id) {
  1692. dev->devtype = &coda_devdata[pdev_id->driver_data];
  1693. } else {
  1694. v4l2_device_unregister(&dev->v4l2_dev);
  1695. return -EINVAL;
  1696. }
  1697. /* allocate auxiliary per-device buffers for the BIT processor */
  1698. switch (dev->devtype->product) {
  1699. case CODA_DX6:
  1700. dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
  1701. break;
  1702. default:
  1703. dev->workbuf.size = CODA7_WORK_BUF_SIZE;
  1704. }
  1705. dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
  1706. &dev->workbuf.paddr,
  1707. GFP_KERNEL);
  1708. if (!dev->workbuf.vaddr) {
  1709. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  1710. v4l2_device_unregister(&dev->v4l2_dev);
  1711. return -ENOMEM;
  1712. }
  1713. if (dev->devtype->product == CODA_DX6) {
  1714. dev->iram_paddr = 0xffff4c00;
  1715. } else {
  1716. void __iomem *iram_vaddr;
  1717. iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
  1718. &dev->iram_paddr);
  1719. if (!iram_vaddr) {
  1720. dev_err(&pdev->dev, "unable to alloc iram\n");
  1721. return -ENOMEM;
  1722. }
  1723. }
  1724. platform_set_drvdata(pdev, dev);
  1725. return coda_firmware_request(dev);
  1726. }
  1727. static int coda_remove(struct platform_device *pdev)
  1728. {
  1729. struct coda_dev *dev = platform_get_drvdata(pdev);
  1730. video_unregister_device(&dev->vfd);
  1731. if (dev->m2m_dev)
  1732. v4l2_m2m_release(dev->m2m_dev);
  1733. if (dev->alloc_ctx)
  1734. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1735. v4l2_device_unregister(&dev->v4l2_dev);
  1736. if (dev->iram_paddr)
  1737. iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
  1738. if (dev->codebuf.vaddr)
  1739. dma_free_coherent(&pdev->dev, dev->codebuf.size,
  1740. &dev->codebuf.vaddr, dev->codebuf.paddr);
  1741. if (dev->workbuf.vaddr)
  1742. dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
  1743. dev->workbuf.paddr);
  1744. return 0;
  1745. }
  1746. static struct platform_driver coda_driver = {
  1747. .probe = coda_probe,
  1748. .remove = __devexit_p(coda_remove),
  1749. .driver = {
  1750. .name = CODA_NAME,
  1751. .owner = THIS_MODULE,
  1752. .of_match_table = of_match_ptr(coda_dt_ids),
  1753. },
  1754. .id_table = coda_platform_ids,
  1755. };
  1756. module_platform_driver(coda_driver);
  1757. MODULE_LICENSE("GPL");
  1758. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  1759. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");