iwl-core.c 88 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO2_##s##M_PLCP,\
  48. IWL_RATE_MIMO3_##s##M_PLCP,\
  49. IWL_RATE_##r##M_IEEE, \
  50. IWL_RATE_##ip##M_INDEX, \
  51. IWL_RATE_##in##M_INDEX, \
  52. IWL_RATE_##rp##M_INDEX, \
  53. IWL_RATE_##rn##M_INDEX, \
  54. IWL_RATE_##pp##M_INDEX, \
  55. IWL_RATE_##np##M_INDEX }
  56. u32 iwl_debug_level;
  57. EXPORT_SYMBOL(iwl_debug_level);
  58. static irqreturn_t iwl_isr(int irq, void *data);
  59. /*
  60. * Parameter order:
  61. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  62. *
  63. * If there isn't a valid next or previous rate then INV is used which
  64. * maps to IWL_RATE_INVALID
  65. *
  66. */
  67. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  68. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  69. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  70. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  71. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  72. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  73. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  74. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  75. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  76. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  77. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  78. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  79. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  80. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  81. /* FIXME:RS: ^^ should be INV (legacy) */
  82. };
  83. EXPORT_SYMBOL(iwl_rates);
  84. /**
  85. * translate ucode response to mac80211 tx status control values
  86. */
  87. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  88. struct ieee80211_tx_info *info)
  89. {
  90. struct ieee80211_tx_rate *r = &info->control.rates[0];
  91. info->antenna_sel_tx =
  92. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  93. if (rate_n_flags & RATE_MCS_HT_MSK)
  94. r->flags |= IEEE80211_TX_RC_MCS;
  95. if (rate_n_flags & RATE_MCS_GF_MSK)
  96. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  97. if (rate_n_flags & RATE_MCS_HT40_MSK)
  98. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  99. if (rate_n_flags & RATE_MCS_DUP_MSK)
  100. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  101. if (rate_n_flags & RATE_MCS_SGI_MSK)
  102. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  103. r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
  104. }
  105. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  106. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  107. {
  108. int idx = 0;
  109. /* HT rate format */
  110. if (rate_n_flags & RATE_MCS_HT_MSK) {
  111. idx = (rate_n_flags & 0xff);
  112. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  113. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  114. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  115. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  116. idx += IWL_FIRST_OFDM_RATE;
  117. /* skip 9M not supported in ht*/
  118. if (idx >= IWL_RATE_9M_INDEX)
  119. idx += 1;
  120. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  121. return idx;
  122. /* legacy rate format, search for match in table */
  123. } else {
  124. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  125. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  126. return idx;
  127. }
  128. return -1;
  129. }
  130. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  131. int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  132. {
  133. int idx = 0;
  134. int band_offset = 0;
  135. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  136. if (rate_n_flags & RATE_MCS_HT_MSK) {
  137. idx = (rate_n_flags & 0xff);
  138. return idx;
  139. /* Legacy rate format, search for match in table */
  140. } else {
  141. if (band == IEEE80211_BAND_5GHZ)
  142. band_offset = IWL_FIRST_OFDM_RATE;
  143. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  144. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  145. return idx - band_offset;
  146. }
  147. return -1;
  148. }
  149. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  150. {
  151. int i;
  152. u8 ind = ant;
  153. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  154. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  155. if (priv->hw_params.valid_tx_ant & BIT(ind))
  156. return ind;
  157. }
  158. return ant;
  159. }
  160. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  161. EXPORT_SYMBOL(iwl_bcast_addr);
  162. /* This function both allocates and initializes hw and priv. */
  163. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  164. struct ieee80211_ops *hw_ops)
  165. {
  166. struct iwl_priv *priv;
  167. /* mac80211 allocates memory for this device instance, including
  168. * space for this driver's private structure */
  169. struct ieee80211_hw *hw =
  170. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  171. if (hw == NULL) {
  172. printk(KERN_ERR "%s: Can not allocate network device\n",
  173. cfg->name);
  174. goto out;
  175. }
  176. priv = hw->priv;
  177. priv->hw = hw;
  178. out:
  179. return hw;
  180. }
  181. EXPORT_SYMBOL(iwl_alloc_all);
  182. void iwl_hw_detect(struct iwl_priv *priv)
  183. {
  184. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  185. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  186. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  187. }
  188. EXPORT_SYMBOL(iwl_hw_detect);
  189. int iwl_hw_nic_init(struct iwl_priv *priv)
  190. {
  191. unsigned long flags;
  192. struct iwl_rx_queue *rxq = &priv->rxq;
  193. int ret;
  194. /* nic_init */
  195. spin_lock_irqsave(&priv->lock, flags);
  196. priv->cfg->ops->lib->apm_ops.init(priv);
  197. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  198. spin_unlock_irqrestore(&priv->lock, flags);
  199. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  200. priv->cfg->ops->lib->apm_ops.config(priv);
  201. /* Allocate the RX queue, or reset if it is already allocated */
  202. if (!rxq->bd) {
  203. ret = iwl_rx_queue_alloc(priv);
  204. if (ret) {
  205. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  206. return -ENOMEM;
  207. }
  208. } else
  209. iwl_rx_queue_reset(priv, rxq);
  210. iwl_rx_replenish(priv);
  211. iwl_rx_init(priv, rxq);
  212. spin_lock_irqsave(&priv->lock, flags);
  213. rxq->need_update = 1;
  214. iwl_rx_queue_update_write_ptr(priv, rxq);
  215. spin_unlock_irqrestore(&priv->lock, flags);
  216. /* Allocate and init all Tx and Command queues */
  217. ret = iwl_txq_ctx_reset(priv);
  218. if (ret)
  219. return ret;
  220. set_bit(STATUS_INIT, &priv->status);
  221. return 0;
  222. }
  223. EXPORT_SYMBOL(iwl_hw_nic_init);
  224. /*
  225. * QoS support
  226. */
  227. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  228. {
  229. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  230. return;
  231. priv->qos_data.def_qos_parm.qos_flags = 0;
  232. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  233. !priv->qos_data.qos_cap.q_AP.txop_request)
  234. priv->qos_data.def_qos_parm.qos_flags |=
  235. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  236. if (priv->qos_data.qos_active)
  237. priv->qos_data.def_qos_parm.qos_flags |=
  238. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  239. if (priv->current_ht_config.is_ht)
  240. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  241. if (force || iwl_is_associated(priv)) {
  242. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  243. priv->qos_data.qos_active,
  244. priv->qos_data.def_qos_parm.qos_flags);
  245. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  246. sizeof(struct iwl_qosparam_cmd),
  247. &priv->qos_data.def_qos_parm, NULL);
  248. }
  249. }
  250. EXPORT_SYMBOL(iwl_activate_qos);
  251. /*
  252. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  253. * (802.11b) (802.11a/g)
  254. * AC_BK 15 1023 7 0 0
  255. * AC_BE 15 1023 3 0 0
  256. * AC_VI 7 15 2 6.016ms 3.008ms
  257. * AC_VO 3 7 2 3.264ms 1.504ms
  258. */
  259. void iwl_reset_qos(struct iwl_priv *priv)
  260. {
  261. u16 cw_min = 15;
  262. u16 cw_max = 1023;
  263. u8 aifs = 2;
  264. bool is_legacy = false;
  265. unsigned long flags;
  266. int i;
  267. spin_lock_irqsave(&priv->lock, flags);
  268. /* QoS always active in AP and ADHOC mode
  269. * In STA mode wait for association
  270. */
  271. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  272. priv->iw_mode == NL80211_IFTYPE_AP)
  273. priv->qos_data.qos_active = 1;
  274. else
  275. priv->qos_data.qos_active = 0;
  276. /* check for legacy mode */
  277. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  278. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  279. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  280. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  281. cw_min = 31;
  282. is_legacy = 1;
  283. }
  284. if (priv->qos_data.qos_active)
  285. aifs = 3;
  286. /* AC_BE */
  287. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  288. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  289. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  290. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  291. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  292. if (priv->qos_data.qos_active) {
  293. /* AC_BK */
  294. i = 1;
  295. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  296. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  297. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  298. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  299. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  300. /* AC_VI */
  301. i = 2;
  302. priv->qos_data.def_qos_parm.ac[i].cw_min =
  303. cpu_to_le16((cw_min + 1) / 2 - 1);
  304. priv->qos_data.def_qos_parm.ac[i].cw_max =
  305. cpu_to_le16(cw_min);
  306. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  307. if (is_legacy)
  308. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  309. cpu_to_le16(6016);
  310. else
  311. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  312. cpu_to_le16(3008);
  313. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  314. /* AC_VO */
  315. i = 3;
  316. priv->qos_data.def_qos_parm.ac[i].cw_min =
  317. cpu_to_le16((cw_min + 1) / 4 - 1);
  318. priv->qos_data.def_qos_parm.ac[i].cw_max =
  319. cpu_to_le16((cw_min + 1) / 2 - 1);
  320. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  321. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  322. if (is_legacy)
  323. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  324. cpu_to_le16(3264);
  325. else
  326. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  327. cpu_to_le16(1504);
  328. } else {
  329. for (i = 1; i < 4; i++) {
  330. priv->qos_data.def_qos_parm.ac[i].cw_min =
  331. cpu_to_le16(cw_min);
  332. priv->qos_data.def_qos_parm.ac[i].cw_max =
  333. cpu_to_le16(cw_max);
  334. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  335. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  336. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  337. }
  338. }
  339. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  340. spin_unlock_irqrestore(&priv->lock, flags);
  341. }
  342. EXPORT_SYMBOL(iwl_reset_qos);
  343. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  344. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  345. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  346. struct ieee80211_sta_ht_cap *ht_info,
  347. enum ieee80211_band band)
  348. {
  349. u16 max_bit_rate = 0;
  350. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  351. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  352. ht_info->cap = 0;
  353. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  354. ht_info->ht_supported = true;
  355. if (priv->cfg->ht_greenfield_support)
  356. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  357. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  358. if (priv->cfg->support_sm_ps)
  359. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  360. (WLAN_HT_CAP_SM_PS_DYNAMIC << 2));
  361. else
  362. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  363. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  364. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  365. if (priv->hw_params.ht40_channel & BIT(band)) {
  366. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  367. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  368. ht_info->mcs.rx_mask[4] = 0x01;
  369. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  370. }
  371. if (priv->cfg->mod_params->amsdu_size_8K)
  372. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  373. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  374. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  375. ht_info->mcs.rx_mask[0] = 0xFF;
  376. if (rx_chains_num >= 2)
  377. ht_info->mcs.rx_mask[1] = 0xFF;
  378. if (rx_chains_num >= 3)
  379. ht_info->mcs.rx_mask[2] = 0xFF;
  380. /* Highest supported Rx data rate */
  381. max_bit_rate *= rx_chains_num;
  382. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  383. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  384. /* Tx MCS capabilities */
  385. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  386. if (tx_chains_num != rx_chains_num) {
  387. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  388. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  389. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  390. }
  391. }
  392. /**
  393. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  394. */
  395. int iwlcore_init_geos(struct iwl_priv *priv)
  396. {
  397. struct iwl_channel_info *ch;
  398. struct ieee80211_supported_band *sband;
  399. struct ieee80211_channel *channels;
  400. struct ieee80211_channel *geo_ch;
  401. struct ieee80211_rate *rates;
  402. int i = 0;
  403. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  404. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  405. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  406. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  407. return 0;
  408. }
  409. channels = kzalloc(sizeof(struct ieee80211_channel) *
  410. priv->channel_count, GFP_KERNEL);
  411. if (!channels)
  412. return -ENOMEM;
  413. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  414. GFP_KERNEL);
  415. if (!rates) {
  416. kfree(channels);
  417. return -ENOMEM;
  418. }
  419. /* 5.2GHz channels start after the 2.4GHz channels */
  420. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  421. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  422. /* just OFDM */
  423. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  424. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  425. if (priv->cfg->sku & IWL_SKU_N)
  426. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  427. IEEE80211_BAND_5GHZ);
  428. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  429. sband->channels = channels;
  430. /* OFDM & CCK */
  431. sband->bitrates = rates;
  432. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  433. if (priv->cfg->sku & IWL_SKU_N)
  434. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  435. IEEE80211_BAND_2GHZ);
  436. priv->ieee_channels = channels;
  437. priv->ieee_rates = rates;
  438. for (i = 0; i < priv->channel_count; i++) {
  439. ch = &priv->channel_info[i];
  440. /* FIXME: might be removed if scan is OK */
  441. if (!is_channel_valid(ch))
  442. continue;
  443. if (is_channel_a_band(ch))
  444. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  445. else
  446. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  447. geo_ch = &sband->channels[sband->n_channels++];
  448. geo_ch->center_freq =
  449. ieee80211_channel_to_frequency(ch->channel);
  450. geo_ch->max_power = ch->max_power_avg;
  451. geo_ch->max_antenna_gain = 0xff;
  452. geo_ch->hw_value = ch->channel;
  453. if (is_channel_valid(ch)) {
  454. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  455. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  456. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  457. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  458. if (ch->flags & EEPROM_CHANNEL_RADAR)
  459. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  460. geo_ch->flags |= ch->ht40_extension_channel;
  461. if (ch->max_power_avg > priv->tx_power_device_lmt)
  462. priv->tx_power_device_lmt = ch->max_power_avg;
  463. } else {
  464. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  465. }
  466. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  467. ch->channel, geo_ch->center_freq,
  468. is_channel_a_band(ch) ? "5.2" : "2.4",
  469. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  470. "restricted" : "valid",
  471. geo_ch->flags);
  472. }
  473. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  474. priv->cfg->sku & IWL_SKU_A) {
  475. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  476. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  477. priv->pci_dev->device,
  478. priv->pci_dev->subsystem_device);
  479. priv->cfg->sku &= ~IWL_SKU_A;
  480. }
  481. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  482. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  483. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  484. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  485. return 0;
  486. }
  487. EXPORT_SYMBOL(iwlcore_init_geos);
  488. /*
  489. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  490. */
  491. void iwlcore_free_geos(struct iwl_priv *priv)
  492. {
  493. kfree(priv->ieee_channels);
  494. kfree(priv->ieee_rates);
  495. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  496. }
  497. EXPORT_SYMBOL(iwlcore_free_geos);
  498. /*
  499. * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
  500. * function.
  501. */
  502. void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
  503. __le32 *tx_flags)
  504. {
  505. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  506. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  507. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  508. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  509. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  510. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  511. }
  512. }
  513. EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
  514. static bool is_single_rx_stream(struct iwl_priv *priv)
  515. {
  516. return !priv->current_ht_config.is_ht ||
  517. priv->current_ht_config.single_chain_sufficient;
  518. }
  519. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  520. enum ieee80211_band band,
  521. u16 channel, u8 extension_chan_offset)
  522. {
  523. const struct iwl_channel_info *ch_info;
  524. ch_info = iwl_get_channel_info(priv, band, channel);
  525. if (!is_channel_valid(ch_info))
  526. return 0;
  527. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  528. return !(ch_info->ht40_extension_channel &
  529. IEEE80211_CHAN_NO_HT40PLUS);
  530. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  531. return !(ch_info->ht40_extension_channel &
  532. IEEE80211_CHAN_NO_HT40MINUS);
  533. return 0;
  534. }
  535. u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  536. struct ieee80211_sta_ht_cap *sta_ht_inf)
  537. {
  538. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  539. if (!ht_conf->is_ht || !ht_conf->is_40mhz)
  540. return 0;
  541. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  542. * the bit will not set if it is pure 40MHz case
  543. */
  544. if (sta_ht_inf) {
  545. if (!sta_ht_inf->ht_supported)
  546. return 0;
  547. }
  548. #ifdef CONFIG_IWLWIFI_DEBUG
  549. if (priv->disable_ht40)
  550. return 0;
  551. #endif
  552. return iwl_is_channel_extension(priv, priv->band,
  553. le16_to_cpu(priv->staging_rxon.channel),
  554. ht_conf->extension_chan_offset);
  555. }
  556. EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
  557. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  558. {
  559. u16 new_val = 0;
  560. u16 beacon_factor = 0;
  561. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  562. new_val = beacon_val / beacon_factor;
  563. if (!new_val)
  564. new_val = max_beacon_val;
  565. return new_val;
  566. }
  567. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  568. {
  569. u64 tsf;
  570. s32 interval_tm, rem;
  571. unsigned long flags;
  572. struct ieee80211_conf *conf = NULL;
  573. u16 beacon_int;
  574. conf = ieee80211_get_hw_conf(priv->hw);
  575. spin_lock_irqsave(&priv->lock, flags);
  576. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  577. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  578. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  579. beacon_int = priv->beacon_int;
  580. priv->rxon_timing.atim_window = 0;
  581. } else {
  582. beacon_int = priv->vif->bss_conf.beacon_int;
  583. /* TODO: we need to get atim_window from upper stack
  584. * for now we set to 0 */
  585. priv->rxon_timing.atim_window = 0;
  586. }
  587. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  588. priv->hw_params.max_beacon_itrvl * 1024);
  589. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  590. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  591. interval_tm = beacon_int * 1024;
  592. rem = do_div(tsf, interval_tm);
  593. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  594. spin_unlock_irqrestore(&priv->lock, flags);
  595. IWL_DEBUG_ASSOC(priv,
  596. "beacon interval %d beacon timer %d beacon tim %d\n",
  597. le16_to_cpu(priv->rxon_timing.beacon_interval),
  598. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  599. le16_to_cpu(priv->rxon_timing.atim_window));
  600. }
  601. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  602. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  603. {
  604. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  605. if (hw_decrypt)
  606. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  607. else
  608. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  609. }
  610. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  611. /**
  612. * iwl_check_rxon_cmd - validate RXON structure is valid
  613. *
  614. * NOTE: This is really only useful during development and can eventually
  615. * be #ifdef'd out once the driver is stable and folks aren't actively
  616. * making changes
  617. */
  618. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  619. {
  620. int error = 0;
  621. int counter = 1;
  622. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  623. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  624. error |= le32_to_cpu(rxon->flags &
  625. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  626. RXON_FLG_RADAR_DETECT_MSK));
  627. if (error)
  628. IWL_WARN(priv, "check 24G fields %d | %d\n",
  629. counter++, error);
  630. } else {
  631. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  632. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  633. if (error)
  634. IWL_WARN(priv, "check 52 fields %d | %d\n",
  635. counter++, error);
  636. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  637. if (error)
  638. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  639. counter++, error);
  640. }
  641. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  642. if (error)
  643. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  644. /* make sure basic rates 6Mbps and 1Mbps are supported */
  645. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  646. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  647. if (error)
  648. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  649. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  650. if (error)
  651. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  652. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  653. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  654. if (error)
  655. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  656. counter++, error);
  657. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  658. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  659. if (error)
  660. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  661. counter++, error);
  662. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  663. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  664. if (error)
  665. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  666. counter++, error);
  667. if (error)
  668. IWL_WARN(priv, "Tuning to channel %d\n",
  669. le16_to_cpu(rxon->channel));
  670. if (error) {
  671. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  672. return -1;
  673. }
  674. return 0;
  675. }
  676. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  677. /**
  678. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  679. * @priv: staging_rxon is compared to active_rxon
  680. *
  681. * If the RXON structure is changing enough to require a new tune,
  682. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  683. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  684. */
  685. int iwl_full_rxon_required(struct iwl_priv *priv)
  686. {
  687. /* These items are only settable from the full RXON command */
  688. if (!(iwl_is_associated(priv)) ||
  689. compare_ether_addr(priv->staging_rxon.bssid_addr,
  690. priv->active_rxon.bssid_addr) ||
  691. compare_ether_addr(priv->staging_rxon.node_addr,
  692. priv->active_rxon.node_addr) ||
  693. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  694. priv->active_rxon.wlap_bssid_addr) ||
  695. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  696. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  697. (priv->staging_rxon.air_propagation !=
  698. priv->active_rxon.air_propagation) ||
  699. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  700. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  701. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  702. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  703. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  704. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  705. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  706. return 1;
  707. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  708. * be updated with the RXON_ASSOC command -- however only some
  709. * flag transitions are allowed using RXON_ASSOC */
  710. /* Check if we are not switching bands */
  711. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  712. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  713. return 1;
  714. /* Check if we are switching association toggle */
  715. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  716. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  717. return 1;
  718. return 0;
  719. }
  720. EXPORT_SYMBOL(iwl_full_rxon_required);
  721. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  722. {
  723. int i;
  724. int rate_mask;
  725. /* Set rate mask*/
  726. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  727. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  728. else
  729. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  730. /* Find lowest valid rate */
  731. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  732. i = iwl_rates[i].next_ieee) {
  733. if (rate_mask & (1 << i))
  734. return iwl_rates[i].plcp;
  735. }
  736. /* No valid rate was found. Assign the lowest one */
  737. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  738. return IWL_RATE_1M_PLCP;
  739. else
  740. return IWL_RATE_6M_PLCP;
  741. }
  742. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  743. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
  744. {
  745. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  746. if (!ht_conf->is_ht) {
  747. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  748. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  749. RXON_FLG_HT40_PROT_MSK |
  750. RXON_FLG_HT_PROT_MSK);
  751. return;
  752. }
  753. /* FIXME: if the definition of ht_protection changed, the "translation"
  754. * will be needed for rxon->flags
  755. */
  756. rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  757. /* Set up channel bandwidth:
  758. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  759. /* clear the HT channel mode before set the mode */
  760. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  761. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  762. if (iwl_is_ht40_tx_allowed(priv, NULL)) {
  763. /* pure ht40 */
  764. if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  765. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  766. /* Note: control channel is opposite of extension channel */
  767. switch (ht_conf->extension_chan_offset) {
  768. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  769. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  770. break;
  771. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  772. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  773. break;
  774. }
  775. } else {
  776. /* Note: control channel is opposite of extension channel */
  777. switch (ht_conf->extension_chan_offset) {
  778. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  779. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  780. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  781. break;
  782. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  783. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  784. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  785. break;
  786. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  787. default:
  788. /* channel location only valid if in Mixed mode */
  789. IWL_ERR(priv, "invalid extension channel offset\n");
  790. break;
  791. }
  792. }
  793. } else {
  794. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  795. }
  796. if (priv->cfg->ops->hcmd->set_rxon_chain)
  797. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  798. IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
  799. "extension channel offset 0x%x\n",
  800. le32_to_cpu(rxon->flags), ht_conf->ht_protection,
  801. ht_conf->extension_chan_offset);
  802. return;
  803. }
  804. EXPORT_SYMBOL(iwl_set_rxon_ht);
  805. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  806. #define IWL_NUM_RX_CHAINS_SINGLE 2
  807. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  808. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  809. /*
  810. * Determine how many receiver/antenna chains to use.
  811. *
  812. * More provides better reception via diversity. Fewer saves power
  813. * at the expense of throughput, but only when not in powersave to
  814. * start with.
  815. *
  816. * MIMO (dual stream) requires at least 2, but works better with 3.
  817. * This does not determine *which* chains to use, just how many.
  818. */
  819. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  820. {
  821. /* # of Rx chains to use when expecting MIMO. */
  822. if (is_single_rx_stream(priv))
  823. return IWL_NUM_RX_CHAINS_SINGLE;
  824. else
  825. return IWL_NUM_RX_CHAINS_MULTIPLE;
  826. }
  827. /*
  828. * When we are in power saving mode, unless device support spatial
  829. * multiplexing power save, use the active count for rx chain count.
  830. */
  831. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  832. {
  833. int idle_cnt = active_cnt;
  834. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  835. if (priv->cfg->support_sm_ps) {
  836. /* # Rx chains when idling and maybe trying to save power */
  837. switch (priv->current_ht_config.sm_ps) {
  838. case WLAN_HT_CAP_SM_PS_STATIC:
  839. case WLAN_HT_CAP_SM_PS_DYNAMIC:
  840. idle_cnt = (is_cam) ? IWL_NUM_IDLE_CHAINS_DUAL :
  841. IWL_NUM_IDLE_CHAINS_SINGLE;
  842. break;
  843. case WLAN_HT_CAP_SM_PS_DISABLED:
  844. idle_cnt = (is_cam) ? active_cnt :
  845. IWL_NUM_IDLE_CHAINS_SINGLE;
  846. break;
  847. case WLAN_HT_CAP_SM_PS_INVALID:
  848. default:
  849. IWL_ERR(priv, "invalid sm_ps mode %d\n",
  850. priv->current_ht_config.sm_ps);
  851. WARN_ON(1);
  852. break;
  853. }
  854. }
  855. return idle_cnt;
  856. }
  857. /* up to 4 chains */
  858. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  859. {
  860. u8 res;
  861. res = (chain_bitmap & BIT(0)) >> 0;
  862. res += (chain_bitmap & BIT(1)) >> 1;
  863. res += (chain_bitmap & BIT(2)) >> 2;
  864. res += (chain_bitmap & BIT(3)) >> 3;
  865. return res;
  866. }
  867. /**
  868. * iwl_is_monitor_mode - Determine if interface in monitor mode
  869. *
  870. * priv->iw_mode is set in add_interface, but add_interface is
  871. * never called for monitor mode. The only way mac80211 informs us about
  872. * monitor mode is through configuring filters (call to configure_filter).
  873. */
  874. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  875. {
  876. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  877. }
  878. EXPORT_SYMBOL(iwl_is_monitor_mode);
  879. /**
  880. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  881. *
  882. * Selects how many and which Rx receivers/antennas/chains to use.
  883. * This should not be used for scan command ... it puts data in wrong place.
  884. */
  885. void iwl_set_rxon_chain(struct iwl_priv *priv)
  886. {
  887. bool is_single = is_single_rx_stream(priv);
  888. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  889. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  890. u32 active_chains;
  891. u16 rx_chain;
  892. /* Tell uCode which antennas are actually connected.
  893. * Before first association, we assume all antennas are connected.
  894. * Just after first association, iwl_chain_noise_calibration()
  895. * checks which antennas actually *are* connected. */
  896. if (priv->chain_noise_data.active_chains)
  897. active_chains = priv->chain_noise_data.active_chains;
  898. else
  899. active_chains = priv->hw_params.valid_rx_ant;
  900. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  901. /* How many receivers should we use? */
  902. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  903. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  904. /* correct rx chain count according hw settings
  905. * and chain noise calibration
  906. */
  907. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  908. if (valid_rx_cnt < active_rx_cnt)
  909. active_rx_cnt = valid_rx_cnt;
  910. if (valid_rx_cnt < idle_rx_cnt)
  911. idle_rx_cnt = valid_rx_cnt;
  912. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  913. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  914. /* copied from 'iwl_bg_request_scan()' */
  915. /* Force use of chains B and C (0x6) for Rx for 4965
  916. * Avoid A (0x1) because of its off-channel reception on A-band.
  917. * MIMO is not used here, but value is required */
  918. if (iwl_is_monitor_mode(priv) &&
  919. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  920. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  921. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  922. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  923. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  924. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  925. }
  926. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  927. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  928. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  929. else
  930. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  931. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  932. priv->staging_rxon.rx_chain,
  933. active_rx_cnt, idle_rx_cnt);
  934. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  935. active_rx_cnt < idle_rx_cnt);
  936. }
  937. EXPORT_SYMBOL(iwl_set_rxon_chain);
  938. /**
  939. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  940. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  941. * @channel: Any channel valid for the requested phymode
  942. * In addition to setting the staging RXON, priv->phymode is also set.
  943. *
  944. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  945. * in the staging RXON flag structure based on the phymode
  946. */
  947. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  948. {
  949. enum ieee80211_band band = ch->band;
  950. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  951. if (!iwl_get_channel_info(priv, band, channel)) {
  952. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  953. channel, band);
  954. return -EINVAL;
  955. }
  956. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  957. (priv->band == band))
  958. return 0;
  959. priv->staging_rxon.channel = cpu_to_le16(channel);
  960. if (band == IEEE80211_BAND_5GHZ)
  961. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  962. else
  963. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  964. priv->band = band;
  965. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  966. return 0;
  967. }
  968. EXPORT_SYMBOL(iwl_set_rxon_channel);
  969. void iwl_set_flags_for_band(struct iwl_priv *priv,
  970. enum ieee80211_band band)
  971. {
  972. if (band == IEEE80211_BAND_5GHZ) {
  973. priv->staging_rxon.flags &=
  974. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  975. | RXON_FLG_CCK_MSK);
  976. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  977. } else {
  978. /* Copied from iwl_post_associate() */
  979. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  980. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  981. else
  982. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  983. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  984. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  985. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  986. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  987. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  988. }
  989. }
  990. /*
  991. * initialize rxon structure with default values from eeprom
  992. */
  993. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  994. {
  995. const struct iwl_channel_info *ch_info;
  996. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  997. switch (mode) {
  998. case NL80211_IFTYPE_AP:
  999. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1000. break;
  1001. case NL80211_IFTYPE_STATION:
  1002. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1003. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1004. break;
  1005. case NL80211_IFTYPE_ADHOC:
  1006. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1007. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1008. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1009. RXON_FILTER_ACCEPT_GRP_MSK;
  1010. break;
  1011. default:
  1012. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1013. break;
  1014. }
  1015. #if 0
  1016. /* TODO: Figure out when short_preamble would be set and cache from
  1017. * that */
  1018. if (!hw_to_local(priv->hw)->short_preamble)
  1019. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1020. else
  1021. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1022. #endif
  1023. ch_info = iwl_get_channel_info(priv, priv->band,
  1024. le16_to_cpu(priv->active_rxon.channel));
  1025. if (!ch_info)
  1026. ch_info = &priv->channel_info[0];
  1027. /*
  1028. * in some case A channels are all non IBSS
  1029. * in this case force B/G channel
  1030. */
  1031. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1032. !(is_channel_ibss(ch_info)))
  1033. ch_info = &priv->channel_info[0];
  1034. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1035. priv->band = ch_info->band;
  1036. iwl_set_flags_for_band(priv, priv->band);
  1037. priv->staging_rxon.ofdm_basic_rates =
  1038. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1039. priv->staging_rxon.cck_basic_rates =
  1040. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1041. /* clear both MIX and PURE40 mode flag */
  1042. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1043. RXON_FLG_CHANNEL_MODE_PURE_40);
  1044. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1045. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1046. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1047. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1048. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1049. }
  1050. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1051. static void iwl_set_rate(struct iwl_priv *priv)
  1052. {
  1053. const struct ieee80211_supported_band *hw = NULL;
  1054. struct ieee80211_rate *rate;
  1055. int i;
  1056. hw = iwl_get_hw_mode(priv, priv->band);
  1057. if (!hw) {
  1058. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1059. return;
  1060. }
  1061. priv->active_rate = 0;
  1062. priv->active_rate_basic = 0;
  1063. for (i = 0; i < hw->n_bitrates; i++) {
  1064. rate = &(hw->bitrates[i]);
  1065. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  1066. priv->active_rate |= (1 << rate->hw_value);
  1067. }
  1068. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  1069. priv->active_rate, priv->active_rate_basic);
  1070. /*
  1071. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1072. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1073. * OFDM
  1074. */
  1075. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1076. priv->staging_rxon.cck_basic_rates =
  1077. ((priv->active_rate_basic &
  1078. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1079. else
  1080. priv->staging_rxon.cck_basic_rates =
  1081. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1082. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1083. priv->staging_rxon.ofdm_basic_rates =
  1084. ((priv->active_rate_basic &
  1085. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1086. IWL_FIRST_OFDM_RATE) & 0xFF;
  1087. else
  1088. priv->staging_rxon.ofdm_basic_rates =
  1089. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1090. }
  1091. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1092. {
  1093. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1094. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1095. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1096. if (!le32_to_cpu(csa->status)) {
  1097. rxon->channel = csa->channel;
  1098. priv->staging_rxon.channel = csa->channel;
  1099. IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
  1100. le16_to_cpu(csa->channel));
  1101. } else
  1102. IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
  1103. le16_to_cpu(csa->channel));
  1104. }
  1105. EXPORT_SYMBOL(iwl_rx_csa);
  1106. #ifdef CONFIG_IWLWIFI_DEBUG
  1107. static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1108. {
  1109. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1110. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1111. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1112. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1113. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1114. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1115. le32_to_cpu(rxon->filter_flags));
  1116. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1117. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1118. rxon->ofdm_basic_rates);
  1119. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1120. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1121. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1122. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1123. }
  1124. #endif
  1125. /**
  1126. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1127. */
  1128. void iwl_irq_handle_error(struct iwl_priv *priv)
  1129. {
  1130. /* Set the FW error flag -- cleared on iwl_down */
  1131. set_bit(STATUS_FW_ERROR, &priv->status);
  1132. /* Cancel currently queued command. */
  1133. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1134. #ifdef CONFIG_IWLWIFI_DEBUG
  1135. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
  1136. priv->cfg->ops->lib->dump_nic_error_log(priv);
  1137. priv->cfg->ops->lib->dump_nic_event_log(priv);
  1138. iwl_print_rx_config_cmd(priv);
  1139. }
  1140. #endif
  1141. wake_up_interruptible(&priv->wait_command_queue);
  1142. /* Keep the restart process from trying to send host
  1143. * commands by clearing the INIT status bit */
  1144. clear_bit(STATUS_READY, &priv->status);
  1145. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1146. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1147. "Restarting adapter due to uCode error.\n");
  1148. if (priv->cfg->mod_params->restart_fw)
  1149. queue_work(priv->workqueue, &priv->restart);
  1150. }
  1151. }
  1152. EXPORT_SYMBOL(iwl_irq_handle_error);
  1153. int iwl_apm_stop_master(struct iwl_priv *priv)
  1154. {
  1155. int ret = 0;
  1156. /* stop device's busmaster DMA activity */
  1157. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  1158. ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  1159. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  1160. if (ret)
  1161. IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
  1162. IWL_DEBUG_INFO(priv, "stop master\n");
  1163. return ret;
  1164. }
  1165. EXPORT_SYMBOL(iwl_apm_stop_master);
  1166. void iwl_apm_stop(struct iwl_priv *priv)
  1167. {
  1168. IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
  1169. /* Stop device's DMA activity */
  1170. iwl_apm_stop_master(priv);
  1171. /* Reset the entire device */
  1172. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  1173. udelay(10);
  1174. /*
  1175. * Clear "initialization complete" bit to move adapter from
  1176. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  1177. */
  1178. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1179. }
  1180. EXPORT_SYMBOL(iwl_apm_stop);
  1181. /*
  1182. * Start up NIC's basic functionality after it has been reset
  1183. * (e.g. after platform boot, or shutdown via iwl_apm_stop())
  1184. * NOTE: This does not load uCode nor start the embedded processor
  1185. */
  1186. int iwl_apm_init(struct iwl_priv *priv)
  1187. {
  1188. int ret = 0;
  1189. u16 lctl;
  1190. IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
  1191. /*
  1192. * Use "set_bit" below rather than "write", to preserve any hardware
  1193. * bits already set by default after reset.
  1194. */
  1195. /* Disable L0S exit timer (platform NMI Work/Around) */
  1196. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1197. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  1198. /*
  1199. * Disable L0s without affecting L1;
  1200. * don't wait for ICH L0s (ICH bug W/A)
  1201. */
  1202. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1203. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  1204. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  1205. iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  1206. /*
  1207. * Enable HAP INTA (interrupt from management bus) to
  1208. * wake device's PCI Express link L1a -> L0s
  1209. * NOTE: This is no-op for 3945 (non-existant bit)
  1210. */
  1211. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1212. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  1213. /*
  1214. * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
  1215. * Check if BIOS (or OS) enabled L1-ASPM on this device.
  1216. * If so (likely), disable L0S, so device moves directly L0->L1;
  1217. * costs negligible amount of power savings.
  1218. * If not (unlikely), enable L0S, so there is at least some
  1219. * power savings, even without L1.
  1220. */
  1221. if (priv->cfg->set_l0s) {
  1222. lctl = iwl_pcie_link_ctl(priv);
  1223. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  1224. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  1225. /* L1-ASPM enabled; disable(!) L0S */
  1226. iwl_set_bit(priv, CSR_GIO_REG,
  1227. CSR_GIO_REG_VAL_L0S_ENABLED);
  1228. IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
  1229. } else {
  1230. /* L1-ASPM disabled; enable(!) L0S */
  1231. iwl_clear_bit(priv, CSR_GIO_REG,
  1232. CSR_GIO_REG_VAL_L0S_ENABLED);
  1233. IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
  1234. }
  1235. }
  1236. /* Configure analog phase-lock-loop before activating to D0A */
  1237. if (priv->cfg->pll_cfg_val)
  1238. iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
  1239. /*
  1240. * Set "initialization complete" bit to move adapter from
  1241. * D0U* --> D0A* (powered-up active) state.
  1242. */
  1243. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1244. /*
  1245. * Wait for clock stabilization; once stabilized, access to
  1246. * device-internal resources is supported, e.g. iwl_write_prph()
  1247. * and accesses to uCode SRAM.
  1248. */
  1249. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  1250. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  1251. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  1252. if (ret < 0) {
  1253. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  1254. goto out;
  1255. }
  1256. /*
  1257. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  1258. * BSM (Boostrap State Machine) is only in 3945 and 4965;
  1259. * later devices (i.e. 5000 and later) have non-volatile SRAM,
  1260. * and don't need BSM to restore data after power-saving sleep.
  1261. *
  1262. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  1263. * do not disable clocks. This preserves any hardware bits already
  1264. * set by default in "CLK_CTRL_REG" after reset.
  1265. */
  1266. if (priv->cfg->use_bsm)
  1267. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1268. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  1269. else
  1270. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1271. APMG_CLK_VAL_DMA_CLK_RQT);
  1272. udelay(20);
  1273. /* Disable L1-Active */
  1274. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  1275. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  1276. out:
  1277. return ret;
  1278. }
  1279. EXPORT_SYMBOL(iwl_apm_init);
  1280. void iwl_configure_filter(struct ieee80211_hw *hw,
  1281. unsigned int changed_flags,
  1282. unsigned int *total_flags,
  1283. u64 multicast)
  1284. {
  1285. struct iwl_priv *priv = hw->priv;
  1286. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1287. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1288. changed_flags, *total_flags);
  1289. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1290. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1291. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1292. else
  1293. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1294. }
  1295. if (changed_flags & FIF_ALLMULTI) {
  1296. if (*total_flags & FIF_ALLMULTI)
  1297. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1298. else
  1299. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1300. }
  1301. if (changed_flags & FIF_CONTROL) {
  1302. if (*total_flags & FIF_CONTROL)
  1303. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1304. else
  1305. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1306. }
  1307. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1308. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1309. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1310. else
  1311. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1312. }
  1313. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1314. * since mac80211 will call ieee80211_hw_config immediately.
  1315. * (mc_list is not supported at this time). Otherwise, we need to
  1316. * queue a background iwl_commit_rxon work.
  1317. */
  1318. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1319. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1320. }
  1321. EXPORT_SYMBOL(iwl_configure_filter);
  1322. int iwl_set_hw_params(struct iwl_priv *priv)
  1323. {
  1324. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1325. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1326. if (priv->cfg->mod_params->amsdu_size_8K)
  1327. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  1328. else
  1329. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  1330. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1331. if (priv->cfg->mod_params->disable_11n)
  1332. priv->cfg->sku &= ~IWL_SKU_N;
  1333. /* Device-specific setup */
  1334. return priv->cfg->ops->lib->set_hw_params(priv);
  1335. }
  1336. EXPORT_SYMBOL(iwl_set_hw_params);
  1337. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1338. {
  1339. int ret = 0;
  1340. s8 prev_tx_power = priv->tx_power_user_lmt;
  1341. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1342. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1343. tx_power,
  1344. IWL_TX_POWER_TARGET_POWER_MIN);
  1345. return -EINVAL;
  1346. }
  1347. if (tx_power > priv->tx_power_device_lmt) {
  1348. IWL_WARN(priv,
  1349. "Requested user TXPOWER %d above upper limit %d.\n",
  1350. tx_power, priv->tx_power_device_lmt);
  1351. return -EINVAL;
  1352. }
  1353. if (priv->tx_power_user_lmt != tx_power)
  1354. force = true;
  1355. /* if nic is not up don't send command */
  1356. if (iwl_is_ready_rf(priv)) {
  1357. priv->tx_power_user_lmt = tx_power;
  1358. if (force && priv->cfg->ops->lib->send_tx_power)
  1359. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1360. else if (!priv->cfg->ops->lib->send_tx_power)
  1361. ret = -EOPNOTSUPP;
  1362. /*
  1363. * if fail to set tx_power, restore the orig. tx power
  1364. */
  1365. if (ret)
  1366. priv->tx_power_user_lmt = prev_tx_power;
  1367. }
  1368. /*
  1369. * Even this is an async host command, the command
  1370. * will always report success from uCode
  1371. * So once driver can placing the command into the queue
  1372. * successfully, driver can use priv->tx_power_user_lmt
  1373. * to reflect the current tx power
  1374. */
  1375. return ret;
  1376. }
  1377. EXPORT_SYMBOL(iwl_set_tx_power);
  1378. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1379. /* Free dram table */
  1380. void iwl_free_isr_ict(struct iwl_priv *priv)
  1381. {
  1382. if (priv->ict_tbl_vir) {
  1383. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1384. PAGE_SIZE, priv->ict_tbl_vir,
  1385. priv->ict_tbl_dma);
  1386. priv->ict_tbl_vir = NULL;
  1387. }
  1388. }
  1389. EXPORT_SYMBOL(iwl_free_isr_ict);
  1390. /* allocate dram shared table it is a PAGE_SIZE aligned
  1391. * also reset all data related to ICT table interrupt.
  1392. */
  1393. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1394. {
  1395. if (priv->cfg->use_isr_legacy)
  1396. return 0;
  1397. /* allocate shrared data table */
  1398. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1399. ICT_COUNT) + PAGE_SIZE,
  1400. &priv->ict_tbl_dma);
  1401. if (!priv->ict_tbl_vir)
  1402. return -ENOMEM;
  1403. /* align table to PAGE_SIZE boundry */
  1404. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1405. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1406. (unsigned long long)priv->ict_tbl_dma,
  1407. (unsigned long long)priv->aligned_ict_tbl_dma,
  1408. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1409. priv->ict_tbl = priv->ict_tbl_vir +
  1410. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1411. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1412. priv->ict_tbl, priv->ict_tbl_vir,
  1413. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1414. /* reset table and index to all 0 */
  1415. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1416. priv->ict_index = 0;
  1417. /* add periodic RX interrupt */
  1418. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1419. return 0;
  1420. }
  1421. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1422. /* Device is going up inform it about using ICT interrupt table,
  1423. * also we need to tell the driver to start using ICT interrupt.
  1424. */
  1425. int iwl_reset_ict(struct iwl_priv *priv)
  1426. {
  1427. u32 val;
  1428. unsigned long flags;
  1429. if (!priv->ict_tbl_vir)
  1430. return 0;
  1431. spin_lock_irqsave(&priv->lock, flags);
  1432. iwl_disable_interrupts(priv);
  1433. memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
  1434. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1435. val |= CSR_DRAM_INT_TBL_ENABLE;
  1436. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1437. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1438. "aligned dma address %Lx\n",
  1439. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1440. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1441. priv->use_ict = true;
  1442. priv->ict_index = 0;
  1443. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1444. iwl_enable_interrupts(priv);
  1445. spin_unlock_irqrestore(&priv->lock, flags);
  1446. return 0;
  1447. }
  1448. EXPORT_SYMBOL(iwl_reset_ict);
  1449. /* Device is going down disable ict interrupt usage */
  1450. void iwl_disable_ict(struct iwl_priv *priv)
  1451. {
  1452. unsigned long flags;
  1453. spin_lock_irqsave(&priv->lock, flags);
  1454. priv->use_ict = false;
  1455. spin_unlock_irqrestore(&priv->lock, flags);
  1456. }
  1457. EXPORT_SYMBOL(iwl_disable_ict);
  1458. /* interrupt handler using ict table, with this interrupt driver will
  1459. * stop using INTA register to get device's interrupt, reading this register
  1460. * is expensive, device will write interrupts in ICT dram table, increment
  1461. * index then will fire interrupt to driver, driver will OR all ICT table
  1462. * entries from current index up to table entry with 0 value. the result is
  1463. * the interrupt we need to service, driver will set the entries back to 0 and
  1464. * set index.
  1465. */
  1466. irqreturn_t iwl_isr_ict(int irq, void *data)
  1467. {
  1468. struct iwl_priv *priv = data;
  1469. u32 inta, inta_mask;
  1470. u32 val = 0;
  1471. if (!priv)
  1472. return IRQ_NONE;
  1473. /* dram interrupt table not set yet,
  1474. * use legacy interrupt.
  1475. */
  1476. if (!priv->use_ict)
  1477. return iwl_isr(irq, data);
  1478. spin_lock(&priv->lock);
  1479. /* Disable (but don't clear!) interrupts here to avoid
  1480. * back-to-back ISRs and sporadic interrupts from our NIC.
  1481. * If we have something to service, the tasklet will re-enable ints.
  1482. * If we *don't* have something, we'll re-enable before leaving here.
  1483. */
  1484. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1485. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1486. /* Ignore interrupt if there's nothing in NIC to service.
  1487. * This may be due to IRQ shared with another device,
  1488. * or due to sporadic interrupts thrown from our NIC. */
  1489. if (!priv->ict_tbl[priv->ict_index]) {
  1490. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1491. goto none;
  1492. }
  1493. /* read all entries that not 0 start with ict_index */
  1494. while (priv->ict_tbl[priv->ict_index]) {
  1495. val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
  1496. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1497. priv->ict_index,
  1498. le32_to_cpu(priv->ict_tbl[priv->ict_index]));
  1499. priv->ict_tbl[priv->ict_index] = 0;
  1500. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1501. ICT_COUNT);
  1502. }
  1503. /* We should not get this value, just ignore it. */
  1504. if (val == 0xffffffff)
  1505. val = 0;
  1506. inta = (0xff & val) | ((0xff00 & val) << 16);
  1507. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1508. inta, inta_mask, val);
  1509. inta &= priv->inta_mask;
  1510. priv->inta |= inta;
  1511. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1512. if (likely(inta))
  1513. tasklet_schedule(&priv->irq_tasklet);
  1514. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1515. /* Allow interrupt if was disabled by this handler and
  1516. * no tasklet was schedules, We should not enable interrupt,
  1517. * tasklet will enable it.
  1518. */
  1519. iwl_enable_interrupts(priv);
  1520. }
  1521. spin_unlock(&priv->lock);
  1522. return IRQ_HANDLED;
  1523. none:
  1524. /* re-enable interrupts here since we don't have anything to service.
  1525. * only Re-enable if disabled by irq.
  1526. */
  1527. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1528. iwl_enable_interrupts(priv);
  1529. spin_unlock(&priv->lock);
  1530. return IRQ_NONE;
  1531. }
  1532. EXPORT_SYMBOL(iwl_isr_ict);
  1533. static irqreturn_t iwl_isr(int irq, void *data)
  1534. {
  1535. struct iwl_priv *priv = data;
  1536. u32 inta, inta_mask;
  1537. #ifdef CONFIG_IWLWIFI_DEBUG
  1538. u32 inta_fh;
  1539. #endif
  1540. if (!priv)
  1541. return IRQ_NONE;
  1542. spin_lock(&priv->lock);
  1543. /* Disable (but don't clear!) interrupts here to avoid
  1544. * back-to-back ISRs and sporadic interrupts from our NIC.
  1545. * If we have something to service, the tasklet will re-enable ints.
  1546. * If we *don't* have something, we'll re-enable before leaving here. */
  1547. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1548. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1549. /* Discover which interrupts are active/pending */
  1550. inta = iwl_read32(priv, CSR_INT);
  1551. /* Ignore interrupt if there's nothing in NIC to service.
  1552. * This may be due to IRQ shared with another device,
  1553. * or due to sporadic interrupts thrown from our NIC. */
  1554. if (!inta) {
  1555. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1556. goto none;
  1557. }
  1558. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1559. /* Hardware disappeared. It might have already raised
  1560. * an interrupt */
  1561. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1562. goto unplugged;
  1563. }
  1564. #ifdef CONFIG_IWLWIFI_DEBUG
  1565. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1566. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1567. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1568. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1569. }
  1570. #endif
  1571. priv->inta |= inta;
  1572. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1573. if (likely(inta))
  1574. tasklet_schedule(&priv->irq_tasklet);
  1575. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1576. iwl_enable_interrupts(priv);
  1577. unplugged:
  1578. spin_unlock(&priv->lock);
  1579. return IRQ_HANDLED;
  1580. none:
  1581. /* re-enable interrupts here since we don't have anything to service. */
  1582. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1583. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1584. iwl_enable_interrupts(priv);
  1585. spin_unlock(&priv->lock);
  1586. return IRQ_NONE;
  1587. }
  1588. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1589. {
  1590. struct iwl_priv *priv = data;
  1591. u32 inta, inta_mask;
  1592. u32 inta_fh;
  1593. if (!priv)
  1594. return IRQ_NONE;
  1595. spin_lock(&priv->lock);
  1596. /* Disable (but don't clear!) interrupts here to avoid
  1597. * back-to-back ISRs and sporadic interrupts from our NIC.
  1598. * If we have something to service, the tasklet will re-enable ints.
  1599. * If we *don't* have something, we'll re-enable before leaving here. */
  1600. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1601. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1602. /* Discover which interrupts are active/pending */
  1603. inta = iwl_read32(priv, CSR_INT);
  1604. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1605. /* Ignore interrupt if there's nothing in NIC to service.
  1606. * This may be due to IRQ shared with another device,
  1607. * or due to sporadic interrupts thrown from our NIC. */
  1608. if (!inta && !inta_fh) {
  1609. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1610. goto none;
  1611. }
  1612. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1613. /* Hardware disappeared. It might have already raised
  1614. * an interrupt */
  1615. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1616. goto unplugged;
  1617. }
  1618. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1619. inta, inta_mask, inta_fh);
  1620. inta &= ~CSR_INT_BIT_SCD;
  1621. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1622. if (likely(inta || inta_fh))
  1623. tasklet_schedule(&priv->irq_tasklet);
  1624. unplugged:
  1625. spin_unlock(&priv->lock);
  1626. return IRQ_HANDLED;
  1627. none:
  1628. /* re-enable interrupts here since we don't have anything to service. */
  1629. /* only Re-enable if diabled by irq */
  1630. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1631. iwl_enable_interrupts(priv);
  1632. spin_unlock(&priv->lock);
  1633. return IRQ_NONE;
  1634. }
  1635. EXPORT_SYMBOL(iwl_isr_legacy);
  1636. int iwl_send_bt_config(struct iwl_priv *priv)
  1637. {
  1638. struct iwl_bt_cmd bt_cmd = {
  1639. .flags = BT_COEX_MODE_4W,
  1640. .lead_time = BT_LEAD_TIME_DEF,
  1641. .max_kill = BT_MAX_KILL_DEF,
  1642. .kill_ack_mask = 0,
  1643. .kill_cts_mask = 0,
  1644. };
  1645. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1646. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1647. }
  1648. EXPORT_SYMBOL(iwl_send_bt_config);
  1649. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
  1650. {
  1651. u32 stat_flags = 0;
  1652. struct iwl_host_cmd cmd = {
  1653. .id = REPLY_STATISTICS_CMD,
  1654. .flags = flags,
  1655. .len = sizeof(stat_flags),
  1656. .data = (u8 *) &stat_flags,
  1657. };
  1658. return iwl_send_cmd(priv, &cmd);
  1659. }
  1660. EXPORT_SYMBOL(iwl_send_statistics_request);
  1661. /**
  1662. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1663. * using sample data 100 bytes apart. If these sample points are good,
  1664. * it's a pretty good bet that everything between them is good, too.
  1665. */
  1666. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1667. {
  1668. u32 val;
  1669. int ret = 0;
  1670. u32 errcnt = 0;
  1671. u32 i;
  1672. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1673. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1674. /* read data comes through single port, auto-incr addr */
  1675. /* NOTE: Use the debugless read so we don't flood kernel log
  1676. * if IWL_DL_IO is set */
  1677. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1678. i + IWL49_RTC_INST_LOWER_BOUND);
  1679. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1680. if (val != le32_to_cpu(*image)) {
  1681. ret = -EIO;
  1682. errcnt++;
  1683. if (errcnt >= 3)
  1684. break;
  1685. }
  1686. }
  1687. return ret;
  1688. }
  1689. /**
  1690. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1691. * looking at all data.
  1692. */
  1693. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1694. u32 len)
  1695. {
  1696. u32 val;
  1697. u32 save_len = len;
  1698. int ret = 0;
  1699. u32 errcnt;
  1700. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1701. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1702. IWL49_RTC_INST_LOWER_BOUND);
  1703. errcnt = 0;
  1704. for (; len > 0; len -= sizeof(u32), image++) {
  1705. /* read data comes through single port, auto-incr addr */
  1706. /* NOTE: Use the debugless read so we don't flood kernel log
  1707. * if IWL_DL_IO is set */
  1708. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1709. if (val != le32_to_cpu(*image)) {
  1710. IWL_ERR(priv, "uCode INST section is invalid at "
  1711. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1712. save_len - len, val, le32_to_cpu(*image));
  1713. ret = -EIO;
  1714. errcnt++;
  1715. if (errcnt >= 20)
  1716. break;
  1717. }
  1718. }
  1719. if (!errcnt)
  1720. IWL_DEBUG_INFO(priv,
  1721. "ucode image in INSTRUCTION memory is good\n");
  1722. return ret;
  1723. }
  1724. /**
  1725. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1726. * and verify its contents
  1727. */
  1728. int iwl_verify_ucode(struct iwl_priv *priv)
  1729. {
  1730. __le32 *image;
  1731. u32 len;
  1732. int ret;
  1733. /* Try bootstrap */
  1734. image = (__le32 *)priv->ucode_boot.v_addr;
  1735. len = priv->ucode_boot.len;
  1736. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1737. if (!ret) {
  1738. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1739. return 0;
  1740. }
  1741. /* Try initialize */
  1742. image = (__le32 *)priv->ucode_init.v_addr;
  1743. len = priv->ucode_init.len;
  1744. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1745. if (!ret) {
  1746. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1747. return 0;
  1748. }
  1749. /* Try runtime/protocol */
  1750. image = (__le32 *)priv->ucode_code.v_addr;
  1751. len = priv->ucode_code.len;
  1752. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1753. if (!ret) {
  1754. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1755. return 0;
  1756. }
  1757. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1758. /* Since nothing seems to match, show first several data entries in
  1759. * instruction SRAM, so maybe visual inspection will give a clue.
  1760. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1761. image = (__le32 *)priv->ucode_boot.v_addr;
  1762. len = priv->ucode_boot.len;
  1763. ret = iwl_verify_inst_full(priv, image, len);
  1764. return ret;
  1765. }
  1766. EXPORT_SYMBOL(iwl_verify_ucode);
  1767. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1768. {
  1769. struct iwl_ct_kill_config cmd;
  1770. struct iwl_ct_kill_throttling_config adv_cmd;
  1771. unsigned long flags;
  1772. int ret = 0;
  1773. spin_lock_irqsave(&priv->lock, flags);
  1774. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1775. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1776. spin_unlock_irqrestore(&priv->lock, flags);
  1777. priv->thermal_throttle.ct_kill_toggle = false;
  1778. if (priv->cfg->support_ct_kill_exit) {
  1779. adv_cmd.critical_temperature_enter =
  1780. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1781. adv_cmd.critical_temperature_exit =
  1782. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1783. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1784. sizeof(adv_cmd), &adv_cmd);
  1785. if (ret)
  1786. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1787. else
  1788. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1789. "succeeded, "
  1790. "critical temperature enter is %d,"
  1791. "exit is %d\n",
  1792. priv->hw_params.ct_kill_threshold,
  1793. priv->hw_params.ct_kill_exit_threshold);
  1794. } else {
  1795. cmd.critical_temperature_R =
  1796. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1797. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1798. sizeof(cmd), &cmd);
  1799. if (ret)
  1800. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1801. else
  1802. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1803. "succeeded, "
  1804. "critical temperature is %d\n",
  1805. priv->hw_params.ct_kill_threshold);
  1806. }
  1807. }
  1808. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1809. /*
  1810. * CARD_STATE_CMD
  1811. *
  1812. * Use: Sets the device's internal card state to enable, disable, or halt
  1813. *
  1814. * When in the 'enable' state the card operates as normal.
  1815. * When in the 'disable' state, the card enters into a low power mode.
  1816. * When in the 'halt' state, the card is shut down and must be fully
  1817. * restarted to come back on.
  1818. */
  1819. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1820. {
  1821. struct iwl_host_cmd cmd = {
  1822. .id = REPLY_CARD_STATE_CMD,
  1823. .len = sizeof(u32),
  1824. .data = &flags,
  1825. .flags = meta_flag,
  1826. };
  1827. return iwl_send_cmd(priv, &cmd);
  1828. }
  1829. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1830. struct iwl_rx_mem_buffer *rxb)
  1831. {
  1832. #ifdef CONFIG_IWLWIFI_DEBUG
  1833. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1834. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1835. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1836. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1837. #endif
  1838. }
  1839. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1840. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1841. struct iwl_rx_mem_buffer *rxb)
  1842. {
  1843. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1844. u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1845. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1846. "notification for %s:\n", len,
  1847. get_cmd_string(pkt->hdr.cmd));
  1848. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
  1849. }
  1850. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1851. void iwl_rx_reply_error(struct iwl_priv *priv,
  1852. struct iwl_rx_mem_buffer *rxb)
  1853. {
  1854. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1855. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1856. "seq 0x%04X ser 0x%08X\n",
  1857. le32_to_cpu(pkt->u.err_resp.error_type),
  1858. get_cmd_string(pkt->u.err_resp.cmd_id),
  1859. pkt->u.err_resp.cmd_id,
  1860. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1861. le32_to_cpu(pkt->u.err_resp.error_info));
  1862. }
  1863. EXPORT_SYMBOL(iwl_rx_reply_error);
  1864. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1865. {
  1866. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1867. }
  1868. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1869. const struct ieee80211_tx_queue_params *params)
  1870. {
  1871. struct iwl_priv *priv = hw->priv;
  1872. unsigned long flags;
  1873. int q;
  1874. IWL_DEBUG_MAC80211(priv, "enter\n");
  1875. if (!iwl_is_ready_rf(priv)) {
  1876. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1877. return -EIO;
  1878. }
  1879. if (queue >= AC_NUM) {
  1880. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1881. return 0;
  1882. }
  1883. q = AC_NUM - 1 - queue;
  1884. spin_lock_irqsave(&priv->lock, flags);
  1885. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1886. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1887. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1888. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1889. cpu_to_le16((params->txop * 32));
  1890. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1891. priv->qos_data.qos_active = 1;
  1892. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1893. iwl_activate_qos(priv, 1);
  1894. else if (priv->assoc_id && iwl_is_associated(priv))
  1895. iwl_activate_qos(priv, 0);
  1896. spin_unlock_irqrestore(&priv->lock, flags);
  1897. IWL_DEBUG_MAC80211(priv, "leave\n");
  1898. return 0;
  1899. }
  1900. EXPORT_SYMBOL(iwl_mac_conf_tx);
  1901. static void iwl_ht_conf(struct iwl_priv *priv,
  1902. struct ieee80211_bss_conf *bss_conf)
  1903. {
  1904. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  1905. struct ieee80211_sta *sta;
  1906. IWL_DEBUG_MAC80211(priv, "enter: \n");
  1907. if (!ht_conf->is_ht)
  1908. return;
  1909. ht_conf->ht_protection =
  1910. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  1911. ht_conf->non_GF_STA_present =
  1912. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1913. ht_conf->single_chain_sufficient = false;
  1914. switch (priv->iw_mode) {
  1915. case NL80211_IFTYPE_STATION:
  1916. rcu_read_lock();
  1917. sta = ieee80211_find_sta(priv->hw, priv->bssid);
  1918. if (sta) {
  1919. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  1920. int maxstreams;
  1921. maxstreams = (ht_cap->mcs.tx_params &
  1922. IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  1923. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1924. maxstreams += 1;
  1925. ht_conf->sm_ps =
  1926. (u8)((ht_cap->cap & IEEE80211_HT_CAP_SM_PS)
  1927. >> 2);
  1928. IWL_DEBUG_MAC80211(priv, "sm_ps: 0x%x\n",
  1929. ht_conf->sm_ps);
  1930. if ((ht_cap->mcs.rx_mask[1] == 0) &&
  1931. (ht_cap->mcs.rx_mask[2] == 0))
  1932. ht_conf->single_chain_sufficient = true;
  1933. if (maxstreams <= 1)
  1934. ht_conf->single_chain_sufficient = true;
  1935. } else {
  1936. /*
  1937. * If at all, this can only happen through a race
  1938. * when the AP disconnects us while we're still
  1939. * setting up the connection, in that case mac80211
  1940. * will soon tell us about that.
  1941. */
  1942. ht_conf->single_chain_sufficient = true;
  1943. }
  1944. rcu_read_unlock();
  1945. break;
  1946. case NL80211_IFTYPE_ADHOC:
  1947. ht_conf->single_chain_sufficient = true;
  1948. break;
  1949. default:
  1950. break;
  1951. }
  1952. IWL_DEBUG_MAC80211(priv, "leave\n");
  1953. }
  1954. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  1955. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  1956. struct ieee80211_vif *vif,
  1957. struct ieee80211_bss_conf *bss_conf,
  1958. u32 changes)
  1959. {
  1960. struct iwl_priv *priv = hw->priv;
  1961. int ret;
  1962. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  1963. if (!iwl_is_alive(priv))
  1964. return;
  1965. mutex_lock(&priv->mutex);
  1966. if (changes & BSS_CHANGED_BEACON &&
  1967. priv->iw_mode == NL80211_IFTYPE_AP) {
  1968. dev_kfree_skb(priv->ibss_beacon);
  1969. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  1970. }
  1971. if (changes & BSS_CHANGED_BEACON_INT) {
  1972. priv->beacon_int = bss_conf->beacon_int;
  1973. /* TODO: in AP mode, do something to make this take effect */
  1974. }
  1975. if (changes & BSS_CHANGED_BSSID) {
  1976. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  1977. /*
  1978. * If there is currently a HW scan going on in the
  1979. * background then we need to cancel it else the RXON
  1980. * below/in post_associate will fail.
  1981. */
  1982. if (iwl_scan_cancel_timeout(priv, 100)) {
  1983. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1984. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  1985. mutex_unlock(&priv->mutex);
  1986. return;
  1987. }
  1988. /* mac80211 only sets assoc when in STATION mode */
  1989. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  1990. bss_conf->assoc) {
  1991. memcpy(priv->staging_rxon.bssid_addr,
  1992. bss_conf->bssid, ETH_ALEN);
  1993. /* currently needed in a few places */
  1994. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  1995. } else {
  1996. priv->staging_rxon.filter_flags &=
  1997. ~RXON_FILTER_ASSOC_MSK;
  1998. }
  1999. }
  2000. /*
  2001. * This needs to be after setting the BSSID in case
  2002. * mac80211 decides to do both changes at once because
  2003. * it will invoke post_associate.
  2004. */
  2005. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2006. changes & BSS_CHANGED_BEACON) {
  2007. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2008. if (beacon)
  2009. iwl_mac_beacon_update(hw, beacon);
  2010. }
  2011. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2012. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2013. bss_conf->use_short_preamble);
  2014. if (bss_conf->use_short_preamble)
  2015. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2016. else
  2017. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2018. }
  2019. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2020. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2021. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2022. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2023. else
  2024. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2025. }
  2026. if (changes & BSS_CHANGED_BASIC_RATES) {
  2027. /* XXX use this information
  2028. *
  2029. * To do that, remove code from iwl_set_rate() and put something
  2030. * like this here:
  2031. *
  2032. if (A-band)
  2033. priv->staging_rxon.ofdm_basic_rates =
  2034. bss_conf->basic_rates;
  2035. else
  2036. priv->staging_rxon.ofdm_basic_rates =
  2037. bss_conf->basic_rates >> 4;
  2038. priv->staging_rxon.cck_basic_rates =
  2039. bss_conf->basic_rates & 0xF;
  2040. */
  2041. }
  2042. if (changes & BSS_CHANGED_HT) {
  2043. iwl_ht_conf(priv, bss_conf);
  2044. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2045. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2046. }
  2047. if (changes & BSS_CHANGED_ASSOC) {
  2048. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2049. if (bss_conf->assoc) {
  2050. priv->assoc_id = bss_conf->aid;
  2051. priv->beacon_int = bss_conf->beacon_int;
  2052. priv->timestamp = bss_conf->timestamp;
  2053. priv->assoc_capability = bss_conf->assoc_capability;
  2054. iwl_led_associate(priv);
  2055. /*
  2056. * We have just associated, don't start scan too early
  2057. * leave time for EAPOL exchange to complete.
  2058. *
  2059. * XXX: do this in mac80211
  2060. */
  2061. priv->next_scan_jiffies = jiffies +
  2062. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2063. if (!iwl_is_rfkill(priv))
  2064. priv->cfg->ops->lib->post_associate(priv);
  2065. } else {
  2066. priv->assoc_id = 0;
  2067. iwl_led_disassociate(priv);
  2068. }
  2069. }
  2070. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2071. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2072. changes);
  2073. ret = iwl_send_rxon_assoc(priv);
  2074. if (!ret) {
  2075. /* Sync active_rxon with latest change. */
  2076. memcpy((void *)&priv->active_rxon,
  2077. &priv->staging_rxon,
  2078. sizeof(struct iwl_rxon_cmd));
  2079. }
  2080. }
  2081. mutex_unlock(&priv->mutex);
  2082. IWL_DEBUG_MAC80211(priv, "leave\n");
  2083. }
  2084. EXPORT_SYMBOL(iwl_bss_info_changed);
  2085. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2086. {
  2087. struct iwl_priv *priv = hw->priv;
  2088. unsigned long flags;
  2089. __le64 timestamp;
  2090. IWL_DEBUG_MAC80211(priv, "enter\n");
  2091. if (!iwl_is_ready_rf(priv)) {
  2092. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2093. return -EIO;
  2094. }
  2095. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2096. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2097. return -EIO;
  2098. }
  2099. spin_lock_irqsave(&priv->lock, flags);
  2100. if (priv->ibss_beacon)
  2101. dev_kfree_skb(priv->ibss_beacon);
  2102. priv->ibss_beacon = skb;
  2103. priv->assoc_id = 0;
  2104. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2105. priv->timestamp = le64_to_cpu(timestamp);
  2106. IWL_DEBUG_MAC80211(priv, "leave\n");
  2107. spin_unlock_irqrestore(&priv->lock, flags);
  2108. iwl_reset_qos(priv);
  2109. priv->cfg->ops->lib->post_associate(priv);
  2110. return 0;
  2111. }
  2112. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2113. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2114. {
  2115. if (mode == NL80211_IFTYPE_ADHOC) {
  2116. const struct iwl_channel_info *ch_info;
  2117. ch_info = iwl_get_channel_info(priv,
  2118. priv->band,
  2119. le16_to_cpu(priv->staging_rxon.channel));
  2120. if (!ch_info || !is_channel_ibss(ch_info)) {
  2121. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2122. le16_to_cpu(priv->staging_rxon.channel));
  2123. return -EINVAL;
  2124. }
  2125. }
  2126. iwl_connection_init_rx_config(priv, mode);
  2127. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2128. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2129. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2130. iwl_clear_stations_table(priv);
  2131. /* dont commit rxon if rf-kill is on*/
  2132. if (!iwl_is_ready_rf(priv))
  2133. return -EAGAIN;
  2134. iwlcore_commit_rxon(priv);
  2135. return 0;
  2136. }
  2137. EXPORT_SYMBOL(iwl_set_mode);
  2138. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2139. struct ieee80211_if_init_conf *conf)
  2140. {
  2141. struct iwl_priv *priv = hw->priv;
  2142. unsigned long flags;
  2143. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2144. if (priv->vif) {
  2145. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2146. return -EOPNOTSUPP;
  2147. }
  2148. spin_lock_irqsave(&priv->lock, flags);
  2149. priv->vif = conf->vif;
  2150. priv->iw_mode = conf->type;
  2151. spin_unlock_irqrestore(&priv->lock, flags);
  2152. mutex_lock(&priv->mutex);
  2153. if (conf->mac_addr) {
  2154. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2155. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2156. }
  2157. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2158. /* we are not ready, will run again when ready */
  2159. set_bit(STATUS_MODE_PENDING, &priv->status);
  2160. mutex_unlock(&priv->mutex);
  2161. IWL_DEBUG_MAC80211(priv, "leave\n");
  2162. return 0;
  2163. }
  2164. EXPORT_SYMBOL(iwl_mac_add_interface);
  2165. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2166. struct ieee80211_if_init_conf *conf)
  2167. {
  2168. struct iwl_priv *priv = hw->priv;
  2169. IWL_DEBUG_MAC80211(priv, "enter\n");
  2170. mutex_lock(&priv->mutex);
  2171. if (iwl_is_ready_rf(priv)) {
  2172. iwl_scan_cancel_timeout(priv, 100);
  2173. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2174. iwlcore_commit_rxon(priv);
  2175. }
  2176. if (priv->vif == conf->vif) {
  2177. priv->vif = NULL;
  2178. memset(priv->bssid, 0, ETH_ALEN);
  2179. }
  2180. mutex_unlock(&priv->mutex);
  2181. IWL_DEBUG_MAC80211(priv, "leave\n");
  2182. }
  2183. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2184. /**
  2185. * iwl_mac_config - mac80211 config callback
  2186. *
  2187. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2188. * be set inappropriately and the driver currently sets the hardware up to
  2189. * use it whenever needed.
  2190. */
  2191. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2192. {
  2193. struct iwl_priv *priv = hw->priv;
  2194. const struct iwl_channel_info *ch_info;
  2195. struct ieee80211_conf *conf = &hw->conf;
  2196. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2197. unsigned long flags = 0;
  2198. int ret = 0;
  2199. u16 ch;
  2200. int scan_active = 0;
  2201. mutex_lock(&priv->mutex);
  2202. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2203. conf->channel->hw_value, changed);
  2204. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2205. test_bit(STATUS_SCANNING, &priv->status))) {
  2206. scan_active = 1;
  2207. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2208. }
  2209. /* during scanning mac80211 will delay channel setting until
  2210. * scan finish with changed = 0
  2211. */
  2212. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2213. if (scan_active)
  2214. goto set_ch_out;
  2215. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2216. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2217. if (!is_channel_valid(ch_info)) {
  2218. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2219. ret = -EINVAL;
  2220. goto set_ch_out;
  2221. }
  2222. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2223. !is_channel_ibss(ch_info)) {
  2224. IWL_ERR(priv, "channel %d in band %d not "
  2225. "IBSS channel\n",
  2226. conf->channel->hw_value, conf->channel->band);
  2227. ret = -EINVAL;
  2228. goto set_ch_out;
  2229. }
  2230. if (iwl_is_associated(priv) &&
  2231. (le16_to_cpu(priv->active_rxon.channel) != ch) &&
  2232. priv->cfg->ops->lib->set_channel_switch) {
  2233. ret = priv->cfg->ops->lib->set_channel_switch(priv,
  2234. ch);
  2235. goto out;
  2236. }
  2237. spin_lock_irqsave(&priv->lock, flags);
  2238. /* Configure HT40 channels */
  2239. ht_conf->is_ht = conf_is_ht(conf);
  2240. if (ht_conf->is_ht) {
  2241. if (conf_is_ht40_minus(conf)) {
  2242. ht_conf->extension_chan_offset =
  2243. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2244. ht_conf->is_40mhz = true;
  2245. } else if (conf_is_ht40_plus(conf)) {
  2246. ht_conf->extension_chan_offset =
  2247. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2248. ht_conf->is_40mhz = true;
  2249. } else {
  2250. ht_conf->extension_chan_offset =
  2251. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2252. ht_conf->is_40mhz = false;
  2253. }
  2254. } else
  2255. ht_conf->is_40mhz = false;
  2256. /* Default to no protection. Protection mode will later be set
  2257. * from BSS config in iwl_ht_conf */
  2258. ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  2259. /* if we are switching from ht to 2.4 clear flags
  2260. * from any ht related info since 2.4 does not
  2261. * support ht */
  2262. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2263. priv->staging_rxon.flags = 0;
  2264. iwl_set_rxon_channel(priv, conf->channel);
  2265. iwl_set_flags_for_band(priv, conf->channel->band);
  2266. spin_unlock_irqrestore(&priv->lock, flags);
  2267. set_ch_out:
  2268. /* The list of supported rates and rate mask can be different
  2269. * for each band; since the band may have changed, reset
  2270. * the rate mask to what mac80211 lists */
  2271. iwl_set_rate(priv);
  2272. }
  2273. if (changed & (IEEE80211_CONF_CHANGE_PS |
  2274. IEEE80211_CONF_CHANGE_IDLE)) {
  2275. ret = iwl_power_update_mode(priv, false);
  2276. if (ret)
  2277. IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
  2278. }
  2279. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2280. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2281. priv->tx_power_user_lmt, conf->power_level);
  2282. iwl_set_tx_power(priv, conf->power_level, false);
  2283. }
  2284. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2285. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2286. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2287. if (!iwl_is_ready(priv)) {
  2288. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2289. goto out;
  2290. }
  2291. if (scan_active)
  2292. goto out;
  2293. if (memcmp(&priv->active_rxon,
  2294. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2295. iwlcore_commit_rxon(priv);
  2296. else
  2297. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2298. out:
  2299. IWL_DEBUG_MAC80211(priv, "leave\n");
  2300. mutex_unlock(&priv->mutex);
  2301. return ret;
  2302. }
  2303. EXPORT_SYMBOL(iwl_mac_config);
  2304. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2305. struct ieee80211_tx_queue_stats *stats)
  2306. {
  2307. struct iwl_priv *priv = hw->priv;
  2308. int i, avail;
  2309. struct iwl_tx_queue *txq;
  2310. struct iwl_queue *q;
  2311. unsigned long flags;
  2312. IWL_DEBUG_MAC80211(priv, "enter\n");
  2313. if (!iwl_is_ready_rf(priv)) {
  2314. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2315. return -EIO;
  2316. }
  2317. spin_lock_irqsave(&priv->lock, flags);
  2318. for (i = 0; i < AC_NUM; i++) {
  2319. txq = &priv->txq[i];
  2320. q = &txq->q;
  2321. avail = iwl_queue_space(q);
  2322. stats[i].len = q->n_window - avail;
  2323. stats[i].limit = q->n_window - q->high_mark;
  2324. stats[i].count = q->n_window;
  2325. }
  2326. spin_unlock_irqrestore(&priv->lock, flags);
  2327. IWL_DEBUG_MAC80211(priv, "leave\n");
  2328. return 0;
  2329. }
  2330. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2331. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2332. {
  2333. struct iwl_priv *priv = hw->priv;
  2334. unsigned long flags;
  2335. mutex_lock(&priv->mutex);
  2336. IWL_DEBUG_MAC80211(priv, "enter\n");
  2337. spin_lock_irqsave(&priv->lock, flags);
  2338. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
  2339. spin_unlock_irqrestore(&priv->lock, flags);
  2340. iwl_reset_qos(priv);
  2341. spin_lock_irqsave(&priv->lock, flags);
  2342. priv->assoc_id = 0;
  2343. priv->assoc_capability = 0;
  2344. priv->assoc_station_added = 0;
  2345. /* new association get rid of ibss beacon skb */
  2346. if (priv->ibss_beacon)
  2347. dev_kfree_skb(priv->ibss_beacon);
  2348. priv->ibss_beacon = NULL;
  2349. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2350. priv->timestamp = 0;
  2351. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2352. priv->beacon_int = 0;
  2353. spin_unlock_irqrestore(&priv->lock, flags);
  2354. if (!iwl_is_ready_rf(priv)) {
  2355. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2356. mutex_unlock(&priv->mutex);
  2357. return;
  2358. }
  2359. /* we are restarting association process
  2360. * clear RXON_FILTER_ASSOC_MSK bit
  2361. */
  2362. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2363. iwl_scan_cancel_timeout(priv, 100);
  2364. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2365. iwlcore_commit_rxon(priv);
  2366. }
  2367. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2368. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2369. mutex_unlock(&priv->mutex);
  2370. return;
  2371. }
  2372. iwl_set_rate(priv);
  2373. mutex_unlock(&priv->mutex);
  2374. IWL_DEBUG_MAC80211(priv, "leave\n");
  2375. }
  2376. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2377. int iwl_alloc_txq_mem(struct iwl_priv *priv)
  2378. {
  2379. if (!priv->txq)
  2380. priv->txq = kzalloc(
  2381. sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
  2382. GFP_KERNEL);
  2383. if (!priv->txq) {
  2384. IWL_ERR(priv, "Not enough memory for txq \n");
  2385. return -ENOMEM;
  2386. }
  2387. return 0;
  2388. }
  2389. EXPORT_SYMBOL(iwl_alloc_txq_mem);
  2390. void iwl_free_txq_mem(struct iwl_priv *priv)
  2391. {
  2392. kfree(priv->txq);
  2393. priv->txq = NULL;
  2394. }
  2395. EXPORT_SYMBOL(iwl_free_txq_mem);
  2396. #ifdef CONFIG_IWLWIFI_DEBUGFS
  2397. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  2398. void iwl_reset_traffic_log(struct iwl_priv *priv)
  2399. {
  2400. priv->tx_traffic_idx = 0;
  2401. priv->rx_traffic_idx = 0;
  2402. if (priv->tx_traffic)
  2403. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2404. if (priv->rx_traffic)
  2405. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2406. }
  2407. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  2408. {
  2409. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  2410. if (iwl_debug_level & IWL_DL_TX) {
  2411. if (!priv->tx_traffic) {
  2412. priv->tx_traffic =
  2413. kzalloc(traffic_size, GFP_KERNEL);
  2414. if (!priv->tx_traffic)
  2415. return -ENOMEM;
  2416. }
  2417. }
  2418. if (iwl_debug_level & IWL_DL_RX) {
  2419. if (!priv->rx_traffic) {
  2420. priv->rx_traffic =
  2421. kzalloc(traffic_size, GFP_KERNEL);
  2422. if (!priv->rx_traffic)
  2423. return -ENOMEM;
  2424. }
  2425. }
  2426. iwl_reset_traffic_log(priv);
  2427. return 0;
  2428. }
  2429. EXPORT_SYMBOL(iwl_alloc_traffic_mem);
  2430. void iwl_free_traffic_mem(struct iwl_priv *priv)
  2431. {
  2432. kfree(priv->tx_traffic);
  2433. priv->tx_traffic = NULL;
  2434. kfree(priv->rx_traffic);
  2435. priv->rx_traffic = NULL;
  2436. }
  2437. EXPORT_SYMBOL(iwl_free_traffic_mem);
  2438. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  2439. u16 length, struct ieee80211_hdr *header)
  2440. {
  2441. __le16 fc;
  2442. u16 len;
  2443. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  2444. return;
  2445. if (!priv->tx_traffic)
  2446. return;
  2447. fc = header->frame_control;
  2448. if (ieee80211_is_data(fc)) {
  2449. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2450. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2451. memcpy((priv->tx_traffic +
  2452. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2453. header, len);
  2454. priv->tx_traffic_idx =
  2455. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2456. }
  2457. }
  2458. EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
  2459. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  2460. u16 length, struct ieee80211_hdr *header)
  2461. {
  2462. __le16 fc;
  2463. u16 len;
  2464. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  2465. return;
  2466. if (!priv->rx_traffic)
  2467. return;
  2468. fc = header->frame_control;
  2469. if (ieee80211_is_data(fc)) {
  2470. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2471. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2472. memcpy((priv->rx_traffic +
  2473. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2474. header, len);
  2475. priv->rx_traffic_idx =
  2476. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2477. }
  2478. }
  2479. EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
  2480. const char *get_mgmt_string(int cmd)
  2481. {
  2482. switch (cmd) {
  2483. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  2484. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  2485. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  2486. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  2487. IWL_CMD(MANAGEMENT_PROBE_REQ);
  2488. IWL_CMD(MANAGEMENT_PROBE_RESP);
  2489. IWL_CMD(MANAGEMENT_BEACON);
  2490. IWL_CMD(MANAGEMENT_ATIM);
  2491. IWL_CMD(MANAGEMENT_DISASSOC);
  2492. IWL_CMD(MANAGEMENT_AUTH);
  2493. IWL_CMD(MANAGEMENT_DEAUTH);
  2494. IWL_CMD(MANAGEMENT_ACTION);
  2495. default:
  2496. return "UNKNOWN";
  2497. }
  2498. }
  2499. const char *get_ctrl_string(int cmd)
  2500. {
  2501. switch (cmd) {
  2502. IWL_CMD(CONTROL_BACK_REQ);
  2503. IWL_CMD(CONTROL_BACK);
  2504. IWL_CMD(CONTROL_PSPOLL);
  2505. IWL_CMD(CONTROL_RTS);
  2506. IWL_CMD(CONTROL_CTS);
  2507. IWL_CMD(CONTROL_ACK);
  2508. IWL_CMD(CONTROL_CFEND);
  2509. IWL_CMD(CONTROL_CFENDACK);
  2510. default:
  2511. return "UNKNOWN";
  2512. }
  2513. }
  2514. void iwl_clear_tx_stats(struct iwl_priv *priv)
  2515. {
  2516. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  2517. }
  2518. void iwl_clear_rx_stats(struct iwl_priv *priv)
  2519. {
  2520. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  2521. }
  2522. /*
  2523. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  2524. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  2525. * Use debugFs to display the rx/rx_statistics
  2526. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  2527. * information will be recorded, but DATA pkt still will be recorded
  2528. * for the reason of iwl_led.c need to control the led blinking based on
  2529. * number of tx and rx data.
  2530. *
  2531. */
  2532. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  2533. {
  2534. struct traffic_stats *stats;
  2535. if (is_tx)
  2536. stats = &priv->tx_stats;
  2537. else
  2538. stats = &priv->rx_stats;
  2539. if (ieee80211_is_mgmt(fc)) {
  2540. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2541. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  2542. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  2543. break;
  2544. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  2545. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  2546. break;
  2547. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  2548. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  2549. break;
  2550. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  2551. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  2552. break;
  2553. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  2554. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  2555. break;
  2556. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  2557. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  2558. break;
  2559. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  2560. stats->mgmt[MANAGEMENT_BEACON]++;
  2561. break;
  2562. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  2563. stats->mgmt[MANAGEMENT_ATIM]++;
  2564. break;
  2565. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  2566. stats->mgmt[MANAGEMENT_DISASSOC]++;
  2567. break;
  2568. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  2569. stats->mgmt[MANAGEMENT_AUTH]++;
  2570. break;
  2571. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  2572. stats->mgmt[MANAGEMENT_DEAUTH]++;
  2573. break;
  2574. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  2575. stats->mgmt[MANAGEMENT_ACTION]++;
  2576. break;
  2577. }
  2578. } else if (ieee80211_is_ctl(fc)) {
  2579. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2580. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  2581. stats->ctrl[CONTROL_BACK_REQ]++;
  2582. break;
  2583. case cpu_to_le16(IEEE80211_STYPE_BACK):
  2584. stats->ctrl[CONTROL_BACK]++;
  2585. break;
  2586. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  2587. stats->ctrl[CONTROL_PSPOLL]++;
  2588. break;
  2589. case cpu_to_le16(IEEE80211_STYPE_RTS):
  2590. stats->ctrl[CONTROL_RTS]++;
  2591. break;
  2592. case cpu_to_le16(IEEE80211_STYPE_CTS):
  2593. stats->ctrl[CONTROL_CTS]++;
  2594. break;
  2595. case cpu_to_le16(IEEE80211_STYPE_ACK):
  2596. stats->ctrl[CONTROL_ACK]++;
  2597. break;
  2598. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  2599. stats->ctrl[CONTROL_CFEND]++;
  2600. break;
  2601. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  2602. stats->ctrl[CONTROL_CFENDACK]++;
  2603. break;
  2604. }
  2605. } else {
  2606. /* data */
  2607. stats->data_cnt++;
  2608. stats->data_bytes += len;
  2609. }
  2610. }
  2611. EXPORT_SYMBOL(iwl_update_stats);
  2612. #endif
  2613. #ifdef CONFIG_PM
  2614. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2615. {
  2616. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2617. /*
  2618. * This function is called when system goes into suspend state
  2619. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2620. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2621. * it will not call apm_ops.stop() to stop the DMA operation.
  2622. * Calling apm_ops.stop here to make sure we stop the DMA.
  2623. */
  2624. priv->cfg->ops->lib->apm_ops.stop(priv);
  2625. pci_save_state(pdev);
  2626. pci_disable_device(pdev);
  2627. pci_set_power_state(pdev, PCI_D3hot);
  2628. return 0;
  2629. }
  2630. EXPORT_SYMBOL(iwl_pci_suspend);
  2631. int iwl_pci_resume(struct pci_dev *pdev)
  2632. {
  2633. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2634. int ret;
  2635. pci_set_power_state(pdev, PCI_D0);
  2636. ret = pci_enable_device(pdev);
  2637. if (ret)
  2638. return ret;
  2639. pci_restore_state(pdev);
  2640. iwl_enable_interrupts(priv);
  2641. return 0;
  2642. }
  2643. EXPORT_SYMBOL(iwl_pci_resume);
  2644. #endif /* CONFIG_PM */