rt2x00queue.c 21 KB

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  1. /*
  2. Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
  3. <http://rt2x00.serialmonkey.com>
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the
  14. Free Software Foundation, Inc.,
  15. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. /*
  18. Module: rt2x00lib
  19. Abstract: rt2x00 queue specific routines.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/dma-mapping.h>
  24. #include "rt2x00.h"
  25. #include "rt2x00lib.h"
  26. struct sk_buff *rt2x00queue_alloc_rxskb(struct rt2x00_dev *rt2x00dev,
  27. struct queue_entry *entry)
  28. {
  29. struct sk_buff *skb;
  30. struct skb_frame_desc *skbdesc;
  31. unsigned int frame_size;
  32. unsigned int head_size = 0;
  33. unsigned int tail_size = 0;
  34. /*
  35. * The frame size includes descriptor size, because the
  36. * hardware directly receive the frame into the skbuffer.
  37. */
  38. frame_size = entry->queue->data_size + entry->queue->desc_size;
  39. /*
  40. * The payload should be aligned to a 4-byte boundary,
  41. * this means we need at least 3 bytes for moving the frame
  42. * into the correct offset.
  43. */
  44. head_size = 4;
  45. /*
  46. * For IV/EIV/ICV assembly we must make sure there is
  47. * at least 8 bytes bytes available in headroom for IV/EIV
  48. * and 4 bytes for ICV data as tailroon.
  49. */
  50. #ifdef CONFIG_RT2X00_LIB_CRYPTO
  51. if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
  52. head_size += 8;
  53. tail_size += 4;
  54. }
  55. #endif /* CONFIG_RT2X00_LIB_CRYPTO */
  56. /*
  57. * Allocate skbuffer.
  58. */
  59. skb = dev_alloc_skb(frame_size + head_size + tail_size);
  60. if (!skb)
  61. return NULL;
  62. /*
  63. * Make sure we not have a frame with the requested bytes
  64. * available in the head and tail.
  65. */
  66. skb_reserve(skb, head_size);
  67. skb_put(skb, frame_size);
  68. /*
  69. * Populate skbdesc.
  70. */
  71. skbdesc = get_skb_frame_desc(skb);
  72. memset(skbdesc, 0, sizeof(*skbdesc));
  73. skbdesc->entry = entry;
  74. if (test_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags)) {
  75. skbdesc->skb_dma = dma_map_single(rt2x00dev->dev,
  76. skb->data,
  77. skb->len,
  78. DMA_FROM_DEVICE);
  79. skbdesc->flags |= SKBDESC_DMA_MAPPED_RX;
  80. }
  81. return skb;
  82. }
  83. void rt2x00queue_map_txskb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  84. {
  85. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  86. /*
  87. * If device has requested headroom, we should make sure that
  88. * is also mapped to the DMA so it can be used for transfering
  89. * additional descriptor information to the hardware.
  90. */
  91. skb_push(skb, rt2x00dev->hw->extra_tx_headroom);
  92. skbdesc->skb_dma =
  93. dma_map_single(rt2x00dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
  94. /*
  95. * Restore data pointer to original location again.
  96. */
  97. skb_pull(skb, rt2x00dev->hw->extra_tx_headroom);
  98. skbdesc->flags |= SKBDESC_DMA_MAPPED_TX;
  99. }
  100. EXPORT_SYMBOL_GPL(rt2x00queue_map_txskb);
  101. void rt2x00queue_unmap_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  102. {
  103. struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
  104. if (skbdesc->flags & SKBDESC_DMA_MAPPED_RX) {
  105. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma, skb->len,
  106. DMA_FROM_DEVICE);
  107. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_RX;
  108. }
  109. if (skbdesc->flags & SKBDESC_DMA_MAPPED_TX) {
  110. /*
  111. * Add headroom to the skb length, it has been removed
  112. * by the driver, but it was actually mapped to DMA.
  113. */
  114. dma_unmap_single(rt2x00dev->dev, skbdesc->skb_dma,
  115. skb->len + rt2x00dev->hw->extra_tx_headroom,
  116. DMA_TO_DEVICE);
  117. skbdesc->flags &= ~SKBDESC_DMA_MAPPED_TX;
  118. }
  119. }
  120. void rt2x00queue_free_skb(struct rt2x00_dev *rt2x00dev, struct sk_buff *skb)
  121. {
  122. if (!skb)
  123. return;
  124. rt2x00queue_unmap_skb(rt2x00dev, skb);
  125. dev_kfree_skb_any(skb);
  126. }
  127. static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
  128. struct txentry_desc *txdesc)
  129. {
  130. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  131. struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
  132. struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
  133. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
  134. struct ieee80211_rate *rate =
  135. ieee80211_get_tx_rate(rt2x00dev->hw, tx_info);
  136. const struct rt2x00_rate *hwrate;
  137. unsigned int data_length;
  138. unsigned int duration;
  139. unsigned int residual;
  140. unsigned long irqflags;
  141. memset(txdesc, 0, sizeof(*txdesc));
  142. /*
  143. * Initialize information from queue
  144. */
  145. txdesc->queue = entry->queue->qid;
  146. txdesc->cw_min = entry->queue->cw_min;
  147. txdesc->cw_max = entry->queue->cw_max;
  148. txdesc->aifs = entry->queue->aifs;
  149. /* Data length + CRC + IV/EIV/ICV/MMIC (when using encryption) */
  150. data_length = entry->skb->len + 4;
  151. /*
  152. * Check whether this frame is to be acked.
  153. */
  154. if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK))
  155. __set_bit(ENTRY_TXD_ACK, &txdesc->flags);
  156. #ifdef CONFIG_RT2X00_LIB_CRYPTO
  157. if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags) &&
  158. !entry->skb->do_not_encrypt) {
  159. struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
  160. __set_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags);
  161. txdesc->cipher = rt2x00crypto_key_to_cipher(hw_key);
  162. if (hw_key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
  163. __set_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags);
  164. txdesc->key_idx = hw_key->hw_key_idx;
  165. txdesc->iv_offset = ieee80211_get_hdrlen_from_skb(entry->skb);
  166. /*
  167. * Extend frame length to include all encryption overhead
  168. * that will be added by the hardware.
  169. */
  170. data_length += rt2x00crypto_tx_overhead(tx_info);
  171. if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_IV))
  172. __set_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags);
  173. if (!(hw_key->flags & IEEE80211_KEY_FLAG_GENERATE_MMIC))
  174. __set_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags);
  175. }
  176. #endif /* CONFIG_RT2X00_LIB_CRYPTO */
  177. /*
  178. * Check if this is a RTS/CTS frame
  179. */
  180. if (ieee80211_is_rts(hdr->frame_control) ||
  181. ieee80211_is_cts(hdr->frame_control)) {
  182. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  183. if (ieee80211_is_rts(hdr->frame_control))
  184. __set_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags);
  185. else
  186. __set_bit(ENTRY_TXD_CTS_FRAME, &txdesc->flags);
  187. if (tx_info->control.rts_cts_rate_idx >= 0)
  188. rate =
  189. ieee80211_get_rts_cts_rate(rt2x00dev->hw, tx_info);
  190. }
  191. /*
  192. * Determine retry information.
  193. */
  194. txdesc->retry_limit = tx_info->control.retry_limit;
  195. if (tx_info->flags & IEEE80211_TX_CTL_LONG_RETRY_LIMIT)
  196. __set_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags);
  197. /*
  198. * Check if more fragments are pending
  199. */
  200. if (ieee80211_has_morefrags(hdr->frame_control)) {
  201. __set_bit(ENTRY_TXD_BURST, &txdesc->flags);
  202. __set_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags);
  203. }
  204. /*
  205. * Beacons and probe responses require the tsf timestamp
  206. * to be inserted into the frame.
  207. */
  208. if (ieee80211_is_beacon(hdr->frame_control) ||
  209. ieee80211_is_probe_resp(hdr->frame_control))
  210. __set_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags);
  211. /*
  212. * Determine with what IFS priority this frame should be send.
  213. * Set ifs to IFS_SIFS when the this is not the first fragment,
  214. * or this fragment came after RTS/CTS.
  215. */
  216. if (test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)) {
  217. txdesc->ifs = IFS_SIFS;
  218. } else if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) {
  219. __set_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags);
  220. txdesc->ifs = IFS_BACKOFF;
  221. } else {
  222. txdesc->ifs = IFS_SIFS;
  223. }
  224. /*
  225. * Hardware should insert sequence counter.
  226. * FIXME: We insert a software sequence counter first for
  227. * hardware that doesn't support hardware sequence counting.
  228. *
  229. * This is wrong because beacons are not getting sequence
  230. * numbers assigned properly.
  231. *
  232. * A secondary problem exists for drivers that cannot toggle
  233. * sequence counting per-frame, since those will override the
  234. * sequence counter given by mac80211.
  235. */
  236. if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  237. spin_lock_irqsave(&intf->seqlock, irqflags);
  238. if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags))
  239. intf->seqno += 0x10;
  240. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  241. hdr->seq_ctrl |= cpu_to_le16(intf->seqno);
  242. spin_unlock_irqrestore(&intf->seqlock, irqflags);
  243. __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags);
  244. }
  245. /*
  246. * PLCP setup
  247. * Length calculation depends on OFDM/CCK rate.
  248. */
  249. hwrate = rt2x00_get_rate(rate->hw_value);
  250. txdesc->signal = hwrate->plcp;
  251. txdesc->service = 0x04;
  252. if (hwrate->flags & DEV_RATE_OFDM) {
  253. __set_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags);
  254. txdesc->length_high = (data_length >> 6) & 0x3f;
  255. txdesc->length_low = data_length & 0x3f;
  256. } else {
  257. /*
  258. * Convert length to microseconds.
  259. */
  260. residual = get_duration_res(data_length, hwrate->bitrate);
  261. duration = get_duration(data_length, hwrate->bitrate);
  262. if (residual != 0) {
  263. duration++;
  264. /*
  265. * Check if we need to set the Length Extension
  266. */
  267. if (hwrate->bitrate == 110 && residual <= 30)
  268. txdesc->service |= 0x80;
  269. }
  270. txdesc->length_high = (duration >> 8) & 0xff;
  271. txdesc->length_low = duration & 0xff;
  272. /*
  273. * When preamble is enabled we should set the
  274. * preamble bit for the signal.
  275. */
  276. if (rt2x00_get_rate_preamble(rate->hw_value))
  277. txdesc->signal |= 0x08;
  278. }
  279. }
  280. static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
  281. struct txentry_desc *txdesc)
  282. {
  283. struct data_queue *queue = entry->queue;
  284. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  285. rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
  286. /*
  287. * All processing on the frame has been completed, this means
  288. * it is now ready to be dumped to userspace through debugfs.
  289. */
  290. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb);
  291. /*
  292. * Check if we need to kick the queue, there are however a few rules
  293. * 1) Don't kick beacon queue
  294. * 2) Don't kick unless this is the last in frame in a burst.
  295. * When the burst flag is set, this frame is always followed
  296. * by another frame which in some way are related to eachother.
  297. * This is true for fragments, RTS or CTS-to-self frames.
  298. * 3) Rule 2 can be broken when the available entries
  299. * in the queue are less then a certain threshold.
  300. */
  301. if (entry->queue->qid == QID_BEACON)
  302. return;
  303. if (rt2x00queue_threshold(queue) ||
  304. !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
  305. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
  306. }
  307. int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb)
  308. {
  309. struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
  310. struct txentry_desc txdesc;
  311. struct skb_frame_desc *skbdesc;
  312. unsigned int iv_len = IEEE80211_SKB_CB(skb)->control.iv_len;
  313. if (unlikely(rt2x00queue_full(queue)))
  314. return -EINVAL;
  315. if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags)) {
  316. ERROR(queue->rt2x00dev,
  317. "Arrived at non-free entry in the non-full queue %d.\n"
  318. "Please file bug report to %s.\n",
  319. queue->qid, DRV_PROJECT);
  320. return -EINVAL;
  321. }
  322. /*
  323. * Copy all TX descriptor information into txdesc,
  324. * after that we are free to use the skb->cb array
  325. * for our information.
  326. */
  327. entry->skb = skb;
  328. rt2x00queue_create_tx_descriptor(entry, &txdesc);
  329. /*
  330. * All information is retreived from the skb->cb array,
  331. * now we should claim ownership of the driver part of that
  332. * array.
  333. */
  334. skbdesc = get_skb_frame_desc(entry->skb);
  335. memset(skbdesc, 0, sizeof(*skbdesc));
  336. skbdesc->entry = entry;
  337. /*
  338. * When hardware encryption is supported, and this frame
  339. * is to be encrypted, we should strip the IV/EIV data from
  340. * the frame so we can provide it to the driver seperately.
  341. */
  342. if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc.flags) &&
  343. !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc.flags))
  344. rt2x00crypto_tx_remove_iv(skb, iv_len);
  345. /*
  346. * It could be possible that the queue was corrupted and this
  347. * call failed. Just drop the frame, we cannot rollback and pass
  348. * the frame to mac80211 because the skb->cb has now been tainted.
  349. */
  350. if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) {
  351. clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
  352. dev_kfree_skb_any(entry->skb);
  353. entry->skb = NULL;
  354. return 0;
  355. }
  356. if (test_bit(DRIVER_REQUIRE_DMA, &queue->rt2x00dev->flags))
  357. rt2x00queue_map_txskb(queue->rt2x00dev, skb);
  358. set_bit(ENTRY_DATA_PENDING, &entry->flags);
  359. rt2x00queue_index_inc(queue, Q_INDEX);
  360. rt2x00queue_write_tx_descriptor(entry, &txdesc);
  361. return 0;
  362. }
  363. int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
  364. struct ieee80211_vif *vif)
  365. {
  366. struct rt2x00_intf *intf = vif_to_intf(vif);
  367. struct skb_frame_desc *skbdesc;
  368. struct txentry_desc txdesc;
  369. __le32 desc[16];
  370. if (unlikely(!intf->beacon))
  371. return -ENOBUFS;
  372. intf->beacon->skb = ieee80211_beacon_get(rt2x00dev->hw, vif);
  373. if (!intf->beacon->skb)
  374. return -ENOMEM;
  375. /*
  376. * Copy all TX descriptor information into txdesc,
  377. * after that we are free to use the skb->cb array
  378. * for our information.
  379. */
  380. rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
  381. /*
  382. * For the descriptor we use a local array from where the
  383. * driver can move it to the correct location required for
  384. * the hardware.
  385. */
  386. memset(desc, 0, sizeof(desc));
  387. /*
  388. * Fill in skb descriptor
  389. */
  390. skbdesc = get_skb_frame_desc(intf->beacon->skb);
  391. memset(skbdesc, 0, sizeof(*skbdesc));
  392. skbdesc->desc = desc;
  393. skbdesc->desc_len = intf->beacon->queue->desc_size;
  394. skbdesc->entry = intf->beacon;
  395. /*
  396. * Write TX descriptor into reserved room in front of the beacon.
  397. */
  398. rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
  399. /*
  400. * Send beacon to hardware.
  401. * Also enable beacon generation, which might have been disabled
  402. * by the driver during the config_beacon() callback function.
  403. */
  404. rt2x00dev->ops->lib->write_beacon(intf->beacon);
  405. rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
  406. return 0;
  407. }
  408. struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
  409. const enum data_queue_qid queue)
  410. {
  411. int atim = test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  412. if (queue < rt2x00dev->ops->tx_queues && rt2x00dev->tx)
  413. return &rt2x00dev->tx[queue];
  414. if (!rt2x00dev->bcn)
  415. return NULL;
  416. if (queue == QID_BEACON)
  417. return &rt2x00dev->bcn[0];
  418. else if (queue == QID_ATIM && atim)
  419. return &rt2x00dev->bcn[1];
  420. return NULL;
  421. }
  422. EXPORT_SYMBOL_GPL(rt2x00queue_get_queue);
  423. struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
  424. enum queue_index index)
  425. {
  426. struct queue_entry *entry;
  427. unsigned long irqflags;
  428. if (unlikely(index >= Q_INDEX_MAX)) {
  429. ERROR(queue->rt2x00dev,
  430. "Entry requested from invalid index type (%d)\n", index);
  431. return NULL;
  432. }
  433. spin_lock_irqsave(&queue->lock, irqflags);
  434. entry = &queue->entries[queue->index[index]];
  435. spin_unlock_irqrestore(&queue->lock, irqflags);
  436. return entry;
  437. }
  438. EXPORT_SYMBOL_GPL(rt2x00queue_get_entry);
  439. void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
  440. {
  441. unsigned long irqflags;
  442. if (unlikely(index >= Q_INDEX_MAX)) {
  443. ERROR(queue->rt2x00dev,
  444. "Index change on invalid index type (%d)\n", index);
  445. return;
  446. }
  447. spin_lock_irqsave(&queue->lock, irqflags);
  448. queue->index[index]++;
  449. if (queue->index[index] >= queue->limit)
  450. queue->index[index] = 0;
  451. if (index == Q_INDEX) {
  452. queue->length++;
  453. } else if (index == Q_INDEX_DONE) {
  454. queue->length--;
  455. queue->count ++;
  456. }
  457. spin_unlock_irqrestore(&queue->lock, irqflags);
  458. }
  459. static void rt2x00queue_reset(struct data_queue *queue)
  460. {
  461. unsigned long irqflags;
  462. spin_lock_irqsave(&queue->lock, irqflags);
  463. queue->count = 0;
  464. queue->length = 0;
  465. memset(queue->index, 0, sizeof(queue->index));
  466. spin_unlock_irqrestore(&queue->lock, irqflags);
  467. }
  468. void rt2x00queue_init_rx(struct rt2x00_dev *rt2x00dev)
  469. {
  470. struct data_queue *queue = rt2x00dev->rx;
  471. unsigned int i;
  472. rt2x00queue_reset(queue);
  473. if (!rt2x00dev->ops->lib->init_rxentry)
  474. return;
  475. for (i = 0; i < queue->limit; i++) {
  476. queue->entries[i].flags = 0;
  477. rt2x00dev->ops->lib->init_rxentry(rt2x00dev,
  478. &queue->entries[i]);
  479. }
  480. }
  481. void rt2x00queue_init_tx(struct rt2x00_dev *rt2x00dev)
  482. {
  483. struct data_queue *queue;
  484. unsigned int i;
  485. txall_queue_for_each(rt2x00dev, queue) {
  486. rt2x00queue_reset(queue);
  487. if (!rt2x00dev->ops->lib->init_txentry)
  488. continue;
  489. for (i = 0; i < queue->limit; i++) {
  490. queue->entries[i].flags = 0;
  491. rt2x00dev->ops->lib->init_txentry(rt2x00dev,
  492. &queue->entries[i]);
  493. }
  494. }
  495. }
  496. static int rt2x00queue_alloc_entries(struct data_queue *queue,
  497. const struct data_queue_desc *qdesc)
  498. {
  499. struct queue_entry *entries;
  500. unsigned int entry_size;
  501. unsigned int i;
  502. rt2x00queue_reset(queue);
  503. queue->limit = qdesc->entry_num;
  504. queue->threshold = DIV_ROUND_UP(qdesc->entry_num, 10);
  505. queue->data_size = qdesc->data_size;
  506. queue->desc_size = qdesc->desc_size;
  507. /*
  508. * Allocate all queue entries.
  509. */
  510. entry_size = sizeof(*entries) + qdesc->priv_size;
  511. entries = kzalloc(queue->limit * entry_size, GFP_KERNEL);
  512. if (!entries)
  513. return -ENOMEM;
  514. #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
  515. ( ((char *)(__base)) + ((__limit) * (__esize)) + \
  516. ((__index) * (__psize)) )
  517. for (i = 0; i < queue->limit; i++) {
  518. entries[i].flags = 0;
  519. entries[i].queue = queue;
  520. entries[i].skb = NULL;
  521. entries[i].entry_idx = i;
  522. entries[i].priv_data =
  523. QUEUE_ENTRY_PRIV_OFFSET(entries, i, queue->limit,
  524. sizeof(*entries), qdesc->priv_size);
  525. }
  526. #undef QUEUE_ENTRY_PRIV_OFFSET
  527. queue->entries = entries;
  528. return 0;
  529. }
  530. static void rt2x00queue_free_skbs(struct rt2x00_dev *rt2x00dev,
  531. struct data_queue *queue)
  532. {
  533. unsigned int i;
  534. if (!queue->entries)
  535. return;
  536. for (i = 0; i < queue->limit; i++) {
  537. if (queue->entries[i].skb)
  538. rt2x00queue_free_skb(rt2x00dev, queue->entries[i].skb);
  539. }
  540. }
  541. static int rt2x00queue_alloc_rxskbs(struct rt2x00_dev *rt2x00dev,
  542. struct data_queue *queue)
  543. {
  544. unsigned int i;
  545. struct sk_buff *skb;
  546. for (i = 0; i < queue->limit; i++) {
  547. skb = rt2x00queue_alloc_rxskb(rt2x00dev, &queue->entries[i]);
  548. if (!skb)
  549. return -ENOMEM;
  550. queue->entries[i].skb = skb;
  551. }
  552. return 0;
  553. }
  554. int rt2x00queue_initialize(struct rt2x00_dev *rt2x00dev)
  555. {
  556. struct data_queue *queue;
  557. int status;
  558. status = rt2x00queue_alloc_entries(rt2x00dev->rx, rt2x00dev->ops->rx);
  559. if (status)
  560. goto exit;
  561. tx_queue_for_each(rt2x00dev, queue) {
  562. status = rt2x00queue_alloc_entries(queue, rt2x00dev->ops->tx);
  563. if (status)
  564. goto exit;
  565. }
  566. status = rt2x00queue_alloc_entries(rt2x00dev->bcn, rt2x00dev->ops->bcn);
  567. if (status)
  568. goto exit;
  569. if (test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags)) {
  570. status = rt2x00queue_alloc_entries(&rt2x00dev->bcn[1],
  571. rt2x00dev->ops->atim);
  572. if (status)
  573. goto exit;
  574. }
  575. status = rt2x00queue_alloc_rxskbs(rt2x00dev, rt2x00dev->rx);
  576. if (status)
  577. goto exit;
  578. return 0;
  579. exit:
  580. ERROR(rt2x00dev, "Queue entries allocation failed.\n");
  581. rt2x00queue_uninitialize(rt2x00dev);
  582. return status;
  583. }
  584. void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
  585. {
  586. struct data_queue *queue;
  587. rt2x00queue_free_skbs(rt2x00dev, rt2x00dev->rx);
  588. queue_for_each(rt2x00dev, queue) {
  589. kfree(queue->entries);
  590. queue->entries = NULL;
  591. }
  592. }
  593. static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
  594. struct data_queue *queue, enum data_queue_qid qid)
  595. {
  596. spin_lock_init(&queue->lock);
  597. queue->rt2x00dev = rt2x00dev;
  598. queue->qid = qid;
  599. queue->aifs = 2;
  600. queue->cw_min = 5;
  601. queue->cw_max = 10;
  602. }
  603. int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
  604. {
  605. struct data_queue *queue;
  606. enum data_queue_qid qid;
  607. unsigned int req_atim =
  608. !!test_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
  609. /*
  610. * We need the following queues:
  611. * RX: 1
  612. * TX: ops->tx_queues
  613. * Beacon: 1
  614. * Atim: 1 (if required)
  615. */
  616. rt2x00dev->data_queues = 2 + rt2x00dev->ops->tx_queues + req_atim;
  617. queue = kzalloc(rt2x00dev->data_queues * sizeof(*queue), GFP_KERNEL);
  618. if (!queue) {
  619. ERROR(rt2x00dev, "Queue allocation failed.\n");
  620. return -ENOMEM;
  621. }
  622. /*
  623. * Initialize pointers
  624. */
  625. rt2x00dev->rx = queue;
  626. rt2x00dev->tx = &queue[1];
  627. rt2x00dev->bcn = &queue[1 + rt2x00dev->ops->tx_queues];
  628. /*
  629. * Initialize queue parameters.
  630. * RX: qid = QID_RX
  631. * TX: qid = QID_AC_BE + index
  632. * TX: cw_min: 2^5 = 32.
  633. * TX: cw_max: 2^10 = 1024.
  634. * BCN: qid = QID_BEACON
  635. * ATIM: qid = QID_ATIM
  636. */
  637. rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
  638. qid = QID_AC_BE;
  639. tx_queue_for_each(rt2x00dev, queue)
  640. rt2x00queue_init(rt2x00dev, queue, qid++);
  641. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[0], QID_BEACON);
  642. if (req_atim)
  643. rt2x00queue_init(rt2x00dev, &rt2x00dev->bcn[1], QID_ATIM);
  644. return 0;
  645. }
  646. void rt2x00queue_free(struct rt2x00_dev *rt2x00dev)
  647. {
  648. kfree(rt2x00dev->rx);
  649. rt2x00dev->rx = NULL;
  650. rt2x00dev->tx = NULL;
  651. rt2x00dev->bcn = NULL;
  652. }