kirkwood.dtsi 4.2 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,kirkwood";
  5. interrupt-parent = <&intc>;
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "marvell,feroceon";
  12. clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  13. clock-names = "cpu_clk", "ddrclk", "powersave";
  14. };
  15. };
  16. aliases {
  17. gpio0 = &gpio0;
  18. gpio1 = &gpio1;
  19. };
  20. intc: interrupt-controller {
  21. compatible = "marvell,orion-intc", "marvell,intc";
  22. interrupt-controller;
  23. #interrupt-cells = <1>;
  24. reg = <0xf1020204 0x04>,
  25. <0xf1020214 0x04>;
  26. };
  27. mbus {
  28. compatible = "marvell,kirkwood-mbus", "simple-bus";
  29. controller = <&mbusc>;
  30. };
  31. ocp@f1000000 {
  32. compatible = "simple-bus";
  33. ranges = <0x00000000 0xf1000000 0x0100000
  34. 0xe0000000 0xe0000000 0x8100000 /* PCIE */
  35. 0xf4000000 0xf4000000 0x0000400
  36. 0xf5000000 0xf5000000 0x0000400>;
  37. #address-cells = <1>;
  38. #size-cells = <1>;
  39. mbusc: mbus-controller@20000 {
  40. compatible = "marvell,mbus-controller";
  41. reg = <0x20000 0x80>, <0x1500 0x20>;
  42. };
  43. core_clk: core-clocks@10030 {
  44. compatible = "marvell,kirkwood-core-clock";
  45. reg = <0x10030 0x4>;
  46. #clock-cells = <1>;
  47. };
  48. gpio0: gpio@10100 {
  49. compatible = "marvell,orion-gpio";
  50. #gpio-cells = <2>;
  51. gpio-controller;
  52. reg = <0x10100 0x40>;
  53. ngpios = <32>;
  54. interrupt-controller;
  55. #interrupt-cells = <2>;
  56. interrupts = <35>, <36>, <37>, <38>;
  57. clocks = <&gate_clk 7>;
  58. };
  59. gpio1: gpio@10140 {
  60. compatible = "marvell,orion-gpio";
  61. #gpio-cells = <2>;
  62. gpio-controller;
  63. reg = <0x10140 0x40>;
  64. ngpios = <18>;
  65. interrupt-controller;
  66. #interrupt-cells = <2>;
  67. interrupts = <39>, <40>, <41>;
  68. clocks = <&gate_clk 7>;
  69. };
  70. serial@12000 {
  71. compatible = "ns16550a";
  72. reg = <0x12000 0x100>;
  73. reg-shift = <2>;
  74. interrupts = <33>;
  75. clocks = <&gate_clk 7>;
  76. status = "disabled";
  77. };
  78. serial@12100 {
  79. compatible = "ns16550a";
  80. reg = <0x12100 0x100>;
  81. reg-shift = <2>;
  82. interrupts = <34>;
  83. clocks = <&gate_clk 7>;
  84. status = "disabled";
  85. };
  86. spi@10600 {
  87. compatible = "marvell,orion-spi";
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. cell-index = <0>;
  91. interrupts = <23>;
  92. reg = <0x10600 0x28>;
  93. clocks = <&gate_clk 7>;
  94. status = "disabled";
  95. };
  96. gate_clk: clock-gating-control@2011c {
  97. compatible = "marvell,kirkwood-gating-clock";
  98. reg = <0x2011c 0x4>;
  99. clocks = <&core_clk 0>;
  100. #clock-cells = <1>;
  101. };
  102. wdt@20300 {
  103. compatible = "marvell,orion-wdt";
  104. reg = <0x20300 0x28>;
  105. clocks = <&gate_clk 7>;
  106. status = "okay";
  107. };
  108. xor@60800 {
  109. compatible = "marvell,orion-xor";
  110. reg = <0x60800 0x100
  111. 0x60A00 0x100>;
  112. status = "okay";
  113. clocks = <&gate_clk 8>;
  114. xor00 {
  115. interrupts = <5>;
  116. dmacap,memcpy;
  117. dmacap,xor;
  118. };
  119. xor01 {
  120. interrupts = <6>;
  121. dmacap,memcpy;
  122. dmacap,xor;
  123. dmacap,memset;
  124. };
  125. };
  126. xor@60900 {
  127. compatible = "marvell,orion-xor";
  128. reg = <0x60900 0x100
  129. 0xd0B00 0x100>;
  130. status = "okay";
  131. clocks = <&gate_clk 16>;
  132. xor00 {
  133. interrupts = <7>;
  134. dmacap,memcpy;
  135. dmacap,xor;
  136. };
  137. xor01 {
  138. interrupts = <8>;
  139. dmacap,memcpy;
  140. dmacap,xor;
  141. dmacap,memset;
  142. };
  143. };
  144. ehci@50000 {
  145. compatible = "marvell,orion-ehci";
  146. reg = <0x50000 0x1000>;
  147. interrupts = <19>;
  148. clocks = <&gate_clk 3>;
  149. status = "okay";
  150. };
  151. nand@3000000 {
  152. #address-cells = <1>;
  153. #size-cells = <1>;
  154. cle = <0>;
  155. ale = <1>;
  156. bank-width = <1>;
  157. compatible = "marvell,orion-nand";
  158. reg = <0xf4000000 0x400>;
  159. chip-delay = <25>;
  160. /* set partition map and/or chip-delay in board dts */
  161. clocks = <&gate_clk 7>;
  162. status = "disabled";
  163. };
  164. i2c@11000 {
  165. compatible = "marvell,mv64xxx-i2c";
  166. reg = <0x11000 0x20>;
  167. #address-cells = <1>;
  168. #size-cells = <0>;
  169. interrupts = <29>;
  170. clock-frequency = <100000>;
  171. clocks = <&gate_clk 7>;
  172. status = "disabled";
  173. };
  174. crypto@30000 {
  175. compatible = "marvell,orion-crypto";
  176. reg = <0x30000 0x10000>,
  177. <0xf5000000 0x800>;
  178. reg-names = "regs", "sram";
  179. interrupts = <22>;
  180. clocks = <&gate_clk 17>;
  181. status = "okay";
  182. };
  183. };
  184. };