amd_iommu_init.c 29 KB

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  1. /*
  2. * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
  3. * Author: Joerg Roedel <joerg.roedel@amd.com>
  4. * Leo Duran <leo.duran@amd.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/pci.h>
  20. #include <linux/acpi.h>
  21. #include <linux/gfp.h>
  22. #include <linux/list.h>
  23. #include <linux/sysdev.h>
  24. #include <asm/pci-direct.h>
  25. #include <asm/amd_iommu_types.h>
  26. #include <asm/amd_iommu.h>
  27. #include <asm/iommu.h>
  28. /*
  29. * definitions for the ACPI scanning code
  30. */
  31. #define PCI_BUS(x) (((x) >> 8) & 0xff)
  32. #define IVRS_HEADER_LENGTH 48
  33. #define ACPI_IVHD_TYPE 0x10
  34. #define ACPI_IVMD_TYPE_ALL 0x20
  35. #define ACPI_IVMD_TYPE 0x21
  36. #define ACPI_IVMD_TYPE_RANGE 0x22
  37. #define IVHD_DEV_ALL 0x01
  38. #define IVHD_DEV_SELECT 0x02
  39. #define IVHD_DEV_SELECT_RANGE_START 0x03
  40. #define IVHD_DEV_RANGE_END 0x04
  41. #define IVHD_DEV_ALIAS 0x42
  42. #define IVHD_DEV_ALIAS_RANGE 0x43
  43. #define IVHD_DEV_EXT_SELECT 0x46
  44. #define IVHD_DEV_EXT_SELECT_RANGE 0x47
  45. #define IVHD_FLAG_HT_TUN_EN 0x00
  46. #define IVHD_FLAG_PASSPW_EN 0x01
  47. #define IVHD_FLAG_RESPASSPW_EN 0x02
  48. #define IVHD_FLAG_ISOC_EN 0x03
  49. #define IVMD_FLAG_EXCL_RANGE 0x08
  50. #define IVMD_FLAG_UNITY_MAP 0x01
  51. #define ACPI_DEVFLAG_INITPASS 0x01
  52. #define ACPI_DEVFLAG_EXTINT 0x02
  53. #define ACPI_DEVFLAG_NMI 0x04
  54. #define ACPI_DEVFLAG_SYSMGT1 0x10
  55. #define ACPI_DEVFLAG_SYSMGT2 0x20
  56. #define ACPI_DEVFLAG_LINT0 0x40
  57. #define ACPI_DEVFLAG_LINT1 0x80
  58. #define ACPI_DEVFLAG_ATSDIS 0x10000000
  59. /*
  60. * ACPI table definitions
  61. *
  62. * These data structures are laid over the table to parse the important values
  63. * out of it.
  64. */
  65. /*
  66. * structure describing one IOMMU in the ACPI table. Typically followed by one
  67. * or more ivhd_entrys.
  68. */
  69. struct ivhd_header {
  70. u8 type;
  71. u8 flags;
  72. u16 length;
  73. u16 devid;
  74. u16 cap_ptr;
  75. u64 mmio_phys;
  76. u16 pci_seg;
  77. u16 info;
  78. u32 reserved;
  79. } __attribute__((packed));
  80. /*
  81. * A device entry describing which devices a specific IOMMU translates and
  82. * which requestor ids they use.
  83. */
  84. struct ivhd_entry {
  85. u8 type;
  86. u16 devid;
  87. u8 flags;
  88. u32 ext;
  89. } __attribute__((packed));
  90. /*
  91. * An AMD IOMMU memory definition structure. It defines things like exclusion
  92. * ranges for devices and regions that should be unity mapped.
  93. */
  94. struct ivmd_header {
  95. u8 type;
  96. u8 flags;
  97. u16 length;
  98. u16 devid;
  99. u16 aux;
  100. u64 resv;
  101. u64 range_start;
  102. u64 range_length;
  103. } __attribute__((packed));
  104. static int __initdata amd_iommu_detected;
  105. u16 amd_iommu_last_bdf; /* largest PCI device id we have
  106. to handle */
  107. LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
  108. we find in ACPI */
  109. unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
  110. int amd_iommu_isolate; /* if 1, device isolation is enabled */
  111. LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
  112. system */
  113. /*
  114. * Pointer to the device table which is shared by all AMD IOMMUs
  115. * it is indexed by the PCI device id or the HT unit id and contains
  116. * information about the domain the device belongs to as well as the
  117. * page table root pointer.
  118. */
  119. struct dev_table_entry *amd_iommu_dev_table;
  120. /*
  121. * The alias table is a driver specific data structure which contains the
  122. * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
  123. * More than one device can share the same requestor id.
  124. */
  125. u16 *amd_iommu_alias_table;
  126. /*
  127. * The rlookup table is used to find the IOMMU which is responsible
  128. * for a specific device. It is also indexed by the PCI device id.
  129. */
  130. struct amd_iommu **amd_iommu_rlookup_table;
  131. /*
  132. * The pd table (protection domain table) is used to find the protection domain
  133. * data structure a device belongs to. Indexed with the PCI device id too.
  134. */
  135. struct protection_domain **amd_iommu_pd_table;
  136. /*
  137. * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
  138. * to know which ones are already in use.
  139. */
  140. unsigned long *amd_iommu_pd_alloc_bitmap;
  141. static u32 dev_table_size; /* size of the device table */
  142. static u32 alias_table_size; /* size of the alias table */
  143. static u32 rlookup_table_size; /* size if the rlookup table */
  144. static inline void update_last_devid(u16 devid)
  145. {
  146. if (devid > amd_iommu_last_bdf)
  147. amd_iommu_last_bdf = devid;
  148. }
  149. static inline unsigned long tbl_size(int entry_size)
  150. {
  151. unsigned shift = PAGE_SHIFT +
  152. get_order(amd_iommu_last_bdf * entry_size);
  153. return 1UL << shift;
  154. }
  155. /****************************************************************************
  156. *
  157. * AMD IOMMU MMIO register space handling functions
  158. *
  159. * These functions are used to program the IOMMU device registers in
  160. * MMIO space required for that driver.
  161. *
  162. ****************************************************************************/
  163. /*
  164. * This function set the exclusion range in the IOMMU. DMA accesses to the
  165. * exclusion range are passed through untranslated
  166. */
  167. static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
  168. {
  169. u64 start = iommu->exclusion_start & PAGE_MASK;
  170. u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
  171. u64 entry;
  172. if (!iommu->exclusion_start)
  173. return;
  174. entry = start | MMIO_EXCL_ENABLE_MASK;
  175. memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
  176. &entry, sizeof(entry));
  177. entry = limit;
  178. memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
  179. &entry, sizeof(entry));
  180. }
  181. /* Programs the physical address of the device table into the IOMMU hardware */
  182. static void __init iommu_set_device_table(struct amd_iommu *iommu)
  183. {
  184. u32 entry;
  185. BUG_ON(iommu->mmio_base == NULL);
  186. entry = virt_to_phys(amd_iommu_dev_table);
  187. entry |= (dev_table_size >> 12) - 1;
  188. memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
  189. &entry, sizeof(entry));
  190. }
  191. /* Generic functions to enable/disable certain features of the IOMMU. */
  192. static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
  193. {
  194. u32 ctrl;
  195. ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
  196. ctrl |= (1 << bit);
  197. writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
  198. }
  199. static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
  200. {
  201. u32 ctrl;
  202. ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
  203. ctrl &= ~(1 << bit);
  204. writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
  205. }
  206. /* Function to enable the hardware */
  207. void __init iommu_enable(struct amd_iommu *iommu)
  208. {
  209. printk(KERN_INFO "AMD IOMMU: Enabling IOMMU "
  210. "at %02x:%02x.%x cap 0x%hx\n",
  211. iommu->dev->bus->number,
  212. PCI_SLOT(iommu->dev->devfn),
  213. PCI_FUNC(iommu->dev->devfn),
  214. iommu->cap_ptr);
  215. iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
  216. }
  217. /*
  218. * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
  219. * the system has one.
  220. */
  221. static u8 * __init iommu_map_mmio_space(u64 address)
  222. {
  223. u8 *ret;
  224. if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
  225. return NULL;
  226. ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
  227. if (ret != NULL)
  228. return ret;
  229. release_mem_region(address, MMIO_REGION_LENGTH);
  230. return NULL;
  231. }
  232. static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
  233. {
  234. if (iommu->mmio_base)
  235. iounmap(iommu->mmio_base);
  236. release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
  237. }
  238. /****************************************************************************
  239. *
  240. * The functions below belong to the first pass of AMD IOMMU ACPI table
  241. * parsing. In this pass we try to find out the highest device id this
  242. * code has to handle. Upon this information the size of the shared data
  243. * structures is determined later.
  244. *
  245. ****************************************************************************/
  246. /*
  247. * This function reads the last device id the IOMMU has to handle from the PCI
  248. * capability header for this IOMMU
  249. */
  250. static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
  251. {
  252. u32 cap;
  253. cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
  254. update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
  255. return 0;
  256. }
  257. /*
  258. * After reading the highest device id from the IOMMU PCI capability header
  259. * this function looks if there is a higher device id defined in the ACPI table
  260. */
  261. static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
  262. {
  263. u8 *p = (void *)h, *end = (void *)h;
  264. struct ivhd_entry *dev;
  265. p += sizeof(*h);
  266. end += h->length;
  267. find_last_devid_on_pci(PCI_BUS(h->devid),
  268. PCI_SLOT(h->devid),
  269. PCI_FUNC(h->devid),
  270. h->cap_ptr);
  271. while (p < end) {
  272. dev = (struct ivhd_entry *)p;
  273. switch (dev->type) {
  274. case IVHD_DEV_SELECT:
  275. case IVHD_DEV_RANGE_END:
  276. case IVHD_DEV_ALIAS:
  277. case IVHD_DEV_EXT_SELECT:
  278. /* all the above subfield types refer to device ids */
  279. update_last_devid(dev->devid);
  280. break;
  281. default:
  282. break;
  283. }
  284. p += 0x04 << (*p >> 6);
  285. }
  286. WARN_ON(p != end);
  287. return 0;
  288. }
  289. /*
  290. * Iterate over all IVHD entries in the ACPI table and find the highest device
  291. * id which we need to handle. This is the first of three functions which parse
  292. * the ACPI table. So we check the checksum here.
  293. */
  294. static int __init find_last_devid_acpi(struct acpi_table_header *table)
  295. {
  296. int i;
  297. u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
  298. struct ivhd_header *h;
  299. /*
  300. * Validate checksum here so we don't need to do it when
  301. * we actually parse the table
  302. */
  303. for (i = 0; i < table->length; ++i)
  304. checksum += p[i];
  305. if (checksum != 0)
  306. /* ACPI table corrupt */
  307. return -ENODEV;
  308. p += IVRS_HEADER_LENGTH;
  309. end += table->length;
  310. while (p < end) {
  311. h = (struct ivhd_header *)p;
  312. switch (h->type) {
  313. case ACPI_IVHD_TYPE:
  314. find_last_devid_from_ivhd(h);
  315. break;
  316. default:
  317. break;
  318. }
  319. p += h->length;
  320. }
  321. WARN_ON(p != end);
  322. return 0;
  323. }
  324. /****************************************************************************
  325. *
  326. * The following functions belong the the code path which parses the ACPI table
  327. * the second time. In this ACPI parsing iteration we allocate IOMMU specific
  328. * data structures, initialize the device/alias/rlookup table and also
  329. * basically initialize the hardware.
  330. *
  331. ****************************************************************************/
  332. /*
  333. * Allocates the command buffer. This buffer is per AMD IOMMU. We can
  334. * write commands to that buffer later and the IOMMU will execute them
  335. * asynchronously
  336. */
  337. static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
  338. {
  339. u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
  340. get_order(CMD_BUFFER_SIZE));
  341. u64 entry;
  342. if (cmd_buf == NULL)
  343. return NULL;
  344. iommu->cmd_buf_size = CMD_BUFFER_SIZE;
  345. entry = (u64)virt_to_phys(cmd_buf);
  346. entry |= MMIO_CMD_SIZE_512;
  347. memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
  348. &entry, sizeof(entry));
  349. iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
  350. return cmd_buf;
  351. }
  352. static void __init free_command_buffer(struct amd_iommu *iommu)
  353. {
  354. free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
  355. }
  356. /* allocates the memory where the IOMMU will log its events to */
  357. static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
  358. {
  359. u64 entry;
  360. iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
  361. get_order(EVT_BUFFER_SIZE));
  362. if (iommu->evt_buf == NULL)
  363. return NULL;
  364. entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
  365. memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
  366. &entry, sizeof(entry));
  367. iommu->evt_buf_size = EVT_BUFFER_SIZE;
  368. return iommu->evt_buf;
  369. }
  370. static void __init free_event_buffer(struct amd_iommu *iommu)
  371. {
  372. free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
  373. }
  374. /* sets a specific bit in the device table entry. */
  375. static void set_dev_entry_bit(u16 devid, u8 bit)
  376. {
  377. int i = (bit >> 5) & 0x07;
  378. int _bit = bit & 0x1f;
  379. amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
  380. }
  381. /* Writes the specific IOMMU for a device into the rlookup table */
  382. static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
  383. {
  384. amd_iommu_rlookup_table[devid] = iommu;
  385. }
  386. /*
  387. * This function takes the device specific flags read from the ACPI
  388. * table and sets up the device table entry with that information
  389. */
  390. static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
  391. u16 devid, u32 flags, u32 ext_flags)
  392. {
  393. if (flags & ACPI_DEVFLAG_INITPASS)
  394. set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
  395. if (flags & ACPI_DEVFLAG_EXTINT)
  396. set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
  397. if (flags & ACPI_DEVFLAG_NMI)
  398. set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
  399. if (flags & ACPI_DEVFLAG_SYSMGT1)
  400. set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
  401. if (flags & ACPI_DEVFLAG_SYSMGT2)
  402. set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
  403. if (flags & ACPI_DEVFLAG_LINT0)
  404. set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
  405. if (flags & ACPI_DEVFLAG_LINT1)
  406. set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
  407. set_iommu_for_device(iommu, devid);
  408. }
  409. /*
  410. * Reads the device exclusion range from ACPI and initialize IOMMU with
  411. * it
  412. */
  413. static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
  414. {
  415. struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
  416. if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
  417. return;
  418. if (iommu) {
  419. /*
  420. * We only can configure exclusion ranges per IOMMU, not
  421. * per device. But we can enable the exclusion range per
  422. * device. This is done here
  423. */
  424. set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
  425. iommu->exclusion_start = m->range_start;
  426. iommu->exclusion_length = m->range_length;
  427. }
  428. }
  429. /*
  430. * This function reads some important data from the IOMMU PCI space and
  431. * initializes the driver data structure with it. It reads the hardware
  432. * capabilities and the first/last device entries
  433. */
  434. static void __init init_iommu_from_pci(struct amd_iommu *iommu)
  435. {
  436. int cap_ptr = iommu->cap_ptr;
  437. u32 range;
  438. pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
  439. &iommu->cap);
  440. pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
  441. &range);
  442. iommu->first_device = calc_devid(MMIO_GET_BUS(range),
  443. MMIO_GET_FD(range));
  444. iommu->last_device = calc_devid(MMIO_GET_BUS(range),
  445. MMIO_GET_LD(range));
  446. }
  447. /*
  448. * Takes a pointer to an AMD IOMMU entry in the ACPI table and
  449. * initializes the hardware and our data structures with it.
  450. */
  451. static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
  452. struct ivhd_header *h)
  453. {
  454. u8 *p = (u8 *)h;
  455. u8 *end = p, flags = 0;
  456. u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
  457. u32 ext_flags = 0;
  458. bool alias = false;
  459. struct ivhd_entry *e;
  460. /*
  461. * First set the recommended feature enable bits from ACPI
  462. * into the IOMMU control registers
  463. */
  464. h->flags & IVHD_FLAG_HT_TUN_EN ?
  465. iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
  466. iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
  467. h->flags & IVHD_FLAG_PASSPW_EN ?
  468. iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
  469. iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
  470. h->flags & IVHD_FLAG_RESPASSPW_EN ?
  471. iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
  472. iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
  473. h->flags & IVHD_FLAG_ISOC_EN ?
  474. iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
  475. iommu_feature_disable(iommu, CONTROL_ISOC_EN);
  476. /*
  477. * make IOMMU memory accesses cache coherent
  478. */
  479. iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
  480. /*
  481. * Done. Now parse the device entries
  482. */
  483. p += sizeof(struct ivhd_header);
  484. end += h->length;
  485. while (p < end) {
  486. e = (struct ivhd_entry *)p;
  487. switch (e->type) {
  488. case IVHD_DEV_ALL:
  489. for (dev_i = iommu->first_device;
  490. dev_i <= iommu->last_device; ++dev_i)
  491. set_dev_entry_from_acpi(iommu, dev_i,
  492. e->flags, 0);
  493. break;
  494. case IVHD_DEV_SELECT:
  495. devid = e->devid;
  496. set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
  497. break;
  498. case IVHD_DEV_SELECT_RANGE_START:
  499. devid_start = e->devid;
  500. flags = e->flags;
  501. ext_flags = 0;
  502. alias = false;
  503. break;
  504. case IVHD_DEV_ALIAS:
  505. devid = e->devid;
  506. devid_to = e->ext >> 8;
  507. set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
  508. amd_iommu_alias_table[devid] = devid_to;
  509. break;
  510. case IVHD_DEV_ALIAS_RANGE:
  511. devid_start = e->devid;
  512. flags = e->flags;
  513. devid_to = e->ext >> 8;
  514. ext_flags = 0;
  515. alias = true;
  516. break;
  517. case IVHD_DEV_EXT_SELECT:
  518. devid = e->devid;
  519. set_dev_entry_from_acpi(iommu, devid, e->flags,
  520. e->ext);
  521. break;
  522. case IVHD_DEV_EXT_SELECT_RANGE:
  523. devid_start = e->devid;
  524. flags = e->flags;
  525. ext_flags = e->ext;
  526. alias = false;
  527. break;
  528. case IVHD_DEV_RANGE_END:
  529. devid = e->devid;
  530. for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
  531. if (alias)
  532. amd_iommu_alias_table[dev_i] = devid_to;
  533. set_dev_entry_from_acpi(iommu,
  534. amd_iommu_alias_table[dev_i],
  535. flags, ext_flags);
  536. }
  537. break;
  538. default:
  539. break;
  540. }
  541. p += 0x04 << (e->type >> 6);
  542. }
  543. }
  544. /* Initializes the device->iommu mapping for the driver */
  545. static int __init init_iommu_devices(struct amd_iommu *iommu)
  546. {
  547. u16 i;
  548. for (i = iommu->first_device; i <= iommu->last_device; ++i)
  549. set_iommu_for_device(iommu, i);
  550. return 0;
  551. }
  552. static void __init free_iommu_one(struct amd_iommu *iommu)
  553. {
  554. free_command_buffer(iommu);
  555. free_event_buffer(iommu);
  556. iommu_unmap_mmio_space(iommu);
  557. }
  558. static void __init free_iommu_all(void)
  559. {
  560. struct amd_iommu *iommu, *next;
  561. list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
  562. list_del(&iommu->list);
  563. free_iommu_one(iommu);
  564. kfree(iommu);
  565. }
  566. }
  567. /*
  568. * This function clues the initialization function for one IOMMU
  569. * together and also allocates the command buffer and programs the
  570. * hardware. It does NOT enable the IOMMU. This is done afterwards.
  571. */
  572. static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
  573. {
  574. spin_lock_init(&iommu->lock);
  575. list_add_tail(&iommu->list, &amd_iommu_list);
  576. /*
  577. * Copy data from ACPI table entry to the iommu struct
  578. */
  579. iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
  580. if (!iommu->dev)
  581. return 1;
  582. iommu->cap_ptr = h->cap_ptr;
  583. iommu->pci_seg = h->pci_seg;
  584. iommu->mmio_phys = h->mmio_phys;
  585. iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
  586. if (!iommu->mmio_base)
  587. return -ENOMEM;
  588. iommu_set_device_table(iommu);
  589. iommu->cmd_buf = alloc_command_buffer(iommu);
  590. if (!iommu->cmd_buf)
  591. return -ENOMEM;
  592. iommu->evt_buf = alloc_event_buffer(iommu);
  593. if (!iommu->evt_buf)
  594. return -ENOMEM;
  595. init_iommu_from_pci(iommu);
  596. init_iommu_from_acpi(iommu, h);
  597. init_iommu_devices(iommu);
  598. pci_enable_device(iommu->dev);
  599. return 0;
  600. }
  601. /*
  602. * Iterates over all IOMMU entries in the ACPI table, allocates the
  603. * IOMMU structure and initializes it with init_iommu_one()
  604. */
  605. static int __init init_iommu_all(struct acpi_table_header *table)
  606. {
  607. u8 *p = (u8 *)table, *end = (u8 *)table;
  608. struct ivhd_header *h;
  609. struct amd_iommu *iommu;
  610. int ret;
  611. end += table->length;
  612. p += IVRS_HEADER_LENGTH;
  613. while (p < end) {
  614. h = (struct ivhd_header *)p;
  615. switch (*p) {
  616. case ACPI_IVHD_TYPE:
  617. iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
  618. if (iommu == NULL)
  619. return -ENOMEM;
  620. ret = init_iommu_one(iommu, h);
  621. if (ret)
  622. return ret;
  623. break;
  624. default:
  625. break;
  626. }
  627. p += h->length;
  628. }
  629. WARN_ON(p != end);
  630. return 0;
  631. }
  632. /****************************************************************************
  633. *
  634. * The next functions belong to the third pass of parsing the ACPI
  635. * table. In this last pass the memory mapping requirements are
  636. * gathered (like exclusion and unity mapping reanges).
  637. *
  638. ****************************************************************************/
  639. static void __init free_unity_maps(void)
  640. {
  641. struct unity_map_entry *entry, *next;
  642. list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
  643. list_del(&entry->list);
  644. kfree(entry);
  645. }
  646. }
  647. /* called when we find an exclusion range definition in ACPI */
  648. static int __init init_exclusion_range(struct ivmd_header *m)
  649. {
  650. int i;
  651. switch (m->type) {
  652. case ACPI_IVMD_TYPE:
  653. set_device_exclusion_range(m->devid, m);
  654. break;
  655. case ACPI_IVMD_TYPE_ALL:
  656. for (i = 0; i <= amd_iommu_last_bdf; ++i)
  657. set_device_exclusion_range(i, m);
  658. break;
  659. case ACPI_IVMD_TYPE_RANGE:
  660. for (i = m->devid; i <= m->aux; ++i)
  661. set_device_exclusion_range(i, m);
  662. break;
  663. default:
  664. break;
  665. }
  666. return 0;
  667. }
  668. /* called for unity map ACPI definition */
  669. static int __init init_unity_map_range(struct ivmd_header *m)
  670. {
  671. struct unity_map_entry *e = 0;
  672. e = kzalloc(sizeof(*e), GFP_KERNEL);
  673. if (e == NULL)
  674. return -ENOMEM;
  675. switch (m->type) {
  676. default:
  677. case ACPI_IVMD_TYPE:
  678. e->devid_start = e->devid_end = m->devid;
  679. break;
  680. case ACPI_IVMD_TYPE_ALL:
  681. e->devid_start = 0;
  682. e->devid_end = amd_iommu_last_bdf;
  683. break;
  684. case ACPI_IVMD_TYPE_RANGE:
  685. e->devid_start = m->devid;
  686. e->devid_end = m->aux;
  687. break;
  688. }
  689. e->address_start = PAGE_ALIGN(m->range_start);
  690. e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
  691. e->prot = m->flags >> 1;
  692. list_add_tail(&e->list, &amd_iommu_unity_map);
  693. return 0;
  694. }
  695. /* iterates over all memory definitions we find in the ACPI table */
  696. static int __init init_memory_definitions(struct acpi_table_header *table)
  697. {
  698. u8 *p = (u8 *)table, *end = (u8 *)table;
  699. struct ivmd_header *m;
  700. end += table->length;
  701. p += IVRS_HEADER_LENGTH;
  702. while (p < end) {
  703. m = (struct ivmd_header *)p;
  704. if (m->flags & IVMD_FLAG_EXCL_RANGE)
  705. init_exclusion_range(m);
  706. else if (m->flags & IVMD_FLAG_UNITY_MAP)
  707. init_unity_map_range(m);
  708. p += m->length;
  709. }
  710. return 0;
  711. }
  712. /*
  713. * Init the device table to not allow DMA access for devices and
  714. * suppress all page faults
  715. */
  716. static void init_device_table(void)
  717. {
  718. u16 devid;
  719. for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
  720. set_dev_entry_bit(devid, DEV_ENTRY_VALID);
  721. set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
  722. set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
  723. }
  724. }
  725. /*
  726. * This function finally enables all IOMMUs found in the system after
  727. * they have been initialized
  728. */
  729. static void __init enable_iommus(void)
  730. {
  731. struct amd_iommu *iommu;
  732. list_for_each_entry(iommu, &amd_iommu_list, list) {
  733. iommu_set_exclusion_range(iommu);
  734. iommu_enable(iommu);
  735. }
  736. }
  737. /*
  738. * Suspend/Resume support
  739. * disable suspend until real resume implemented
  740. */
  741. static int amd_iommu_resume(struct sys_device *dev)
  742. {
  743. return 0;
  744. }
  745. static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
  746. {
  747. return -EINVAL;
  748. }
  749. static struct sysdev_class amd_iommu_sysdev_class = {
  750. .name = "amd_iommu",
  751. .suspend = amd_iommu_suspend,
  752. .resume = amd_iommu_resume,
  753. };
  754. static struct sys_device device_amd_iommu = {
  755. .id = 0,
  756. .cls = &amd_iommu_sysdev_class,
  757. };
  758. /*
  759. * This is the core init function for AMD IOMMU hardware in the system.
  760. * This function is called from the generic x86 DMA layer initialization
  761. * code.
  762. *
  763. * This function basically parses the ACPI table for AMD IOMMU (IVRS)
  764. * three times:
  765. *
  766. * 1 pass) Find the highest PCI device id the driver has to handle.
  767. * Upon this information the size of the data structures is
  768. * determined that needs to be allocated.
  769. *
  770. * 2 pass) Initialize the data structures just allocated with the
  771. * information in the ACPI table about available AMD IOMMUs
  772. * in the system. It also maps the PCI devices in the
  773. * system to specific IOMMUs
  774. *
  775. * 3 pass) After the basic data structures are allocated and
  776. * initialized we update them with information about memory
  777. * remapping requirements parsed out of the ACPI table in
  778. * this last pass.
  779. *
  780. * After that the hardware is initialized and ready to go. In the last
  781. * step we do some Linux specific things like registering the driver in
  782. * the dma_ops interface and initializing the suspend/resume support
  783. * functions. Finally it prints some information about AMD IOMMUs and
  784. * the driver state and enables the hardware.
  785. */
  786. int __init amd_iommu_init(void)
  787. {
  788. int i, ret = 0;
  789. if (no_iommu) {
  790. printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
  791. return 0;
  792. }
  793. if (!amd_iommu_detected)
  794. return -ENODEV;
  795. /*
  796. * First parse ACPI tables to find the largest Bus/Dev/Func
  797. * we need to handle. Upon this information the shared data
  798. * structures for the IOMMUs in the system will be allocated
  799. */
  800. if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
  801. return -ENODEV;
  802. dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
  803. alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
  804. rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
  805. ret = -ENOMEM;
  806. /* Device table - directly used by all IOMMUs */
  807. amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
  808. get_order(dev_table_size));
  809. if (amd_iommu_dev_table == NULL)
  810. goto out;
  811. /*
  812. * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
  813. * IOMMU see for that device
  814. */
  815. amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
  816. get_order(alias_table_size));
  817. if (amd_iommu_alias_table == NULL)
  818. goto free;
  819. /* IOMMU rlookup table - find the IOMMU for a specific device */
  820. amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
  821. get_order(rlookup_table_size));
  822. if (amd_iommu_rlookup_table == NULL)
  823. goto free;
  824. /*
  825. * Protection Domain table - maps devices to protection domains
  826. * This table has the same size as the rlookup_table
  827. */
  828. amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
  829. get_order(rlookup_table_size));
  830. if (amd_iommu_pd_table == NULL)
  831. goto free;
  832. amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
  833. GFP_KERNEL | __GFP_ZERO,
  834. get_order(MAX_DOMAIN_ID/8));
  835. if (amd_iommu_pd_alloc_bitmap == NULL)
  836. goto free;
  837. /* init the device table */
  838. init_device_table();
  839. /*
  840. * let all alias entries point to itself
  841. */
  842. for (i = 0; i <= amd_iommu_last_bdf; ++i)
  843. amd_iommu_alias_table[i] = i;
  844. /*
  845. * never allocate domain 0 because its used as the non-allocated and
  846. * error value placeholder
  847. */
  848. amd_iommu_pd_alloc_bitmap[0] = 1;
  849. /*
  850. * now the data structures are allocated and basically initialized
  851. * start the real acpi table scan
  852. */
  853. ret = -ENODEV;
  854. if (acpi_table_parse("IVRS", init_iommu_all) != 0)
  855. goto free;
  856. if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
  857. goto free;
  858. ret = sysdev_class_register(&amd_iommu_sysdev_class);
  859. if (ret)
  860. goto free;
  861. ret = sysdev_register(&device_amd_iommu);
  862. if (ret)
  863. goto free;
  864. ret = amd_iommu_init_dma_ops();
  865. if (ret)
  866. goto free;
  867. enable_iommus();
  868. printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
  869. (1 << (amd_iommu_aperture_order-20)));
  870. printk(KERN_INFO "AMD IOMMU: device isolation ");
  871. if (amd_iommu_isolate)
  872. printk("enabled\n");
  873. else
  874. printk("disabled\n");
  875. if (iommu_fullflush)
  876. printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
  877. else
  878. printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
  879. out:
  880. return ret;
  881. free:
  882. free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
  883. free_pages((unsigned long)amd_iommu_pd_table,
  884. get_order(rlookup_table_size));
  885. free_pages((unsigned long)amd_iommu_rlookup_table,
  886. get_order(rlookup_table_size));
  887. free_pages((unsigned long)amd_iommu_alias_table,
  888. get_order(alias_table_size));
  889. free_pages((unsigned long)amd_iommu_dev_table,
  890. get_order(dev_table_size));
  891. free_iommu_all();
  892. free_unity_maps();
  893. goto out;
  894. }
  895. /****************************************************************************
  896. *
  897. * Early detect code. This code runs at IOMMU detection time in the DMA
  898. * layer. It just looks if there is an IVRS ACPI table to detect AMD
  899. * IOMMUs
  900. *
  901. ****************************************************************************/
  902. static int __init early_amd_iommu_detect(struct acpi_table_header *table)
  903. {
  904. return 0;
  905. }
  906. void __init amd_iommu_detect(void)
  907. {
  908. if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
  909. return;
  910. if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
  911. iommu_detected = 1;
  912. amd_iommu_detected = 1;
  913. #ifdef CONFIG_GART_IOMMU
  914. gart_iommu_aperture_disabled = 1;
  915. gart_iommu_aperture = 0;
  916. #endif
  917. }
  918. }
  919. /****************************************************************************
  920. *
  921. * Parsing functions for the AMD IOMMU specific kernel command line
  922. * options.
  923. *
  924. ****************************************************************************/
  925. static int __init parse_amd_iommu_options(char *str)
  926. {
  927. for (; *str; ++str) {
  928. if (strncmp(str, "isolate", 7) == 0)
  929. amd_iommu_isolate = 1;
  930. }
  931. return 1;
  932. }
  933. static int __init parse_amd_iommu_size_options(char *str)
  934. {
  935. unsigned order = PAGE_SHIFT + get_order(memparse(str, &str));
  936. if ((order > 24) && (order < 31))
  937. amd_iommu_aperture_order = order;
  938. return 1;
  939. }
  940. __setup("amd_iommu=", parse_amd_iommu_options);
  941. __setup("amd_iommu_size=", parse_amd_iommu_size_options);