islpci_dev.c 26 KB

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  1. /*
  2. * Copyright (C) 2002 Intersil Americas Inc.
  3. * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
  4. * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/module.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/pci.h>
  23. #include <linux/etherdevice.h>
  24. #include <linux/delay.h>
  25. #include <linux/if_arp.h>
  26. #include <asm/io.h>
  27. #include "prismcompat.h"
  28. #include "isl_38xx.h"
  29. #include "isl_ioctl.h"
  30. #include "islpci_dev.h"
  31. #include "islpci_mgt.h"
  32. #include "islpci_eth.h"
  33. #include "oid_mgt.h"
  34. #define ISL3877_IMAGE_FILE "isl3877"
  35. #define ISL3886_IMAGE_FILE "isl3886"
  36. #define ISL3890_IMAGE_FILE "isl3890"
  37. static int prism54_bring_down(islpci_private *);
  38. static int islpci_alloc_memory(islpci_private *);
  39. static struct net_device_stats *islpci_statistics(struct net_device *);
  40. /* Temporary dummy MAC address to use until firmware is loaded.
  41. * The idea there is that some tools (such as nameif) may query
  42. * the MAC address before the netdev is 'open'. By using a valid
  43. * OUI prefix, they can process the netdev properly.
  44. * Of course, this is not the final/real MAC address. It doesn't
  45. * matter, as you are suppose to be able to change it anytime via
  46. * ndev->set_mac_address. Jean II */
  47. static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 };
  48. static int
  49. isl_upload_firmware(islpci_private *priv)
  50. {
  51. u32 reg, rc;
  52. void __iomem *device_base = priv->device_base;
  53. /* clear the RAMBoot and the Reset bit */
  54. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  55. reg &= ~ISL38XX_CTRL_STAT_RESET;
  56. reg &= ~ISL38XX_CTRL_STAT_RAMBOOT;
  57. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  58. wmb();
  59. udelay(ISL38XX_WRITEIO_DELAY);
  60. /* set the Reset bit without reading the register ! */
  61. reg |= ISL38XX_CTRL_STAT_RESET;
  62. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  63. wmb();
  64. udelay(ISL38XX_WRITEIO_DELAY);
  65. /* clear the Reset bit */
  66. reg &= ~ISL38XX_CTRL_STAT_RESET;
  67. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  68. wmb();
  69. /* wait a while for the device to reboot */
  70. mdelay(50);
  71. {
  72. const struct firmware *fw_entry = NULL;
  73. long fw_len;
  74. const u32 *fw_ptr;
  75. rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV);
  76. if (rc) {
  77. printk(KERN_ERR
  78. "%s: request_firmware() failed for '%s'\n",
  79. "prism54", priv->firmware);
  80. return rc;
  81. }
  82. /* prepare the Direct Memory Base register */
  83. reg = ISL38XX_DEV_FIRMWARE_ADDRES;
  84. fw_ptr = (u32 *) fw_entry->data;
  85. fw_len = fw_entry->size;
  86. if (fw_len % 4) {
  87. printk(KERN_ERR
  88. "%s: firmware '%s' size is not multiple of 32bit, aborting!\n",
  89. "prism54", priv->firmware);
  90. release_firmware(fw_entry);
  91. return -EILSEQ; /* Illegal byte sequence */;
  92. }
  93. while (fw_len > 0) {
  94. long _fw_len =
  95. (fw_len >
  96. ISL38XX_MEMORY_WINDOW_SIZE) ?
  97. ISL38XX_MEMORY_WINDOW_SIZE : fw_len;
  98. u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN;
  99. /* set the cards base address for writting the data */
  100. isl38xx_w32_flush(device_base, reg,
  101. ISL38XX_DIR_MEM_BASE_REG);
  102. wmb(); /* be paranoid */
  103. /* increment the write address for next iteration */
  104. reg += _fw_len;
  105. fw_len -= _fw_len;
  106. /* write the data to the Direct Memory Window 32bit-wise */
  107. /* memcpy_toio() doesn't guarantee 32bit writes :-| */
  108. while (_fw_len > 0) {
  109. /* use non-swapping writel() */
  110. __raw_writel(*fw_ptr, dev_fw_ptr);
  111. fw_ptr++, dev_fw_ptr++;
  112. _fw_len -= 4;
  113. }
  114. /* flush PCI posting */
  115. (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH);
  116. wmb(); /* be paranoid again */
  117. BUG_ON(_fw_len != 0);
  118. }
  119. BUG_ON(fw_len != 0);
  120. /* Firmware version is at offset 40 (also for "newmac") */
  121. printk(KERN_DEBUG "%s: firmware version: %.8s\n",
  122. priv->ndev->name, fw_entry->data + 40);
  123. release_firmware(fw_entry);
  124. }
  125. /* now reset the device
  126. * clear the Reset & ClkRun bit, set the RAMBoot bit */
  127. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  128. reg &= ~ISL38XX_CTRL_STAT_CLKRUN;
  129. reg &= ~ISL38XX_CTRL_STAT_RESET;
  130. reg |= ISL38XX_CTRL_STAT_RAMBOOT;
  131. isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG);
  132. wmb();
  133. udelay(ISL38XX_WRITEIO_DELAY);
  134. /* set the reset bit latches the host override and RAMBoot bits
  135. * into the device for operation when the reset bit is reset */
  136. reg |= ISL38XX_CTRL_STAT_RESET;
  137. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  138. /* don't do flush PCI posting here! */
  139. wmb();
  140. udelay(ISL38XX_WRITEIO_DELAY);
  141. /* clear the reset bit should start the whole circus */
  142. reg &= ~ISL38XX_CTRL_STAT_RESET;
  143. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  144. /* don't do flush PCI posting here! */
  145. wmb();
  146. udelay(ISL38XX_WRITEIO_DELAY);
  147. return 0;
  148. }
  149. /******************************************************************************
  150. Device Interrupt Handler
  151. ******************************************************************************/
  152. irqreturn_t
  153. islpci_interrupt(int irq, void *config)
  154. {
  155. u32 reg;
  156. islpci_private *priv = config;
  157. struct net_device *ndev = priv->ndev;
  158. void __iomem *device = priv->device_base;
  159. int powerstate = ISL38XX_PSM_POWERSAVE_STATE;
  160. /* lock the interrupt handler */
  161. spin_lock(&priv->slock);
  162. /* received an interrupt request on a shared IRQ line
  163. * first check whether the device is in sleep mode */
  164. reg = readl(device + ISL38XX_CTRL_STAT_REG);
  165. if (reg & ISL38XX_CTRL_STAT_SLEEPMODE)
  166. /* device is in sleep mode, IRQ was generated by someone else */
  167. {
  168. #if VERBOSE > SHOW_ERROR_MESSAGES
  169. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  170. #endif
  171. spin_unlock(&priv->slock);
  172. return IRQ_NONE;
  173. }
  174. /* check whether there is any source of interrupt on the device */
  175. reg = readl(device + ISL38XX_INT_IDENT_REG);
  176. /* also check the contents of the Interrupt Enable Register, because this
  177. * will filter out interrupt sources from other devices on the same irq ! */
  178. reg &= readl(device + ISL38XX_INT_EN_REG);
  179. reg &= ISL38XX_INT_SOURCES;
  180. if (reg != 0) {
  181. if (islpci_get_state(priv) != PRV_STATE_SLEEP)
  182. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  183. /* reset the request bits in the Identification register */
  184. isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG);
  185. #if VERBOSE > SHOW_ERROR_MESSAGES
  186. DEBUG(SHOW_FUNCTION_CALLS,
  187. "IRQ: Identification register 0x%p 0x%x \n", device, reg);
  188. #endif
  189. /* check for each bit in the register separately */
  190. if (reg & ISL38XX_INT_IDENT_UPDATE) {
  191. #if VERBOSE > SHOW_ERROR_MESSAGES
  192. /* Queue has been updated */
  193. DEBUG(SHOW_TRACING, "IRQ: Update flag \n");
  194. DEBUG(SHOW_QUEUE_INDEXES,
  195. "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n",
  196. le32_to_cpu(priv->control_block->
  197. driver_curr_frag[0]),
  198. le32_to_cpu(priv->control_block->
  199. driver_curr_frag[1]),
  200. le32_to_cpu(priv->control_block->
  201. driver_curr_frag[2]),
  202. le32_to_cpu(priv->control_block->
  203. driver_curr_frag[3]),
  204. le32_to_cpu(priv->control_block->
  205. driver_curr_frag[4]),
  206. le32_to_cpu(priv->control_block->
  207. driver_curr_frag[5])
  208. );
  209. DEBUG(SHOW_QUEUE_INDEXES,
  210. "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n",
  211. le32_to_cpu(priv->control_block->
  212. device_curr_frag[0]),
  213. le32_to_cpu(priv->control_block->
  214. device_curr_frag[1]),
  215. le32_to_cpu(priv->control_block->
  216. device_curr_frag[2]),
  217. le32_to_cpu(priv->control_block->
  218. device_curr_frag[3]),
  219. le32_to_cpu(priv->control_block->
  220. device_curr_frag[4]),
  221. le32_to_cpu(priv->control_block->
  222. device_curr_frag[5])
  223. );
  224. #endif
  225. /* cleanup the data low transmit queue */
  226. islpci_eth_cleanup_transmit(priv, priv->control_block);
  227. /* device is in active state, update the
  228. * powerstate flag if necessary */
  229. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  230. /* check all three queues in priority order
  231. * call the PIMFOR receive function until the
  232. * queue is empty */
  233. if (isl38xx_in_queue(priv->control_block,
  234. ISL38XX_CB_RX_MGMTQ) != 0) {
  235. #if VERBOSE > SHOW_ERROR_MESSAGES
  236. DEBUG(SHOW_TRACING,
  237. "Received frame in Management Queue\n");
  238. #endif
  239. islpci_mgt_receive(ndev);
  240. islpci_mgt_cleanup_transmit(ndev);
  241. /* Refill slots in receive queue */
  242. islpci_mgmt_rx_fill(ndev);
  243. /* no need to trigger the device, next
  244. islpci_mgt_transaction does it */
  245. }
  246. while (isl38xx_in_queue(priv->control_block,
  247. ISL38XX_CB_RX_DATA_LQ) != 0) {
  248. #if VERBOSE > SHOW_ERROR_MESSAGES
  249. DEBUG(SHOW_TRACING,
  250. "Received frame in Data Low Queue \n");
  251. #endif
  252. islpci_eth_receive(priv);
  253. }
  254. /* check whether the data transmit queues were full */
  255. if (priv->data_low_tx_full) {
  256. /* check whether the transmit is not full anymore */
  257. if (ISL38XX_CB_TX_QSIZE -
  258. isl38xx_in_queue(priv->control_block,
  259. ISL38XX_CB_TX_DATA_LQ) >=
  260. ISL38XX_MIN_QTHRESHOLD) {
  261. /* nope, the driver is ready for more network frames */
  262. netif_wake_queue(priv->ndev);
  263. /* reset the full flag */
  264. priv->data_low_tx_full = 0;
  265. }
  266. }
  267. }
  268. if (reg & ISL38XX_INT_IDENT_INIT) {
  269. /* Device has been initialized */
  270. #if VERBOSE > SHOW_ERROR_MESSAGES
  271. DEBUG(SHOW_TRACING,
  272. "IRQ: Init flag, device initialized \n");
  273. #endif
  274. wake_up(&priv->reset_done);
  275. }
  276. if (reg & ISL38XX_INT_IDENT_SLEEP) {
  277. /* Device intends to move to powersave state */
  278. #if VERBOSE > SHOW_ERROR_MESSAGES
  279. DEBUG(SHOW_TRACING, "IRQ: Sleep flag \n");
  280. #endif
  281. isl38xx_handle_sleep_request(priv->control_block,
  282. &powerstate,
  283. priv->device_base);
  284. }
  285. if (reg & ISL38XX_INT_IDENT_WAKEUP) {
  286. /* Device has been woken up to active state */
  287. #if VERBOSE > SHOW_ERROR_MESSAGES
  288. DEBUG(SHOW_TRACING, "IRQ: Wakeup flag \n");
  289. #endif
  290. isl38xx_handle_wakeup(priv->control_block,
  291. &powerstate, priv->device_base);
  292. }
  293. } else {
  294. #if VERBOSE > SHOW_ERROR_MESSAGES
  295. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  296. #endif
  297. spin_unlock(&priv->slock);
  298. return IRQ_NONE;
  299. }
  300. /* sleep -> ready */
  301. if (islpci_get_state(priv) == PRV_STATE_SLEEP
  302. && powerstate == ISL38XX_PSM_ACTIVE_STATE)
  303. islpci_set_state(priv, PRV_STATE_READY);
  304. /* !sleep -> sleep */
  305. if (islpci_get_state(priv) != PRV_STATE_SLEEP
  306. && powerstate == ISL38XX_PSM_POWERSAVE_STATE)
  307. islpci_set_state(priv, PRV_STATE_SLEEP);
  308. /* unlock the interrupt handler */
  309. spin_unlock(&priv->slock);
  310. return IRQ_HANDLED;
  311. }
  312. /******************************************************************************
  313. Network Interface Control & Statistical functions
  314. ******************************************************************************/
  315. static int
  316. islpci_open(struct net_device *ndev)
  317. {
  318. u32 rc;
  319. islpci_private *priv = netdev_priv(ndev);
  320. /* reset data structures, upload firmware and reset device */
  321. rc = islpci_reset(priv,1);
  322. if (rc) {
  323. prism54_bring_down(priv);
  324. return rc; /* Returns informative message */
  325. }
  326. netif_start_queue(ndev);
  327. /* netif_mark_up( ndev ); */
  328. return 0;
  329. }
  330. static int
  331. islpci_close(struct net_device *ndev)
  332. {
  333. islpci_private *priv = netdev_priv(ndev);
  334. printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name);
  335. netif_stop_queue(ndev);
  336. return prism54_bring_down(priv);
  337. }
  338. static int
  339. prism54_bring_down(islpci_private *priv)
  340. {
  341. void __iomem *device_base = priv->device_base;
  342. u32 reg;
  343. /* we are going to shutdown the device */
  344. islpci_set_state(priv, PRV_STATE_PREBOOT);
  345. /* disable all device interrupts in case they weren't */
  346. isl38xx_disable_interrupts(priv->device_base);
  347. /* For safety reasons, we may want to ensure that no DMA transfer is
  348. * currently in progress by emptying the TX and RX queues. */
  349. /* wait until interrupts have finished executing on other CPUs */
  350. synchronize_irq(priv->pdev->irq);
  351. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  352. reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT);
  353. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  354. wmb();
  355. udelay(ISL38XX_WRITEIO_DELAY);
  356. reg |= ISL38XX_CTRL_STAT_RESET;
  357. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  358. wmb();
  359. udelay(ISL38XX_WRITEIO_DELAY);
  360. /* clear the Reset bit */
  361. reg &= ~ISL38XX_CTRL_STAT_RESET;
  362. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  363. wmb();
  364. /* wait a while for the device to reset */
  365. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  366. return 0;
  367. }
  368. static int
  369. islpci_upload_fw(islpci_private *priv)
  370. {
  371. islpci_state_t old_state;
  372. u32 rc;
  373. old_state = islpci_set_state(priv, PRV_STATE_BOOT);
  374. printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name);
  375. rc = isl_upload_firmware(priv);
  376. if (rc) {
  377. /* error uploading the firmware */
  378. printk(KERN_ERR "%s: could not upload firmware ('%s')\n",
  379. priv->ndev->name, priv->firmware);
  380. islpci_set_state(priv, old_state);
  381. return rc;
  382. }
  383. printk(KERN_DEBUG "%s: firmware upload complete\n",
  384. priv->ndev->name);
  385. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  386. return 0;
  387. }
  388. static int
  389. islpci_reset_if(islpci_private *priv)
  390. {
  391. long remaining;
  392. int result = -ETIME;
  393. int count;
  394. DEFINE_WAIT(wait);
  395. prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE);
  396. /* now the last step is to reset the interface */
  397. isl38xx_interface_reset(priv->device_base, priv->device_host_address);
  398. islpci_set_state(priv, PRV_STATE_PREINIT);
  399. for(count = 0; count < 2 && result; count++) {
  400. /* The software reset acknowledge needs about 220 msec here.
  401. * Be conservative and wait for up to one second. */
  402. remaining = schedule_timeout_uninterruptible(HZ);
  403. if(remaining > 0) {
  404. result = 0;
  405. break;
  406. }
  407. /* If we're here it's because our IRQ hasn't yet gone through.
  408. * Retry a bit more...
  409. */
  410. printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n",
  411. priv->ndev->name);
  412. }
  413. finish_wait(&priv->reset_done, &wait);
  414. if (result) {
  415. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  416. return result;
  417. }
  418. islpci_set_state(priv, PRV_STATE_INIT);
  419. /* Now that the device is 100% up, let's allow
  420. * for the other interrupts --
  421. * NOTE: this is not *yet* true since we've only allowed the
  422. * INIT interrupt on the IRQ line. We can perhaps poll
  423. * the IRQ line until we know for sure the reset went through */
  424. isl38xx_enable_common_interrupts(priv->device_base);
  425. down_write(&priv->mib_sem);
  426. result = mgt_commit(priv);
  427. if (result) {
  428. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  429. up_write(&priv->mib_sem);
  430. return result;
  431. }
  432. up_write(&priv->mib_sem);
  433. islpci_set_state(priv, PRV_STATE_READY);
  434. printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name);
  435. return 0;
  436. }
  437. int
  438. islpci_reset(islpci_private *priv, int reload_firmware)
  439. {
  440. isl38xx_control_block *cb = /* volatile not needed */
  441. (isl38xx_control_block *) priv->control_block;
  442. unsigned counter;
  443. int rc;
  444. if (reload_firmware)
  445. islpci_set_state(priv, PRV_STATE_PREBOOT);
  446. else
  447. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  448. printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name);
  449. /* disable all device interrupts in case they weren't */
  450. isl38xx_disable_interrupts(priv->device_base);
  451. /* flush all management queues */
  452. priv->index_mgmt_tx = 0;
  453. priv->index_mgmt_rx = 0;
  454. /* clear the indexes in the frame pointer */
  455. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  456. cb->driver_curr_frag[counter] = cpu_to_le32(0);
  457. cb->device_curr_frag[counter] = cpu_to_le32(0);
  458. }
  459. /* reset the mgmt receive queue */
  460. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  461. isl38xx_fragment *frag = &cb->rx_data_mgmt[counter];
  462. frag->size = cpu_to_le16(MGMT_FRAME_SIZE);
  463. frag->flags = 0;
  464. frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr);
  465. }
  466. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  467. cb->rx_data_low[counter].address =
  468. cpu_to_le32((u32) priv->pci_map_rx_address[counter]);
  469. }
  470. /* since the receive queues are filled with empty fragments, now we can
  471. * set the corresponding indexes in the Control Block */
  472. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] =
  473. cpu_to_le32(ISL38XX_CB_RX_QSIZE);
  474. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] =
  475. cpu_to_le32(ISL38XX_CB_MGMT_QSIZE);
  476. /* reset the remaining real index registers and full flags */
  477. priv->free_data_rx = 0;
  478. priv->free_data_tx = 0;
  479. priv->data_low_tx_full = 0;
  480. if (reload_firmware) { /* Should we load the firmware ? */
  481. /* now that the data structures are cleaned up, upload
  482. * firmware and reset interface */
  483. rc = islpci_upload_fw(priv);
  484. if (rc) {
  485. printk(KERN_ERR "%s: islpci_reset: failure\n",
  486. priv->ndev->name);
  487. return rc;
  488. }
  489. }
  490. /* finally reset interface */
  491. rc = islpci_reset_if(priv);
  492. if (rc)
  493. printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n");
  494. return rc;
  495. }
  496. static struct net_device_stats *
  497. islpci_statistics(struct net_device *ndev)
  498. {
  499. islpci_private *priv = netdev_priv(ndev);
  500. #if VERBOSE > SHOW_ERROR_MESSAGES
  501. DEBUG(SHOW_FUNCTION_CALLS, "islpci_statistics\n");
  502. #endif
  503. return &priv->statistics;
  504. }
  505. /******************************************************************************
  506. Network device configuration functions
  507. ******************************************************************************/
  508. static int
  509. islpci_alloc_memory(islpci_private *priv)
  510. {
  511. int counter;
  512. #if VERBOSE > SHOW_ERROR_MESSAGES
  513. printk(KERN_DEBUG "islpci_alloc_memory\n");
  514. #endif
  515. /* remap the PCI device base address to accessable */
  516. if (!(priv->device_base =
  517. ioremap(pci_resource_start(priv->pdev, 0),
  518. ISL38XX_PCI_MEM_SIZE))) {
  519. /* error in remapping the PCI device memory address range */
  520. printk(KERN_ERR "PCI memory remapping failed \n");
  521. return -1;
  522. }
  523. /* memory layout for consistent DMA region:
  524. *
  525. * Area 1: Control Block for the device interface
  526. * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that
  527. * the number of supported stations in the AP determines the minimal
  528. * size of the buffer !
  529. */
  530. /* perform the allocation */
  531. priv->driver_mem_address = pci_alloc_consistent(priv->pdev,
  532. HOST_MEM_BLOCK,
  533. &priv->
  534. device_host_address);
  535. if (!priv->driver_mem_address) {
  536. /* error allocating the block of PCI memory */
  537. printk(KERN_ERR "%s: could not allocate DMA memory, aborting!",
  538. "prism54");
  539. return -1;
  540. }
  541. /* assign the Control Block to the first address of the allocated area */
  542. priv->control_block =
  543. (isl38xx_control_block *) priv->driver_mem_address;
  544. /* set the Power Save Buffer pointer directly behind the CB */
  545. priv->device_psm_buffer =
  546. priv->device_host_address + CONTROL_BLOCK_SIZE;
  547. /* make sure all buffer pointers are initialized */
  548. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  549. priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0);
  550. priv->control_block->device_curr_frag[counter] = cpu_to_le32(0);
  551. }
  552. priv->index_mgmt_rx = 0;
  553. memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx));
  554. memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx));
  555. /* allocate rx queue for management frames */
  556. if (islpci_mgmt_rx_fill(priv->ndev) < 0)
  557. goto out_free;
  558. /* now get the data rx skb's */
  559. memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx));
  560. memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address));
  561. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  562. struct sk_buff *skb;
  563. /* allocate an sk_buff for received data frames storage
  564. * each frame on receive size consists of 1 fragment
  565. * include any required allignment operations */
  566. if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) {
  567. /* error allocating an sk_buff structure elements */
  568. printk(KERN_ERR "Error allocating skb.\n");
  569. skb = NULL;
  570. goto out_free;
  571. }
  572. skb_reserve(skb, (4 - (long) skb->data) & 0x03);
  573. /* add the new allocated sk_buff to the buffer array */
  574. priv->data_low_rx[counter] = skb;
  575. /* map the allocated skb data area to pci */
  576. priv->pci_map_rx_address[counter] =
  577. pci_map_single(priv->pdev, (void *) skb->data,
  578. MAX_FRAGMENT_SIZE_RX + 2,
  579. PCI_DMA_FROMDEVICE);
  580. if (!priv->pci_map_rx_address[counter]) {
  581. /* error mapping the buffer to device
  582. accessable memory address */
  583. printk(KERN_ERR "failed to map skb DMA'able\n");
  584. goto out_free;
  585. }
  586. }
  587. prism54_acl_init(&priv->acl);
  588. prism54_wpa_bss_ie_init(priv);
  589. if (mgt_init(priv))
  590. goto out_free;
  591. return 0;
  592. out_free:
  593. islpci_free_memory(priv);
  594. return -1;
  595. }
  596. int
  597. islpci_free_memory(islpci_private *priv)
  598. {
  599. int counter;
  600. if (priv->device_base)
  601. iounmap(priv->device_base);
  602. priv->device_base = NULL;
  603. /* free consistent DMA area... */
  604. if (priv->driver_mem_address)
  605. pci_free_consistent(priv->pdev, HOST_MEM_BLOCK,
  606. priv->driver_mem_address,
  607. priv->device_host_address);
  608. /* clear some dangling pointers */
  609. priv->driver_mem_address = NULL;
  610. priv->device_host_address = 0;
  611. priv->device_psm_buffer = 0;
  612. priv->control_block = NULL;
  613. /* clean up mgmt rx buffers */
  614. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  615. struct islpci_membuf *buf = &priv->mgmt_rx[counter];
  616. if (buf->pci_addr)
  617. pci_unmap_single(priv->pdev, buf->pci_addr,
  618. buf->size, PCI_DMA_FROMDEVICE);
  619. buf->pci_addr = 0;
  620. kfree(buf->mem);
  621. buf->size = 0;
  622. buf->mem = NULL;
  623. }
  624. /* clean up data rx buffers */
  625. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  626. if (priv->pci_map_rx_address[counter])
  627. pci_unmap_single(priv->pdev,
  628. priv->pci_map_rx_address[counter],
  629. MAX_FRAGMENT_SIZE_RX + 2,
  630. PCI_DMA_FROMDEVICE);
  631. priv->pci_map_rx_address[counter] = 0;
  632. if (priv->data_low_rx[counter])
  633. dev_kfree_skb(priv->data_low_rx[counter]);
  634. priv->data_low_rx[counter] = NULL;
  635. }
  636. /* Free the acces control list and the WPA list */
  637. prism54_acl_clean(&priv->acl);
  638. prism54_wpa_bss_ie_clean(priv);
  639. mgt_clean(priv);
  640. return 0;
  641. }
  642. #if 0
  643. static void
  644. islpci_set_multicast_list(struct net_device *dev)
  645. {
  646. /* put device into promisc mode and let network layer handle it */
  647. }
  648. #endif
  649. struct net_device *
  650. islpci_setup(struct pci_dev *pdev)
  651. {
  652. islpci_private *priv;
  653. struct net_device *ndev = alloc_etherdev(sizeof (islpci_private));
  654. if (!ndev)
  655. return ndev;
  656. SET_MODULE_OWNER(ndev);
  657. pci_set_drvdata(pdev, ndev);
  658. #if defined(SET_NETDEV_DEV)
  659. SET_NETDEV_DEV(ndev, &pdev->dev);
  660. #endif
  661. /* setup the structure members */
  662. ndev->base_addr = pci_resource_start(pdev, 0);
  663. ndev->irq = pdev->irq;
  664. /* initialize the function pointers */
  665. ndev->open = &islpci_open;
  666. ndev->stop = &islpci_close;
  667. ndev->get_stats = &islpci_statistics;
  668. ndev->do_ioctl = &prism54_ioctl;
  669. ndev->wireless_handlers =
  670. (struct iw_handler_def *) &prism54_handler_def;
  671. ndev->hard_start_xmit = &islpci_eth_transmit;
  672. /* ndev->set_multicast_list = &islpci_set_multicast_list; */
  673. ndev->addr_len = ETH_ALEN;
  674. ndev->set_mac_address = &prism54_set_mac_address;
  675. /* Get a non-zero dummy MAC address for nameif. Jean II */
  676. memcpy(ndev->dev_addr, dummy_mac, 6);
  677. #ifdef HAVE_TX_TIMEOUT
  678. ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT;
  679. ndev->tx_timeout = &islpci_eth_tx_timeout;
  680. #endif
  681. /* allocate a private device structure to the network device */
  682. priv = netdev_priv(ndev);
  683. priv->ndev = ndev;
  684. priv->pdev = pdev;
  685. priv->monitor_type = ARPHRD_IEEE80211;
  686. priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ?
  687. priv->monitor_type : ARPHRD_ETHER;
  688. /* Add pointers to enable iwspy support. */
  689. priv->wireless_data.spy_data = &priv->spy_data;
  690. ndev->wireless_data = &priv->wireless_data;
  691. /* save the start and end address of the PCI memory area */
  692. ndev->mem_start = (unsigned long) priv->device_base;
  693. ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE;
  694. #if VERBOSE > SHOW_ERROR_MESSAGES
  695. DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base);
  696. #endif
  697. init_waitqueue_head(&priv->reset_done);
  698. /* init the queue read locks, process wait counter */
  699. sema_init(&priv->mgmt_sem, 1);
  700. priv->mgmt_received = NULL;
  701. init_waitqueue_head(&priv->mgmt_wqueue);
  702. sema_init(&priv->stats_sem, 1);
  703. spin_lock_init(&priv->slock);
  704. /* init state machine with off#1 state */
  705. priv->state = PRV_STATE_OFF;
  706. priv->state_off = 1;
  707. /* initialize workqueue's */
  708. INIT_WORK(&priv->stats_work,
  709. (void (*)(void *)) prism54_update_stats, priv);
  710. priv->stats_timestamp = 0;
  711. INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake, priv);
  712. priv->reset_task_pending = 0;
  713. /* allocate various memory areas */
  714. if (islpci_alloc_memory(priv))
  715. goto do_free_netdev;
  716. /* select the firmware file depending on the device id */
  717. switch (pdev->device) {
  718. case 0x3877:
  719. strcpy(priv->firmware, ISL3877_IMAGE_FILE);
  720. break;
  721. case 0x3886:
  722. strcpy(priv->firmware, ISL3886_IMAGE_FILE);
  723. break;
  724. default:
  725. strcpy(priv->firmware, ISL3890_IMAGE_FILE);
  726. break;
  727. }
  728. if (register_netdev(ndev)) {
  729. DEBUG(SHOW_ERROR_MESSAGES,
  730. "ERROR: register_netdev() failed \n");
  731. goto do_islpci_free_memory;
  732. }
  733. return ndev;
  734. do_islpci_free_memory:
  735. islpci_free_memory(priv);
  736. do_free_netdev:
  737. pci_set_drvdata(pdev, NULL);
  738. free_netdev(ndev);
  739. priv = NULL;
  740. return NULL;
  741. }
  742. islpci_state_t
  743. islpci_set_state(islpci_private *priv, islpci_state_t new_state)
  744. {
  745. islpci_state_t old_state;
  746. /* lock */
  747. old_state = priv->state;
  748. /* this means either a race condition or some serious error in
  749. * the driver code */
  750. switch (new_state) {
  751. case PRV_STATE_OFF:
  752. priv->state_off++;
  753. default:
  754. priv->state = new_state;
  755. break;
  756. case PRV_STATE_PREBOOT:
  757. /* there are actually many off-states, enumerated by
  758. * state_off */
  759. if (old_state == PRV_STATE_OFF)
  760. priv->state_off--;
  761. /* only if hw_unavailable is zero now it means we either
  762. * were in off#1 state, or came here from
  763. * somewhere else */
  764. if (!priv->state_off)
  765. priv->state = new_state;
  766. break;
  767. };
  768. #if 0
  769. printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n",
  770. priv->ndev->name, old_state, new_state, priv->state_off);
  771. #endif
  772. /* invariants */
  773. BUG_ON(priv->state_off < 0);
  774. BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF));
  775. BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF));
  776. /* unlock */
  777. return old_state;
  778. }