katmai.dts 11 KB

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  1. /*
  2. * Device Tree Source for AMCC Katmai eval board
  3. *
  4. * Copyright (c) 2006, 2007 IBM Corp.
  5. * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  6. *
  7. * Copyright (c) 2006, 2007 IBM Corp.
  8. * Josh Boyer <jwboyer@linux.vnet.ibm.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without
  12. * any warranty of any kind, whether express or implied.
  13. */
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "amcc,katmai";
  18. compatible = "amcc,katmai";
  19. dcr-parent = <&/cpus/PowerPC,440SPe@0>;
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. PowerPC,440SPe@0 {
  24. device_type = "cpu";
  25. reg = <0>;
  26. clock-frequency = <0>; /* Filled in by zImage */
  27. timebase-frequency = <0>; /* Filled in by zImage */
  28. i-cache-line-size = <20>;
  29. d-cache-line-size = <20>;
  30. i-cache-size = <20000>;
  31. d-cache-size = <20000>;
  32. dcr-controller;
  33. dcr-access-method = "native";
  34. };
  35. };
  36. memory {
  37. device_type = "memory";
  38. reg = <0 0 0>; /* Filled in by zImage */
  39. };
  40. UIC0: interrupt-controller0 {
  41. compatible = "ibm,uic-440spe","ibm,uic";
  42. interrupt-controller;
  43. cell-index = <0>;
  44. dcr-reg = <0c0 009>;
  45. #address-cells = <0>;
  46. #size-cells = <0>;
  47. #interrupt-cells = <2>;
  48. };
  49. UIC1: interrupt-controller1 {
  50. compatible = "ibm,uic-440spe","ibm,uic";
  51. interrupt-controller;
  52. cell-index = <1>;
  53. dcr-reg = <0d0 009>;
  54. #address-cells = <0>;
  55. #size-cells = <0>;
  56. #interrupt-cells = <2>;
  57. interrupts = <1e 4 1f 4>; /* cascade */
  58. interrupt-parent = <&UIC0>;
  59. };
  60. UIC2: interrupt-controller2 {
  61. compatible = "ibm,uic-440spe","ibm,uic";
  62. interrupt-controller;
  63. cell-index = <2>;
  64. dcr-reg = <0e0 009>;
  65. #address-cells = <0>;
  66. #size-cells = <0>;
  67. #interrupt-cells = <2>;
  68. interrupts = <a 4 b 4>; /* cascade */
  69. interrupt-parent = <&UIC0>;
  70. };
  71. UIC3: interrupt-controller3 {
  72. compatible = "ibm,uic-440spe","ibm,uic";
  73. interrupt-controller;
  74. cell-index = <3>;
  75. dcr-reg = <0f0 009>;
  76. #address-cells = <0>;
  77. #size-cells = <0>;
  78. #interrupt-cells = <2>;
  79. interrupts = <10 4 11 4>; /* cascade */
  80. interrupt-parent = <&UIC0>;
  81. };
  82. SDR0: sdr {
  83. compatible = "ibm,sdr-440spe";
  84. dcr-reg = <00e 002>;
  85. };
  86. CPR0: cpr {
  87. compatible = "ibm,cpr-440spe";
  88. dcr-reg = <00c 002>;
  89. };
  90. plb {
  91. compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
  92. #address-cells = <2>;
  93. #size-cells = <1>;
  94. ranges;
  95. clock-frequency = <0>; /* Filled in by zImage */
  96. SDRAM0: sdram {
  97. compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
  98. dcr-reg = <010 2>;
  99. };
  100. MAL0: mcmal {
  101. compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
  102. dcr-reg = <180 62>;
  103. num-tx-chans = <2>;
  104. num-rx-chans = <1>;
  105. interrupt-parent = <&MAL0>;
  106. interrupts = <0 1 2 3 4>;
  107. #interrupt-cells = <1>;
  108. #address-cells = <0>;
  109. #size-cells = <0>;
  110. interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
  111. /*RXEOB*/ 1 &UIC1 7 4
  112. /*SERR*/ 2 &UIC1 1 4
  113. /*TXDE*/ 3 &UIC1 2 4
  114. /*RXDE*/ 4 &UIC1 3 4>;
  115. };
  116. POB0: opb {
  117. compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
  118. #address-cells = <1>;
  119. #size-cells = <1>;
  120. ranges = <00000000 4 e0000000 20000000>;
  121. clock-frequency = <0>; /* Filled in by zImage */
  122. EBC0: ebc {
  123. compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
  124. dcr-reg = <012 2>;
  125. #address-cells = <2>;
  126. #size-cells = <1>;
  127. clock-frequency = <0>; /* Filled in by zImage */
  128. interrupts = <5 1>;
  129. interrupt-parent = <&UIC1>;
  130. };
  131. UART0: serial@10000200 {
  132. device_type = "serial";
  133. compatible = "ns16550";
  134. reg = <10000200 8>;
  135. virtual-reg = <a0000200>;
  136. clock-frequency = <0>; /* Filled in by zImage */
  137. current-speed = <1c200>;
  138. interrupt-parent = <&UIC0>;
  139. interrupts = <0 4>;
  140. };
  141. UART1: serial@10000300 {
  142. device_type = "serial";
  143. compatible = "ns16550";
  144. reg = <10000300 8>;
  145. virtual-reg = <a0000300>;
  146. clock-frequency = <0>;
  147. current-speed = <0>;
  148. interrupt-parent = <&UIC0>;
  149. interrupts = <1 4>;
  150. };
  151. UART2: serial@10000600 {
  152. device_type = "serial";
  153. compatible = "ns16550";
  154. reg = <10000600 8>;
  155. virtual-reg = <a0000600>;
  156. clock-frequency = <0>;
  157. current-speed = <0>;
  158. interrupt-parent = <&UIC1>;
  159. interrupts = <5 4>;
  160. };
  161. IIC0: i2c@10000400 {
  162. device_type = "i2c";
  163. compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
  164. reg = <10000400 14>;
  165. interrupt-parent = <&UIC0>;
  166. interrupts = <2 4>;
  167. };
  168. IIC1: i2c@10000500 {
  169. device_type = "i2c";
  170. compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
  171. reg = <10000500 14>;
  172. interrupt-parent = <&UIC0>;
  173. interrupts = <3 4>;
  174. };
  175. EMAC0: ethernet@10000800 {
  176. linux,network-index = <0>;
  177. device_type = "network";
  178. compatible = "ibm,emac-440spe", "ibm,emac4";
  179. interrupt-parent = <&UIC1>;
  180. interrupts = <1c 4 1d 4>;
  181. reg = <10000800 70>;
  182. local-mac-address = [000000000000];
  183. mal-device = <&MAL0>;
  184. mal-tx-channel = <0>;
  185. mal-rx-channel = <0>;
  186. cell-index = <0>;
  187. max-frame-size = <5dc>;
  188. rx-fifo-size = <1000>;
  189. tx-fifo-size = <800>;
  190. phy-mode = "gmii";
  191. phy-map = <00000000>;
  192. has-inverted-stacr-oc;
  193. has-new-stacr-staopc;
  194. };
  195. };
  196. PCIX0: pci@c0ec00000 {
  197. device_type = "pci";
  198. #interrupt-cells = <1>;
  199. #size-cells = <2>;
  200. #address-cells = <3>;
  201. compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
  202. primary;
  203. large-inbound-windows;
  204. enable-msi-hole;
  205. reg = <c 0ec00000 8 /* Config space access */
  206. 0 0 0 /* no IACK cycles */
  207. c 0ed00000 4 /* Special cycles */
  208. c 0ec80000 100 /* Internal registers */
  209. c 0ec80100 fc>; /* Internal messaging registers */
  210. /* Outbound ranges, one memory and one IO,
  211. * later cannot be changed
  212. */
  213. ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
  214. 01000000 0 00000000 0000000c 08000000 0 00010000>;
  215. /* Inbound 2GB range starting at 0 */
  216. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  217. /* This drives busses 0 to 0xf */
  218. bus-range = <0 f>;
  219. /*
  220. * On Katmai, the following PCI-X interrupts signals
  221. * have to be enabled via jumpers (only INTA is
  222. * enabled per default):
  223. *
  224. * INTB: J3: 1-2
  225. * INTC: J2: 1-2
  226. * INTD: J1: 1-2
  227. */
  228. interrupt-map-mask = <f800 0 0 7>;
  229. interrupt-map = <
  230. /* IDSEL 1 */
  231. 0800 0 0 1 &UIC1 14 8
  232. 0800 0 0 2 &UIC1 13 8
  233. 0800 0 0 3 &UIC1 12 8
  234. 0800 0 0 4 &UIC1 11 8
  235. >;
  236. };
  237. PCIE0: pciex@d00000000 {
  238. device_type = "pci";
  239. #interrupt-cells = <1>;
  240. #size-cells = <2>;
  241. #address-cells = <3>;
  242. compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
  243. primary;
  244. port = <0>; /* port number */
  245. reg = <d 00000000 20000000 /* Config space access */
  246. c 10000000 00001000>; /* Registers */
  247. dcr-reg = <100 020>;
  248. sdr-base = <300>;
  249. /* Outbound ranges, one memory and one IO,
  250. * later cannot be changed
  251. */
  252. ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
  253. 01000000 0 00000000 0000000f 80000000 0 00010000>;
  254. /* Inbound 2GB range starting at 0 */
  255. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  256. /* This drives busses 10 to 0x1f */
  257. bus-range = <10 1f>;
  258. /* Legacy interrupts (note the weird polarity, the bridge seems
  259. * to invert PCIe legacy interrupts).
  260. * We are de-swizzling here because the numbers are actually for
  261. * port of the root complex virtual P2P bridge. But I want
  262. * to avoid putting a node for it in the tree, so the numbers
  263. * below are basically de-swizzled numbers.
  264. * The real slot is on idsel 0, so the swizzling is 1:1
  265. */
  266. interrupt-map-mask = <0000 0 0 7>;
  267. interrupt-map = <
  268. 0000 0 0 1 &UIC3 0 4 /* swizzled int A */
  269. 0000 0 0 2 &UIC3 1 4 /* swizzled int B */
  270. 0000 0 0 3 &UIC3 2 4 /* swizzled int C */
  271. 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
  272. };
  273. PCIE1: pciex@d20000000 {
  274. device_type = "pci";
  275. #interrupt-cells = <1>;
  276. #size-cells = <2>;
  277. #address-cells = <3>;
  278. compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
  279. primary;
  280. port = <1>; /* port number */
  281. reg = <d 20000000 20000000 /* Config space access */
  282. c 10001000 00001000>; /* Registers */
  283. dcr-reg = <120 020>;
  284. sdr-base = <340>;
  285. /* Outbound ranges, one memory and one IO,
  286. * later cannot be changed
  287. */
  288. ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
  289. 01000000 0 00000000 0000000f 80010000 0 00010000>;
  290. /* Inbound 2GB range starting at 0 */
  291. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  292. /* This drives busses 10 to 0x1f */
  293. bus-range = <20 2f>;
  294. /* Legacy interrupts (note the weird polarity, the bridge seems
  295. * to invert PCIe legacy interrupts).
  296. * We are de-swizzling here because the numbers are actually for
  297. * port of the root complex virtual P2P bridge. But I want
  298. * to avoid putting a node for it in the tree, so the numbers
  299. * below are basically de-swizzled numbers.
  300. * The real slot is on idsel 0, so the swizzling is 1:1
  301. */
  302. interrupt-map-mask = <0000 0 0 7>;
  303. interrupt-map = <
  304. 0000 0 0 1 &UIC3 4 4 /* swizzled int A */
  305. 0000 0 0 2 &UIC3 5 4 /* swizzled int B */
  306. 0000 0 0 3 &UIC3 6 4 /* swizzled int C */
  307. 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
  308. };
  309. PCIE2: pciex@d40000000 {
  310. device_type = "pci";
  311. #interrupt-cells = <1>;
  312. #size-cells = <2>;
  313. #address-cells = <3>;
  314. compatible = "ibm,plb-pciex-440speB", "ibm,plb-pciex";
  315. primary;
  316. port = <2>; /* port number */
  317. reg = <d 40000000 20000000 /* Config space access */
  318. c 10002000 00001000>; /* Registers */
  319. dcr-reg = <140 020>;
  320. sdr-base = <370>;
  321. /* Outbound ranges, one memory and one IO,
  322. * later cannot be changed
  323. */
  324. ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
  325. 01000000 0 00000000 0000000f 80020000 0 00010000>;
  326. /* Inbound 2GB range starting at 0 */
  327. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  328. /* This drives busses 10 to 0x1f */
  329. bus-range = <30 3f>;
  330. /* Legacy interrupts (note the weird polarity, the bridge seems
  331. * to invert PCIe legacy interrupts).
  332. * We are de-swizzling here because the numbers are actually for
  333. * port of the root complex virtual P2P bridge. But I want
  334. * to avoid putting a node for it in the tree, so the numbers
  335. * below are basically de-swizzled numbers.
  336. * The real slot is on idsel 0, so the swizzling is 1:1
  337. */
  338. interrupt-map-mask = <0000 0 0 7>;
  339. interrupt-map = <
  340. 0000 0 0 1 &UIC3 8 4 /* swizzled int A */
  341. 0000 0 0 2 &UIC3 9 4 /* swizzled int B */
  342. 0000 0 0 3 &UIC3 a 4 /* swizzled int C */
  343. 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
  344. };
  345. };
  346. chosen {
  347. linux,stdout-path = "/plb/opb/serial@10000200";
  348. };
  349. };