mce_amd.c 15 KB

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  1. /*
  2. * (c) 2005, 2006 Advanced Micro Devices, Inc.
  3. * Your use of this code is subject to the terms and conditions of the
  4. * GNU general public license version 2. See "COPYING" or
  5. * http://www.gnu.org/licenses/gpl.html
  6. *
  7. * Written by Jacob Shin - AMD, Inc.
  8. *
  9. * Support : jacob.shin@amd.com
  10. *
  11. * April 2006
  12. * - added support for AMD Family 0x10 processors
  13. *
  14. * All MC4_MISCi registers are shared between multi-cores
  15. */
  16. #include <linux/cpu.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/kobject.h>
  21. #include <linux/notifier.h>
  22. #include <linux/sched.h>
  23. #include <linux/smp.h>
  24. #include <linux/sysdev.h>
  25. #include <linux/sysfs.h>
  26. #include <asm/apic.h>
  27. #include <asm/mce.h>
  28. #include <asm/msr.h>
  29. #include <asm/percpu.h>
  30. #include <asm/idle.h>
  31. #define PFX "mce_threshold: "
  32. #define VERSION "version 1.1.1"
  33. #define NR_BANKS 6
  34. #define NR_BLOCKS 9
  35. #define THRESHOLD_MAX 0xFFF
  36. #define INT_TYPE_APIC 0x00020000
  37. #define MASK_VALID_HI 0x80000000
  38. #define MASK_LVTOFF_HI 0x00F00000
  39. #define MASK_COUNT_EN_HI 0x00080000
  40. #define MASK_INT_TYPE_HI 0x00060000
  41. #define MASK_OVERFLOW_HI 0x00010000
  42. #define MASK_ERR_COUNT_HI 0x00000FFF
  43. #define MASK_BLKPTR_LO 0xFF000000
  44. #define MCG_XBLK_ADDR 0xC0000400
  45. struct threshold_block {
  46. unsigned int block;
  47. unsigned int bank;
  48. unsigned int cpu;
  49. u32 address;
  50. u16 interrupt_enable;
  51. u16 threshold_limit;
  52. struct kobject kobj;
  53. struct list_head miscj;
  54. };
  55. /* defaults used early on boot */
  56. static struct threshold_block threshold_defaults = {
  57. .interrupt_enable = 0,
  58. .threshold_limit = THRESHOLD_MAX,
  59. };
  60. struct threshold_bank {
  61. struct kobject kobj;
  62. struct threshold_block *blocks;
  63. cpumask_t cpus;
  64. };
  65. static DEFINE_PER_CPU(struct threshold_bank *, threshold_banks[NR_BANKS]);
  66. #ifdef CONFIG_SMP
  67. static unsigned char shared_bank[NR_BANKS] = {
  68. 0, 0, 0, 0, 1
  69. };
  70. #endif
  71. static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
  72. /*
  73. * CPU Initialization
  74. */
  75. /* must be called with correct cpu affinity */
  76. static void threshold_restart_bank(struct threshold_block *b,
  77. int reset, u16 old_limit)
  78. {
  79. u32 mci_misc_hi, mci_misc_lo;
  80. rdmsr(b->address, mci_misc_lo, mci_misc_hi);
  81. if (b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
  82. reset = 1; /* limit cannot be lower than err count */
  83. if (reset) { /* reset err count and overflow bit */
  84. mci_misc_hi =
  85. (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
  86. (THRESHOLD_MAX - b->threshold_limit);
  87. } else if (old_limit) { /* change limit w/o reset */
  88. int new_count = (mci_misc_hi & THRESHOLD_MAX) +
  89. (old_limit - b->threshold_limit);
  90. mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
  91. (new_count & THRESHOLD_MAX);
  92. }
  93. b->interrupt_enable ?
  94. (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
  95. (mci_misc_hi &= ~MASK_INT_TYPE_HI);
  96. mci_misc_hi |= MASK_COUNT_EN_HI;
  97. wrmsr(b->address, mci_misc_lo, mci_misc_hi);
  98. }
  99. /* cpu init entry point, called from mce.c with preempt off */
  100. void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c)
  101. {
  102. unsigned int bank, block;
  103. unsigned int cpu = smp_processor_id();
  104. u32 low = 0, high = 0, address = 0;
  105. for (bank = 0; bank < NR_BANKS; ++bank) {
  106. for (block = 0; block < NR_BLOCKS; ++block) {
  107. if (block == 0)
  108. address = MSR_IA32_MC0_MISC + bank * 4;
  109. else if (block == 1)
  110. address = MCG_XBLK_ADDR
  111. + ((low & MASK_BLKPTR_LO) >> 21);
  112. else
  113. ++address;
  114. if (rdmsr_safe(address, &low, &high))
  115. continue;
  116. if (!(high & MASK_VALID_HI)) {
  117. if (block)
  118. continue;
  119. else
  120. break;
  121. }
  122. if (!(high & MASK_VALID_HI >> 1) ||
  123. (high & MASK_VALID_HI >> 2))
  124. continue;
  125. if (!block)
  126. per_cpu(bank_map, cpu) |= (1 << bank);
  127. #ifdef CONFIG_SMP
  128. if (shared_bank[bank] && c->cpu_core_id)
  129. break;
  130. #endif
  131. high &= ~MASK_LVTOFF_HI;
  132. high |= K8_APIC_EXT_LVT_ENTRY_THRESHOLD << 20;
  133. wrmsr(address, low, high);
  134. setup_APIC_extened_lvt(K8_APIC_EXT_LVT_ENTRY_THRESHOLD,
  135. THRESHOLD_APIC_VECTOR,
  136. K8_APIC_EXT_INT_MSG_FIX, 0);
  137. threshold_defaults.address = address;
  138. threshold_restart_bank(&threshold_defaults, 0, 0);
  139. }
  140. }
  141. }
  142. /*
  143. * APIC Interrupt Handler
  144. */
  145. /*
  146. * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
  147. * the interrupt goes off when error_count reaches threshold_limit.
  148. * the handler will simply log mcelog w/ software defined bank number.
  149. */
  150. asmlinkage void mce_threshold_interrupt(void)
  151. {
  152. unsigned int bank, block;
  153. struct mce m;
  154. u32 low = 0, high = 0, address = 0;
  155. ack_APIC_irq();
  156. exit_idle();
  157. irq_enter();
  158. memset(&m, 0, sizeof(m));
  159. rdtscll(m.tsc);
  160. m.cpu = smp_processor_id();
  161. /* assume first bank caused it */
  162. for (bank = 0; bank < NR_BANKS; ++bank) {
  163. for (block = 0; block < NR_BLOCKS; ++block) {
  164. if (block == 0)
  165. address = MSR_IA32_MC0_MISC + bank * 4;
  166. else if (block == 1)
  167. address = MCG_XBLK_ADDR
  168. + ((low & MASK_BLKPTR_LO) >> 21);
  169. else
  170. ++address;
  171. if (rdmsr_safe(address, &low, &high))
  172. continue;
  173. if (!(high & MASK_VALID_HI)) {
  174. if (block)
  175. continue;
  176. else
  177. break;
  178. }
  179. if (!(high & MASK_VALID_HI >> 1) ||
  180. (high & MASK_VALID_HI >> 2))
  181. continue;
  182. if (high & MASK_OVERFLOW_HI) {
  183. rdmsrl(address, m.misc);
  184. rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
  185. m.status);
  186. m.bank = K8_MCE_THRESHOLD_BASE
  187. + bank * NR_BLOCKS
  188. + block;
  189. mce_log(&m);
  190. goto out;
  191. }
  192. }
  193. }
  194. out:
  195. irq_exit();
  196. }
  197. /*
  198. * Sysfs Interface
  199. */
  200. struct threshold_attr {
  201. struct attribute attr;
  202. ssize_t(*show) (struct threshold_block *, char *);
  203. ssize_t(*store) (struct threshold_block *, const char *, size_t count);
  204. };
  205. static cpumask_t affinity_set(unsigned int cpu)
  206. {
  207. cpumask_t oldmask = current->cpus_allowed;
  208. cpumask_t newmask = CPU_MASK_NONE;
  209. cpu_set(cpu, newmask);
  210. set_cpus_allowed(current, newmask);
  211. return oldmask;
  212. }
  213. static void affinity_restore(cpumask_t oldmask)
  214. {
  215. set_cpus_allowed(current, oldmask);
  216. }
  217. #define SHOW_FIELDS(name) \
  218. static ssize_t show_ ## name(struct threshold_block * b, char *buf) \
  219. { \
  220. return sprintf(buf, "%lx\n", (unsigned long) b->name); \
  221. }
  222. SHOW_FIELDS(interrupt_enable)
  223. SHOW_FIELDS(threshold_limit)
  224. static ssize_t store_interrupt_enable(struct threshold_block *b,
  225. const char *buf, size_t count)
  226. {
  227. char *end;
  228. cpumask_t oldmask;
  229. unsigned long new = simple_strtoul(buf, &end, 0);
  230. if (end == buf)
  231. return -EINVAL;
  232. b->interrupt_enable = !!new;
  233. oldmask = affinity_set(b->cpu);
  234. threshold_restart_bank(b, 0, 0);
  235. affinity_restore(oldmask);
  236. return end - buf;
  237. }
  238. static ssize_t store_threshold_limit(struct threshold_block *b,
  239. const char *buf, size_t count)
  240. {
  241. char *end;
  242. cpumask_t oldmask;
  243. u16 old;
  244. unsigned long new = simple_strtoul(buf, &end, 0);
  245. if (end == buf)
  246. return -EINVAL;
  247. if (new > THRESHOLD_MAX)
  248. new = THRESHOLD_MAX;
  249. if (new < 1)
  250. new = 1;
  251. old = b->threshold_limit;
  252. b->threshold_limit = new;
  253. oldmask = affinity_set(b->cpu);
  254. threshold_restart_bank(b, 0, old);
  255. affinity_restore(oldmask);
  256. return end - buf;
  257. }
  258. static ssize_t show_error_count(struct threshold_block *b, char *buf)
  259. {
  260. u32 high, low;
  261. cpumask_t oldmask;
  262. oldmask = affinity_set(b->cpu);
  263. rdmsr(b->address, low, high);
  264. affinity_restore(oldmask);
  265. return sprintf(buf, "%x\n",
  266. (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit));
  267. }
  268. static ssize_t store_error_count(struct threshold_block *b,
  269. const char *buf, size_t count)
  270. {
  271. cpumask_t oldmask;
  272. oldmask = affinity_set(b->cpu);
  273. threshold_restart_bank(b, 1, 0);
  274. affinity_restore(oldmask);
  275. return 1;
  276. }
  277. #define THRESHOLD_ATTR(_name,_mode,_show,_store) { \
  278. .attr = {.name = __stringify(_name), .mode = _mode }, \
  279. .show = _show, \
  280. .store = _store, \
  281. };
  282. #define RW_ATTR(name) \
  283. static struct threshold_attr name = \
  284. THRESHOLD_ATTR(name, 0644, show_## name, store_## name)
  285. RW_ATTR(interrupt_enable);
  286. RW_ATTR(threshold_limit);
  287. RW_ATTR(error_count);
  288. static struct attribute *default_attrs[] = {
  289. &interrupt_enable.attr,
  290. &threshold_limit.attr,
  291. &error_count.attr,
  292. NULL
  293. };
  294. #define to_block(k) container_of(k, struct threshold_block, kobj)
  295. #define to_attr(a) container_of(a, struct threshold_attr, attr)
  296. static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
  297. {
  298. struct threshold_block *b = to_block(kobj);
  299. struct threshold_attr *a = to_attr(attr);
  300. ssize_t ret;
  301. ret = a->show ? a->show(b, buf) : -EIO;
  302. return ret;
  303. }
  304. static ssize_t store(struct kobject *kobj, struct attribute *attr,
  305. const char *buf, size_t count)
  306. {
  307. struct threshold_block *b = to_block(kobj);
  308. struct threshold_attr *a = to_attr(attr);
  309. ssize_t ret;
  310. ret = a->store ? a->store(b, buf, count) : -EIO;
  311. return ret;
  312. }
  313. static struct sysfs_ops threshold_ops = {
  314. .show = show,
  315. .store = store,
  316. };
  317. static struct kobj_type threshold_ktype = {
  318. .sysfs_ops = &threshold_ops,
  319. .default_attrs = default_attrs,
  320. };
  321. static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
  322. unsigned int bank,
  323. unsigned int block,
  324. u32 address)
  325. {
  326. int err;
  327. u32 low, high;
  328. struct threshold_block *b = NULL;
  329. if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
  330. return 0;
  331. if (rdmsr_safe(address, &low, &high))
  332. goto recurse;
  333. if (!(high & MASK_VALID_HI)) {
  334. if (block)
  335. goto recurse;
  336. else
  337. return 0;
  338. }
  339. if (!(high & MASK_VALID_HI >> 1) ||
  340. (high & MASK_VALID_HI >> 2))
  341. goto recurse;
  342. b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
  343. if (!b)
  344. return -ENOMEM;
  345. b->block = block;
  346. b->bank = bank;
  347. b->cpu = cpu;
  348. b->address = address;
  349. b->interrupt_enable = 0;
  350. b->threshold_limit = THRESHOLD_MAX;
  351. INIT_LIST_HEAD(&b->miscj);
  352. if (per_cpu(threshold_banks, cpu)[bank]->blocks)
  353. list_add(&b->miscj,
  354. &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
  355. else
  356. per_cpu(threshold_banks, cpu)[bank]->blocks = b;
  357. kobject_set_name(&b->kobj, "misc%i", block);
  358. b->kobj.parent = &per_cpu(threshold_banks, cpu)[bank]->kobj;
  359. b->kobj.ktype = &threshold_ktype;
  360. err = kobject_register(&b->kobj);
  361. if (err)
  362. goto out_free;
  363. recurse:
  364. if (!block) {
  365. address = (low & MASK_BLKPTR_LO) >> 21;
  366. if (!address)
  367. return 0;
  368. address += MCG_XBLK_ADDR;
  369. } else
  370. ++address;
  371. err = allocate_threshold_blocks(cpu, bank, ++block, address);
  372. if (err)
  373. goto out_free;
  374. return err;
  375. out_free:
  376. if (b) {
  377. kobject_unregister(&b->kobj);
  378. kfree(b);
  379. }
  380. return err;
  381. }
  382. /* symlinks sibling shared banks to first core. first core owns dir/files. */
  383. static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
  384. {
  385. int i, err = 0;
  386. struct threshold_bank *b = NULL;
  387. cpumask_t oldmask = CPU_MASK_NONE;
  388. char name[32];
  389. sprintf(name, "threshold_bank%i", bank);
  390. #ifdef CONFIG_SMP
  391. if (cpu_data[cpu].cpu_core_id && shared_bank[bank]) { /* symlink */
  392. i = first_cpu(cpu_core_map[cpu]);
  393. /* first core not up yet */
  394. if (cpu_data[i].cpu_core_id)
  395. goto out;
  396. /* already linked */
  397. if (per_cpu(threshold_banks, cpu)[bank])
  398. goto out;
  399. b = per_cpu(threshold_banks, i)[bank];
  400. if (!b)
  401. goto out;
  402. err = sysfs_create_link(&per_cpu(device_mce, cpu).kobj,
  403. &b->kobj, name);
  404. if (err)
  405. goto out;
  406. b->cpus = cpu_core_map[cpu];
  407. per_cpu(threshold_banks, cpu)[bank] = b;
  408. goto out;
  409. }
  410. #endif
  411. b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
  412. if (!b) {
  413. err = -ENOMEM;
  414. goto out;
  415. }
  416. kobject_set_name(&b->kobj, "threshold_bank%i", bank);
  417. b->kobj.parent = &per_cpu(device_mce, cpu).kobj;
  418. #ifndef CONFIG_SMP
  419. b->cpus = CPU_MASK_ALL;
  420. #else
  421. b->cpus = cpu_core_map[cpu];
  422. #endif
  423. err = kobject_register(&b->kobj);
  424. if (err)
  425. goto out_free;
  426. per_cpu(threshold_banks, cpu)[bank] = b;
  427. oldmask = affinity_set(cpu);
  428. err = allocate_threshold_blocks(cpu, bank, 0,
  429. MSR_IA32_MC0_MISC + bank * 4);
  430. affinity_restore(oldmask);
  431. if (err)
  432. goto out_free;
  433. for_each_cpu_mask(i, b->cpus) {
  434. if (i == cpu)
  435. continue;
  436. err = sysfs_create_link(&per_cpu(device_mce, i).kobj,
  437. &b->kobj, name);
  438. if (err)
  439. goto out;
  440. per_cpu(threshold_banks, i)[bank] = b;
  441. }
  442. goto out;
  443. out_free:
  444. per_cpu(threshold_banks, cpu)[bank] = NULL;
  445. kfree(b);
  446. out:
  447. return err;
  448. }
  449. /* create dir/files for all valid threshold banks */
  450. static __cpuinit int threshold_create_device(unsigned int cpu)
  451. {
  452. unsigned int bank;
  453. int err = 0;
  454. for (bank = 0; bank < NR_BANKS; ++bank) {
  455. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  456. continue;
  457. err = threshold_create_bank(cpu, bank);
  458. if (err)
  459. goto out;
  460. }
  461. out:
  462. return err;
  463. }
  464. /*
  465. * let's be hotplug friendly.
  466. * in case of multiple core processors, the first core always takes ownership
  467. * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
  468. */
  469. static void deallocate_threshold_block(unsigned int cpu,
  470. unsigned int bank)
  471. {
  472. struct threshold_block *pos = NULL;
  473. struct threshold_block *tmp = NULL;
  474. struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
  475. if (!head)
  476. return;
  477. list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
  478. kobject_unregister(&pos->kobj);
  479. list_del(&pos->miscj);
  480. kfree(pos);
  481. }
  482. kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
  483. per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
  484. }
  485. static void threshold_remove_bank(unsigned int cpu, int bank)
  486. {
  487. int i = 0;
  488. struct threshold_bank *b;
  489. char name[32];
  490. b = per_cpu(threshold_banks, cpu)[bank];
  491. if (!b)
  492. return;
  493. if (!b->blocks)
  494. goto free_out;
  495. sprintf(name, "threshold_bank%i", bank);
  496. #ifdef CONFIG_SMP
  497. /* sibling symlink */
  498. if (shared_bank[bank] && b->blocks->cpu != cpu) {
  499. sysfs_remove_link(&per_cpu(device_mce, cpu).kobj, name);
  500. per_cpu(threshold_banks, cpu)[bank] = NULL;
  501. return;
  502. }
  503. #endif
  504. /* remove all sibling symlinks before unregistering */
  505. for_each_cpu_mask(i, b->cpus) {
  506. if (i == cpu)
  507. continue;
  508. sysfs_remove_link(&per_cpu(device_mce, i).kobj, name);
  509. per_cpu(threshold_banks, i)[bank] = NULL;
  510. }
  511. deallocate_threshold_block(cpu, bank);
  512. free_out:
  513. kobject_unregister(&b->kobj);
  514. kfree(b);
  515. per_cpu(threshold_banks, cpu)[bank] = NULL;
  516. }
  517. static void threshold_remove_device(unsigned int cpu)
  518. {
  519. unsigned int bank;
  520. for (bank = 0; bank < NR_BANKS; ++bank) {
  521. if (!(per_cpu(bank_map, cpu) & 1 << bank))
  522. continue;
  523. threshold_remove_bank(cpu, bank);
  524. }
  525. }
  526. /* get notified when a cpu comes on/off */
  527. static int threshold_cpu_callback(struct notifier_block *nfb,
  528. unsigned long action, void *hcpu)
  529. {
  530. /* cpu was unsigned int to begin with */
  531. unsigned int cpu = (unsigned long)hcpu;
  532. if (cpu >= NR_CPUS)
  533. goto out;
  534. switch (action) {
  535. case CPU_ONLINE:
  536. threshold_create_device(cpu);
  537. break;
  538. case CPU_DEAD:
  539. threshold_remove_device(cpu);
  540. break;
  541. default:
  542. break;
  543. }
  544. out:
  545. return NOTIFY_OK;
  546. }
  547. static struct notifier_block threshold_cpu_notifier = {
  548. .notifier_call = threshold_cpu_callback,
  549. };
  550. static __init int threshold_init_device(void)
  551. {
  552. unsigned lcpu = 0;
  553. /* to hit CPUs online before the notifier is up */
  554. for_each_online_cpu(lcpu) {
  555. int err = threshold_create_device(lcpu);
  556. if (err)
  557. return err;
  558. }
  559. register_hotcpu_notifier(&threshold_cpu_notifier);
  560. return 0;
  561. }
  562. device_initcall(threshold_init_device);