mcbsp.c 6.5 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/mcbsp.c
  3. *
  4. * Copyright (C) 2008 Instituto Nokia de Tecnologia
  5. * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * Multichannel mode not supported.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/clk.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/platform_device.h>
  19. #include <mach/irqs.h>
  20. #include <mach/dma.h>
  21. #include <mach/irqs.h>
  22. #include <mach/mux.h>
  23. #include <mach/cpu.h>
  24. #include <mach/mcbsp.h>
  25. #include <mach/dsp_common.h>
  26. #define DPS_RSTCT2_PER_EN (1 << 0)
  27. #define DSP_RSTCT2_WD_PER_EN (1 << 1)
  28. struct mcbsp_internal_clk {
  29. struct clk clk;
  30. struct clk **childs;
  31. int n_childs;
  32. };
  33. #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  34. static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
  35. {
  36. const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
  37. int i;
  38. mclk->n_childs = ARRAY_SIZE(clk_names);
  39. mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
  40. GFP_KERNEL);
  41. for (i = 0; i < mclk->n_childs; i++) {
  42. /* We fake a platform device to get correct device id */
  43. struct platform_device pdev;
  44. pdev.dev.bus = &platform_bus_type;
  45. pdev.id = mclk->clk.id;
  46. mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
  47. if (IS_ERR(mclk->childs[i]))
  48. printk(KERN_ERR "Could not get clock %s (%d).\n",
  49. clk_names[i], mclk->clk.id);
  50. }
  51. }
  52. static int omap_mcbsp_clk_enable(struct clk *clk)
  53. {
  54. struct mcbsp_internal_clk *mclk = container_of(clk,
  55. struct mcbsp_internal_clk, clk);
  56. int i;
  57. for (i = 0; i < mclk->n_childs; i++)
  58. clk_enable(mclk->childs[i]);
  59. return 0;
  60. }
  61. static void omap_mcbsp_clk_disable(struct clk *clk)
  62. {
  63. struct mcbsp_internal_clk *mclk = container_of(clk,
  64. struct mcbsp_internal_clk, clk);
  65. int i;
  66. for (i = 0; i < mclk->n_childs; i++)
  67. clk_disable(mclk->childs[i]);
  68. }
  69. static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
  70. {
  71. .clk = {
  72. .name = "mcbsp_clk",
  73. .id = 1,
  74. .enable = omap_mcbsp_clk_enable,
  75. .disable = omap_mcbsp_clk_disable,
  76. },
  77. },
  78. {
  79. .clk = {
  80. .name = "mcbsp_clk",
  81. .id = 3,
  82. .enable = omap_mcbsp_clk_enable,
  83. .disable = omap_mcbsp_clk_disable,
  84. },
  85. },
  86. };
  87. #define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
  88. #else
  89. #define omap_mcbsp_clks_size 0
  90. static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
  91. static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
  92. { }
  93. #endif
  94. static void omap1_mcbsp_request(unsigned int id)
  95. {
  96. /*
  97. * On 1510, 1610 and 1710, McBSP1 and McBSP3
  98. * are DSP public peripherals.
  99. */
  100. if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
  101. omap_dsp_request_mem();
  102. /*
  103. * DSP external peripheral reset
  104. * FIXME: This should be moved to dsp code
  105. */
  106. __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
  107. DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
  108. }
  109. }
  110. static void omap1_mcbsp_free(unsigned int id)
  111. {
  112. if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
  113. omap_dsp_release_mem();
  114. }
  115. static struct omap_mcbsp_ops omap1_mcbsp_ops = {
  116. .request = omap1_mcbsp_request,
  117. .free = omap1_mcbsp_free,
  118. };
  119. #ifdef CONFIG_ARCH_OMAP730
  120. static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
  121. {
  122. .phys_base = OMAP730_MCBSP1_BASE,
  123. .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
  124. .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
  125. .rx_irq = INT_730_McBSP1RX,
  126. .tx_irq = INT_730_McBSP1TX,
  127. .ops = &omap1_mcbsp_ops,
  128. },
  129. {
  130. .phys_base = OMAP730_MCBSP2_BASE,
  131. .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
  132. .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
  133. .rx_irq = INT_730_McBSP2RX,
  134. .tx_irq = INT_730_McBSP2TX,
  135. .ops = &omap1_mcbsp_ops,
  136. },
  137. };
  138. #define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
  139. #else
  140. #define omap730_mcbsp_pdata NULL
  141. #define OMAP730_MCBSP_PDATA_SZ 0
  142. #endif
  143. #ifdef CONFIG_ARCH_OMAP15XX
  144. static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
  145. {
  146. .phys_base = OMAP1510_MCBSP1_BASE,
  147. .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
  148. .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
  149. .rx_irq = INT_McBSP1RX,
  150. .tx_irq = INT_McBSP1TX,
  151. .ops = &omap1_mcbsp_ops,
  152. .clk_name = "mcbsp_clk",
  153. },
  154. {
  155. .phys_base = OMAP1510_MCBSP2_BASE,
  156. .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
  157. .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
  158. .rx_irq = INT_1510_SPI_RX,
  159. .tx_irq = INT_1510_SPI_TX,
  160. .ops = &omap1_mcbsp_ops,
  161. },
  162. {
  163. .phys_base = OMAP1510_MCBSP3_BASE,
  164. .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
  165. .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
  166. .rx_irq = INT_McBSP3RX,
  167. .tx_irq = INT_McBSP3TX,
  168. .ops = &omap1_mcbsp_ops,
  169. .clk_name = "mcbsp_clk",
  170. },
  171. };
  172. #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
  173. #else
  174. #define omap15xx_mcbsp_pdata NULL
  175. #define OMAP15XX_MCBSP_PDATA_SZ 0
  176. #endif
  177. #ifdef CONFIG_ARCH_OMAP16XX
  178. static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
  179. {
  180. .phys_base = OMAP1610_MCBSP1_BASE,
  181. .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
  182. .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
  183. .rx_irq = INT_McBSP1RX,
  184. .tx_irq = INT_McBSP1TX,
  185. .ops = &omap1_mcbsp_ops,
  186. .clk_name = "mcbsp_clk",
  187. },
  188. {
  189. .phys_base = OMAP1610_MCBSP2_BASE,
  190. .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
  191. .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
  192. .rx_irq = INT_1610_McBSP2_RX,
  193. .tx_irq = INT_1610_McBSP2_TX,
  194. .ops = &omap1_mcbsp_ops,
  195. },
  196. {
  197. .phys_base = OMAP1610_MCBSP3_BASE,
  198. .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
  199. .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
  200. .rx_irq = INT_McBSP3RX,
  201. .tx_irq = INT_McBSP3TX,
  202. .ops = &omap1_mcbsp_ops,
  203. .clk_name = "mcbsp_clk",
  204. },
  205. };
  206. #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
  207. #else
  208. #define omap16xx_mcbsp_pdata NULL
  209. #define OMAP16XX_MCBSP_PDATA_SZ 0
  210. #endif
  211. int __init omap1_mcbsp_init(void)
  212. {
  213. int i;
  214. for (i = 0; i < omap_mcbsp_clks_size; i++) {
  215. if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
  216. omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
  217. clk_register(&omap_mcbsp_clks[i].clk);
  218. }
  219. }
  220. if (cpu_is_omap730())
  221. omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
  222. if (cpu_is_omap15xx())
  223. omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
  224. if (cpu_is_omap16xx())
  225. omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
  226. mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
  227. GFP_KERNEL);
  228. if (!mcbsp_ptr)
  229. return -ENOMEM;
  230. if (cpu_is_omap730())
  231. omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
  232. OMAP730_MCBSP_PDATA_SZ);
  233. if (cpu_is_omap15xx())
  234. omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
  235. OMAP15XX_MCBSP_PDATA_SZ);
  236. if (cpu_is_omap16xx())
  237. omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
  238. OMAP16XX_MCBSP_PDATA_SZ);
  239. return omap_mcbsp_init();
  240. }
  241. arch_initcall(omap1_mcbsp_init);