it913x-fe.h 4.7 KB

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  1. /*
  2. * Driver for it913x Frontend
  3. *
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. *
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
  19. */
  20. #ifndef IT913X_FE_H
  21. #define IT913X_FE_H
  22. #include <linux/dvb/frontend.h>
  23. #include "dvb_frontend.h"
  24. #if defined(CONFIG_DVB_IT913X_FE) || (defined(CONFIG_DVB_IT913X_FE_MODULE) && \
  25. defined(MODULE))
  26. extern struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
  27. u8 i2c_addr, u8 adf, u8 type);
  28. #else
  29. static inline struct dvb_frontend *it913x_fe_attach(
  30. struct i2c_adapter *i2c_adap, u8 i2c_addr, u8 adf, u8 type)
  31. {
  32. printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
  33. return NULL;
  34. }
  35. #endif /* CONFIG_IT913X_FE */
  36. #define I2C_BASE_ADDR 0x10
  37. #define DEV_0 0x0
  38. #define DEV_1 0x10
  39. #define PRO_LINK 0x0
  40. #define PRO_DMOD 0x1
  41. #define DEV_0_DMOD (PRO_DMOD << 0x7)
  42. #define DEV_1_DMOD (DEV_0_DMOD | DEV_1)
  43. #define CHIP2_I2C_ADDR 0x3a
  44. #define AFE_MEM0 0xfb24
  45. #define MP2_SW_RST 0xf99d
  46. #define MP2IF2_SW_RST 0xf9a4
  47. #define PADODPU 0xd827
  48. #define THIRDODPU 0xd828
  49. #define AGC_O_D 0xd829
  50. #define EP0_TX_EN 0xdd11
  51. #define EP0_TX_NAK 0xdd13
  52. #define EP4_TX_LEN_LSB 0xdd88
  53. #define EP4_TX_LEN_MSB 0xdd89
  54. #define EP4_MAX_PKT 0xdd0c
  55. #define EP5_TX_LEN_LSB 0xdd8a
  56. #define EP5_TX_LEN_MSB 0xdd8b
  57. #define EP5_MAX_PKT 0xdd0d
  58. #define IO_MUX_POWER_CLK 0xd800
  59. #define CLK_O_EN 0xd81a
  60. #define I2C_CLK 0xf103
  61. #define I2C_CLK_100 0x7
  62. #define I2C_CLK_400 0x1a
  63. #define D_TPSD_LOCK 0xf5a9
  64. #define MP2IF2_EN 0xf9a3
  65. #define MP2IF_SERIAL 0xf985
  66. #define TSIS_ENABLE 0xf9cd
  67. #define MP2IF2_HALF_PSB 0xf9a5
  68. #define MP2IF_STOP_EN 0xf9b5
  69. #define MPEG_FULL_SPEED 0xf990
  70. #define TOP_HOSTB_SER_MODE 0xd91c
  71. #define PID_RST 0xf992
  72. #define PID_EN 0xf993
  73. #define PID_INX_EN 0xf994
  74. #define PID_INX 0xf995
  75. #define PID_LSB 0xf996
  76. #define PID_MSB 0xf997
  77. #define MP2IF_MPEG_PAR_MODE 0xf986
  78. #define DCA_UPPER_CHIP 0xf731
  79. #define DCA_LOWER_CHIP 0xf732
  80. #define DCA_PLATCH 0xf730
  81. #define DCA_FPGA_LATCH 0xf778
  82. #define DCA_STAND_ALONE 0xf73c
  83. #define DCA_ENABLE 0xf776
  84. #define DVBT_INTEN 0xf41f
  85. #define DVBT_ENABLE 0xf41a
  86. #define HOSTB_DCA_LOWER 0xd91f
  87. #define HOSTB_MPEG_PAR_MODE 0xd91b
  88. #define HOSTB_MPEG_SER_MODE 0xd91c
  89. #define HOSTB_MPEG_SER_DO7 0xd91d
  90. #define HOSTB_DCA_UPPER 0xd91e
  91. #define PADMISCDR2 0xd830
  92. #define PADMISCDR4 0xd831
  93. #define PADMISCDR8 0xd832
  94. #define PADMISCDRSR 0xd833
  95. #define LOCK3_OUT 0xd8fd
  96. #define GPIOH1_O 0xd8af
  97. #define GPIOH1_EN 0xd8b0
  98. #define GPIOH1_ON 0xd8b1
  99. #define GPIOH3_O 0xd8b3
  100. #define GPIOH3_EN 0xd8b4
  101. #define GPIOH3_ON 0xd8b5
  102. #define GPIOH5_O 0xd8bb
  103. #define GPIOH5_EN 0xd8bc
  104. #define GPIOH5_ON 0xd8bd
  105. #define AFE_MEM0 0xfb24
  106. #define REG_TPSD_TX_MODE 0xf900
  107. #define REG_TPSD_GI 0xf901
  108. #define REG_TPSD_HIER 0xf902
  109. #define REG_TPSD_CONST 0xf903
  110. #define REG_BW 0xf904
  111. #define REG_PRIV 0xf905
  112. #define REG_TPSD_HP_CODE 0xf906
  113. #define REG_TPSD_LP_CODE 0xf907
  114. #define MP2IF_SYNC_LK 0xf999
  115. #define ADC_FREQ 0xf1cd
  116. #define TRIGGER_OFSM 0x0000
  117. /* COEFF Registers start at 0x0001 to 0x0020 */
  118. #define COEFF_1_2048 0x0001
  119. #define XTAL_CLK 0x0025
  120. #define BFS_FCW 0x0029
  121. #define TPSD_LOCK 0x003c
  122. #define TRAINING_MODE 0x0040
  123. #define ADC_X_2 0x0045
  124. #define TUNER_ID 0x0046
  125. #define EMPTY_CHANNEL_STATUS 0x0047
  126. #define SIGNAL_LEVEL 0x0048
  127. #define SIGNAL_QUALITY 0x0049
  128. #define EST_SIGNAL_LEVEL 0x004a
  129. #define FREE_BAND 0x004b
  130. #define SUSPEND_FLAG 0x004c
  131. /* Build in tuners */
  132. #define IT9137 0x38
  133. enum {
  134. CMD_DEMOD_READ = 0,
  135. CMD_DEMOD_WRITE,
  136. CMD_TUNER_READ,
  137. CMD_TUNER_WRITE,
  138. CMD_REG_EEPROM_READ,
  139. CMD_REG_EEPROM_WRITE,
  140. CMD_DATA_READ,
  141. CMD_VAR_READ = 8,
  142. CMD_VAR_WRITE,
  143. CMD_PLATFORM_GET,
  144. CMD_PLATFORM_SET,
  145. CMD_IP_CACHE,
  146. CMD_IP_ADD,
  147. CMD_IP_REMOVE,
  148. CMD_PID_ADD,
  149. CMD_PID_REMOVE,
  150. CMD_SIPSI_GET,
  151. CMD_SIPSI_MPE_RESET,
  152. CMD_H_PID_ADD = 0x15,
  153. CMD_H_PID_REMOVE,
  154. CMD_ABORT,
  155. CMD_IR_GET,
  156. CMD_IR_SET,
  157. CMD_FW_DOWNLOAD = 0x21,
  158. CMD_QUERYINFO,
  159. CMD_BOOT,
  160. CMD_FW_DOWNLOAD_BEGIN,
  161. CMD_FW_DOWNLOAD_END,
  162. CMD_RUN_CODE,
  163. CMD_SCATTER_READ = 0x28,
  164. CMD_SCATTER_WRITE,
  165. CMD_GENERIC_READ,
  166. CMD_GENERIC_WRITE
  167. };
  168. enum {
  169. READ_LONG,
  170. WRITE_LONG,
  171. READ_SHORT,
  172. WRITE_SHORT,
  173. READ_DATA,
  174. WRITE_DATA,
  175. WRITE_CMD,
  176. };
  177. #endif /* IT913X_FE_H */