hw.c 105 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/io.h>
  17. #include <asm/unaligned.h>
  18. #include "hw.h"
  19. #include "rc.h"
  20. #include "initvals.h"
  21. #define ATH9K_CLOCK_RATE_CCK 22
  22. #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
  23. #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
  24. static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  25. static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  26. static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  27. struct ar5416_eeprom_def *pEepData,
  28. u32 reg, u32 value);
  29. MODULE_AUTHOR("Atheros Communications");
  30. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  31. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  32. MODULE_LICENSE("Dual BSD/GPL");
  33. static int __init ath9k_init(void)
  34. {
  35. return 0;
  36. }
  37. module_init(ath9k_init);
  38. static void __exit ath9k_exit(void)
  39. {
  40. return;
  41. }
  42. module_exit(ath9k_exit);
  43. /********************/
  44. /* Helper Functions */
  45. /********************/
  46. static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  47. {
  48. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  49. if (!ah->curchan) /* should really check for CCK instead */
  50. return clks / ATH9K_CLOCK_RATE_CCK;
  51. if (conf->channel->band == IEEE80211_BAND_2GHZ)
  52. return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  53. return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54. }
  55. static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  56. {
  57. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  58. if (conf_is_ht40(conf))
  59. return ath9k_hw_mac_usec(ah, clks) / 2;
  60. else
  61. return ath9k_hw_mac_usec(ah, clks);
  62. }
  63. static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  64. {
  65. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  66. if (!ah->curchan) /* should really check for CCK instead */
  67. return usecs *ATH9K_CLOCK_RATE_CCK;
  68. if (conf->channel->band == IEEE80211_BAND_2GHZ)
  69. return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  70. return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  71. }
  72. static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  73. {
  74. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  75. if (conf_is_ht40(conf))
  76. return ath9k_hw_mac_clks(ah, usecs) * 2;
  77. else
  78. return ath9k_hw_mac_clks(ah, usecs);
  79. }
  80. bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  81. {
  82. int i;
  83. BUG_ON(timeout < AH_TIME_QUANTUM);
  84. for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  85. if ((REG_READ(ah, reg) & mask) == val)
  86. return true;
  87. udelay(AH_TIME_QUANTUM);
  88. }
  89. ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  90. "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  91. timeout, reg, REG_READ(ah, reg), mask, val);
  92. return false;
  93. }
  94. EXPORT_SYMBOL(ath9k_hw_wait);
  95. u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  96. {
  97. u32 retval;
  98. int i;
  99. for (i = 0, retval = 0; i < n; i++) {
  100. retval = (retval << 1) | (val & 1);
  101. val >>= 1;
  102. }
  103. return retval;
  104. }
  105. bool ath9k_get_channel_edges(struct ath_hw *ah,
  106. u16 flags, u16 *low,
  107. u16 *high)
  108. {
  109. struct ath9k_hw_capabilities *pCap = &ah->caps;
  110. if (flags & CHANNEL_5GHZ) {
  111. *low = pCap->low_5ghz_chan;
  112. *high = pCap->high_5ghz_chan;
  113. return true;
  114. }
  115. if ((flags & CHANNEL_2GHZ)) {
  116. *low = pCap->low_2ghz_chan;
  117. *high = pCap->high_2ghz_chan;
  118. return true;
  119. }
  120. return false;
  121. }
  122. u16 ath9k_hw_computetxtime(struct ath_hw *ah,
  123. u8 phy, int kbps,
  124. u32 frameLen, u16 rateix,
  125. bool shortPreamble)
  126. {
  127. u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
  128. if (kbps == 0)
  129. return 0;
  130. switch (phy) {
  131. case WLAN_RC_PHY_CCK:
  132. phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
  133. if (shortPreamble)
  134. phyTime >>= 1;
  135. numBits = frameLen << 3;
  136. txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
  137. break;
  138. case WLAN_RC_PHY_OFDM:
  139. if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
  140. bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
  141. numBits = OFDM_PLCP_BITS + (frameLen << 3);
  142. numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
  143. txTime = OFDM_SIFS_TIME_QUARTER
  144. + OFDM_PREAMBLE_TIME_QUARTER
  145. + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
  146. } else if (ah->curchan &&
  147. IS_CHAN_HALF_RATE(ah->curchan)) {
  148. bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
  149. numBits = OFDM_PLCP_BITS + (frameLen << 3);
  150. numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
  151. txTime = OFDM_SIFS_TIME_HALF +
  152. OFDM_PREAMBLE_TIME_HALF
  153. + (numSymbols * OFDM_SYMBOL_TIME_HALF);
  154. } else {
  155. bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
  156. numBits = OFDM_PLCP_BITS + (frameLen << 3);
  157. numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
  158. txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
  159. + (numSymbols * OFDM_SYMBOL_TIME);
  160. }
  161. break;
  162. default:
  163. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  164. "Unknown phy %u (rate ix %u)\n", phy, rateix);
  165. txTime = 0;
  166. break;
  167. }
  168. return txTime;
  169. }
  170. EXPORT_SYMBOL(ath9k_hw_computetxtime);
  171. void ath9k_hw_get_channel_centers(struct ath_hw *ah,
  172. struct ath9k_channel *chan,
  173. struct chan_centers *centers)
  174. {
  175. int8_t extoff;
  176. if (!IS_CHAN_HT40(chan)) {
  177. centers->ctl_center = centers->ext_center =
  178. centers->synth_center = chan->channel;
  179. return;
  180. }
  181. if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
  182. (chan->chanmode == CHANNEL_G_HT40PLUS)) {
  183. centers->synth_center =
  184. chan->channel + HT40_CHANNEL_CENTER_SHIFT;
  185. extoff = 1;
  186. } else {
  187. centers->synth_center =
  188. chan->channel - HT40_CHANNEL_CENTER_SHIFT;
  189. extoff = -1;
  190. }
  191. centers->ctl_center =
  192. centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
  193. /* 25 MHz spacing is supported by hw but not on upper layers */
  194. centers->ext_center =
  195. centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
  196. }
  197. /******************/
  198. /* Chip Revisions */
  199. /******************/
  200. static void ath9k_hw_read_revisions(struct ath_hw *ah)
  201. {
  202. u32 val;
  203. val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
  204. if (val == 0xFF) {
  205. val = REG_READ(ah, AR_SREV);
  206. ah->hw_version.macVersion =
  207. (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
  208. ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
  209. ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
  210. } else {
  211. if (!AR_SREV_9100(ah))
  212. ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
  213. ah->hw_version.macRev = val & AR_SREV_REVISION;
  214. if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
  215. ah->is_pciexpress = true;
  216. }
  217. }
  218. static int ath9k_hw_get_radiorev(struct ath_hw *ah)
  219. {
  220. u32 val;
  221. int i;
  222. REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
  223. for (i = 0; i < 8; i++)
  224. REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
  225. val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
  226. val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
  227. return ath9k_hw_reverse_bits(val, 8);
  228. }
  229. /************************************/
  230. /* HW Attach, Detach, Init Routines */
  231. /************************************/
  232. static void ath9k_hw_disablepcie(struct ath_hw *ah)
  233. {
  234. if (AR_SREV_9100(ah))
  235. return;
  236. REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
  237. REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
  238. REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
  239. REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
  240. REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
  241. REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
  242. REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
  243. REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
  244. REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
  245. REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
  246. }
  247. static bool ath9k_hw_chip_test(struct ath_hw *ah)
  248. {
  249. struct ath_common *common = ath9k_hw_common(ah);
  250. u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
  251. u32 regHold[2];
  252. u32 patternData[4] = { 0x55555555,
  253. 0xaaaaaaaa,
  254. 0x66666666,
  255. 0x99999999 };
  256. int i, j;
  257. for (i = 0; i < 2; i++) {
  258. u32 addr = regAddr[i];
  259. u32 wrData, rdData;
  260. regHold[i] = REG_READ(ah, addr);
  261. for (j = 0; j < 0x100; j++) {
  262. wrData = (j << 16) | j;
  263. REG_WRITE(ah, addr, wrData);
  264. rdData = REG_READ(ah, addr);
  265. if (rdData != wrData) {
  266. ath_print(common, ATH_DBG_FATAL,
  267. "address test failed "
  268. "addr: 0x%08x - wr:0x%08x != "
  269. "rd:0x%08x\n",
  270. addr, wrData, rdData);
  271. return false;
  272. }
  273. }
  274. for (j = 0; j < 4; j++) {
  275. wrData = patternData[j];
  276. REG_WRITE(ah, addr, wrData);
  277. rdData = REG_READ(ah, addr);
  278. if (wrData != rdData) {
  279. ath_print(common, ATH_DBG_FATAL,
  280. "address test failed "
  281. "addr: 0x%08x - wr:0x%08x != "
  282. "rd:0x%08x\n",
  283. addr, wrData, rdData);
  284. return false;
  285. }
  286. }
  287. REG_WRITE(ah, regAddr[i], regHold[i]);
  288. }
  289. udelay(100);
  290. return true;
  291. }
  292. static const char *ath9k_hw_devname(u16 devid)
  293. {
  294. switch (devid) {
  295. case AR5416_DEVID_PCI:
  296. return "Atheros 5416";
  297. case AR5416_DEVID_PCIE:
  298. return "Atheros 5418";
  299. case AR9160_DEVID_PCI:
  300. return "Atheros 9160";
  301. case AR5416_AR9100_DEVID:
  302. return "Atheros 9100";
  303. case AR9280_DEVID_PCI:
  304. case AR9280_DEVID_PCIE:
  305. return "Atheros 9280";
  306. case AR9285_DEVID_PCIE:
  307. return "Atheros 9285";
  308. case AR5416_DEVID_AR9287_PCI:
  309. case AR5416_DEVID_AR9287_PCIE:
  310. return "Atheros 9287";
  311. }
  312. return NULL;
  313. }
  314. static void ath9k_hw_init_config(struct ath_hw *ah)
  315. {
  316. int i;
  317. ah->config.dma_beacon_response_time = 2;
  318. ah->config.sw_beacon_response_time = 10;
  319. ah->config.additional_swba_backoff = 0;
  320. ah->config.ack_6mb = 0x0;
  321. ah->config.cwm_ignore_extcca = 0;
  322. ah->config.pcie_powersave_enable = 0;
  323. ah->config.pcie_clock_req = 0;
  324. ah->config.pcie_waen = 0;
  325. ah->config.analog_shiftreg = 1;
  326. ah->config.ht_enable = 1;
  327. ah->config.ofdm_trig_low = 200;
  328. ah->config.ofdm_trig_high = 500;
  329. ah->config.cck_trig_high = 200;
  330. ah->config.cck_trig_low = 100;
  331. ah->config.enable_ani = 1;
  332. for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
  333. ah->config.spurchans[i][0] = AR_NO_SPUR;
  334. ah->config.spurchans[i][1] = AR_NO_SPUR;
  335. }
  336. ah->config.intr_mitigation = true;
  337. /*
  338. * We need this for PCI devices only (Cardbus, PCI, miniPCI)
  339. * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
  340. * This means we use it for all AR5416 devices, and the few
  341. * minor PCI AR9280 devices out there.
  342. *
  343. * Serialization is required because these devices do not handle
  344. * well the case of two concurrent reads/writes due to the latency
  345. * involved. During one read/write another read/write can be issued
  346. * on another CPU while the previous read/write may still be working
  347. * on our hardware, if we hit this case the hardware poops in a loop.
  348. * We prevent this by serializing reads and writes.
  349. *
  350. * This issue is not present on PCI-Express devices or pre-AR5416
  351. * devices (legacy, 802.11abg).
  352. */
  353. if (num_possible_cpus() > 1)
  354. ah->config.serialize_regmode = SER_REG_MODE_AUTO;
  355. }
  356. EXPORT_SYMBOL(ath9k_hw_init);
  357. static void ath9k_hw_init_defaults(struct ath_hw *ah)
  358. {
  359. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  360. regulatory->country_code = CTRY_DEFAULT;
  361. regulatory->power_limit = MAX_RATE_POWER;
  362. regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
  363. ah->hw_version.magic = AR5416_MAGIC;
  364. ah->hw_version.subvendorid = 0;
  365. ah->ah_flags = 0;
  366. if (ah->hw_version.devid == AR5416_AR9100_DEVID)
  367. ah->hw_version.macVersion = AR_SREV_VERSION_9100;
  368. if (!AR_SREV_9100(ah))
  369. ah->ah_flags = AH_USE_EEPROM;
  370. ah->atim_window = 0;
  371. ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
  372. ah->beacon_interval = 100;
  373. ah->enable_32kHz_clock = DONT_USE_32KHZ;
  374. ah->slottime = (u32) -1;
  375. ah->acktimeout = (u32) -1;
  376. ah->ctstimeout = (u32) -1;
  377. ah->globaltxtimeout = (u32) -1;
  378. ah->power_mode = ATH9K_PM_UNDEFINED;
  379. }
  380. static int ath9k_hw_rf_claim(struct ath_hw *ah)
  381. {
  382. u32 val;
  383. REG_WRITE(ah, AR_PHY(0), 0x00000007);
  384. val = ath9k_hw_get_radiorev(ah);
  385. switch (val & AR_RADIO_SREV_MAJOR) {
  386. case 0:
  387. val = AR_RAD5133_SREV_MAJOR;
  388. break;
  389. case AR_RAD5133_SREV_MAJOR:
  390. case AR_RAD5122_SREV_MAJOR:
  391. case AR_RAD2133_SREV_MAJOR:
  392. case AR_RAD2122_SREV_MAJOR:
  393. break;
  394. default:
  395. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  396. "Radio Chip Rev 0x%02X not supported\n",
  397. val & AR_RADIO_SREV_MAJOR);
  398. return -EOPNOTSUPP;
  399. }
  400. ah->hw_version.analog5GhzRev = val;
  401. return 0;
  402. }
  403. static int ath9k_hw_init_macaddr(struct ath_hw *ah)
  404. {
  405. struct ath_common *common = ath9k_hw_common(ah);
  406. u32 sum;
  407. int i;
  408. u16 eeval;
  409. sum = 0;
  410. for (i = 0; i < 3; i++) {
  411. eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
  412. sum += eeval;
  413. common->macaddr[2 * i] = eeval >> 8;
  414. common->macaddr[2 * i + 1] = eeval & 0xff;
  415. }
  416. if (sum == 0 || sum == 0xffff * 3)
  417. return -EADDRNOTAVAIL;
  418. return 0;
  419. }
  420. static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
  421. {
  422. u32 rxgain_type;
  423. if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
  424. rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
  425. if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
  426. INIT_INI_ARRAY(&ah->iniModesRxGain,
  427. ar9280Modes_backoff_13db_rxgain_9280_2,
  428. ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
  429. else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
  430. INIT_INI_ARRAY(&ah->iniModesRxGain,
  431. ar9280Modes_backoff_23db_rxgain_9280_2,
  432. ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
  433. else
  434. INIT_INI_ARRAY(&ah->iniModesRxGain,
  435. ar9280Modes_original_rxgain_9280_2,
  436. ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
  437. } else {
  438. INIT_INI_ARRAY(&ah->iniModesRxGain,
  439. ar9280Modes_original_rxgain_9280_2,
  440. ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
  441. }
  442. }
  443. static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
  444. {
  445. u32 txgain_type;
  446. if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
  447. txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
  448. if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
  449. INIT_INI_ARRAY(&ah->iniModesTxGain,
  450. ar9280Modes_high_power_tx_gain_9280_2,
  451. ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
  452. else
  453. INIT_INI_ARRAY(&ah->iniModesTxGain,
  454. ar9280Modes_original_tx_gain_9280_2,
  455. ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
  456. } else {
  457. INIT_INI_ARRAY(&ah->iniModesTxGain,
  458. ar9280Modes_original_tx_gain_9280_2,
  459. ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
  460. }
  461. }
  462. static int ath9k_hw_post_init(struct ath_hw *ah)
  463. {
  464. int ecode;
  465. if (!ath9k_hw_chip_test(ah))
  466. return -ENODEV;
  467. ecode = ath9k_hw_rf_claim(ah);
  468. if (ecode != 0)
  469. return ecode;
  470. ecode = ath9k_hw_eeprom_init(ah);
  471. if (ecode != 0)
  472. return ecode;
  473. ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
  474. "Eeprom VER: %d, REV: %d\n",
  475. ah->eep_ops->get_eeprom_ver(ah),
  476. ah->eep_ops->get_eeprom_rev(ah));
  477. if (!AR_SREV_9280_10_OR_LATER(ah)) {
  478. ecode = ath9k_hw_rf_alloc_ext_banks(ah);
  479. if (ecode) {
  480. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  481. "Failed allocating banks for "
  482. "external radio\n");
  483. return ecode;
  484. }
  485. }
  486. if (!AR_SREV_9100(ah)) {
  487. ath9k_hw_ani_setup(ah);
  488. ath9k_hw_ani_init(ah);
  489. }
  490. return 0;
  491. }
  492. static bool ath9k_hw_devid_supported(u16 devid)
  493. {
  494. switch (devid) {
  495. case AR5416_DEVID_PCI:
  496. case AR5416_DEVID_PCIE:
  497. case AR5416_AR9100_DEVID:
  498. case AR9160_DEVID_PCI:
  499. case AR9280_DEVID_PCI:
  500. case AR9280_DEVID_PCIE:
  501. case AR9285_DEVID_PCIE:
  502. case AR5416_DEVID_AR9287_PCI:
  503. case AR5416_DEVID_AR9287_PCIE:
  504. case AR9271_USB:
  505. return true;
  506. default:
  507. break;
  508. }
  509. return false;
  510. }
  511. static bool ath9k_hw_macversion_supported(u32 macversion)
  512. {
  513. switch (macversion) {
  514. case AR_SREV_VERSION_5416_PCI:
  515. case AR_SREV_VERSION_5416_PCIE:
  516. case AR_SREV_VERSION_9160:
  517. case AR_SREV_VERSION_9100:
  518. case AR_SREV_VERSION_9280:
  519. case AR_SREV_VERSION_9285:
  520. case AR_SREV_VERSION_9287:
  521. case AR_SREV_VERSION_9271:
  522. return true;
  523. default:
  524. break;
  525. }
  526. return false;
  527. }
  528. static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  529. {
  530. if (AR_SREV_9160_10_OR_LATER(ah)) {
  531. if (AR_SREV_9280_10_OR_LATER(ah)) {
  532. ah->iq_caldata.calData = &iq_cal_single_sample;
  533. ah->adcgain_caldata.calData =
  534. &adc_gain_cal_single_sample;
  535. ah->adcdc_caldata.calData =
  536. &adc_dc_cal_single_sample;
  537. ah->adcdc_calinitdata.calData =
  538. &adc_init_dc_cal;
  539. } else {
  540. ah->iq_caldata.calData = &iq_cal_multi_sample;
  541. ah->adcgain_caldata.calData =
  542. &adc_gain_cal_multi_sample;
  543. ah->adcdc_caldata.calData =
  544. &adc_dc_cal_multi_sample;
  545. ah->adcdc_calinitdata.calData =
  546. &adc_init_dc_cal;
  547. }
  548. ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
  549. }
  550. }
  551. static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  552. {
  553. if (AR_SREV_9271(ah)) {
  554. INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
  555. ARRAY_SIZE(ar9271Modes_9271), 6);
  556. INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
  557. ARRAY_SIZE(ar9271Common_9271), 2);
  558. INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
  559. ar9271Modes_9271_1_0_only,
  560. ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
  561. return;
  562. }
  563. if (AR_SREV_9287_11_OR_LATER(ah)) {
  564. INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
  565. ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
  566. INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
  567. ARRAY_SIZE(ar9287Common_9287_1_1), 2);
  568. if (ah->config.pcie_clock_req)
  569. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  570. ar9287PciePhy_clkreq_off_L1_9287_1_1,
  571. ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
  572. else
  573. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  574. ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
  575. ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
  576. 2);
  577. } else if (AR_SREV_9287_10_OR_LATER(ah)) {
  578. INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
  579. ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
  580. INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
  581. ARRAY_SIZE(ar9287Common_9287_1_0), 2);
  582. if (ah->config.pcie_clock_req)
  583. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  584. ar9287PciePhy_clkreq_off_L1_9287_1_0,
  585. ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
  586. else
  587. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  588. ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
  589. ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
  590. 2);
  591. } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  592. INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
  593. ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
  594. INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
  595. ARRAY_SIZE(ar9285Common_9285_1_2), 2);
  596. if (ah->config.pcie_clock_req) {
  597. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  598. ar9285PciePhy_clkreq_off_L1_9285_1_2,
  599. ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
  600. } else {
  601. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  602. ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
  603. ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
  604. 2);
  605. }
  606. } else if (AR_SREV_9285_10_OR_LATER(ah)) {
  607. INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
  608. ARRAY_SIZE(ar9285Modes_9285), 6);
  609. INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
  610. ARRAY_SIZE(ar9285Common_9285), 2);
  611. if (ah->config.pcie_clock_req) {
  612. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  613. ar9285PciePhy_clkreq_off_L1_9285,
  614. ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
  615. } else {
  616. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  617. ar9285PciePhy_clkreq_always_on_L1_9285,
  618. ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
  619. }
  620. } else if (AR_SREV_9280_20_OR_LATER(ah)) {
  621. INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
  622. ARRAY_SIZE(ar9280Modes_9280_2), 6);
  623. INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
  624. ARRAY_SIZE(ar9280Common_9280_2), 2);
  625. if (ah->config.pcie_clock_req) {
  626. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  627. ar9280PciePhy_clkreq_off_L1_9280,
  628. ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
  629. } else {
  630. INIT_INI_ARRAY(&ah->iniPcieSerdes,
  631. ar9280PciePhy_clkreq_always_on_L1_9280,
  632. ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
  633. }
  634. INIT_INI_ARRAY(&ah->iniModesAdditional,
  635. ar9280Modes_fast_clock_9280_2,
  636. ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
  637. } else if (AR_SREV_9280_10_OR_LATER(ah)) {
  638. INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
  639. ARRAY_SIZE(ar9280Modes_9280), 6);
  640. INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
  641. ARRAY_SIZE(ar9280Common_9280), 2);
  642. } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  643. INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
  644. ARRAY_SIZE(ar5416Modes_9160), 6);
  645. INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
  646. ARRAY_SIZE(ar5416Common_9160), 2);
  647. INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
  648. ARRAY_SIZE(ar5416Bank0_9160), 2);
  649. INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
  650. ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
  651. INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
  652. ARRAY_SIZE(ar5416Bank1_9160), 2);
  653. INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
  654. ARRAY_SIZE(ar5416Bank2_9160), 2);
  655. INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
  656. ARRAY_SIZE(ar5416Bank3_9160), 3);
  657. INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
  658. ARRAY_SIZE(ar5416Bank6_9160), 3);
  659. INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
  660. ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
  661. INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
  662. ARRAY_SIZE(ar5416Bank7_9160), 2);
  663. if (AR_SREV_9160_11(ah)) {
  664. INIT_INI_ARRAY(&ah->iniAddac,
  665. ar5416Addac_91601_1,
  666. ARRAY_SIZE(ar5416Addac_91601_1), 2);
  667. } else {
  668. INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
  669. ARRAY_SIZE(ar5416Addac_9160), 2);
  670. }
  671. } else if (AR_SREV_9100_OR_LATER(ah)) {
  672. INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
  673. ARRAY_SIZE(ar5416Modes_9100), 6);
  674. INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
  675. ARRAY_SIZE(ar5416Common_9100), 2);
  676. INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
  677. ARRAY_SIZE(ar5416Bank0_9100), 2);
  678. INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
  679. ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
  680. INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
  681. ARRAY_SIZE(ar5416Bank1_9100), 2);
  682. INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
  683. ARRAY_SIZE(ar5416Bank2_9100), 2);
  684. INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
  685. ARRAY_SIZE(ar5416Bank3_9100), 3);
  686. INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
  687. ARRAY_SIZE(ar5416Bank6_9100), 3);
  688. INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
  689. ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
  690. INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
  691. ARRAY_SIZE(ar5416Bank7_9100), 2);
  692. INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
  693. ARRAY_SIZE(ar5416Addac_9100), 2);
  694. } else {
  695. INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
  696. ARRAY_SIZE(ar5416Modes), 6);
  697. INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
  698. ARRAY_SIZE(ar5416Common), 2);
  699. INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
  700. ARRAY_SIZE(ar5416Bank0), 2);
  701. INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
  702. ARRAY_SIZE(ar5416BB_RfGain), 3);
  703. INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
  704. ARRAY_SIZE(ar5416Bank1), 2);
  705. INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
  706. ARRAY_SIZE(ar5416Bank2), 2);
  707. INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
  708. ARRAY_SIZE(ar5416Bank3), 3);
  709. INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
  710. ARRAY_SIZE(ar5416Bank6), 3);
  711. INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
  712. ARRAY_SIZE(ar5416Bank6TPC), 3);
  713. INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
  714. ARRAY_SIZE(ar5416Bank7), 2);
  715. INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
  716. ARRAY_SIZE(ar5416Addac), 2);
  717. }
  718. }
  719. static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  720. {
  721. if (AR_SREV_9287_11_OR_LATER(ah))
  722. INIT_INI_ARRAY(&ah->iniModesRxGain,
  723. ar9287Modes_rx_gain_9287_1_1,
  724. ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
  725. else if (AR_SREV_9287_10(ah))
  726. INIT_INI_ARRAY(&ah->iniModesRxGain,
  727. ar9287Modes_rx_gain_9287_1_0,
  728. ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
  729. else if (AR_SREV_9280_20(ah))
  730. ath9k_hw_init_rxgain_ini(ah);
  731. if (AR_SREV_9287_11_OR_LATER(ah)) {
  732. INIT_INI_ARRAY(&ah->iniModesTxGain,
  733. ar9287Modes_tx_gain_9287_1_1,
  734. ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
  735. } else if (AR_SREV_9287_10(ah)) {
  736. INIT_INI_ARRAY(&ah->iniModesTxGain,
  737. ar9287Modes_tx_gain_9287_1_0,
  738. ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
  739. } else if (AR_SREV_9280_20(ah)) {
  740. ath9k_hw_init_txgain_ini(ah);
  741. } else if (AR_SREV_9285_12_OR_LATER(ah)) {
  742. u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
  743. /* txgain table */
  744. if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
  745. INIT_INI_ARRAY(&ah->iniModesTxGain,
  746. ar9285Modes_high_power_tx_gain_9285_1_2,
  747. ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
  748. } else {
  749. INIT_INI_ARRAY(&ah->iniModesTxGain,
  750. ar9285Modes_original_tx_gain_9285_1_2,
  751. ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
  752. }
  753. }
  754. }
  755. static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
  756. {
  757. u32 i, j;
  758. if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
  759. test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
  760. /* EEPROM Fixup */
  761. for (i = 0; i < ah->iniModes.ia_rows; i++) {
  762. u32 reg = INI_RA(&ah->iniModes, i, 0);
  763. for (j = 1; j < ah->iniModes.ia_columns; j++) {
  764. u32 val = INI_RA(&ah->iniModes, i, j);
  765. INI_RA(&ah->iniModes, i, j) =
  766. ath9k_hw_ini_fixup(ah,
  767. &ah->eeprom.def,
  768. reg, val);
  769. }
  770. }
  771. }
  772. }
  773. int ath9k_hw_init(struct ath_hw *ah)
  774. {
  775. struct ath_common *common = ath9k_hw_common(ah);
  776. int r = 0;
  777. if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
  778. ath_print(common, ATH_DBG_FATAL,
  779. "Unsupported device ID: 0x%0x\n",
  780. ah->hw_version.devid);
  781. return -EOPNOTSUPP;
  782. }
  783. ath9k_hw_init_defaults(ah);
  784. ath9k_hw_init_config(ah);
  785. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
  786. ath_print(common, ATH_DBG_FATAL,
  787. "Couldn't reset chip\n");
  788. return -EIO;
  789. }
  790. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
  791. ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
  792. return -EIO;
  793. }
  794. if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
  795. if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
  796. (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
  797. ah->config.serialize_regmode =
  798. SER_REG_MODE_ON;
  799. } else {
  800. ah->config.serialize_regmode =
  801. SER_REG_MODE_OFF;
  802. }
  803. }
  804. ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
  805. ah->config.serialize_regmode);
  806. if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
  807. ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
  808. else
  809. ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
  810. if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
  811. ath_print(common, ATH_DBG_FATAL,
  812. "Mac Chip Rev 0x%02x.%x is not supported by "
  813. "this driver\n", ah->hw_version.macVersion,
  814. ah->hw_version.macRev);
  815. return -EOPNOTSUPP;
  816. }
  817. if (AR_SREV_9100(ah)) {
  818. ah->iq_caldata.calData = &iq_cal_multi_sample;
  819. ah->supp_cals = IQ_MISMATCH_CAL;
  820. ah->is_pciexpress = false;
  821. }
  822. if (AR_SREV_9271(ah))
  823. ah->is_pciexpress = false;
  824. ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
  825. ath9k_hw_init_cal_settings(ah);
  826. ah->ani_function = ATH9K_ANI_ALL;
  827. if (AR_SREV_9280_10_OR_LATER(ah)) {
  828. ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
  829. ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
  830. ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
  831. } else {
  832. ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
  833. ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
  834. }
  835. ath9k_hw_init_mode_regs(ah);
  836. if (ah->is_pciexpress)
  837. ath9k_hw_configpcipowersave(ah, 0, 0);
  838. else
  839. ath9k_hw_disablepcie(ah);
  840. /* Support for Japan ch.14 (2484) spread */
  841. if (AR_SREV_9287_11_OR_LATER(ah)) {
  842. INIT_INI_ARRAY(&ah->iniCckfirNormal,
  843. ar9287Common_normal_cck_fir_coeff_92871_1,
  844. ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
  845. INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  846. ar9287Common_japan_2484_cck_fir_coeff_92871_1,
  847. ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
  848. }
  849. r = ath9k_hw_post_init(ah);
  850. if (r)
  851. return r;
  852. ath9k_hw_init_mode_gain_regs(ah);
  853. r = ath9k_hw_fill_cap_info(ah);
  854. if (r)
  855. return r;
  856. ath9k_hw_init_11a_eeprom_fix(ah);
  857. r = ath9k_hw_init_macaddr(ah);
  858. if (r) {
  859. ath_print(common, ATH_DBG_FATAL,
  860. "Failed to initialize MAC address\n");
  861. return r;
  862. }
  863. if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
  864. ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
  865. else
  866. ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
  867. ath9k_init_nfcal_hist_buffer(ah);
  868. common->state = ATH_HW_INITIALIZED;
  869. return 0;
  870. }
  871. static void ath9k_hw_init_bb(struct ath_hw *ah,
  872. struct ath9k_channel *chan)
  873. {
  874. u32 synthDelay;
  875. synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
  876. if (IS_CHAN_B(chan))
  877. synthDelay = (4 * synthDelay) / 22;
  878. else
  879. synthDelay /= 10;
  880. REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
  881. udelay(synthDelay + BASE_ACTIVATE_DELAY);
  882. }
  883. static void ath9k_hw_init_qos(struct ath_hw *ah)
  884. {
  885. REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
  886. REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
  887. REG_WRITE(ah, AR_QOS_NO_ACK,
  888. SM(2, AR_QOS_NO_ACK_TWO_BIT) |
  889. SM(5, AR_QOS_NO_ACK_BIT_OFF) |
  890. SM(0, AR_QOS_NO_ACK_BYTE_OFF));
  891. REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
  892. REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
  893. REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
  894. REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
  895. REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
  896. }
  897. static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
  898. {
  899. u32 lcr;
  900. u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
  901. lcr = REG_READ(ah , 0x5100c);
  902. lcr |= 0x80;
  903. REG_WRITE(ah, 0x5100c, lcr);
  904. REG_WRITE(ah, 0x51004, (baud_divider >> 8));
  905. REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
  906. lcr &= ~0x80;
  907. REG_WRITE(ah, 0x5100c, lcr);
  908. }
  909. static void ath9k_hw_init_pll(struct ath_hw *ah,
  910. struct ath9k_channel *chan)
  911. {
  912. u32 pll;
  913. if (AR_SREV_9100(ah)) {
  914. if (chan && IS_CHAN_5GHZ(chan))
  915. pll = 0x1450;
  916. else
  917. pll = 0x1458;
  918. } else {
  919. if (AR_SREV_9280_10_OR_LATER(ah)) {
  920. pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
  921. if (chan && IS_CHAN_HALF_RATE(chan))
  922. pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
  923. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  924. pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
  925. if (chan && IS_CHAN_5GHZ(chan)) {
  926. pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
  927. if (AR_SREV_9280_20(ah)) {
  928. if (((chan->channel % 20) == 0)
  929. || ((chan->channel % 10) == 0))
  930. pll = 0x2850;
  931. else
  932. pll = 0x142c;
  933. }
  934. } else {
  935. pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
  936. }
  937. } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  938. pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
  939. if (chan && IS_CHAN_HALF_RATE(chan))
  940. pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
  941. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  942. pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
  943. if (chan && IS_CHAN_5GHZ(chan))
  944. pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
  945. else
  946. pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
  947. } else {
  948. pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
  949. if (chan && IS_CHAN_HALF_RATE(chan))
  950. pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
  951. else if (chan && IS_CHAN_QUARTER_RATE(chan))
  952. pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
  953. if (chan && IS_CHAN_5GHZ(chan))
  954. pll |= SM(0xa, AR_RTC_PLL_DIV);
  955. else
  956. pll |= SM(0xb, AR_RTC_PLL_DIV);
  957. }
  958. }
  959. REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
  960. /* Switch the core clock for ar9271 to 117Mhz */
  961. if (AR_SREV_9271(ah)) {
  962. if ((pll == 0x142c) || (pll == 0x2850) ) {
  963. udelay(500);
  964. /* set CLKOBS to output AHB clock */
  965. REG_WRITE(ah, 0x7020, 0xe);
  966. /*
  967. * 0x304: 117Mhz, ahb_ratio: 1x1
  968. * 0x306: 40Mhz, ahb_ratio: 1x1
  969. */
  970. REG_WRITE(ah, 0x50040, 0x304);
  971. /*
  972. * makes adjustments for the baud dividor to keep the
  973. * targetted baud rate based on the used core clock.
  974. */
  975. ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
  976. AR9271_TARGET_BAUD_RATE);
  977. }
  978. }
  979. udelay(RTC_PLL_SETTLE_DELAY);
  980. REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
  981. }
  982. static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
  983. {
  984. int rx_chainmask, tx_chainmask;
  985. rx_chainmask = ah->rxchainmask;
  986. tx_chainmask = ah->txchainmask;
  987. switch (rx_chainmask) {
  988. case 0x5:
  989. REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
  990. AR_PHY_SWAP_ALT_CHAIN);
  991. case 0x3:
  992. if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
  993. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
  994. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
  995. break;
  996. }
  997. case 0x1:
  998. case 0x2:
  999. case 0x7:
  1000. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
  1001. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
  1002. break;
  1003. default:
  1004. break;
  1005. }
  1006. REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
  1007. if (tx_chainmask == 0x5) {
  1008. REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
  1009. AR_PHY_SWAP_ALT_CHAIN);
  1010. }
  1011. if (AR_SREV_9100(ah))
  1012. REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
  1013. REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
  1014. }
  1015. static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
  1016. enum nl80211_iftype opmode)
  1017. {
  1018. ah->mask_reg = AR_IMR_TXERR |
  1019. AR_IMR_TXURN |
  1020. AR_IMR_RXERR |
  1021. AR_IMR_RXORN |
  1022. AR_IMR_BCNMISC;
  1023. if (ah->config.intr_mitigation)
  1024. ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
  1025. else
  1026. ah->mask_reg |= AR_IMR_RXOK;
  1027. ah->mask_reg |= AR_IMR_TXOK;
  1028. if (opmode == NL80211_IFTYPE_AP)
  1029. ah->mask_reg |= AR_IMR_MIB;
  1030. REG_WRITE(ah, AR_IMR, ah->mask_reg);
  1031. REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
  1032. if (!AR_SREV_9100(ah)) {
  1033. REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
  1034. REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
  1035. REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
  1036. }
  1037. }
  1038. static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
  1039. {
  1040. if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
  1041. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
  1042. "bad ack timeout %u\n", us);
  1043. ah->acktimeout = (u32) -1;
  1044. return false;
  1045. } else {
  1046. REG_RMW_FIELD(ah, AR_TIME_OUT,
  1047. AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
  1048. ah->acktimeout = us;
  1049. return true;
  1050. }
  1051. }
  1052. static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
  1053. {
  1054. if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
  1055. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
  1056. "bad cts timeout %u\n", us);
  1057. ah->ctstimeout = (u32) -1;
  1058. return false;
  1059. } else {
  1060. REG_RMW_FIELD(ah, AR_TIME_OUT,
  1061. AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
  1062. ah->ctstimeout = us;
  1063. return true;
  1064. }
  1065. }
  1066. static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
  1067. {
  1068. if (tu > 0xFFFF) {
  1069. ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
  1070. "bad global tx timeout %u\n", tu);
  1071. ah->globaltxtimeout = (u32) -1;
  1072. return false;
  1073. } else {
  1074. REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
  1075. ah->globaltxtimeout = tu;
  1076. return true;
  1077. }
  1078. }
  1079. static void ath9k_hw_init_user_settings(struct ath_hw *ah)
  1080. {
  1081. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
  1082. ah->misc_mode);
  1083. if (ah->misc_mode != 0)
  1084. REG_WRITE(ah, AR_PCU_MISC,
  1085. REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
  1086. if (ah->slottime != (u32) -1)
  1087. ath9k_hw_setslottime(ah, ah->slottime);
  1088. if (ah->acktimeout != (u32) -1)
  1089. ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
  1090. if (ah->ctstimeout != (u32) -1)
  1091. ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
  1092. if (ah->globaltxtimeout != (u32) -1)
  1093. ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
  1094. }
  1095. const char *ath9k_hw_probe(u16 vendorid, u16 devid)
  1096. {
  1097. return vendorid == ATHEROS_VENDOR_ID ?
  1098. ath9k_hw_devname(devid) : NULL;
  1099. }
  1100. void ath9k_hw_detach(struct ath_hw *ah)
  1101. {
  1102. struct ath_common *common = ath9k_hw_common(ah);
  1103. if (common->state <= ATH_HW_INITIALIZED)
  1104. goto free_hw;
  1105. if (!AR_SREV_9100(ah))
  1106. ath9k_hw_ani_disable(ah);
  1107. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  1108. free_hw:
  1109. if (!AR_SREV_9280_10_OR_LATER(ah))
  1110. ath9k_hw_rf_free_ext_banks(ah);
  1111. kfree(ah);
  1112. ah = NULL;
  1113. }
  1114. EXPORT_SYMBOL(ath9k_hw_detach);
  1115. /*******/
  1116. /* INI */
  1117. /*******/
  1118. static void ath9k_hw_override_ini(struct ath_hw *ah,
  1119. struct ath9k_channel *chan)
  1120. {
  1121. u32 val;
  1122. if (AR_SREV_9271(ah)) {
  1123. /*
  1124. * Enable spectral scan to solution for issues with stuck
  1125. * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
  1126. * AR9271 1.1
  1127. */
  1128. if (AR_SREV_9271_10(ah)) {
  1129. val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
  1130. AR_PHY_SPECTRAL_SCAN_ENABLE;
  1131. REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
  1132. }
  1133. else if (AR_SREV_9271_11(ah))
  1134. /*
  1135. * change AR_PHY_RF_CTL3 setting to fix MAC issue
  1136. * present on AR9271 1.1
  1137. */
  1138. REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
  1139. return;
  1140. }
  1141. /*
  1142. * Set the RX_ABORT and RX_DIS and clear if off only after
  1143. * RXE is set for MAC. This prevents frames with corrupted
  1144. * descriptor status.
  1145. */
  1146. REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
  1147. if (AR_SREV_9280_10_OR_LATER(ah)) {
  1148. val = REG_READ(ah, AR_PCU_MISC_MODE2) &
  1149. (~AR_PCU_MISC_MODE2_HWWAR1);
  1150. if (AR_SREV_9287_10_OR_LATER(ah))
  1151. val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
  1152. REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
  1153. }
  1154. if (!AR_SREV_5416_20_OR_LATER(ah) ||
  1155. AR_SREV_9280_10_OR_LATER(ah))
  1156. return;
  1157. /*
  1158. * Disable BB clock gating
  1159. * Necessary to avoid issues on AR5416 2.0
  1160. */
  1161. REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
  1162. }
  1163. static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
  1164. struct ar5416_eeprom_def *pEepData,
  1165. u32 reg, u32 value)
  1166. {
  1167. struct base_eep_header *pBase = &(pEepData->baseEepHeader);
  1168. struct ath_common *common = ath9k_hw_common(ah);
  1169. switch (ah->hw_version.devid) {
  1170. case AR9280_DEVID_PCI:
  1171. if (reg == 0x7894) {
  1172. ath_print(common, ATH_DBG_EEPROM,
  1173. "ini VAL: %x EEPROM: %x\n", value,
  1174. (pBase->version & 0xff));
  1175. if ((pBase->version & 0xff) > 0x0a) {
  1176. ath_print(common, ATH_DBG_EEPROM,
  1177. "PWDCLKIND: %d\n",
  1178. pBase->pwdclkind);
  1179. value &= ~AR_AN_TOP2_PWDCLKIND;
  1180. value |= AR_AN_TOP2_PWDCLKIND &
  1181. (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
  1182. } else {
  1183. ath_print(common, ATH_DBG_EEPROM,
  1184. "PWDCLKIND Earlier Rev\n");
  1185. }
  1186. ath_print(common, ATH_DBG_EEPROM,
  1187. "final ini VAL: %x\n", value);
  1188. }
  1189. break;
  1190. }
  1191. return value;
  1192. }
  1193. static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  1194. struct ar5416_eeprom_def *pEepData,
  1195. u32 reg, u32 value)
  1196. {
  1197. if (ah->eep_map == EEP_MAP_4KBITS)
  1198. return value;
  1199. else
  1200. return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
  1201. }
  1202. static void ath9k_olc_init(struct ath_hw *ah)
  1203. {
  1204. u32 i;
  1205. if (OLC_FOR_AR9287_10_LATER) {
  1206. REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
  1207. AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
  1208. ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
  1209. AR9287_AN_TXPC0_TXPCMODE,
  1210. AR9287_AN_TXPC0_TXPCMODE_S,
  1211. AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
  1212. udelay(100);
  1213. } else {
  1214. for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
  1215. ah->originalGain[i] =
  1216. MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
  1217. AR_PHY_TX_GAIN);
  1218. ah->PDADCdelta = 0;
  1219. }
  1220. }
  1221. static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
  1222. struct ath9k_channel *chan)
  1223. {
  1224. u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
  1225. if (IS_CHAN_B(chan))
  1226. ctl |= CTL_11B;
  1227. else if (IS_CHAN_G(chan))
  1228. ctl |= CTL_11G;
  1229. else
  1230. ctl |= CTL_11A;
  1231. return ctl;
  1232. }
  1233. static int ath9k_hw_process_ini(struct ath_hw *ah,
  1234. struct ath9k_channel *chan)
  1235. {
  1236. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  1237. int i, regWrites = 0;
  1238. struct ieee80211_channel *channel = chan->chan;
  1239. u32 modesIndex, freqIndex;
  1240. switch (chan->chanmode) {
  1241. case CHANNEL_A:
  1242. case CHANNEL_A_HT20:
  1243. modesIndex = 1;
  1244. freqIndex = 1;
  1245. break;
  1246. case CHANNEL_A_HT40PLUS:
  1247. case CHANNEL_A_HT40MINUS:
  1248. modesIndex = 2;
  1249. freqIndex = 1;
  1250. break;
  1251. case CHANNEL_G:
  1252. case CHANNEL_G_HT20:
  1253. case CHANNEL_B:
  1254. modesIndex = 4;
  1255. freqIndex = 2;
  1256. break;
  1257. case CHANNEL_G_HT40PLUS:
  1258. case CHANNEL_G_HT40MINUS:
  1259. modesIndex = 3;
  1260. freqIndex = 2;
  1261. break;
  1262. default:
  1263. return -EINVAL;
  1264. }
  1265. REG_WRITE(ah, AR_PHY(0), 0x00000007);
  1266. REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
  1267. ah->eep_ops->set_addac(ah, chan);
  1268. if (AR_SREV_5416_22_OR_LATER(ah)) {
  1269. REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
  1270. } else {
  1271. struct ar5416IniArray temp;
  1272. u32 addacSize =
  1273. sizeof(u32) * ah->iniAddac.ia_rows *
  1274. ah->iniAddac.ia_columns;
  1275. memcpy(ah->addac5416_21,
  1276. ah->iniAddac.ia_array, addacSize);
  1277. (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
  1278. temp.ia_array = ah->addac5416_21;
  1279. temp.ia_columns = ah->iniAddac.ia_columns;
  1280. temp.ia_rows = ah->iniAddac.ia_rows;
  1281. REG_WRITE_ARRAY(&temp, 1, regWrites);
  1282. }
  1283. REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
  1284. for (i = 0; i < ah->iniModes.ia_rows; i++) {
  1285. u32 reg = INI_RA(&ah->iniModes, i, 0);
  1286. u32 val = INI_RA(&ah->iniModes, i, modesIndex);
  1287. REG_WRITE(ah, reg, val);
  1288. if (reg >= 0x7800 && reg < 0x78a0
  1289. && ah->config.analog_shiftreg) {
  1290. udelay(100);
  1291. }
  1292. DO_DELAY(regWrites);
  1293. }
  1294. if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
  1295. REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
  1296. if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
  1297. AR_SREV_9287_10_OR_LATER(ah))
  1298. REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
  1299. for (i = 0; i < ah->iniCommon.ia_rows; i++) {
  1300. u32 reg = INI_RA(&ah->iniCommon, i, 0);
  1301. u32 val = INI_RA(&ah->iniCommon, i, 1);
  1302. REG_WRITE(ah, reg, val);
  1303. if (reg >= 0x7800 && reg < 0x78a0
  1304. && ah->config.analog_shiftreg) {
  1305. udelay(100);
  1306. }
  1307. DO_DELAY(regWrites);
  1308. }
  1309. ath9k_hw_write_regs(ah, freqIndex, regWrites);
  1310. if (AR_SREV_9271_10(ah))
  1311. REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
  1312. modesIndex, regWrites);
  1313. if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
  1314. REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
  1315. regWrites);
  1316. }
  1317. ath9k_hw_override_ini(ah, chan);
  1318. ath9k_hw_set_regs(ah, chan);
  1319. ath9k_hw_init_chain_masks(ah);
  1320. if (OLC_FOR_AR9280_20_LATER)
  1321. ath9k_olc_init(ah);
  1322. ah->eep_ops->set_txpower(ah, chan,
  1323. ath9k_regd_get_ctl(regulatory, chan),
  1324. channel->max_antenna_gain * 2,
  1325. channel->max_power * 2,
  1326. min((u32) MAX_RATE_POWER,
  1327. (u32) regulatory->power_limit));
  1328. if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
  1329. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  1330. "ar5416SetRfRegs failed\n");
  1331. return -EIO;
  1332. }
  1333. return 0;
  1334. }
  1335. /****************************************/
  1336. /* Reset and Channel Switching Routines */
  1337. /****************************************/
  1338. static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
  1339. {
  1340. u32 rfMode = 0;
  1341. if (chan == NULL)
  1342. return;
  1343. rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
  1344. ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
  1345. if (!AR_SREV_9280_10_OR_LATER(ah))
  1346. rfMode |= (IS_CHAN_5GHZ(chan)) ?
  1347. AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
  1348. if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
  1349. rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
  1350. REG_WRITE(ah, AR_PHY_MODE, rfMode);
  1351. }
  1352. static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
  1353. {
  1354. REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
  1355. }
  1356. static inline void ath9k_hw_set_dma(struct ath_hw *ah)
  1357. {
  1358. u32 regval;
  1359. /*
  1360. * set AHB_MODE not to do cacheline prefetches
  1361. */
  1362. regval = REG_READ(ah, AR_AHB_MODE);
  1363. REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
  1364. /*
  1365. * let mac dma reads be in 128 byte chunks
  1366. */
  1367. regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
  1368. REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
  1369. /*
  1370. * Restore TX Trigger Level to its pre-reset value.
  1371. * The initial value depends on whether aggregation is enabled, and is
  1372. * adjusted whenever underruns are detected.
  1373. */
  1374. REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
  1375. /*
  1376. * let mac dma writes be in 128 byte chunks
  1377. */
  1378. regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
  1379. REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
  1380. /*
  1381. * Setup receive FIFO threshold to hold off TX activities
  1382. */
  1383. REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
  1384. /*
  1385. * reduce the number of usable entries in PCU TXBUF to avoid
  1386. * wrap around issues.
  1387. */
  1388. if (AR_SREV_9285(ah)) {
  1389. /* For AR9285 the number of Fifos are reduced to half.
  1390. * So set the usable tx buf size also to half to
  1391. * avoid data/delimiter underruns
  1392. */
  1393. REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
  1394. AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
  1395. } else if (!AR_SREV_9271(ah)) {
  1396. REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
  1397. AR_PCU_TXBUF_CTRL_USABLE_SIZE);
  1398. }
  1399. }
  1400. static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
  1401. {
  1402. u32 val;
  1403. val = REG_READ(ah, AR_STA_ID1);
  1404. val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
  1405. switch (opmode) {
  1406. case NL80211_IFTYPE_AP:
  1407. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
  1408. | AR_STA_ID1_KSRCH_MODE);
  1409. REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
  1410. break;
  1411. case NL80211_IFTYPE_ADHOC:
  1412. case NL80211_IFTYPE_MESH_POINT:
  1413. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
  1414. | AR_STA_ID1_KSRCH_MODE);
  1415. REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
  1416. break;
  1417. case NL80211_IFTYPE_STATION:
  1418. case NL80211_IFTYPE_MONITOR:
  1419. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
  1420. break;
  1421. }
  1422. }
  1423. static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
  1424. u32 coef_scaled,
  1425. u32 *coef_mantissa,
  1426. u32 *coef_exponent)
  1427. {
  1428. u32 coef_exp, coef_man;
  1429. for (coef_exp = 31; coef_exp > 0; coef_exp--)
  1430. if ((coef_scaled >> coef_exp) & 0x1)
  1431. break;
  1432. coef_exp = 14 - (coef_exp - COEF_SCALE_S);
  1433. coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
  1434. *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
  1435. *coef_exponent = coef_exp - 16;
  1436. }
  1437. static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
  1438. struct ath9k_channel *chan)
  1439. {
  1440. u32 coef_scaled, ds_coef_exp, ds_coef_man;
  1441. u32 clockMhzScaled = 0x64000000;
  1442. struct chan_centers centers;
  1443. if (IS_CHAN_HALF_RATE(chan))
  1444. clockMhzScaled = clockMhzScaled >> 1;
  1445. else if (IS_CHAN_QUARTER_RATE(chan))
  1446. clockMhzScaled = clockMhzScaled >> 2;
  1447. ath9k_hw_get_channel_centers(ah, chan, &centers);
  1448. coef_scaled = clockMhzScaled / centers.synth_center;
  1449. ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
  1450. &ds_coef_exp);
  1451. REG_RMW_FIELD(ah, AR_PHY_TIMING3,
  1452. AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
  1453. REG_RMW_FIELD(ah, AR_PHY_TIMING3,
  1454. AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
  1455. coef_scaled = (9 * coef_scaled) / 10;
  1456. ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
  1457. &ds_coef_exp);
  1458. REG_RMW_FIELD(ah, AR_PHY_HALFGI,
  1459. AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
  1460. REG_RMW_FIELD(ah, AR_PHY_HALFGI,
  1461. AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
  1462. }
  1463. static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
  1464. {
  1465. u32 rst_flags;
  1466. u32 tmpReg;
  1467. if (AR_SREV_9100(ah)) {
  1468. u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
  1469. val &= ~AR_RTC_DERIVED_CLK_PERIOD;
  1470. val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
  1471. REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
  1472. (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
  1473. }
  1474. REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
  1475. AR_RTC_FORCE_WAKE_ON_INT);
  1476. if (AR_SREV_9100(ah)) {
  1477. rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
  1478. AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
  1479. } else {
  1480. tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
  1481. if (tmpReg &
  1482. (AR_INTR_SYNC_LOCAL_TIMEOUT |
  1483. AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
  1484. REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
  1485. REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
  1486. } else {
  1487. REG_WRITE(ah, AR_RC, AR_RC_AHB);
  1488. }
  1489. rst_flags = AR_RTC_RC_MAC_WARM;
  1490. if (type == ATH9K_RESET_COLD)
  1491. rst_flags |= AR_RTC_RC_MAC_COLD;
  1492. }
  1493. REG_WRITE(ah, AR_RTC_RC, rst_flags);
  1494. udelay(50);
  1495. REG_WRITE(ah, AR_RTC_RC, 0);
  1496. if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
  1497. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
  1498. "RTC stuck in MAC reset\n");
  1499. return false;
  1500. }
  1501. if (!AR_SREV_9100(ah))
  1502. REG_WRITE(ah, AR_RC, 0);
  1503. if (AR_SREV_9100(ah))
  1504. udelay(50);
  1505. return true;
  1506. }
  1507. static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
  1508. {
  1509. REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
  1510. AR_RTC_FORCE_WAKE_ON_INT);
  1511. if (!AR_SREV_9100(ah))
  1512. REG_WRITE(ah, AR_RC, AR_RC_AHB);
  1513. REG_WRITE(ah, AR_RTC_RESET, 0);
  1514. udelay(2);
  1515. if (!AR_SREV_9100(ah))
  1516. REG_WRITE(ah, AR_RC, 0);
  1517. REG_WRITE(ah, AR_RTC_RESET, 1);
  1518. if (!ath9k_hw_wait(ah,
  1519. AR_RTC_STATUS,
  1520. AR_RTC_STATUS_M,
  1521. AR_RTC_STATUS_ON,
  1522. AH_WAIT_TIMEOUT)) {
  1523. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
  1524. "RTC not waking up\n");
  1525. return false;
  1526. }
  1527. ath9k_hw_read_revisions(ah);
  1528. return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
  1529. }
  1530. static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
  1531. {
  1532. REG_WRITE(ah, AR_RTC_FORCE_WAKE,
  1533. AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
  1534. switch (type) {
  1535. case ATH9K_RESET_POWER_ON:
  1536. return ath9k_hw_set_reset_power_on(ah);
  1537. case ATH9K_RESET_WARM:
  1538. case ATH9K_RESET_COLD:
  1539. return ath9k_hw_set_reset(ah, type);
  1540. default:
  1541. return false;
  1542. }
  1543. }
  1544. static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
  1545. {
  1546. u32 phymode;
  1547. u32 enableDacFifo = 0;
  1548. if (AR_SREV_9285_10_OR_LATER(ah))
  1549. enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
  1550. AR_PHY_FC_ENABLE_DAC_FIFO);
  1551. phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
  1552. | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
  1553. if (IS_CHAN_HT40(chan)) {
  1554. phymode |= AR_PHY_FC_DYN2040_EN;
  1555. if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
  1556. (chan->chanmode == CHANNEL_G_HT40PLUS))
  1557. phymode |= AR_PHY_FC_DYN2040_PRI_CH;
  1558. }
  1559. REG_WRITE(ah, AR_PHY_TURBO, phymode);
  1560. ath9k_hw_set11nmac2040(ah);
  1561. REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
  1562. REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
  1563. }
  1564. static bool ath9k_hw_chip_reset(struct ath_hw *ah,
  1565. struct ath9k_channel *chan)
  1566. {
  1567. if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
  1568. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
  1569. return false;
  1570. } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
  1571. return false;
  1572. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
  1573. return false;
  1574. ah->chip_fullsleep = false;
  1575. ath9k_hw_init_pll(ah, chan);
  1576. ath9k_hw_set_rfmode(ah, chan);
  1577. return true;
  1578. }
  1579. static bool ath9k_hw_channel_change(struct ath_hw *ah,
  1580. struct ath9k_channel *chan)
  1581. {
  1582. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  1583. struct ath_common *common = ath9k_hw_common(ah);
  1584. struct ieee80211_channel *channel = chan->chan;
  1585. u32 synthDelay, qnum;
  1586. int r;
  1587. for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
  1588. if (ath9k_hw_numtxpending(ah, qnum)) {
  1589. ath_print(common, ATH_DBG_QUEUE,
  1590. "Transmit frames pending on "
  1591. "queue %d\n", qnum);
  1592. return false;
  1593. }
  1594. }
  1595. REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
  1596. if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
  1597. AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
  1598. ath_print(common, ATH_DBG_FATAL,
  1599. "Could not kill baseband RX\n");
  1600. return false;
  1601. }
  1602. ath9k_hw_set_regs(ah, chan);
  1603. r = ah->ath9k_hw_rf_set_freq(ah, chan);
  1604. if (r) {
  1605. ath_print(common, ATH_DBG_FATAL,
  1606. "Failed to set channel\n");
  1607. return false;
  1608. }
  1609. ah->eep_ops->set_txpower(ah, chan,
  1610. ath9k_regd_get_ctl(regulatory, chan),
  1611. channel->max_antenna_gain * 2,
  1612. channel->max_power * 2,
  1613. min((u32) MAX_RATE_POWER,
  1614. (u32) regulatory->power_limit));
  1615. synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
  1616. if (IS_CHAN_B(chan))
  1617. synthDelay = (4 * synthDelay) / 22;
  1618. else
  1619. synthDelay /= 10;
  1620. udelay(synthDelay + BASE_ACTIVATE_DELAY);
  1621. REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
  1622. if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
  1623. ath9k_hw_set_delta_slope(ah, chan);
  1624. ah->ath9k_hw_spur_mitigate_freq(ah, chan);
  1625. if (!chan->oneTimeCalsDone)
  1626. chan->oneTimeCalsDone = true;
  1627. return true;
  1628. }
  1629. static void ath9k_enable_rfkill(struct ath_hw *ah)
  1630. {
  1631. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
  1632. AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
  1633. REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
  1634. AR_GPIO_INPUT_MUX2_RFSILENT);
  1635. ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
  1636. REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
  1637. }
  1638. int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  1639. bool bChannelChange)
  1640. {
  1641. struct ath_common *common = ath9k_hw_common(ah);
  1642. u32 saveLedState;
  1643. struct ath9k_channel *curchan = ah->curchan;
  1644. u32 saveDefAntenna;
  1645. u32 macStaId1;
  1646. u64 tsf = 0;
  1647. int i, rx_chainmask, r;
  1648. ah->txchainmask = common->tx_chainmask;
  1649. ah->rxchainmask = common->rx_chainmask;
  1650. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
  1651. return -EIO;
  1652. if (curchan && !ah->chip_fullsleep)
  1653. ath9k_hw_getnf(ah, curchan);
  1654. if (bChannelChange &&
  1655. (ah->chip_fullsleep != true) &&
  1656. (ah->curchan != NULL) &&
  1657. (chan->channel != ah->curchan->channel) &&
  1658. ((chan->channelFlags & CHANNEL_ALL) ==
  1659. (ah->curchan->channelFlags & CHANNEL_ALL)) &&
  1660. !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
  1661. IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
  1662. if (ath9k_hw_channel_change(ah, chan)) {
  1663. ath9k_hw_loadnf(ah, ah->curchan);
  1664. ath9k_hw_start_nfcal(ah);
  1665. return 0;
  1666. }
  1667. }
  1668. saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
  1669. if (saveDefAntenna == 0)
  1670. saveDefAntenna = 1;
  1671. macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
  1672. /* For chips on which RTC reset is done, save TSF before it gets cleared */
  1673. if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
  1674. tsf = ath9k_hw_gettsf64(ah);
  1675. saveLedState = REG_READ(ah, AR_CFG_LED) &
  1676. (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
  1677. AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
  1678. ath9k_hw_mark_phy_inactive(ah);
  1679. if (AR_SREV_9271(ah) && ah->htc_reset_init) {
  1680. REG_WRITE(ah,
  1681. AR9271_RESET_POWER_DOWN_CONTROL,
  1682. AR9271_RADIO_RF_RST);
  1683. udelay(50);
  1684. }
  1685. if (!ath9k_hw_chip_reset(ah, chan)) {
  1686. ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
  1687. return -EINVAL;
  1688. }
  1689. if (AR_SREV_9271(ah) && ah->htc_reset_init) {
  1690. ah->htc_reset_init = false;
  1691. REG_WRITE(ah,
  1692. AR9271_RESET_POWER_DOWN_CONTROL,
  1693. AR9271_GATE_MAC_CTL);
  1694. udelay(50);
  1695. }
  1696. /* Restore TSF */
  1697. if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
  1698. ath9k_hw_settsf64(ah, tsf);
  1699. if (AR_SREV_9280_10_OR_LATER(ah))
  1700. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
  1701. if (AR_SREV_9287_12_OR_LATER(ah)) {
  1702. /* Enable ASYNC FIFO */
  1703. REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
  1704. AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
  1705. REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
  1706. REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
  1707. AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
  1708. REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
  1709. AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
  1710. }
  1711. r = ath9k_hw_process_ini(ah, chan);
  1712. if (r)
  1713. return r;
  1714. /* Setup MFP options for CCMP */
  1715. if (AR_SREV_9280_20_OR_LATER(ah)) {
  1716. /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
  1717. * frames when constructing CCMP AAD. */
  1718. REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
  1719. 0xc7ff);
  1720. ah->sw_mgmt_crypto = false;
  1721. } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  1722. /* Disable hardware crypto for management frames */
  1723. REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
  1724. AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
  1725. REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
  1726. AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
  1727. ah->sw_mgmt_crypto = true;
  1728. } else
  1729. ah->sw_mgmt_crypto = true;
  1730. if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
  1731. ath9k_hw_set_delta_slope(ah, chan);
  1732. ah->ath9k_hw_spur_mitigate_freq(ah, chan);
  1733. ah->eep_ops->set_board_values(ah, chan);
  1734. REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
  1735. REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
  1736. | macStaId1
  1737. | AR_STA_ID1_RTS_USE_DEF
  1738. | (ah->config.
  1739. ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
  1740. | ah->sta_id1_defaults);
  1741. ath9k_hw_set_operating_mode(ah, ah->opmode);
  1742. ath_hw_setbssidmask(common);
  1743. REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
  1744. ath9k_hw_write_associd(ah);
  1745. REG_WRITE(ah, AR_ISR, ~0);
  1746. REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
  1747. r = ah->ath9k_hw_rf_set_freq(ah, chan);
  1748. if (r)
  1749. return r;
  1750. for (i = 0; i < AR_NUM_DCU; i++)
  1751. REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
  1752. ah->intr_txqs = 0;
  1753. for (i = 0; i < ah->caps.total_queues; i++)
  1754. ath9k_hw_resettxqueue(ah, i);
  1755. ath9k_hw_init_interrupt_masks(ah, ah->opmode);
  1756. ath9k_hw_init_qos(ah);
  1757. if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1758. ath9k_enable_rfkill(ah);
  1759. ath9k_hw_init_user_settings(ah);
  1760. if (AR_SREV_9287_12_OR_LATER(ah)) {
  1761. REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
  1762. AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
  1763. REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
  1764. AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
  1765. REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
  1766. AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
  1767. REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
  1768. REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
  1769. REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
  1770. AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
  1771. REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
  1772. AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
  1773. }
  1774. if (AR_SREV_9287_12_OR_LATER(ah)) {
  1775. REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
  1776. AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
  1777. }
  1778. REG_WRITE(ah, AR_STA_ID1,
  1779. REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
  1780. ath9k_hw_set_dma(ah);
  1781. REG_WRITE(ah, AR_OBS, 8);
  1782. if (ah->config.intr_mitigation) {
  1783. REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
  1784. REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
  1785. }
  1786. ath9k_hw_init_bb(ah, chan);
  1787. if (!ath9k_hw_init_cal(ah, chan))
  1788. return -EIO;
  1789. rx_chainmask = ah->rxchainmask;
  1790. if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
  1791. REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
  1792. REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
  1793. }
  1794. REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
  1795. /*
  1796. * For big endian systems turn on swapping for descriptors
  1797. */
  1798. if (AR_SREV_9100(ah)) {
  1799. u32 mask;
  1800. mask = REG_READ(ah, AR_CFG);
  1801. if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
  1802. ath_print(common, ATH_DBG_RESET,
  1803. "CFG Byte Swap Set 0x%x\n", mask);
  1804. } else {
  1805. mask =
  1806. INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
  1807. REG_WRITE(ah, AR_CFG, mask);
  1808. ath_print(common, ATH_DBG_RESET,
  1809. "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
  1810. }
  1811. } else {
  1812. /* Configure AR9271 target WLAN */
  1813. if (AR_SREV_9271(ah))
  1814. REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
  1815. #ifdef __BIG_ENDIAN
  1816. else
  1817. REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
  1818. #endif
  1819. }
  1820. if (ah->btcoex_hw.enabled)
  1821. ath9k_hw_btcoex_enable(ah);
  1822. return 0;
  1823. }
  1824. EXPORT_SYMBOL(ath9k_hw_reset);
  1825. /************************/
  1826. /* Key Cache Management */
  1827. /************************/
  1828. bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
  1829. {
  1830. u32 keyType;
  1831. if (entry >= ah->caps.keycache_size) {
  1832. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  1833. "keychache entry %u out of range\n", entry);
  1834. return false;
  1835. }
  1836. keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
  1837. REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
  1838. REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
  1839. REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
  1840. REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
  1841. REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
  1842. REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
  1843. REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
  1844. REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
  1845. if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
  1846. u16 micentry = entry + 64;
  1847. REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
  1848. REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
  1849. REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
  1850. REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
  1851. }
  1852. return true;
  1853. }
  1854. EXPORT_SYMBOL(ath9k_hw_keyreset);
  1855. bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
  1856. {
  1857. u32 macHi, macLo;
  1858. if (entry >= ah->caps.keycache_size) {
  1859. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  1860. "keychache entry %u out of range\n", entry);
  1861. return false;
  1862. }
  1863. if (mac != NULL) {
  1864. macHi = (mac[5] << 8) | mac[4];
  1865. macLo = (mac[3] << 24) |
  1866. (mac[2] << 16) |
  1867. (mac[1] << 8) |
  1868. mac[0];
  1869. macLo >>= 1;
  1870. macLo |= (macHi & 1) << 31;
  1871. macHi >>= 1;
  1872. } else {
  1873. macLo = macHi = 0;
  1874. }
  1875. REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
  1876. REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
  1877. return true;
  1878. }
  1879. EXPORT_SYMBOL(ath9k_hw_keysetmac);
  1880. bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
  1881. const struct ath9k_keyval *k,
  1882. const u8 *mac)
  1883. {
  1884. const struct ath9k_hw_capabilities *pCap = &ah->caps;
  1885. struct ath_common *common = ath9k_hw_common(ah);
  1886. u32 key0, key1, key2, key3, key4;
  1887. u32 keyType;
  1888. if (entry >= pCap->keycache_size) {
  1889. ath_print(common, ATH_DBG_FATAL,
  1890. "keycache entry %u out of range\n", entry);
  1891. return false;
  1892. }
  1893. switch (k->kv_type) {
  1894. case ATH9K_CIPHER_AES_OCB:
  1895. keyType = AR_KEYTABLE_TYPE_AES;
  1896. break;
  1897. case ATH9K_CIPHER_AES_CCM:
  1898. if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
  1899. ath_print(common, ATH_DBG_ANY,
  1900. "AES-CCM not supported by mac rev 0x%x\n",
  1901. ah->hw_version.macRev);
  1902. return false;
  1903. }
  1904. keyType = AR_KEYTABLE_TYPE_CCM;
  1905. break;
  1906. case ATH9K_CIPHER_TKIP:
  1907. keyType = AR_KEYTABLE_TYPE_TKIP;
  1908. if (ATH9K_IS_MIC_ENABLED(ah)
  1909. && entry + 64 >= pCap->keycache_size) {
  1910. ath_print(common, ATH_DBG_ANY,
  1911. "entry %u inappropriate for TKIP\n", entry);
  1912. return false;
  1913. }
  1914. break;
  1915. case ATH9K_CIPHER_WEP:
  1916. if (k->kv_len < WLAN_KEY_LEN_WEP40) {
  1917. ath_print(common, ATH_DBG_ANY,
  1918. "WEP key length %u too small\n", k->kv_len);
  1919. return false;
  1920. }
  1921. if (k->kv_len <= WLAN_KEY_LEN_WEP40)
  1922. keyType = AR_KEYTABLE_TYPE_40;
  1923. else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
  1924. keyType = AR_KEYTABLE_TYPE_104;
  1925. else
  1926. keyType = AR_KEYTABLE_TYPE_128;
  1927. break;
  1928. case ATH9K_CIPHER_CLR:
  1929. keyType = AR_KEYTABLE_TYPE_CLR;
  1930. break;
  1931. default:
  1932. ath_print(common, ATH_DBG_FATAL,
  1933. "cipher %u not supported\n", k->kv_type);
  1934. return false;
  1935. }
  1936. key0 = get_unaligned_le32(k->kv_val + 0);
  1937. key1 = get_unaligned_le16(k->kv_val + 4);
  1938. key2 = get_unaligned_le32(k->kv_val + 6);
  1939. key3 = get_unaligned_le16(k->kv_val + 10);
  1940. key4 = get_unaligned_le32(k->kv_val + 12);
  1941. if (k->kv_len <= WLAN_KEY_LEN_WEP104)
  1942. key4 &= 0xff;
  1943. /*
  1944. * Note: Key cache registers access special memory area that requires
  1945. * two 32-bit writes to actually update the values in the internal
  1946. * memory. Consequently, the exact order and pairs used here must be
  1947. * maintained.
  1948. */
  1949. if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
  1950. u16 micentry = entry + 64;
  1951. /*
  1952. * Write inverted key[47:0] first to avoid Michael MIC errors
  1953. * on frames that could be sent or received at the same time.
  1954. * The correct key will be written in the end once everything
  1955. * else is ready.
  1956. */
  1957. REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
  1958. REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
  1959. /* Write key[95:48] */
  1960. REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
  1961. REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
  1962. /* Write key[127:96] and key type */
  1963. REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
  1964. REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
  1965. /* Write MAC address for the entry */
  1966. (void) ath9k_hw_keysetmac(ah, entry, mac);
  1967. if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
  1968. /*
  1969. * TKIP uses two key cache entries:
  1970. * Michael MIC TX/RX keys in the same key cache entry
  1971. * (idx = main index + 64):
  1972. * key0 [31:0] = RX key [31:0]
  1973. * key1 [15:0] = TX key [31:16]
  1974. * key1 [31:16] = reserved
  1975. * key2 [31:0] = RX key [63:32]
  1976. * key3 [15:0] = TX key [15:0]
  1977. * key3 [31:16] = reserved
  1978. * key4 [31:0] = TX key [63:32]
  1979. */
  1980. u32 mic0, mic1, mic2, mic3, mic4;
  1981. mic0 = get_unaligned_le32(k->kv_mic + 0);
  1982. mic2 = get_unaligned_le32(k->kv_mic + 4);
  1983. mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
  1984. mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
  1985. mic4 = get_unaligned_le32(k->kv_txmic + 4);
  1986. /* Write RX[31:0] and TX[31:16] */
  1987. REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
  1988. REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
  1989. /* Write RX[63:32] and TX[15:0] */
  1990. REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
  1991. REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
  1992. /* Write TX[63:32] and keyType(reserved) */
  1993. REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
  1994. REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
  1995. AR_KEYTABLE_TYPE_CLR);
  1996. } else {
  1997. /*
  1998. * TKIP uses four key cache entries (two for group
  1999. * keys):
  2000. * Michael MIC TX/RX keys are in different key cache
  2001. * entries (idx = main index + 64 for TX and
  2002. * main index + 32 + 96 for RX):
  2003. * key0 [31:0] = TX/RX MIC key [31:0]
  2004. * key1 [31:0] = reserved
  2005. * key2 [31:0] = TX/RX MIC key [63:32]
  2006. * key3 [31:0] = reserved
  2007. * key4 [31:0] = reserved
  2008. *
  2009. * Upper layer code will call this function separately
  2010. * for TX and RX keys when these registers offsets are
  2011. * used.
  2012. */
  2013. u32 mic0, mic2;
  2014. mic0 = get_unaligned_le32(k->kv_mic + 0);
  2015. mic2 = get_unaligned_le32(k->kv_mic + 4);
  2016. /* Write MIC key[31:0] */
  2017. REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
  2018. REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
  2019. /* Write MIC key[63:32] */
  2020. REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
  2021. REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
  2022. /* Write TX[63:32] and keyType(reserved) */
  2023. REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
  2024. REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
  2025. AR_KEYTABLE_TYPE_CLR);
  2026. }
  2027. /* MAC address registers are reserved for the MIC entry */
  2028. REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
  2029. REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
  2030. /*
  2031. * Write the correct (un-inverted) key[47:0] last to enable
  2032. * TKIP now that all other registers are set with correct
  2033. * values.
  2034. */
  2035. REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
  2036. REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
  2037. } else {
  2038. /* Write key[47:0] */
  2039. REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
  2040. REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
  2041. /* Write key[95:48] */
  2042. REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
  2043. REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
  2044. /* Write key[127:96] and key type */
  2045. REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
  2046. REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
  2047. /* Write MAC address for the entry */
  2048. (void) ath9k_hw_keysetmac(ah, entry, mac);
  2049. }
  2050. return true;
  2051. }
  2052. EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
  2053. bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
  2054. {
  2055. if (entry < ah->caps.keycache_size) {
  2056. u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
  2057. if (val & AR_KEYTABLE_VALID)
  2058. return true;
  2059. }
  2060. return false;
  2061. }
  2062. EXPORT_SYMBOL(ath9k_hw_keyisvalid);
  2063. /******************************/
  2064. /* Power Management (Chipset) */
  2065. /******************************/
  2066. static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
  2067. {
  2068. REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  2069. if (setChip) {
  2070. REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
  2071. AR_RTC_FORCE_WAKE_EN);
  2072. if (!AR_SREV_9100(ah))
  2073. REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
  2074. if(!AR_SREV_5416(ah))
  2075. REG_CLR_BIT(ah, (AR_RTC_RESET),
  2076. AR_RTC_RESET_EN);
  2077. }
  2078. }
  2079. static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
  2080. {
  2081. REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  2082. if (setChip) {
  2083. struct ath9k_hw_capabilities *pCap = &ah->caps;
  2084. if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  2085. REG_WRITE(ah, AR_RTC_FORCE_WAKE,
  2086. AR_RTC_FORCE_WAKE_ON_INT);
  2087. } else {
  2088. REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
  2089. AR_RTC_FORCE_WAKE_EN);
  2090. }
  2091. }
  2092. }
  2093. static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
  2094. {
  2095. u32 val;
  2096. int i;
  2097. if (setChip) {
  2098. if ((REG_READ(ah, AR_RTC_STATUS) &
  2099. AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
  2100. if (ath9k_hw_set_reset_reg(ah,
  2101. ATH9K_RESET_POWER_ON) != true) {
  2102. return false;
  2103. }
  2104. ath9k_hw_init_pll(ah, NULL);
  2105. }
  2106. if (AR_SREV_9100(ah))
  2107. REG_SET_BIT(ah, AR_RTC_RESET,
  2108. AR_RTC_RESET_EN);
  2109. REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
  2110. AR_RTC_FORCE_WAKE_EN);
  2111. udelay(50);
  2112. for (i = POWER_UP_TIME / 50; i > 0; i--) {
  2113. val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
  2114. if (val == AR_RTC_STATUS_ON)
  2115. break;
  2116. udelay(50);
  2117. REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
  2118. AR_RTC_FORCE_WAKE_EN);
  2119. }
  2120. if (i == 0) {
  2121. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  2122. "Failed to wakeup in %uus\n",
  2123. POWER_UP_TIME / 20);
  2124. return false;
  2125. }
  2126. }
  2127. REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  2128. return true;
  2129. }
  2130. bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
  2131. {
  2132. struct ath_common *common = ath9k_hw_common(ah);
  2133. int status = true, setChip = true;
  2134. static const char *modes[] = {
  2135. "AWAKE",
  2136. "FULL-SLEEP",
  2137. "NETWORK SLEEP",
  2138. "UNDEFINED"
  2139. };
  2140. if (ah->power_mode == mode)
  2141. return status;
  2142. ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
  2143. modes[ah->power_mode], modes[mode]);
  2144. switch (mode) {
  2145. case ATH9K_PM_AWAKE:
  2146. status = ath9k_hw_set_power_awake(ah, setChip);
  2147. break;
  2148. case ATH9K_PM_FULL_SLEEP:
  2149. ath9k_set_power_sleep(ah, setChip);
  2150. ah->chip_fullsleep = true;
  2151. break;
  2152. case ATH9K_PM_NETWORK_SLEEP:
  2153. ath9k_set_power_network_sleep(ah, setChip);
  2154. break;
  2155. default:
  2156. ath_print(common, ATH_DBG_FATAL,
  2157. "Unknown power mode %u\n", mode);
  2158. return false;
  2159. }
  2160. ah->power_mode = mode;
  2161. return status;
  2162. }
  2163. EXPORT_SYMBOL(ath9k_hw_setpower);
  2164. /*
  2165. * Helper for ASPM support.
  2166. *
  2167. * Disable PLL when in L0s as well as receiver clock when in L1.
  2168. * This power saving option must be enabled through the SerDes.
  2169. *
  2170. * Programming the SerDes must go through the same 288 bit serial shift
  2171. * register as the other analog registers. Hence the 9 writes.
  2172. */
  2173. void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
  2174. {
  2175. u8 i;
  2176. u32 val;
  2177. if (ah->is_pciexpress != true)
  2178. return;
  2179. /* Do not touch SerDes registers */
  2180. if (ah->config.pcie_powersave_enable == 2)
  2181. return;
  2182. /* Nothing to do on restore for 11N */
  2183. if (!restore) {
  2184. if (AR_SREV_9280_20_OR_LATER(ah)) {
  2185. /*
  2186. * AR9280 2.0 or later chips use SerDes values from the
  2187. * initvals.h initialized depending on chipset during
  2188. * ath9k_hw_init()
  2189. */
  2190. for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
  2191. REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
  2192. INI_RA(&ah->iniPcieSerdes, i, 1));
  2193. }
  2194. } else if (AR_SREV_9280(ah) &&
  2195. (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
  2196. REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
  2197. REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
  2198. /* RX shut off when elecidle is asserted */
  2199. REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
  2200. REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
  2201. REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
  2202. /* Shut off CLKREQ active in L1 */
  2203. if (ah->config.pcie_clock_req)
  2204. REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
  2205. else
  2206. REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
  2207. REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
  2208. REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
  2209. REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
  2210. /* Load the new settings */
  2211. REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
  2212. } else {
  2213. REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
  2214. REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
  2215. /* RX shut off when elecidle is asserted */
  2216. REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
  2217. REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
  2218. REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
  2219. /*
  2220. * Ignore ah->ah_config.pcie_clock_req setting for
  2221. * pre-AR9280 11n
  2222. */
  2223. REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
  2224. REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
  2225. REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
  2226. REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
  2227. /* Load the new settings */
  2228. REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
  2229. }
  2230. udelay(1000);
  2231. /* set bit 19 to allow forcing of pcie core into L1 state */
  2232. REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
  2233. /* Several PCIe massages to ensure proper behaviour */
  2234. if (ah->config.pcie_waen) {
  2235. val = ah->config.pcie_waen;
  2236. if (!power_off)
  2237. val &= (~AR_WA_D3_L1_DISABLE);
  2238. } else {
  2239. if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
  2240. AR_SREV_9287(ah)) {
  2241. val = AR9285_WA_DEFAULT;
  2242. if (!power_off)
  2243. val &= (~AR_WA_D3_L1_DISABLE);
  2244. } else if (AR_SREV_9280(ah)) {
  2245. /*
  2246. * On AR9280 chips bit 22 of 0x4004 needs to be
  2247. * set otherwise card may disappear.
  2248. */
  2249. val = AR9280_WA_DEFAULT;
  2250. if (!power_off)
  2251. val &= (~AR_WA_D3_L1_DISABLE);
  2252. } else
  2253. val = AR_WA_DEFAULT;
  2254. }
  2255. REG_WRITE(ah, AR_WA, val);
  2256. }
  2257. if (power_off) {
  2258. /*
  2259. * Set PCIe workaround bits
  2260. * bit 14 in WA register (disable L1) should only
  2261. * be set when device enters D3 and be cleared
  2262. * when device comes back to D0.
  2263. */
  2264. if (ah->config.pcie_waen) {
  2265. if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
  2266. REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
  2267. } else {
  2268. if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
  2269. AR_SREV_9287(ah)) &&
  2270. (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
  2271. (AR_SREV_9280(ah) &&
  2272. (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
  2273. REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
  2274. }
  2275. }
  2276. }
  2277. }
  2278. EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
  2279. /**********************/
  2280. /* Interrupt Handling */
  2281. /**********************/
  2282. bool ath9k_hw_intrpend(struct ath_hw *ah)
  2283. {
  2284. u32 host_isr;
  2285. if (AR_SREV_9100(ah))
  2286. return true;
  2287. host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
  2288. if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
  2289. return true;
  2290. host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
  2291. if ((host_isr & AR_INTR_SYNC_DEFAULT)
  2292. && (host_isr != AR_INTR_SPURIOUS))
  2293. return true;
  2294. return false;
  2295. }
  2296. EXPORT_SYMBOL(ath9k_hw_intrpend);
  2297. bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
  2298. {
  2299. u32 isr = 0;
  2300. u32 mask2 = 0;
  2301. struct ath9k_hw_capabilities *pCap = &ah->caps;
  2302. u32 sync_cause = 0;
  2303. bool fatal_int = false;
  2304. struct ath_common *common = ath9k_hw_common(ah);
  2305. if (!AR_SREV_9100(ah)) {
  2306. if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
  2307. if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
  2308. == AR_RTC_STATUS_ON) {
  2309. isr = REG_READ(ah, AR_ISR);
  2310. }
  2311. }
  2312. sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
  2313. AR_INTR_SYNC_DEFAULT;
  2314. *masked = 0;
  2315. if (!isr && !sync_cause)
  2316. return false;
  2317. } else {
  2318. *masked = 0;
  2319. isr = REG_READ(ah, AR_ISR);
  2320. }
  2321. if (isr) {
  2322. if (isr & AR_ISR_BCNMISC) {
  2323. u32 isr2;
  2324. isr2 = REG_READ(ah, AR_ISR_S2);
  2325. if (isr2 & AR_ISR_S2_TIM)
  2326. mask2 |= ATH9K_INT_TIM;
  2327. if (isr2 & AR_ISR_S2_DTIM)
  2328. mask2 |= ATH9K_INT_DTIM;
  2329. if (isr2 & AR_ISR_S2_DTIMSYNC)
  2330. mask2 |= ATH9K_INT_DTIMSYNC;
  2331. if (isr2 & (AR_ISR_S2_CABEND))
  2332. mask2 |= ATH9K_INT_CABEND;
  2333. if (isr2 & AR_ISR_S2_GTT)
  2334. mask2 |= ATH9K_INT_GTT;
  2335. if (isr2 & AR_ISR_S2_CST)
  2336. mask2 |= ATH9K_INT_CST;
  2337. if (isr2 & AR_ISR_S2_TSFOOR)
  2338. mask2 |= ATH9K_INT_TSFOOR;
  2339. }
  2340. isr = REG_READ(ah, AR_ISR_RAC);
  2341. if (isr == 0xffffffff) {
  2342. *masked = 0;
  2343. return false;
  2344. }
  2345. *masked = isr & ATH9K_INT_COMMON;
  2346. if (ah->config.intr_mitigation) {
  2347. if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
  2348. *masked |= ATH9K_INT_RX;
  2349. }
  2350. if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
  2351. *masked |= ATH9K_INT_RX;
  2352. if (isr &
  2353. (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
  2354. AR_ISR_TXEOL)) {
  2355. u32 s0_s, s1_s;
  2356. *masked |= ATH9K_INT_TX;
  2357. s0_s = REG_READ(ah, AR_ISR_S0_S);
  2358. ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
  2359. ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
  2360. s1_s = REG_READ(ah, AR_ISR_S1_S);
  2361. ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
  2362. ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
  2363. }
  2364. if (isr & AR_ISR_RXORN) {
  2365. ath_print(common, ATH_DBG_INTERRUPT,
  2366. "receive FIFO overrun interrupt\n");
  2367. }
  2368. if (!AR_SREV_9100(ah)) {
  2369. if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  2370. u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
  2371. if (isr5 & AR_ISR_S5_TIM_TIMER)
  2372. *masked |= ATH9K_INT_TIM_TIMER;
  2373. }
  2374. }
  2375. *masked |= mask2;
  2376. }
  2377. if (AR_SREV_9100(ah))
  2378. return true;
  2379. if (isr & AR_ISR_GENTMR) {
  2380. u32 s5_s;
  2381. s5_s = REG_READ(ah, AR_ISR_S5_S);
  2382. if (isr & AR_ISR_GENTMR) {
  2383. ah->intr_gen_timer_trigger =
  2384. MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
  2385. ah->intr_gen_timer_thresh =
  2386. MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
  2387. if (ah->intr_gen_timer_trigger)
  2388. *masked |= ATH9K_INT_GENTIMER;
  2389. }
  2390. }
  2391. if (sync_cause) {
  2392. fatal_int =
  2393. (sync_cause &
  2394. (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
  2395. ? true : false;
  2396. if (fatal_int) {
  2397. if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
  2398. ath_print(common, ATH_DBG_ANY,
  2399. "received PCI FATAL interrupt\n");
  2400. }
  2401. if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
  2402. ath_print(common, ATH_DBG_ANY,
  2403. "received PCI PERR interrupt\n");
  2404. }
  2405. *masked |= ATH9K_INT_FATAL;
  2406. }
  2407. if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
  2408. ath_print(common, ATH_DBG_INTERRUPT,
  2409. "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
  2410. REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
  2411. REG_WRITE(ah, AR_RC, 0);
  2412. *masked |= ATH9K_INT_FATAL;
  2413. }
  2414. if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
  2415. ath_print(common, ATH_DBG_INTERRUPT,
  2416. "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
  2417. }
  2418. REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
  2419. (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
  2420. }
  2421. return true;
  2422. }
  2423. EXPORT_SYMBOL(ath9k_hw_getisr);
  2424. enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
  2425. {
  2426. u32 omask = ah->mask_reg;
  2427. u32 mask, mask2;
  2428. struct ath9k_hw_capabilities *pCap = &ah->caps;
  2429. struct ath_common *common = ath9k_hw_common(ah);
  2430. ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
  2431. if (omask & ATH9K_INT_GLOBAL) {
  2432. ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
  2433. REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
  2434. (void) REG_READ(ah, AR_IER);
  2435. if (!AR_SREV_9100(ah)) {
  2436. REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
  2437. (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
  2438. REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
  2439. (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
  2440. }
  2441. }
  2442. mask = ints & ATH9K_INT_COMMON;
  2443. mask2 = 0;
  2444. if (ints & ATH9K_INT_TX) {
  2445. if (ah->txok_interrupt_mask)
  2446. mask |= AR_IMR_TXOK;
  2447. if (ah->txdesc_interrupt_mask)
  2448. mask |= AR_IMR_TXDESC;
  2449. if (ah->txerr_interrupt_mask)
  2450. mask |= AR_IMR_TXERR;
  2451. if (ah->txeol_interrupt_mask)
  2452. mask |= AR_IMR_TXEOL;
  2453. }
  2454. if (ints & ATH9K_INT_RX) {
  2455. mask |= AR_IMR_RXERR;
  2456. if (ah->config.intr_mitigation)
  2457. mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
  2458. else
  2459. mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
  2460. if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  2461. mask |= AR_IMR_GENTMR;
  2462. }
  2463. if (ints & (ATH9K_INT_BMISC)) {
  2464. mask |= AR_IMR_BCNMISC;
  2465. if (ints & ATH9K_INT_TIM)
  2466. mask2 |= AR_IMR_S2_TIM;
  2467. if (ints & ATH9K_INT_DTIM)
  2468. mask2 |= AR_IMR_S2_DTIM;
  2469. if (ints & ATH9K_INT_DTIMSYNC)
  2470. mask2 |= AR_IMR_S2_DTIMSYNC;
  2471. if (ints & ATH9K_INT_CABEND)
  2472. mask2 |= AR_IMR_S2_CABEND;
  2473. if (ints & ATH9K_INT_TSFOOR)
  2474. mask2 |= AR_IMR_S2_TSFOOR;
  2475. }
  2476. if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
  2477. mask |= AR_IMR_BCNMISC;
  2478. if (ints & ATH9K_INT_GTT)
  2479. mask2 |= AR_IMR_S2_GTT;
  2480. if (ints & ATH9K_INT_CST)
  2481. mask2 |= AR_IMR_S2_CST;
  2482. }
  2483. ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
  2484. REG_WRITE(ah, AR_IMR, mask);
  2485. mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
  2486. AR_IMR_S2_DTIM |
  2487. AR_IMR_S2_DTIMSYNC |
  2488. AR_IMR_S2_CABEND |
  2489. AR_IMR_S2_CABTO |
  2490. AR_IMR_S2_TSFOOR |
  2491. AR_IMR_S2_GTT | AR_IMR_S2_CST);
  2492. REG_WRITE(ah, AR_IMR_S2, mask | mask2);
  2493. ah->mask_reg = ints;
  2494. if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  2495. if (ints & ATH9K_INT_TIM_TIMER)
  2496. REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
  2497. else
  2498. REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
  2499. }
  2500. if (ints & ATH9K_INT_GLOBAL) {
  2501. ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
  2502. REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
  2503. if (!AR_SREV_9100(ah)) {
  2504. REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
  2505. AR_INTR_MAC_IRQ);
  2506. REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
  2507. REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
  2508. AR_INTR_SYNC_DEFAULT);
  2509. REG_WRITE(ah, AR_INTR_SYNC_MASK,
  2510. AR_INTR_SYNC_DEFAULT);
  2511. }
  2512. ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
  2513. REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
  2514. }
  2515. return omask;
  2516. }
  2517. EXPORT_SYMBOL(ath9k_hw_set_interrupts);
  2518. /*******************/
  2519. /* Beacon Handling */
  2520. /*******************/
  2521. void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
  2522. {
  2523. int flags = 0;
  2524. ah->beacon_interval = beacon_period;
  2525. switch (ah->opmode) {
  2526. case NL80211_IFTYPE_STATION:
  2527. case NL80211_IFTYPE_MONITOR:
  2528. REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
  2529. REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
  2530. REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
  2531. flags |= AR_TBTT_TIMER_EN;
  2532. break;
  2533. case NL80211_IFTYPE_ADHOC:
  2534. case NL80211_IFTYPE_MESH_POINT:
  2535. REG_SET_BIT(ah, AR_TXCFG,
  2536. AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
  2537. REG_WRITE(ah, AR_NEXT_NDP_TIMER,
  2538. TU_TO_USEC(next_beacon +
  2539. (ah->atim_window ? ah->
  2540. atim_window : 1)));
  2541. flags |= AR_NDP_TIMER_EN;
  2542. case NL80211_IFTYPE_AP:
  2543. REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
  2544. REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
  2545. TU_TO_USEC(next_beacon -
  2546. ah->config.
  2547. dma_beacon_response_time));
  2548. REG_WRITE(ah, AR_NEXT_SWBA,
  2549. TU_TO_USEC(next_beacon -
  2550. ah->config.
  2551. sw_beacon_response_time));
  2552. flags |=
  2553. AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
  2554. break;
  2555. default:
  2556. ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
  2557. "%s: unsupported opmode: %d\n",
  2558. __func__, ah->opmode);
  2559. return;
  2560. break;
  2561. }
  2562. REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
  2563. REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
  2564. REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
  2565. REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
  2566. beacon_period &= ~ATH9K_BEACON_ENA;
  2567. if (beacon_period & ATH9K_BEACON_RESET_TSF) {
  2568. ath9k_hw_reset_tsf(ah);
  2569. }
  2570. REG_SET_BIT(ah, AR_TIMER_MODE, flags);
  2571. }
  2572. EXPORT_SYMBOL(ath9k_hw_beaconinit);
  2573. void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
  2574. const struct ath9k_beacon_state *bs)
  2575. {
  2576. u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
  2577. struct ath9k_hw_capabilities *pCap = &ah->caps;
  2578. struct ath_common *common = ath9k_hw_common(ah);
  2579. REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
  2580. REG_WRITE(ah, AR_BEACON_PERIOD,
  2581. TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
  2582. REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
  2583. TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
  2584. REG_RMW_FIELD(ah, AR_RSSI_THR,
  2585. AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
  2586. beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
  2587. if (bs->bs_sleepduration > beaconintval)
  2588. beaconintval = bs->bs_sleepduration;
  2589. dtimperiod = bs->bs_dtimperiod;
  2590. if (bs->bs_sleepduration > dtimperiod)
  2591. dtimperiod = bs->bs_sleepduration;
  2592. if (beaconintval == dtimperiod)
  2593. nextTbtt = bs->bs_nextdtim;
  2594. else
  2595. nextTbtt = bs->bs_nexttbtt;
  2596. ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
  2597. ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
  2598. ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
  2599. ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
  2600. REG_WRITE(ah, AR_NEXT_DTIM,
  2601. TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
  2602. REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
  2603. REG_WRITE(ah, AR_SLEEP1,
  2604. SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
  2605. | AR_SLEEP1_ASSUME_DTIM);
  2606. if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
  2607. beacontimeout = (BEACON_TIMEOUT_VAL << 3);
  2608. else
  2609. beacontimeout = MIN_BEACON_TIMEOUT_VAL;
  2610. REG_WRITE(ah, AR_SLEEP2,
  2611. SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
  2612. REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
  2613. REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
  2614. REG_SET_BIT(ah, AR_TIMER_MODE,
  2615. AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
  2616. AR_DTIM_TIMER_EN);
  2617. /* TSF Out of Range Threshold */
  2618. REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
  2619. }
  2620. EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
  2621. /*******************/
  2622. /* HW Capabilities */
  2623. /*******************/
  2624. int ath9k_hw_fill_cap_info(struct ath_hw *ah)
  2625. {
  2626. struct ath9k_hw_capabilities *pCap = &ah->caps;
  2627. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  2628. struct ath_common *common = ath9k_hw_common(ah);
  2629. struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
  2630. u16 capField = 0, eeval;
  2631. eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
  2632. regulatory->current_rd = eeval;
  2633. eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
  2634. if (AR_SREV_9285_10_OR_LATER(ah))
  2635. eeval |= AR9285_RDEXT_DEFAULT;
  2636. regulatory->current_rd_ext = eeval;
  2637. capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
  2638. if (ah->opmode != NL80211_IFTYPE_AP &&
  2639. ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
  2640. if (regulatory->current_rd == 0x64 ||
  2641. regulatory->current_rd == 0x65)
  2642. regulatory->current_rd += 5;
  2643. else if (regulatory->current_rd == 0x41)
  2644. regulatory->current_rd = 0x43;
  2645. ath_print(common, ATH_DBG_REGULATORY,
  2646. "regdomain mapped to 0x%x\n", regulatory->current_rd);
  2647. }
  2648. eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
  2649. if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
  2650. ath_print(common, ATH_DBG_FATAL,
  2651. "no band has been marked as supported in EEPROM.\n");
  2652. return -EINVAL;
  2653. }
  2654. bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
  2655. if (eeval & AR5416_OPFLAGS_11A) {
  2656. set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
  2657. if (ah->config.ht_enable) {
  2658. if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
  2659. set_bit(ATH9K_MODE_11NA_HT20,
  2660. pCap->wireless_modes);
  2661. if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
  2662. set_bit(ATH9K_MODE_11NA_HT40PLUS,
  2663. pCap->wireless_modes);
  2664. set_bit(ATH9K_MODE_11NA_HT40MINUS,
  2665. pCap->wireless_modes);
  2666. }
  2667. }
  2668. }
  2669. if (eeval & AR5416_OPFLAGS_11G) {
  2670. set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
  2671. if (ah->config.ht_enable) {
  2672. if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
  2673. set_bit(ATH9K_MODE_11NG_HT20,
  2674. pCap->wireless_modes);
  2675. if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
  2676. set_bit(ATH9K_MODE_11NG_HT40PLUS,
  2677. pCap->wireless_modes);
  2678. set_bit(ATH9K_MODE_11NG_HT40MINUS,
  2679. pCap->wireless_modes);
  2680. }
  2681. }
  2682. }
  2683. pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
  2684. /*
  2685. * For AR9271 we will temporarilly uses the rx chainmax as read from
  2686. * the EEPROM.
  2687. */
  2688. if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
  2689. !(eeval & AR5416_OPFLAGS_11A) &&
  2690. !(AR_SREV_9271(ah)))
  2691. /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
  2692. pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
  2693. else
  2694. /* Use rx_chainmask from EEPROM. */
  2695. pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
  2696. if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
  2697. ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
  2698. pCap->low_2ghz_chan = 2312;
  2699. pCap->high_2ghz_chan = 2732;
  2700. pCap->low_5ghz_chan = 4920;
  2701. pCap->high_5ghz_chan = 6100;
  2702. pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
  2703. pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
  2704. pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
  2705. pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
  2706. pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
  2707. pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
  2708. if (ah->config.ht_enable)
  2709. pCap->hw_caps |= ATH9K_HW_CAP_HT;
  2710. else
  2711. pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
  2712. pCap->hw_caps |= ATH9K_HW_CAP_GTT;
  2713. pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
  2714. pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
  2715. pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
  2716. if (capField & AR_EEPROM_EEPCAP_MAXQCU)
  2717. pCap->total_queues =
  2718. MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
  2719. else
  2720. pCap->total_queues = ATH9K_NUM_TX_QUEUES;
  2721. if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
  2722. pCap->keycache_size =
  2723. 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
  2724. else
  2725. pCap->keycache_size = AR_KEYTABLE_SIZE;
  2726. pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
  2727. if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
  2728. pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
  2729. else
  2730. pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
  2731. if (AR_SREV_9285_10_OR_LATER(ah))
  2732. pCap->num_gpio_pins = AR9285_NUM_GPIO;
  2733. else if (AR_SREV_9280_10_OR_LATER(ah))
  2734. pCap->num_gpio_pins = AR928X_NUM_GPIO;
  2735. else
  2736. pCap->num_gpio_pins = AR_NUM_GPIO;
  2737. if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
  2738. pCap->hw_caps |= ATH9K_HW_CAP_CST;
  2739. pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
  2740. } else {
  2741. pCap->rts_aggr_limit = (8 * 1024);
  2742. }
  2743. pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
  2744. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  2745. ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
  2746. if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
  2747. ah->rfkill_gpio =
  2748. MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
  2749. ah->rfkill_polarity =
  2750. MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
  2751. pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
  2752. }
  2753. #endif
  2754. pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
  2755. if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
  2756. pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
  2757. else
  2758. pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
  2759. if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
  2760. pCap->reg_cap =
  2761. AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
  2762. AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
  2763. AR_EEPROM_EEREGCAP_EN_KK_U2 |
  2764. AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
  2765. } else {
  2766. pCap->reg_cap =
  2767. AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
  2768. AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
  2769. }
  2770. /* Advertise midband for AR5416 with FCC midband set in eeprom */
  2771. if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
  2772. AR_SREV_5416(ah))
  2773. pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
  2774. pCap->num_antcfg_5ghz =
  2775. ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
  2776. pCap->num_antcfg_2ghz =
  2777. ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
  2778. if (AR_SREV_9280_10_OR_LATER(ah) &&
  2779. ath9k_hw_btcoex_supported(ah)) {
  2780. btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
  2781. btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
  2782. if (AR_SREV_9285(ah)) {
  2783. btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
  2784. btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
  2785. } else {
  2786. btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
  2787. }
  2788. } else {
  2789. btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
  2790. }
  2791. return 0;
  2792. }
  2793. bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
  2794. u32 capability, u32 *result)
  2795. {
  2796. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  2797. switch (type) {
  2798. case ATH9K_CAP_CIPHER:
  2799. switch (capability) {
  2800. case ATH9K_CIPHER_AES_CCM:
  2801. case ATH9K_CIPHER_AES_OCB:
  2802. case ATH9K_CIPHER_TKIP:
  2803. case ATH9K_CIPHER_WEP:
  2804. case ATH9K_CIPHER_MIC:
  2805. case ATH9K_CIPHER_CLR:
  2806. return true;
  2807. default:
  2808. return false;
  2809. }
  2810. case ATH9K_CAP_TKIP_MIC:
  2811. switch (capability) {
  2812. case 0:
  2813. return true;
  2814. case 1:
  2815. return (ah->sta_id1_defaults &
  2816. AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
  2817. false;
  2818. }
  2819. case ATH9K_CAP_TKIP_SPLIT:
  2820. return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
  2821. false : true;
  2822. case ATH9K_CAP_DIVERSITY:
  2823. return (REG_READ(ah, AR_PHY_CCK_DETECT) &
  2824. AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
  2825. true : false;
  2826. case ATH9K_CAP_MCAST_KEYSRCH:
  2827. switch (capability) {
  2828. case 0:
  2829. return true;
  2830. case 1:
  2831. if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
  2832. return false;
  2833. } else {
  2834. return (ah->sta_id1_defaults &
  2835. AR_STA_ID1_MCAST_KSRCH) ? true :
  2836. false;
  2837. }
  2838. }
  2839. return false;
  2840. case ATH9K_CAP_TXPOW:
  2841. switch (capability) {
  2842. case 0:
  2843. return 0;
  2844. case 1:
  2845. *result = regulatory->power_limit;
  2846. return 0;
  2847. case 2:
  2848. *result = regulatory->max_power_level;
  2849. return 0;
  2850. case 3:
  2851. *result = regulatory->tp_scale;
  2852. return 0;
  2853. }
  2854. return false;
  2855. case ATH9K_CAP_DS:
  2856. return (AR_SREV_9280_20_OR_LATER(ah) &&
  2857. (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
  2858. ? false : true;
  2859. default:
  2860. return false;
  2861. }
  2862. }
  2863. EXPORT_SYMBOL(ath9k_hw_getcapability);
  2864. bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
  2865. u32 capability, u32 setting, int *status)
  2866. {
  2867. u32 v;
  2868. switch (type) {
  2869. case ATH9K_CAP_TKIP_MIC:
  2870. if (setting)
  2871. ah->sta_id1_defaults |=
  2872. AR_STA_ID1_CRPT_MIC_ENABLE;
  2873. else
  2874. ah->sta_id1_defaults &=
  2875. ~AR_STA_ID1_CRPT_MIC_ENABLE;
  2876. return true;
  2877. case ATH9K_CAP_DIVERSITY:
  2878. v = REG_READ(ah, AR_PHY_CCK_DETECT);
  2879. if (setting)
  2880. v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
  2881. else
  2882. v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
  2883. REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
  2884. return true;
  2885. case ATH9K_CAP_MCAST_KEYSRCH:
  2886. if (setting)
  2887. ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
  2888. else
  2889. ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
  2890. return true;
  2891. default:
  2892. return false;
  2893. }
  2894. }
  2895. EXPORT_SYMBOL(ath9k_hw_setcapability);
  2896. /****************************/
  2897. /* GPIO / RFKILL / Antennae */
  2898. /****************************/
  2899. static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
  2900. u32 gpio, u32 type)
  2901. {
  2902. int addr;
  2903. u32 gpio_shift, tmp;
  2904. if (gpio > 11)
  2905. addr = AR_GPIO_OUTPUT_MUX3;
  2906. else if (gpio > 5)
  2907. addr = AR_GPIO_OUTPUT_MUX2;
  2908. else
  2909. addr = AR_GPIO_OUTPUT_MUX1;
  2910. gpio_shift = (gpio % 6) * 5;
  2911. if (AR_SREV_9280_20_OR_LATER(ah)
  2912. || (addr != AR_GPIO_OUTPUT_MUX1)) {
  2913. REG_RMW(ah, addr, (type << gpio_shift),
  2914. (0x1f << gpio_shift));
  2915. } else {
  2916. tmp = REG_READ(ah, addr);
  2917. tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
  2918. tmp &= ~(0x1f << gpio_shift);
  2919. tmp |= (type << gpio_shift);
  2920. REG_WRITE(ah, addr, tmp);
  2921. }
  2922. }
  2923. void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
  2924. {
  2925. u32 gpio_shift;
  2926. BUG_ON(gpio >= ah->caps.num_gpio_pins);
  2927. gpio_shift = gpio << 1;
  2928. REG_RMW(ah,
  2929. AR_GPIO_OE_OUT,
  2930. (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
  2931. (AR_GPIO_OE_OUT_DRV << gpio_shift));
  2932. }
  2933. EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
  2934. u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
  2935. {
  2936. #define MS_REG_READ(x, y) \
  2937. (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
  2938. if (gpio >= ah->caps.num_gpio_pins)
  2939. return 0xffffffff;
  2940. if (AR_SREV_9287_10_OR_LATER(ah))
  2941. return MS_REG_READ(AR9287, gpio) != 0;
  2942. else if (AR_SREV_9285_10_OR_LATER(ah))
  2943. return MS_REG_READ(AR9285, gpio) != 0;
  2944. else if (AR_SREV_9280_10_OR_LATER(ah))
  2945. return MS_REG_READ(AR928X, gpio) != 0;
  2946. else
  2947. return MS_REG_READ(AR, gpio) != 0;
  2948. }
  2949. EXPORT_SYMBOL(ath9k_hw_gpio_get);
  2950. void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
  2951. u32 ah_signal_type)
  2952. {
  2953. u32 gpio_shift;
  2954. ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
  2955. gpio_shift = 2 * gpio;
  2956. REG_RMW(ah,
  2957. AR_GPIO_OE_OUT,
  2958. (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
  2959. (AR_GPIO_OE_OUT_DRV << gpio_shift));
  2960. }
  2961. EXPORT_SYMBOL(ath9k_hw_cfg_output);
  2962. void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
  2963. {
  2964. REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
  2965. AR_GPIO_BIT(gpio));
  2966. }
  2967. EXPORT_SYMBOL(ath9k_hw_set_gpio);
  2968. u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
  2969. {
  2970. return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
  2971. }
  2972. EXPORT_SYMBOL(ath9k_hw_getdefantenna);
  2973. void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
  2974. {
  2975. REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
  2976. }
  2977. EXPORT_SYMBOL(ath9k_hw_setantenna);
  2978. /*********************/
  2979. /* General Operation */
  2980. /*********************/
  2981. u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
  2982. {
  2983. u32 bits = REG_READ(ah, AR_RX_FILTER);
  2984. u32 phybits = REG_READ(ah, AR_PHY_ERR);
  2985. if (phybits & AR_PHY_ERR_RADAR)
  2986. bits |= ATH9K_RX_FILTER_PHYRADAR;
  2987. if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
  2988. bits |= ATH9K_RX_FILTER_PHYERR;
  2989. return bits;
  2990. }
  2991. EXPORT_SYMBOL(ath9k_hw_getrxfilter);
  2992. void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
  2993. {
  2994. u32 phybits;
  2995. REG_WRITE(ah, AR_RX_FILTER, bits);
  2996. phybits = 0;
  2997. if (bits & ATH9K_RX_FILTER_PHYRADAR)
  2998. phybits |= AR_PHY_ERR_RADAR;
  2999. if (bits & ATH9K_RX_FILTER_PHYERR)
  3000. phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
  3001. REG_WRITE(ah, AR_PHY_ERR, phybits);
  3002. if (phybits)
  3003. REG_WRITE(ah, AR_RXCFG,
  3004. REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
  3005. else
  3006. REG_WRITE(ah, AR_RXCFG,
  3007. REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
  3008. }
  3009. EXPORT_SYMBOL(ath9k_hw_setrxfilter);
  3010. bool ath9k_hw_phy_disable(struct ath_hw *ah)
  3011. {
  3012. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
  3013. return false;
  3014. ath9k_hw_init_pll(ah, NULL);
  3015. return true;
  3016. }
  3017. EXPORT_SYMBOL(ath9k_hw_phy_disable);
  3018. bool ath9k_hw_disable(struct ath_hw *ah)
  3019. {
  3020. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
  3021. return false;
  3022. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
  3023. return false;
  3024. ath9k_hw_init_pll(ah, NULL);
  3025. return true;
  3026. }
  3027. EXPORT_SYMBOL(ath9k_hw_disable);
  3028. void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
  3029. {
  3030. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  3031. struct ath9k_channel *chan = ah->curchan;
  3032. struct ieee80211_channel *channel = chan->chan;
  3033. regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
  3034. ah->eep_ops->set_txpower(ah, chan,
  3035. ath9k_regd_get_ctl(regulatory, chan),
  3036. channel->max_antenna_gain * 2,
  3037. channel->max_power * 2,
  3038. min((u32) MAX_RATE_POWER,
  3039. (u32) regulatory->power_limit));
  3040. }
  3041. EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
  3042. void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
  3043. {
  3044. memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
  3045. }
  3046. EXPORT_SYMBOL(ath9k_hw_setmac);
  3047. void ath9k_hw_setopmode(struct ath_hw *ah)
  3048. {
  3049. ath9k_hw_set_operating_mode(ah, ah->opmode);
  3050. }
  3051. EXPORT_SYMBOL(ath9k_hw_setopmode);
  3052. void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
  3053. {
  3054. REG_WRITE(ah, AR_MCAST_FIL0, filter0);
  3055. REG_WRITE(ah, AR_MCAST_FIL1, filter1);
  3056. }
  3057. EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
  3058. void ath9k_hw_write_associd(struct ath_hw *ah)
  3059. {
  3060. struct ath_common *common = ath9k_hw_common(ah);
  3061. REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
  3062. REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
  3063. ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
  3064. }
  3065. EXPORT_SYMBOL(ath9k_hw_write_associd);
  3066. u64 ath9k_hw_gettsf64(struct ath_hw *ah)
  3067. {
  3068. u64 tsf;
  3069. tsf = REG_READ(ah, AR_TSF_U32);
  3070. tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
  3071. return tsf;
  3072. }
  3073. EXPORT_SYMBOL(ath9k_hw_gettsf64);
  3074. void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
  3075. {
  3076. REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
  3077. REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
  3078. }
  3079. EXPORT_SYMBOL(ath9k_hw_settsf64);
  3080. void ath9k_hw_reset_tsf(struct ath_hw *ah)
  3081. {
  3082. if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
  3083. AH_TSF_WRITE_TIMEOUT))
  3084. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
  3085. "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
  3086. REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
  3087. }
  3088. EXPORT_SYMBOL(ath9k_hw_reset_tsf);
  3089. void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
  3090. {
  3091. if (setting)
  3092. ah->misc_mode |= AR_PCU_TX_ADD_TSF;
  3093. else
  3094. ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
  3095. }
  3096. EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
  3097. /*
  3098. * Extend 15-bit time stamp from rx descriptor to
  3099. * a full 64-bit TSF using the current h/w TSF.
  3100. */
  3101. u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
  3102. {
  3103. u64 tsf;
  3104. tsf = ath9k_hw_gettsf64(ah);
  3105. if ((tsf & 0x7fff) < rstamp)
  3106. tsf -= 0x8000;
  3107. return (tsf & ~0x7fff) | rstamp;
  3108. }
  3109. EXPORT_SYMBOL(ath9k_hw_extend_tsf);
  3110. bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
  3111. {
  3112. if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
  3113. ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
  3114. "bad slot time %u\n", us);
  3115. ah->slottime = (u32) -1;
  3116. return false;
  3117. } else {
  3118. REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
  3119. ah->slottime = us;
  3120. return true;
  3121. }
  3122. }
  3123. EXPORT_SYMBOL(ath9k_hw_setslottime);
  3124. void ath9k_hw_set11nmac2040(struct ath_hw *ah)
  3125. {
  3126. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  3127. u32 macmode;
  3128. if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
  3129. macmode = AR_2040_JOINED_RX_CLEAR;
  3130. else
  3131. macmode = 0;
  3132. REG_WRITE(ah, AR_2040_MODE, macmode);
  3133. }
  3134. /* HW Generic timers configuration */
  3135. static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
  3136. {
  3137. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3138. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3139. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3140. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3141. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3142. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3143. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3144. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  3145. {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
  3146. {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
  3147. AR_NDP2_TIMER_MODE, 0x0002},
  3148. {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
  3149. AR_NDP2_TIMER_MODE, 0x0004},
  3150. {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
  3151. AR_NDP2_TIMER_MODE, 0x0008},
  3152. {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
  3153. AR_NDP2_TIMER_MODE, 0x0010},
  3154. {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
  3155. AR_NDP2_TIMER_MODE, 0x0020},
  3156. {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
  3157. AR_NDP2_TIMER_MODE, 0x0040},
  3158. {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
  3159. AR_NDP2_TIMER_MODE, 0x0080}
  3160. };
  3161. /* HW generic timer primitives */
  3162. /* compute and clear index of rightmost 1 */
  3163. static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
  3164. {
  3165. u32 b;
  3166. b = *mask;
  3167. b &= (0-b);
  3168. *mask &= ~b;
  3169. b *= debruijn32;
  3170. b >>= 27;
  3171. return timer_table->gen_timer_index[b];
  3172. }
  3173. u32 ath9k_hw_gettsf32(struct ath_hw *ah)
  3174. {
  3175. return REG_READ(ah, AR_TSF_L32);
  3176. }
  3177. EXPORT_SYMBOL(ath9k_hw_gettsf32);
  3178. struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
  3179. void (*trigger)(void *),
  3180. void (*overflow)(void *),
  3181. void *arg,
  3182. u8 timer_index)
  3183. {
  3184. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  3185. struct ath_gen_timer *timer;
  3186. timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
  3187. if (timer == NULL) {
  3188. ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
  3189. "Failed to allocate memory"
  3190. "for hw timer[%d]\n", timer_index);
  3191. return NULL;
  3192. }
  3193. /* allocate a hardware generic timer slot */
  3194. timer_table->timers[timer_index] = timer;
  3195. timer->index = timer_index;
  3196. timer->trigger = trigger;
  3197. timer->overflow = overflow;
  3198. timer->arg = arg;
  3199. return timer;
  3200. }
  3201. EXPORT_SYMBOL(ath_gen_timer_alloc);
  3202. void ath9k_hw_gen_timer_start(struct ath_hw *ah,
  3203. struct ath_gen_timer *timer,
  3204. u32 timer_next,
  3205. u32 timer_period)
  3206. {
  3207. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  3208. u32 tsf;
  3209. BUG_ON(!timer_period);
  3210. set_bit(timer->index, &timer_table->timer_mask.timer_bits);
  3211. tsf = ath9k_hw_gettsf32(ah);
  3212. ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
  3213. "curent tsf %x period %x"
  3214. "timer_next %x\n", tsf, timer_period, timer_next);
  3215. /*
  3216. * Pull timer_next forward if the current TSF already passed it
  3217. * because of software latency
  3218. */
  3219. if (timer_next < tsf)
  3220. timer_next = tsf + timer_period;
  3221. /*
  3222. * Program generic timer registers
  3223. */
  3224. REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
  3225. timer_next);
  3226. REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
  3227. timer_period);
  3228. REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
  3229. gen_tmr_configuration[timer->index].mode_mask);
  3230. /* Enable both trigger and thresh interrupt masks */
  3231. REG_SET_BIT(ah, AR_IMR_S5,
  3232. (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
  3233. SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
  3234. }
  3235. EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
  3236. void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
  3237. {
  3238. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  3239. if ((timer->index < AR_FIRST_NDP_TIMER) ||
  3240. (timer->index >= ATH_MAX_GEN_TIMER)) {
  3241. return;
  3242. }
  3243. /* Clear generic timer enable bits. */
  3244. REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
  3245. gen_tmr_configuration[timer->index].mode_mask);
  3246. /* Disable both trigger and thresh interrupt masks */
  3247. REG_CLR_BIT(ah, AR_IMR_S5,
  3248. (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
  3249. SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
  3250. clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
  3251. }
  3252. EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
  3253. void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
  3254. {
  3255. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  3256. /* free the hardware generic timer slot */
  3257. timer_table->timers[timer->index] = NULL;
  3258. kfree(timer);
  3259. }
  3260. EXPORT_SYMBOL(ath_gen_timer_free);
  3261. /*
  3262. * Generic Timer Interrupts handling
  3263. */
  3264. void ath_gen_timer_isr(struct ath_hw *ah)
  3265. {
  3266. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  3267. struct ath_gen_timer *timer;
  3268. struct ath_common *common = ath9k_hw_common(ah);
  3269. u32 trigger_mask, thresh_mask, index;
  3270. /* get hardware generic timer interrupt status */
  3271. trigger_mask = ah->intr_gen_timer_trigger;
  3272. thresh_mask = ah->intr_gen_timer_thresh;
  3273. trigger_mask &= timer_table->timer_mask.val;
  3274. thresh_mask &= timer_table->timer_mask.val;
  3275. trigger_mask &= ~thresh_mask;
  3276. while (thresh_mask) {
  3277. index = rightmost_index(timer_table, &thresh_mask);
  3278. timer = timer_table->timers[index];
  3279. BUG_ON(!timer);
  3280. ath_print(common, ATH_DBG_HWTIMER,
  3281. "TSF overflow for Gen timer %d\n", index);
  3282. timer->overflow(timer->arg);
  3283. }
  3284. while (trigger_mask) {
  3285. index = rightmost_index(timer_table, &trigger_mask);
  3286. timer = timer_table->timers[index];
  3287. BUG_ON(!timer);
  3288. ath_print(common, ATH_DBG_HWTIMER,
  3289. "Gen timer[%d] trigger\n", index);
  3290. timer->trigger(timer->arg);
  3291. }
  3292. }
  3293. EXPORT_SYMBOL(ath_gen_timer_isr);
  3294. static struct {
  3295. u32 version;
  3296. const char * name;
  3297. } ath_mac_bb_names[] = {
  3298. /* Devices with external radios */
  3299. { AR_SREV_VERSION_5416_PCI, "5416" },
  3300. { AR_SREV_VERSION_5416_PCIE, "5418" },
  3301. { AR_SREV_VERSION_9100, "9100" },
  3302. { AR_SREV_VERSION_9160, "9160" },
  3303. /* Single-chip solutions */
  3304. { AR_SREV_VERSION_9280, "9280" },
  3305. { AR_SREV_VERSION_9285, "9285" },
  3306. { AR_SREV_VERSION_9287, "9287" },
  3307. { AR_SREV_VERSION_9271, "9271" },
  3308. };
  3309. /* For devices with external radios */
  3310. static struct {
  3311. u16 version;
  3312. const char * name;
  3313. } ath_rf_names[] = {
  3314. { 0, "5133" },
  3315. { AR_RAD5133_SREV_MAJOR, "5133" },
  3316. { AR_RAD5122_SREV_MAJOR, "5122" },
  3317. { AR_RAD2133_SREV_MAJOR, "2133" },
  3318. { AR_RAD2122_SREV_MAJOR, "2122" }
  3319. };
  3320. /*
  3321. * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
  3322. */
  3323. static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
  3324. {
  3325. int i;
  3326. for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
  3327. if (ath_mac_bb_names[i].version == mac_bb_version) {
  3328. return ath_mac_bb_names[i].name;
  3329. }
  3330. }
  3331. return "????";
  3332. }
  3333. /*
  3334. * Return the RF name. "????" is returned if the RF is unknown.
  3335. * Used for devices with external radios.
  3336. */
  3337. static const char *ath9k_hw_rf_name(u16 rf_version)
  3338. {
  3339. int i;
  3340. for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
  3341. if (ath_rf_names[i].version == rf_version) {
  3342. return ath_rf_names[i].name;
  3343. }
  3344. }
  3345. return "????";
  3346. }
  3347. void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
  3348. {
  3349. int used;
  3350. /* chipsets >= AR9280 are single-chip */
  3351. if (AR_SREV_9280_10_OR_LATER(ah)) {
  3352. used = snprintf(hw_name, len,
  3353. "Atheros AR%s Rev:%x",
  3354. ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
  3355. ah->hw_version.macRev);
  3356. }
  3357. else {
  3358. used = snprintf(hw_name, len,
  3359. "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
  3360. ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
  3361. ah->hw_version.macRev,
  3362. ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
  3363. AR_RADIO_SREV_MAJOR)),
  3364. ah->hw_version.phyRev);
  3365. }
  3366. hw_name[used] = '\0';
  3367. }
  3368. EXPORT_SYMBOL(ath9k_hw_name);