es2lan.c 38 KB

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  1. /*******************************************************************************
  2. Intel PRO/1000 Linux driver
  3. Copyright(c) 1999 - 2009 Intel Corporation.
  4. This program is free software; you can redistribute it and/or modify it
  5. under the terms and conditions of the GNU General Public License,
  6. version 2, as published by the Free Software Foundation.
  7. This program is distributed in the hope it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc.,
  13. 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  14. The full GNU General Public License is included in this distribution in
  15. the file called "COPYING".
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20. *******************************************************************************/
  21. /*
  22. * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  23. * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  24. */
  25. #include "e1000.h"
  26. #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
  27. #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
  28. #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
  29. #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
  30. #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
  31. #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
  32. #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
  33. #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  34. #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
  35. #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
  36. #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  37. #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
  38. #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
  39. #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
  40. /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  41. #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
  42. #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
  43. #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
  44. #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
  45. #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
  46. /* PHY Specific Control Register 2 (Page 0, Register 26) */
  47. #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
  48. /* 1=Reverse Auto-Negotiation */
  49. /* MAC Specific Control Register (Page 2, Register 21) */
  50. /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  51. #define GG82563_MSCR_TX_CLK_MASK 0x0007
  52. #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
  53. #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
  54. #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
  55. #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
  56. /* DSP Distance Register (Page 5, Register 26) */
  57. #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
  58. 1 = 50-80M
  59. 2 = 80-110M
  60. 3 = 110-140M
  61. 4 = >140M */
  62. /* Kumeran Mode Control Register (Page 193, Register 16) */
  63. #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
  64. /* Max number of times Kumeran read/write should be validated */
  65. #define GG82563_MAX_KMRN_RETRY 0x5
  66. /* Power Management Control Register (Page 193, Register 20) */
  67. #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
  68. /* 1=Enable SERDES Electrical Idle */
  69. /* In-Band Control Register (Page 194, Register 18) */
  70. #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
  71. /*
  72. * A table for the GG82563 cable length where the range is defined
  73. * with a lower bound at "index" and the upper bound at
  74. * "index + 5".
  75. */
  76. static const u16 e1000_gg82563_cable_length_table[] =
  77. { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
  78. #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  79. ARRAY_SIZE(e1000_gg82563_cable_length_table)
  80. static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  81. static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  82. static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  83. static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  84. static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  85. static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  86. static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  87. static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
  88. static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  89. u16 *data);
  90. static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  91. u16 data);
  92. static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  93. /**
  94. * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  95. * @hw: pointer to the HW structure
  96. **/
  97. static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  98. {
  99. struct e1000_phy_info *phy = &hw->phy;
  100. s32 ret_val;
  101. if (hw->phy.media_type != e1000_media_type_copper) {
  102. phy->type = e1000_phy_none;
  103. return 0;
  104. } else {
  105. phy->ops.power_up = e1000_power_up_phy_copper;
  106. phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
  107. }
  108. phy->addr = 1;
  109. phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  110. phy->reset_delay_us = 100;
  111. phy->type = e1000_phy_gg82563;
  112. /* This can only be done after all function pointers are setup. */
  113. ret_val = e1000e_get_phy_id(hw);
  114. /* Verify phy id */
  115. if (phy->id != GG82563_E_PHY_ID)
  116. return -E1000_ERR_PHY;
  117. return ret_val;
  118. }
  119. /**
  120. * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  121. * @hw: pointer to the HW structure
  122. **/
  123. static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  124. {
  125. struct e1000_nvm_info *nvm = &hw->nvm;
  126. u32 eecd = er32(EECD);
  127. u16 size;
  128. nvm->opcode_bits = 8;
  129. nvm->delay_usec = 1;
  130. switch (nvm->override) {
  131. case e1000_nvm_override_spi_large:
  132. nvm->page_size = 32;
  133. nvm->address_bits = 16;
  134. break;
  135. case e1000_nvm_override_spi_small:
  136. nvm->page_size = 8;
  137. nvm->address_bits = 8;
  138. break;
  139. default:
  140. nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
  141. nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
  142. break;
  143. }
  144. nvm->type = e1000_nvm_eeprom_spi;
  145. size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
  146. E1000_EECD_SIZE_EX_SHIFT);
  147. /*
  148. * Added to a constant, "size" becomes the left-shift value
  149. * for setting word_size.
  150. */
  151. size += NVM_WORD_SIZE_BASE_SHIFT;
  152. /* EEPROM access above 16k is unsupported */
  153. if (size > 14)
  154. size = 14;
  155. nvm->word_size = 1 << size;
  156. return 0;
  157. }
  158. /**
  159. * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
  160. * @hw: pointer to the HW structure
  161. **/
  162. static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
  163. {
  164. struct e1000_hw *hw = &adapter->hw;
  165. struct e1000_mac_info *mac = &hw->mac;
  166. struct e1000_mac_operations *func = &mac->ops;
  167. /* Set media type */
  168. switch (adapter->pdev->device) {
  169. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  170. hw->phy.media_type = e1000_media_type_internal_serdes;
  171. break;
  172. default:
  173. hw->phy.media_type = e1000_media_type_copper;
  174. break;
  175. }
  176. /* Set mta register count */
  177. mac->mta_reg_count = 128;
  178. /* Set rar entry count */
  179. mac->rar_entry_count = E1000_RAR_ENTRIES;
  180. /* Set if manageability features are enabled. */
  181. mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
  182. ? true : false;
  183. /* check for link */
  184. switch (hw->phy.media_type) {
  185. case e1000_media_type_copper:
  186. func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
  187. func->check_for_link = e1000e_check_for_copper_link;
  188. break;
  189. case e1000_media_type_fiber:
  190. func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
  191. func->check_for_link = e1000e_check_for_fiber_link;
  192. break;
  193. case e1000_media_type_internal_serdes:
  194. func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
  195. func->check_for_link = e1000e_check_for_serdes_link;
  196. break;
  197. default:
  198. return -E1000_ERR_CONFIG;
  199. break;
  200. }
  201. return 0;
  202. }
  203. static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
  204. {
  205. struct e1000_hw *hw = &adapter->hw;
  206. s32 rc;
  207. rc = e1000_init_mac_params_80003es2lan(adapter);
  208. if (rc)
  209. return rc;
  210. rc = e1000_init_nvm_params_80003es2lan(hw);
  211. if (rc)
  212. return rc;
  213. rc = e1000_init_phy_params_80003es2lan(hw);
  214. if (rc)
  215. return rc;
  216. return 0;
  217. }
  218. /**
  219. * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
  220. * @hw: pointer to the HW structure
  221. *
  222. * A wrapper to acquire access rights to the correct PHY.
  223. **/
  224. static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
  225. {
  226. u16 mask;
  227. mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
  228. return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
  229. }
  230. /**
  231. * e1000_release_phy_80003es2lan - Release rights to access PHY
  232. * @hw: pointer to the HW structure
  233. *
  234. * A wrapper to release access rights to the correct PHY.
  235. **/
  236. static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
  237. {
  238. u16 mask;
  239. mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
  240. e1000_release_swfw_sync_80003es2lan(hw, mask);
  241. }
  242. /**
  243. * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
  244. * @hw: pointer to the HW structure
  245. *
  246. * Acquire the semaphore to access the Kumeran interface.
  247. *
  248. **/
  249. static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
  250. {
  251. u16 mask;
  252. mask = E1000_SWFW_CSR_SM;
  253. return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
  254. }
  255. /**
  256. * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
  257. * @hw: pointer to the HW structure
  258. *
  259. * Release the semaphore used to access the Kumeran interface
  260. **/
  261. static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
  262. {
  263. u16 mask;
  264. mask = E1000_SWFW_CSR_SM;
  265. e1000_release_swfw_sync_80003es2lan(hw, mask);
  266. }
  267. /**
  268. * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
  269. * @hw: pointer to the HW structure
  270. *
  271. * Acquire the semaphore to access the EEPROM.
  272. **/
  273. static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
  274. {
  275. s32 ret_val;
  276. ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
  277. if (ret_val)
  278. return ret_val;
  279. ret_val = e1000e_acquire_nvm(hw);
  280. if (ret_val)
  281. e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
  282. return ret_val;
  283. }
  284. /**
  285. * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
  286. * @hw: pointer to the HW structure
  287. *
  288. * Release the semaphore used to access the EEPROM.
  289. **/
  290. static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
  291. {
  292. e1000e_release_nvm(hw);
  293. e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
  294. }
  295. /**
  296. * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
  297. * @hw: pointer to the HW structure
  298. * @mask: specifies which semaphore to acquire
  299. *
  300. * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
  301. * will also specify which port we're acquiring the lock for.
  302. **/
  303. static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
  304. {
  305. u32 swfw_sync;
  306. u32 swmask = mask;
  307. u32 fwmask = mask << 16;
  308. s32 i = 0;
  309. s32 timeout = 50;
  310. while (i < timeout) {
  311. if (e1000e_get_hw_semaphore(hw))
  312. return -E1000_ERR_SWFW_SYNC;
  313. swfw_sync = er32(SW_FW_SYNC);
  314. if (!(swfw_sync & (fwmask | swmask)))
  315. break;
  316. /*
  317. * Firmware currently using resource (fwmask)
  318. * or other software thread using resource (swmask)
  319. */
  320. e1000e_put_hw_semaphore(hw);
  321. mdelay(5);
  322. i++;
  323. }
  324. if (i == timeout) {
  325. e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
  326. return -E1000_ERR_SWFW_SYNC;
  327. }
  328. swfw_sync |= swmask;
  329. ew32(SW_FW_SYNC, swfw_sync);
  330. e1000e_put_hw_semaphore(hw);
  331. return 0;
  332. }
  333. /**
  334. * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
  335. * @hw: pointer to the HW structure
  336. * @mask: specifies which semaphore to acquire
  337. *
  338. * Release the SW/FW semaphore used to access the PHY or NVM. The mask
  339. * will also specify which port we're releasing the lock for.
  340. **/
  341. static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
  342. {
  343. u32 swfw_sync;
  344. while (e1000e_get_hw_semaphore(hw) != 0);
  345. /* Empty */
  346. swfw_sync = er32(SW_FW_SYNC);
  347. swfw_sync &= ~mask;
  348. ew32(SW_FW_SYNC, swfw_sync);
  349. e1000e_put_hw_semaphore(hw);
  350. }
  351. /**
  352. * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
  353. * @hw: pointer to the HW structure
  354. * @offset: offset of the register to read
  355. * @data: pointer to the data returned from the operation
  356. *
  357. * Read the GG82563 PHY register.
  358. **/
  359. static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  360. u32 offset, u16 *data)
  361. {
  362. s32 ret_val;
  363. u32 page_select;
  364. u16 temp;
  365. ret_val = e1000_acquire_phy_80003es2lan(hw);
  366. if (ret_val)
  367. return ret_val;
  368. /* Select Configuration Page */
  369. if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
  370. page_select = GG82563_PHY_PAGE_SELECT;
  371. } else {
  372. /*
  373. * Use Alternative Page Select register to access
  374. * registers 30 and 31
  375. */
  376. page_select = GG82563_PHY_PAGE_SELECT_ALT;
  377. }
  378. temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
  379. ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
  380. if (ret_val) {
  381. e1000_release_phy_80003es2lan(hw);
  382. return ret_val;
  383. }
  384. /*
  385. * The "ready" bit in the MDIC register may be incorrectly set
  386. * before the device has completed the "Page Select" MDI
  387. * transaction. So we wait 200us after each MDI command...
  388. */
  389. udelay(200);
  390. /* ...and verify the command was successful. */
  391. ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
  392. if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
  393. ret_val = -E1000_ERR_PHY;
  394. e1000_release_phy_80003es2lan(hw);
  395. return ret_val;
  396. }
  397. udelay(200);
  398. ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
  399. data);
  400. udelay(200);
  401. e1000_release_phy_80003es2lan(hw);
  402. return ret_val;
  403. }
  404. /**
  405. * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
  406. * @hw: pointer to the HW structure
  407. * @offset: offset of the register to read
  408. * @data: value to write to the register
  409. *
  410. * Write to the GG82563 PHY register.
  411. **/
  412. static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
  413. u32 offset, u16 data)
  414. {
  415. s32 ret_val;
  416. u32 page_select;
  417. u16 temp;
  418. ret_val = e1000_acquire_phy_80003es2lan(hw);
  419. if (ret_val)
  420. return ret_val;
  421. /* Select Configuration Page */
  422. if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
  423. page_select = GG82563_PHY_PAGE_SELECT;
  424. } else {
  425. /*
  426. * Use Alternative Page Select register to access
  427. * registers 30 and 31
  428. */
  429. page_select = GG82563_PHY_PAGE_SELECT_ALT;
  430. }
  431. temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
  432. ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
  433. if (ret_val) {
  434. e1000_release_phy_80003es2lan(hw);
  435. return ret_val;
  436. }
  437. /*
  438. * The "ready" bit in the MDIC register may be incorrectly set
  439. * before the device has completed the "Page Select" MDI
  440. * transaction. So we wait 200us after each MDI command...
  441. */
  442. udelay(200);
  443. /* ...and verify the command was successful. */
  444. ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
  445. if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
  446. e1000_release_phy_80003es2lan(hw);
  447. return -E1000_ERR_PHY;
  448. }
  449. udelay(200);
  450. ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
  451. data);
  452. udelay(200);
  453. e1000_release_phy_80003es2lan(hw);
  454. return ret_val;
  455. }
  456. /**
  457. * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
  458. * @hw: pointer to the HW structure
  459. * @offset: offset of the register to read
  460. * @words: number of words to write
  461. * @data: buffer of data to write to the NVM
  462. *
  463. * Write "words" of data to the ESB2 NVM.
  464. **/
  465. static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
  466. u16 words, u16 *data)
  467. {
  468. return e1000e_write_nvm_spi(hw, offset, words, data);
  469. }
  470. /**
  471. * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
  472. * @hw: pointer to the HW structure
  473. *
  474. * Wait a specific amount of time for manageability processes to complete.
  475. * This is a function pointer entry point called by the phy module.
  476. **/
  477. static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
  478. {
  479. s32 timeout = PHY_CFG_TIMEOUT;
  480. u32 mask = E1000_NVM_CFG_DONE_PORT_0;
  481. if (hw->bus.func == 1)
  482. mask = E1000_NVM_CFG_DONE_PORT_1;
  483. while (timeout) {
  484. if (er32(EEMNGCTL) & mask)
  485. break;
  486. msleep(1);
  487. timeout--;
  488. }
  489. if (!timeout) {
  490. e_dbg("MNG configuration cycle has not completed.\n");
  491. return -E1000_ERR_RESET;
  492. }
  493. return 0;
  494. }
  495. /**
  496. * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
  497. * @hw: pointer to the HW structure
  498. *
  499. * Force the speed and duplex settings onto the PHY. This is a
  500. * function pointer entry point called by the phy module.
  501. **/
  502. static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
  503. {
  504. s32 ret_val;
  505. u16 phy_data;
  506. bool link;
  507. /*
  508. * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
  509. * forced whenever speed and duplex are forced.
  510. */
  511. ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  512. if (ret_val)
  513. return ret_val;
  514. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
  515. ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
  516. if (ret_val)
  517. return ret_val;
  518. e_dbg("GG82563 PSCR: %X\n", phy_data);
  519. ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
  520. if (ret_val)
  521. return ret_val;
  522. e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
  523. /* Reset the phy to commit changes. */
  524. phy_data |= MII_CR_RESET;
  525. ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
  526. if (ret_val)
  527. return ret_val;
  528. udelay(1);
  529. if (hw->phy.autoneg_wait_to_complete) {
  530. e_dbg("Waiting for forced speed/duplex link "
  531. "on GG82563 phy.\n");
  532. ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
  533. 100000, &link);
  534. if (ret_val)
  535. return ret_val;
  536. if (!link) {
  537. /*
  538. * We didn't get link.
  539. * Reset the DSP and cross our fingers.
  540. */
  541. ret_val = e1000e_phy_reset_dsp(hw);
  542. if (ret_val)
  543. return ret_val;
  544. }
  545. /* Try once more */
  546. ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
  547. 100000, &link);
  548. if (ret_val)
  549. return ret_val;
  550. }
  551. ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  552. if (ret_val)
  553. return ret_val;
  554. /*
  555. * Resetting the phy means we need to verify the TX_CLK corresponds
  556. * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
  557. */
  558. phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
  559. if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
  560. phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
  561. else
  562. phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
  563. /*
  564. * In addition, we must re-enable CRS on Tx for both half and full
  565. * duplex.
  566. */
  567. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  568. ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  569. return ret_val;
  570. }
  571. /**
  572. * e1000_get_cable_length_80003es2lan - Set approximate cable length
  573. * @hw: pointer to the HW structure
  574. *
  575. * Find the approximate cable length as measured by the GG82563 PHY.
  576. * This is a function pointer entry point called by the phy module.
  577. **/
  578. static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
  579. {
  580. struct e1000_phy_info *phy = &hw->phy;
  581. s32 ret_val = 0;
  582. u16 phy_data, index;
  583. ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
  584. if (ret_val)
  585. goto out;
  586. index = phy_data & GG82563_DSPD_CABLE_LENGTH;
  587. if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
  588. ret_val = -E1000_ERR_PHY;
  589. goto out;
  590. }
  591. phy->min_cable_length = e1000_gg82563_cable_length_table[index];
  592. phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
  593. phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
  594. out:
  595. return ret_val;
  596. }
  597. /**
  598. * e1000_get_link_up_info_80003es2lan - Report speed and duplex
  599. * @hw: pointer to the HW structure
  600. * @speed: pointer to speed buffer
  601. * @duplex: pointer to duplex buffer
  602. *
  603. * Retrieve the current speed and duplex configuration.
  604. **/
  605. static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  606. u16 *duplex)
  607. {
  608. s32 ret_val;
  609. if (hw->phy.media_type == e1000_media_type_copper) {
  610. ret_val = e1000e_get_speed_and_duplex_copper(hw,
  611. speed,
  612. duplex);
  613. hw->phy.ops.cfg_on_link_up(hw);
  614. } else {
  615. ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
  616. speed,
  617. duplex);
  618. }
  619. return ret_val;
  620. }
  621. /**
  622. * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
  623. * @hw: pointer to the HW structure
  624. *
  625. * Perform a global reset to the ESB2 controller.
  626. **/
  627. static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
  628. {
  629. u32 ctrl, icr;
  630. s32 ret_val;
  631. /*
  632. * Prevent the PCI-E bus from sticking if there is no TLP connection
  633. * on the last TLP read/write transaction when MAC is reset.
  634. */
  635. ret_val = e1000e_disable_pcie_master(hw);
  636. if (ret_val)
  637. e_dbg("PCI-E Master disable polling has failed.\n");
  638. e_dbg("Masking off all interrupts\n");
  639. ew32(IMC, 0xffffffff);
  640. ew32(RCTL, 0);
  641. ew32(TCTL, E1000_TCTL_PSP);
  642. e1e_flush();
  643. msleep(10);
  644. ctrl = er32(CTRL);
  645. ret_val = e1000_acquire_phy_80003es2lan(hw);
  646. e_dbg("Issuing a global reset to MAC\n");
  647. ew32(CTRL, ctrl | E1000_CTRL_RST);
  648. e1000_release_phy_80003es2lan(hw);
  649. ret_val = e1000e_get_auto_rd_done(hw);
  650. if (ret_val)
  651. /* We don't want to continue accessing MAC registers. */
  652. return ret_val;
  653. /* Clear any pending interrupt events. */
  654. ew32(IMC, 0xffffffff);
  655. icr = er32(ICR);
  656. return 0;
  657. }
  658. /**
  659. * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
  660. * @hw: pointer to the HW structure
  661. *
  662. * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
  663. **/
  664. static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
  665. {
  666. struct e1000_mac_info *mac = &hw->mac;
  667. u32 reg_data;
  668. s32 ret_val;
  669. u16 i;
  670. e1000_initialize_hw_bits_80003es2lan(hw);
  671. /* Initialize identification LED */
  672. ret_val = e1000e_id_led_init(hw);
  673. if (ret_val)
  674. e_dbg("Error initializing identification LED\n");
  675. /* This is not fatal and we should not stop init due to this */
  676. /* Disabling VLAN filtering */
  677. e_dbg("Initializing the IEEE VLAN\n");
  678. mac->ops.clear_vfta(hw);
  679. /* Setup the receive address. */
  680. e1000e_init_rx_addrs(hw, mac->rar_entry_count);
  681. /* Zero out the Multicast HASH table */
  682. e_dbg("Zeroing the MTA\n");
  683. for (i = 0; i < mac->mta_reg_count; i++)
  684. E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
  685. /* Setup link and flow control */
  686. ret_val = e1000e_setup_link(hw);
  687. /* Set the transmit descriptor write-back policy */
  688. reg_data = er32(TXDCTL(0));
  689. reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
  690. E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
  691. ew32(TXDCTL(0), reg_data);
  692. /* ...for both queues. */
  693. reg_data = er32(TXDCTL(1));
  694. reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
  695. E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
  696. ew32(TXDCTL(1), reg_data);
  697. /* Enable retransmit on late collisions */
  698. reg_data = er32(TCTL);
  699. reg_data |= E1000_TCTL_RTLC;
  700. ew32(TCTL, reg_data);
  701. /* Configure Gigabit Carry Extend Padding */
  702. reg_data = er32(TCTL_EXT);
  703. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  704. reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
  705. ew32(TCTL_EXT, reg_data);
  706. /* Configure Transmit Inter-Packet Gap */
  707. reg_data = er32(TIPG);
  708. reg_data &= ~E1000_TIPG_IPGT_MASK;
  709. reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
  710. ew32(TIPG, reg_data);
  711. reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
  712. reg_data &= ~0x00100000;
  713. E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
  714. /*
  715. * Clear all of the statistics registers (clear on read). It is
  716. * important that we do this after we have tried to establish link
  717. * because the symbol error count will increment wildly if there
  718. * is no link.
  719. */
  720. e1000_clear_hw_cntrs_80003es2lan(hw);
  721. return ret_val;
  722. }
  723. /**
  724. * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
  725. * @hw: pointer to the HW structure
  726. *
  727. * Initializes required hardware-dependent bits needed for normal operation.
  728. **/
  729. static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
  730. {
  731. u32 reg;
  732. /* Transmit Descriptor Control 0 */
  733. reg = er32(TXDCTL(0));
  734. reg |= (1 << 22);
  735. ew32(TXDCTL(0), reg);
  736. /* Transmit Descriptor Control 1 */
  737. reg = er32(TXDCTL(1));
  738. reg |= (1 << 22);
  739. ew32(TXDCTL(1), reg);
  740. /* Transmit Arbitration Control 0 */
  741. reg = er32(TARC(0));
  742. reg &= ~(0xF << 27); /* 30:27 */
  743. if (hw->phy.media_type != e1000_media_type_copper)
  744. reg &= ~(1 << 20);
  745. ew32(TARC(0), reg);
  746. /* Transmit Arbitration Control 1 */
  747. reg = er32(TARC(1));
  748. if (er32(TCTL) & E1000_TCTL_MULR)
  749. reg &= ~(1 << 28);
  750. else
  751. reg |= (1 << 28);
  752. ew32(TARC(1), reg);
  753. }
  754. /**
  755. * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
  756. * @hw: pointer to the HW structure
  757. *
  758. * Setup some GG82563 PHY registers for obtaining link
  759. **/
  760. static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
  761. {
  762. struct e1000_phy_info *phy = &hw->phy;
  763. s32 ret_val;
  764. u32 ctrl_ext;
  765. u16 data;
  766. ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
  767. if (ret_val)
  768. return ret_val;
  769. data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  770. /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
  771. data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
  772. ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
  773. if (ret_val)
  774. return ret_val;
  775. /*
  776. * Options:
  777. * MDI/MDI-X = 0 (default)
  778. * 0 - Auto for all speeds
  779. * 1 - MDI mode
  780. * 2 - MDI-X mode
  781. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  782. */
  783. ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
  784. if (ret_val)
  785. return ret_val;
  786. data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  787. switch (phy->mdix) {
  788. case 1:
  789. data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  790. break;
  791. case 2:
  792. data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  793. break;
  794. case 0:
  795. default:
  796. data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  797. break;
  798. }
  799. /*
  800. * Options:
  801. * disable_polarity_correction = 0 (default)
  802. * Automatic Correction for Reversed Cable Polarity
  803. * 0 - Disabled
  804. * 1 - Enabled
  805. */
  806. data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  807. if (phy->disable_polarity_correction)
  808. data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  809. ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
  810. if (ret_val)
  811. return ret_val;
  812. /* SW Reset the PHY so all changes take effect */
  813. ret_val = e1000e_commit_phy(hw);
  814. if (ret_val) {
  815. e_dbg("Error Resetting the PHY\n");
  816. return ret_val;
  817. }
  818. /* Bypass Rx and Tx FIFO's */
  819. ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
  820. E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
  821. E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
  822. E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
  823. if (ret_val)
  824. return ret_val;
  825. ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
  826. E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
  827. &data);
  828. if (ret_val)
  829. return ret_val;
  830. data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
  831. ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
  832. E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
  833. data);
  834. if (ret_val)
  835. return ret_val;
  836. ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
  837. if (ret_val)
  838. return ret_val;
  839. data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  840. ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
  841. if (ret_val)
  842. return ret_val;
  843. ctrl_ext = er32(CTRL_EXT);
  844. ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  845. ew32(CTRL_EXT, ctrl_ext);
  846. ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
  847. if (ret_val)
  848. return ret_val;
  849. /*
  850. * Do not init these registers when the HW is in IAMT mode, since the
  851. * firmware will have already initialized them. We only initialize
  852. * them if the HW is not in IAMT mode.
  853. */
  854. if (!e1000e_check_mng_mode(hw)) {
  855. /* Enable Electrical Idle on the PHY */
  856. data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  857. ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
  858. if (ret_val)
  859. return ret_val;
  860. ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
  861. if (ret_val)
  862. return ret_val;
  863. data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  864. ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
  865. if (ret_val)
  866. return ret_val;
  867. }
  868. /*
  869. * Workaround: Disable padding in Kumeran interface in the MAC
  870. * and in the PHY to avoid CRC errors.
  871. */
  872. ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
  873. if (ret_val)
  874. return ret_val;
  875. data |= GG82563_ICR_DIS_PADDING;
  876. ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
  877. if (ret_val)
  878. return ret_val;
  879. return 0;
  880. }
  881. /**
  882. * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
  883. * @hw: pointer to the HW structure
  884. *
  885. * Essentially a wrapper for setting up all things "copper" related.
  886. * This is a function pointer entry point called by the mac module.
  887. **/
  888. static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
  889. {
  890. u32 ctrl;
  891. s32 ret_val;
  892. u16 reg_data;
  893. ctrl = er32(CTRL);
  894. ctrl |= E1000_CTRL_SLU;
  895. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  896. ew32(CTRL, ctrl);
  897. /*
  898. * Set the mac to wait the maximum time between each
  899. * iteration and increase the max iterations when
  900. * polling the phy; this fixes erroneous timeouts at 10Mbps.
  901. */
  902. ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
  903. 0xFFFF);
  904. if (ret_val)
  905. return ret_val;
  906. ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
  907. &reg_data);
  908. if (ret_val)
  909. return ret_val;
  910. reg_data |= 0x3F;
  911. ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
  912. reg_data);
  913. if (ret_val)
  914. return ret_val;
  915. ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
  916. E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
  917. &reg_data);
  918. if (ret_val)
  919. return ret_val;
  920. reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
  921. ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
  922. E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
  923. reg_data);
  924. if (ret_val)
  925. return ret_val;
  926. ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
  927. if (ret_val)
  928. return ret_val;
  929. ret_val = e1000e_setup_copper_link(hw);
  930. return 0;
  931. }
  932. /**
  933. * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
  934. * @hw: pointer to the HW structure
  935. * @duplex: current duplex setting
  936. *
  937. * Configure the KMRN interface by applying last minute quirks for
  938. * 10/100 operation.
  939. **/
  940. static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
  941. {
  942. s32 ret_val = 0;
  943. u16 speed;
  944. u16 duplex;
  945. if (hw->phy.media_type == e1000_media_type_copper) {
  946. ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
  947. &duplex);
  948. if (ret_val)
  949. return ret_val;
  950. if (speed == SPEED_1000)
  951. ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
  952. else
  953. ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
  954. }
  955. return ret_val;
  956. }
  957. /**
  958. * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
  959. * @hw: pointer to the HW structure
  960. * @duplex: current duplex setting
  961. *
  962. * Configure the KMRN interface by applying last minute quirks for
  963. * 10/100 operation.
  964. **/
  965. static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
  966. {
  967. s32 ret_val;
  968. u32 tipg;
  969. u32 i = 0;
  970. u16 reg_data, reg_data2;
  971. reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
  972. ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
  973. E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
  974. reg_data);
  975. if (ret_val)
  976. return ret_val;
  977. /* Configure Transmit Inter-Packet Gap */
  978. tipg = er32(TIPG);
  979. tipg &= ~E1000_TIPG_IPGT_MASK;
  980. tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
  981. ew32(TIPG, tipg);
  982. do {
  983. ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  984. if (ret_val)
  985. return ret_val;
  986. ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
  987. if (ret_val)
  988. return ret_val;
  989. i++;
  990. } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
  991. if (duplex == HALF_DUPLEX)
  992. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  993. else
  994. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  995. ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  996. return 0;
  997. }
  998. /**
  999. * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
  1000. * @hw: pointer to the HW structure
  1001. *
  1002. * Configure the KMRN interface by applying last minute quirks for
  1003. * gigabit operation.
  1004. **/
  1005. static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
  1006. {
  1007. s32 ret_val;
  1008. u16 reg_data, reg_data2;
  1009. u32 tipg;
  1010. u32 i = 0;
  1011. reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
  1012. ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
  1013. E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
  1014. reg_data);
  1015. if (ret_val)
  1016. return ret_val;
  1017. /* Configure Transmit Inter-Packet Gap */
  1018. tipg = er32(TIPG);
  1019. tipg &= ~E1000_TIPG_IPGT_MASK;
  1020. tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
  1021. ew32(TIPG, tipg);
  1022. do {
  1023. ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  1024. if (ret_val)
  1025. return ret_val;
  1026. ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
  1027. if (ret_val)
  1028. return ret_val;
  1029. i++;
  1030. } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
  1031. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  1032. ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  1033. return ret_val;
  1034. }
  1035. /**
  1036. * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
  1037. * @hw: pointer to the HW structure
  1038. * @offset: register offset to be read
  1039. * @data: pointer to the read data
  1040. *
  1041. * Acquire semaphore, then read the PHY register at offset
  1042. * using the kumeran interface. The information retrieved is stored in data.
  1043. * Release the semaphore before exiting.
  1044. **/
  1045. static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  1046. u16 *data)
  1047. {
  1048. u32 kmrnctrlsta;
  1049. s32 ret_val = 0;
  1050. ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
  1051. if (ret_val)
  1052. return ret_val;
  1053. kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
  1054. E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
  1055. ew32(KMRNCTRLSTA, kmrnctrlsta);
  1056. udelay(2);
  1057. kmrnctrlsta = er32(KMRNCTRLSTA);
  1058. *data = (u16)kmrnctrlsta;
  1059. e1000_release_mac_csr_80003es2lan(hw);
  1060. return ret_val;
  1061. }
  1062. /**
  1063. * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
  1064. * @hw: pointer to the HW structure
  1065. * @offset: register offset to write to
  1066. * @data: data to write at register offset
  1067. *
  1068. * Acquire semaphore, then write the data to PHY register
  1069. * at the offset using the kumeran interface. Release semaphore
  1070. * before exiting.
  1071. **/
  1072. static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  1073. u16 data)
  1074. {
  1075. u32 kmrnctrlsta;
  1076. s32 ret_val = 0;
  1077. ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
  1078. if (ret_val)
  1079. return ret_val;
  1080. kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
  1081. E1000_KMRNCTRLSTA_OFFSET) | data;
  1082. ew32(KMRNCTRLSTA, kmrnctrlsta);
  1083. udelay(2);
  1084. e1000_release_mac_csr_80003es2lan(hw);
  1085. return ret_val;
  1086. }
  1087. /**
  1088. * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
  1089. * @hw: pointer to the HW structure
  1090. *
  1091. * In the case of a PHY power down to save power, or to turn off link during a
  1092. * driver unload, or wake on lan is not enabled, remove the link.
  1093. **/
  1094. static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
  1095. {
  1096. /* If the management interface is not enabled, then power down */
  1097. if (!(hw->mac.ops.check_mng_mode(hw) ||
  1098. hw->phy.ops.check_reset_block(hw)))
  1099. e1000_power_down_phy_copper(hw);
  1100. return;
  1101. }
  1102. /**
  1103. * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
  1104. * @hw: pointer to the HW structure
  1105. *
  1106. * Clears the hardware counters by reading the counter registers.
  1107. **/
  1108. static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
  1109. {
  1110. e1000e_clear_hw_cntrs_base(hw);
  1111. er32(PRC64);
  1112. er32(PRC127);
  1113. er32(PRC255);
  1114. er32(PRC511);
  1115. er32(PRC1023);
  1116. er32(PRC1522);
  1117. er32(PTC64);
  1118. er32(PTC127);
  1119. er32(PTC255);
  1120. er32(PTC511);
  1121. er32(PTC1023);
  1122. er32(PTC1522);
  1123. er32(ALGNERRC);
  1124. er32(RXERRC);
  1125. er32(TNCRS);
  1126. er32(CEXTERR);
  1127. er32(TSCTC);
  1128. er32(TSCTFC);
  1129. er32(MGTPRC);
  1130. er32(MGTPDC);
  1131. er32(MGTPTC);
  1132. er32(IAC);
  1133. er32(ICRXOC);
  1134. er32(ICRXPTC);
  1135. er32(ICRXATC);
  1136. er32(ICTXPTC);
  1137. er32(ICTXATC);
  1138. er32(ICTXQEC);
  1139. er32(ICTXQMTC);
  1140. er32(ICRXDMTC);
  1141. }
  1142. static struct e1000_mac_operations es2_mac_ops = {
  1143. .id_led_init = e1000e_id_led_init,
  1144. .check_mng_mode = e1000e_check_mng_mode_generic,
  1145. /* check_for_link dependent on media type */
  1146. .cleanup_led = e1000e_cleanup_led_generic,
  1147. .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
  1148. .get_bus_info = e1000e_get_bus_info_pcie,
  1149. .get_link_up_info = e1000_get_link_up_info_80003es2lan,
  1150. .led_on = e1000e_led_on_generic,
  1151. .led_off = e1000e_led_off_generic,
  1152. .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
  1153. .write_vfta = e1000_write_vfta_generic,
  1154. .clear_vfta = e1000_clear_vfta_generic,
  1155. .reset_hw = e1000_reset_hw_80003es2lan,
  1156. .init_hw = e1000_init_hw_80003es2lan,
  1157. .setup_link = e1000e_setup_link,
  1158. /* setup_physical_interface dependent on media type */
  1159. .setup_led = e1000e_setup_led_generic,
  1160. };
  1161. static struct e1000_phy_operations es2_phy_ops = {
  1162. .acquire = e1000_acquire_phy_80003es2lan,
  1163. .check_polarity = e1000_check_polarity_m88,
  1164. .check_reset_block = e1000e_check_reset_block_generic,
  1165. .commit = e1000e_phy_sw_reset,
  1166. .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
  1167. .get_cfg_done = e1000_get_cfg_done_80003es2lan,
  1168. .get_cable_length = e1000_get_cable_length_80003es2lan,
  1169. .get_info = e1000e_get_phy_info_m88,
  1170. .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
  1171. .release = e1000_release_phy_80003es2lan,
  1172. .reset = e1000e_phy_hw_reset_generic,
  1173. .set_d0_lplu_state = NULL,
  1174. .set_d3_lplu_state = e1000e_set_d3_lplu_state,
  1175. .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
  1176. .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
  1177. };
  1178. static struct e1000_nvm_operations es2_nvm_ops = {
  1179. .acquire = e1000_acquire_nvm_80003es2lan,
  1180. .read = e1000e_read_nvm_eerd,
  1181. .release = e1000_release_nvm_80003es2lan,
  1182. .update = e1000e_update_nvm_checksum_generic,
  1183. .valid_led_default = e1000e_valid_led_default,
  1184. .validate = e1000e_validate_nvm_checksum_generic,
  1185. .write = e1000_write_nvm_80003es2lan,
  1186. };
  1187. struct e1000_info e1000_es2_info = {
  1188. .mac = e1000_80003es2lan,
  1189. .flags = FLAG_HAS_HW_VLAN_FILTER
  1190. | FLAG_HAS_JUMBO_FRAMES
  1191. | FLAG_HAS_WOL
  1192. | FLAG_APME_IN_CTRL3
  1193. | FLAG_RX_CSUM_ENABLED
  1194. | FLAG_HAS_CTRLEXT_ON_LOAD
  1195. | FLAG_RX_NEEDS_RESTART /* errata */
  1196. | FLAG_TARC_SET_BIT_ZERO /* errata */
  1197. | FLAG_APME_CHECK_PORT_B
  1198. | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
  1199. | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
  1200. .pba = 38,
  1201. .max_hw_frame_size = DEFAULT_JUMBO,
  1202. .get_variants = e1000_get_variants_80003es2lan,
  1203. .mac_ops = &es2_mac_ops,
  1204. .phy_ops = &es2_phy_ops,
  1205. .nvm_ops = &es2_nvm_ops,
  1206. };