cnic.c 118 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616
  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2009 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/errno.h>
  15. #include <linux/list.h>
  16. #include <linux/slab.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/netdevice.h>
  20. #include <linux/uio_driver.h>
  21. #include <linux/in.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/delay.h>
  24. #include <linux/ethtool.h>
  25. #include <linux/if_vlan.h>
  26. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  27. #define BCM_VLAN 1
  28. #endif
  29. #include <net/ip.h>
  30. #include <net/tcp.h>
  31. #include <net/route.h>
  32. #include <net/ipv6.h>
  33. #include <net/ip6_route.h>
  34. #include <net/ip6_checksum.h>
  35. #include <scsi/iscsi_if.h>
  36. #include "cnic_if.h"
  37. #include "bnx2.h"
  38. #include "bnx2x_reg.h"
  39. #include "bnx2x_fw_defs.h"
  40. #include "bnx2x_hsi.h"
  41. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  43. #include "cnic.h"
  44. #include "cnic_defs.h"
  45. #define DRV_MODULE_NAME "cnic"
  46. #define PFX DRV_MODULE_NAME ": "
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static DEFINE_RWLOCK(cnic_dev_lock);
  56. static DEFINE_MUTEX(cnic_lock);
  57. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  58. static int cnic_service_bnx2(void *, void *);
  59. static int cnic_service_bnx2x(void *, void *);
  60. static int cnic_ctl(void *, struct cnic_ctl_info *);
  61. static struct cnic_ops cnic_bnx2_ops = {
  62. .cnic_owner = THIS_MODULE,
  63. .cnic_handler = cnic_service_bnx2,
  64. .cnic_ctl = cnic_ctl,
  65. };
  66. static struct cnic_ops cnic_bnx2x_ops = {
  67. .cnic_owner = THIS_MODULE,
  68. .cnic_handler = cnic_service_bnx2x,
  69. .cnic_ctl = cnic_ctl,
  70. };
  71. static void cnic_shutdown_rings(struct cnic_dev *);
  72. static void cnic_init_rings(struct cnic_dev *);
  73. static int cnic_cm_set_pg(struct cnic_sock *);
  74. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  75. {
  76. struct cnic_dev *dev = uinfo->priv;
  77. struct cnic_local *cp = dev->cnic_priv;
  78. if (!capable(CAP_NET_ADMIN))
  79. return -EPERM;
  80. if (cp->uio_dev != -1)
  81. return -EBUSY;
  82. rtnl_lock();
  83. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  84. rtnl_unlock();
  85. return -ENODEV;
  86. }
  87. cp->uio_dev = iminor(inode);
  88. cnic_init_rings(dev);
  89. rtnl_unlock();
  90. return 0;
  91. }
  92. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  93. {
  94. struct cnic_dev *dev = uinfo->priv;
  95. struct cnic_local *cp = dev->cnic_priv;
  96. cnic_shutdown_rings(dev);
  97. cp->uio_dev = -1;
  98. return 0;
  99. }
  100. static inline void cnic_hold(struct cnic_dev *dev)
  101. {
  102. atomic_inc(&dev->ref_count);
  103. }
  104. static inline void cnic_put(struct cnic_dev *dev)
  105. {
  106. atomic_dec(&dev->ref_count);
  107. }
  108. static inline void csk_hold(struct cnic_sock *csk)
  109. {
  110. atomic_inc(&csk->ref_count);
  111. }
  112. static inline void csk_put(struct cnic_sock *csk)
  113. {
  114. atomic_dec(&csk->ref_count);
  115. }
  116. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  117. {
  118. struct cnic_dev *cdev;
  119. read_lock(&cnic_dev_lock);
  120. list_for_each_entry(cdev, &cnic_dev_list, list) {
  121. if (netdev == cdev->netdev) {
  122. cnic_hold(cdev);
  123. read_unlock(&cnic_dev_lock);
  124. return cdev;
  125. }
  126. }
  127. read_unlock(&cnic_dev_lock);
  128. return NULL;
  129. }
  130. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  131. {
  132. atomic_inc(&ulp_ops->ref_count);
  133. }
  134. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  135. {
  136. atomic_dec(&ulp_ops->ref_count);
  137. }
  138. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  139. {
  140. struct cnic_local *cp = dev->cnic_priv;
  141. struct cnic_eth_dev *ethdev = cp->ethdev;
  142. struct drv_ctl_info info;
  143. struct drv_ctl_io *io = &info.data.io;
  144. info.cmd = DRV_CTL_CTX_WR_CMD;
  145. io->cid_addr = cid_addr;
  146. io->offset = off;
  147. io->data = val;
  148. ethdev->drv_ctl(dev->netdev, &info);
  149. }
  150. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  157. io->offset = off;
  158. io->dma_addr = addr;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_l2_ring *ring = &info.data.ring;
  167. if (start)
  168. info.cmd = DRV_CTL_START_L2_CMD;
  169. else
  170. info.cmd = DRV_CTL_STOP_L2_CMD;
  171. ring->cid = cid;
  172. ring->client_id = cl_id;
  173. ethdev->drv_ctl(dev->netdev, &info);
  174. }
  175. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  176. {
  177. struct cnic_local *cp = dev->cnic_priv;
  178. struct cnic_eth_dev *ethdev = cp->ethdev;
  179. struct drv_ctl_info info;
  180. struct drv_ctl_io *io = &info.data.io;
  181. info.cmd = DRV_CTL_IO_WR_CMD;
  182. io->offset = off;
  183. io->data = val;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_RD_CMD;
  193. io->offset = off;
  194. ethdev->drv_ctl(dev->netdev, &info);
  195. return io->data;
  196. }
  197. static int cnic_in_use(struct cnic_sock *csk)
  198. {
  199. return test_bit(SK_F_INUSE, &csk->flags);
  200. }
  201. static void cnic_kwq_completion(struct cnic_dev *dev, u32 count)
  202. {
  203. struct cnic_local *cp = dev->cnic_priv;
  204. struct cnic_eth_dev *ethdev = cp->ethdev;
  205. struct drv_ctl_info info;
  206. info.cmd = DRV_CTL_COMPLETION_CMD;
  207. info.data.comp.comp_count = count;
  208. ethdev->drv_ctl(dev->netdev, &info);
  209. }
  210. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  211. {
  212. u32 i;
  213. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  214. if (cp->ctx_tbl[i].cid == cid) {
  215. *l5_cid = i;
  216. return 0;
  217. }
  218. }
  219. return -EINVAL;
  220. }
  221. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  222. struct cnic_sock *csk)
  223. {
  224. struct iscsi_path path_req;
  225. char *buf = NULL;
  226. u16 len = 0;
  227. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  228. struct cnic_ulp_ops *ulp_ops;
  229. if (cp->uio_dev == -1)
  230. return -ENODEV;
  231. if (csk) {
  232. len = sizeof(path_req);
  233. buf = (char *) &path_req;
  234. memset(&path_req, 0, len);
  235. msg_type = ISCSI_KEVENT_PATH_REQ;
  236. path_req.handle = (u64) csk->l5_cid;
  237. if (test_bit(SK_F_IPV6, &csk->flags)) {
  238. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  239. sizeof(struct in6_addr));
  240. path_req.ip_addr_len = 16;
  241. } else {
  242. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  243. sizeof(struct in_addr));
  244. path_req.ip_addr_len = 4;
  245. }
  246. path_req.vlan_id = csk->vlan_id;
  247. path_req.pmtu = csk->mtu;
  248. }
  249. rcu_read_lock();
  250. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  251. if (ulp_ops)
  252. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  253. rcu_read_unlock();
  254. return 0;
  255. }
  256. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  257. char *buf, u16 len)
  258. {
  259. int rc = -EINVAL;
  260. switch (msg_type) {
  261. case ISCSI_UEVENT_PATH_UPDATE: {
  262. struct cnic_local *cp;
  263. u32 l5_cid;
  264. struct cnic_sock *csk;
  265. struct iscsi_path *path_resp;
  266. if (len < sizeof(*path_resp))
  267. break;
  268. path_resp = (struct iscsi_path *) buf;
  269. cp = dev->cnic_priv;
  270. l5_cid = (u32) path_resp->handle;
  271. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  272. break;
  273. csk = &cp->csk_tbl[l5_cid];
  274. csk_hold(csk);
  275. if (cnic_in_use(csk)) {
  276. memcpy(csk->ha, path_resp->mac_addr, 6);
  277. if (test_bit(SK_F_IPV6, &csk->flags))
  278. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  279. sizeof(struct in6_addr));
  280. else
  281. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  282. sizeof(struct in_addr));
  283. if (is_valid_ether_addr(csk->ha))
  284. cnic_cm_set_pg(csk);
  285. }
  286. csk_put(csk);
  287. rc = 0;
  288. }
  289. }
  290. return rc;
  291. }
  292. static int cnic_offld_prep(struct cnic_sock *csk)
  293. {
  294. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  295. return 0;
  296. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  297. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  298. return 0;
  299. }
  300. return 1;
  301. }
  302. static int cnic_close_prep(struct cnic_sock *csk)
  303. {
  304. clear_bit(SK_F_CONNECT_START, &csk->flags);
  305. smp_mb__after_clear_bit();
  306. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  307. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  308. msleep(1);
  309. return 1;
  310. }
  311. return 0;
  312. }
  313. static int cnic_abort_prep(struct cnic_sock *csk)
  314. {
  315. clear_bit(SK_F_CONNECT_START, &csk->flags);
  316. smp_mb__after_clear_bit();
  317. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  318. msleep(1);
  319. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  320. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  321. return 1;
  322. }
  323. return 0;
  324. }
  325. static void cnic_uio_stop(void)
  326. {
  327. struct cnic_dev *dev;
  328. read_lock(&cnic_dev_lock);
  329. list_for_each_entry(dev, &cnic_dev_list, list) {
  330. struct cnic_local *cp = dev->cnic_priv;
  331. if (cp->cnic_uinfo)
  332. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  333. }
  334. read_unlock(&cnic_dev_lock);
  335. }
  336. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  337. {
  338. struct cnic_dev *dev;
  339. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  340. printk(KERN_ERR PFX "cnic_register_driver: Bad type %d\n",
  341. ulp_type);
  342. return -EINVAL;
  343. }
  344. mutex_lock(&cnic_lock);
  345. if (cnic_ulp_tbl[ulp_type]) {
  346. printk(KERN_ERR PFX "cnic_register_driver: Type %d has already "
  347. "been registered\n", ulp_type);
  348. mutex_unlock(&cnic_lock);
  349. return -EBUSY;
  350. }
  351. read_lock(&cnic_dev_lock);
  352. list_for_each_entry(dev, &cnic_dev_list, list) {
  353. struct cnic_local *cp = dev->cnic_priv;
  354. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  355. }
  356. read_unlock(&cnic_dev_lock);
  357. atomic_set(&ulp_ops->ref_count, 0);
  358. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  359. mutex_unlock(&cnic_lock);
  360. /* Prevent race conditions with netdev_event */
  361. rtnl_lock();
  362. read_lock(&cnic_dev_lock);
  363. list_for_each_entry(dev, &cnic_dev_list, list) {
  364. struct cnic_local *cp = dev->cnic_priv;
  365. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  366. ulp_ops->cnic_init(dev);
  367. }
  368. read_unlock(&cnic_dev_lock);
  369. rtnl_unlock();
  370. return 0;
  371. }
  372. int cnic_unregister_driver(int ulp_type)
  373. {
  374. struct cnic_dev *dev;
  375. struct cnic_ulp_ops *ulp_ops;
  376. int i = 0;
  377. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  378. printk(KERN_ERR PFX "cnic_unregister_driver: Bad type %d\n",
  379. ulp_type);
  380. return -EINVAL;
  381. }
  382. mutex_lock(&cnic_lock);
  383. ulp_ops = cnic_ulp_tbl[ulp_type];
  384. if (!ulp_ops) {
  385. printk(KERN_ERR PFX "cnic_unregister_driver: Type %d has not "
  386. "been registered\n", ulp_type);
  387. goto out_unlock;
  388. }
  389. read_lock(&cnic_dev_lock);
  390. list_for_each_entry(dev, &cnic_dev_list, list) {
  391. struct cnic_local *cp = dev->cnic_priv;
  392. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  393. printk(KERN_ERR PFX "cnic_unregister_driver: Type %d "
  394. "still has devices registered\n", ulp_type);
  395. read_unlock(&cnic_dev_lock);
  396. goto out_unlock;
  397. }
  398. }
  399. read_unlock(&cnic_dev_lock);
  400. if (ulp_type == CNIC_ULP_ISCSI)
  401. cnic_uio_stop();
  402. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  403. mutex_unlock(&cnic_lock);
  404. synchronize_rcu();
  405. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  406. msleep(100);
  407. i++;
  408. }
  409. if (atomic_read(&ulp_ops->ref_count) != 0)
  410. printk(KERN_WARNING PFX "%s: Failed waiting for ref count to go"
  411. " to zero.\n", dev->netdev->name);
  412. return 0;
  413. out_unlock:
  414. mutex_unlock(&cnic_lock);
  415. return -EINVAL;
  416. }
  417. static int cnic_start_hw(struct cnic_dev *);
  418. static void cnic_stop_hw(struct cnic_dev *);
  419. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  420. void *ulp_ctx)
  421. {
  422. struct cnic_local *cp = dev->cnic_priv;
  423. struct cnic_ulp_ops *ulp_ops;
  424. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  425. printk(KERN_ERR PFX "cnic_register_device: Bad type %d\n",
  426. ulp_type);
  427. return -EINVAL;
  428. }
  429. mutex_lock(&cnic_lock);
  430. if (cnic_ulp_tbl[ulp_type] == NULL) {
  431. printk(KERN_ERR PFX "cnic_register_device: Driver with type %d "
  432. "has not been registered\n", ulp_type);
  433. mutex_unlock(&cnic_lock);
  434. return -EAGAIN;
  435. }
  436. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  437. printk(KERN_ERR PFX "cnic_register_device: Type %d has already "
  438. "been registered to this device\n", ulp_type);
  439. mutex_unlock(&cnic_lock);
  440. return -EBUSY;
  441. }
  442. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  443. cp->ulp_handle[ulp_type] = ulp_ctx;
  444. ulp_ops = cnic_ulp_tbl[ulp_type];
  445. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  446. cnic_hold(dev);
  447. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  448. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  449. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  450. mutex_unlock(&cnic_lock);
  451. return 0;
  452. }
  453. EXPORT_SYMBOL(cnic_register_driver);
  454. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  455. {
  456. struct cnic_local *cp = dev->cnic_priv;
  457. int i = 0;
  458. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  459. printk(KERN_ERR PFX "cnic_unregister_device: Bad type %d\n",
  460. ulp_type);
  461. return -EINVAL;
  462. }
  463. mutex_lock(&cnic_lock);
  464. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  465. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  466. cnic_put(dev);
  467. } else {
  468. printk(KERN_ERR PFX "cnic_unregister_device: device not "
  469. "registered to this ulp type %d\n", ulp_type);
  470. mutex_unlock(&cnic_lock);
  471. return -EINVAL;
  472. }
  473. mutex_unlock(&cnic_lock);
  474. synchronize_rcu();
  475. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  476. i < 20) {
  477. msleep(100);
  478. i++;
  479. }
  480. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  481. printk(KERN_WARNING PFX "%s: Failed waiting for ULP up call"
  482. " to complete.\n", dev->netdev->name);
  483. return 0;
  484. }
  485. EXPORT_SYMBOL(cnic_unregister_driver);
  486. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  487. {
  488. id_tbl->start = start_id;
  489. id_tbl->max = size;
  490. id_tbl->next = 0;
  491. spin_lock_init(&id_tbl->lock);
  492. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  493. if (!id_tbl->table)
  494. return -ENOMEM;
  495. return 0;
  496. }
  497. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  498. {
  499. kfree(id_tbl->table);
  500. id_tbl->table = NULL;
  501. }
  502. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  503. {
  504. int ret = -1;
  505. id -= id_tbl->start;
  506. if (id >= id_tbl->max)
  507. return ret;
  508. spin_lock(&id_tbl->lock);
  509. if (!test_bit(id, id_tbl->table)) {
  510. set_bit(id, id_tbl->table);
  511. ret = 0;
  512. }
  513. spin_unlock(&id_tbl->lock);
  514. return ret;
  515. }
  516. /* Returns -1 if not successful */
  517. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  518. {
  519. u32 id;
  520. spin_lock(&id_tbl->lock);
  521. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  522. if (id >= id_tbl->max) {
  523. id = -1;
  524. if (id_tbl->next != 0) {
  525. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  526. if (id >= id_tbl->next)
  527. id = -1;
  528. }
  529. }
  530. if (id < id_tbl->max) {
  531. set_bit(id, id_tbl->table);
  532. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  533. id += id_tbl->start;
  534. }
  535. spin_unlock(&id_tbl->lock);
  536. return id;
  537. }
  538. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  539. {
  540. if (id == -1)
  541. return;
  542. id -= id_tbl->start;
  543. if (id >= id_tbl->max)
  544. return;
  545. clear_bit(id, id_tbl->table);
  546. }
  547. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  548. {
  549. int i;
  550. if (!dma->pg_arr)
  551. return;
  552. for (i = 0; i < dma->num_pages; i++) {
  553. if (dma->pg_arr[i]) {
  554. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  555. dma->pg_arr[i], dma->pg_map_arr[i]);
  556. dma->pg_arr[i] = NULL;
  557. }
  558. }
  559. if (dma->pgtbl) {
  560. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  561. dma->pgtbl, dma->pgtbl_map);
  562. dma->pgtbl = NULL;
  563. }
  564. kfree(dma->pg_arr);
  565. dma->pg_arr = NULL;
  566. dma->num_pages = 0;
  567. }
  568. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  569. {
  570. int i;
  571. u32 *page_table = dma->pgtbl;
  572. for (i = 0; i < dma->num_pages; i++) {
  573. /* Each entry needs to be in big endian format. */
  574. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  575. page_table++;
  576. *page_table = (u32) dma->pg_map_arr[i];
  577. page_table++;
  578. }
  579. }
  580. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  581. {
  582. int i;
  583. u32 *page_table = dma->pgtbl;
  584. for (i = 0; i < dma->num_pages; i++) {
  585. /* Each entry needs to be in little endian format. */
  586. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  587. page_table++;
  588. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  589. page_table++;
  590. }
  591. }
  592. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  593. int pages, int use_pg_tbl)
  594. {
  595. int i, size;
  596. struct cnic_local *cp = dev->cnic_priv;
  597. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  598. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  599. if (dma->pg_arr == NULL)
  600. return -ENOMEM;
  601. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  602. dma->num_pages = pages;
  603. for (i = 0; i < pages; i++) {
  604. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  605. BCM_PAGE_SIZE,
  606. &dma->pg_map_arr[i],
  607. GFP_ATOMIC);
  608. if (dma->pg_arr[i] == NULL)
  609. goto error;
  610. }
  611. if (!use_pg_tbl)
  612. return 0;
  613. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  614. ~(BCM_PAGE_SIZE - 1);
  615. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  616. &dma->pgtbl_map, GFP_ATOMIC);
  617. if (dma->pgtbl == NULL)
  618. goto error;
  619. cp->setup_pgtbl(dev, dma);
  620. return 0;
  621. error:
  622. cnic_free_dma(dev, dma);
  623. return -ENOMEM;
  624. }
  625. static void cnic_free_context(struct cnic_dev *dev)
  626. {
  627. struct cnic_local *cp = dev->cnic_priv;
  628. int i;
  629. for (i = 0; i < cp->ctx_blks; i++) {
  630. if (cp->ctx_arr[i].ctx) {
  631. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  632. cp->ctx_arr[i].ctx,
  633. cp->ctx_arr[i].mapping);
  634. cp->ctx_arr[i].ctx = NULL;
  635. }
  636. }
  637. }
  638. static void cnic_free_resc(struct cnic_dev *dev)
  639. {
  640. struct cnic_local *cp = dev->cnic_priv;
  641. int i = 0;
  642. if (cp->cnic_uinfo) {
  643. while (cp->uio_dev != -1 && i < 15) {
  644. msleep(100);
  645. i++;
  646. }
  647. uio_unregister_device(cp->cnic_uinfo);
  648. kfree(cp->cnic_uinfo);
  649. cp->cnic_uinfo = NULL;
  650. }
  651. if (cp->l2_buf) {
  652. dma_free_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  653. cp->l2_buf, cp->l2_buf_map);
  654. cp->l2_buf = NULL;
  655. }
  656. if (cp->l2_ring) {
  657. dma_free_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  658. cp->l2_ring, cp->l2_ring_map);
  659. cp->l2_ring = NULL;
  660. }
  661. cnic_free_context(dev);
  662. kfree(cp->ctx_arr);
  663. cp->ctx_arr = NULL;
  664. cp->ctx_blks = 0;
  665. cnic_free_dma(dev, &cp->gbl_buf_info);
  666. cnic_free_dma(dev, &cp->conn_buf_info);
  667. cnic_free_dma(dev, &cp->kwq_info);
  668. cnic_free_dma(dev, &cp->kwq_16_data_info);
  669. cnic_free_dma(dev, &cp->kcq_info);
  670. kfree(cp->iscsi_tbl);
  671. cp->iscsi_tbl = NULL;
  672. kfree(cp->ctx_tbl);
  673. cp->ctx_tbl = NULL;
  674. cnic_free_id_tbl(&cp->cid_tbl);
  675. }
  676. static int cnic_alloc_context(struct cnic_dev *dev)
  677. {
  678. struct cnic_local *cp = dev->cnic_priv;
  679. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  680. int i, k, arr_size;
  681. cp->ctx_blk_size = BCM_PAGE_SIZE;
  682. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  683. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  684. sizeof(struct cnic_ctx);
  685. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  686. if (cp->ctx_arr == NULL)
  687. return -ENOMEM;
  688. k = 0;
  689. for (i = 0; i < 2; i++) {
  690. u32 j, reg, off, lo, hi;
  691. if (i == 0)
  692. off = BNX2_PG_CTX_MAP;
  693. else
  694. off = BNX2_ISCSI_CTX_MAP;
  695. reg = cnic_reg_rd_ind(dev, off);
  696. lo = reg >> 16;
  697. hi = reg & 0xffff;
  698. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  699. cp->ctx_arr[k].cid = j;
  700. }
  701. cp->ctx_blks = k;
  702. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  703. cp->ctx_blks = 0;
  704. return -ENOMEM;
  705. }
  706. for (i = 0; i < cp->ctx_blks; i++) {
  707. cp->ctx_arr[i].ctx =
  708. dma_alloc_coherent(&dev->pcidev->dev,
  709. BCM_PAGE_SIZE,
  710. &cp->ctx_arr[i].mapping,
  711. GFP_KERNEL);
  712. if (cp->ctx_arr[i].ctx == NULL)
  713. return -ENOMEM;
  714. }
  715. }
  716. return 0;
  717. }
  718. static int cnic_alloc_l2_rings(struct cnic_dev *dev, int pages)
  719. {
  720. struct cnic_local *cp = dev->cnic_priv;
  721. cp->l2_ring_size = pages * BCM_PAGE_SIZE;
  722. cp->l2_ring = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_ring_size,
  723. &cp->l2_ring_map,
  724. GFP_KERNEL | __GFP_COMP);
  725. if (!cp->l2_ring)
  726. return -ENOMEM;
  727. cp->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  728. cp->l2_buf_size = PAGE_ALIGN(cp->l2_buf_size);
  729. cp->l2_buf = dma_alloc_coherent(&dev->pcidev->dev, cp->l2_buf_size,
  730. &cp->l2_buf_map,
  731. GFP_KERNEL | __GFP_COMP);
  732. if (!cp->l2_buf)
  733. return -ENOMEM;
  734. return 0;
  735. }
  736. static int cnic_alloc_uio(struct cnic_dev *dev) {
  737. struct cnic_local *cp = dev->cnic_priv;
  738. struct uio_info *uinfo;
  739. int ret;
  740. uinfo = kzalloc(sizeof(*uinfo), GFP_ATOMIC);
  741. if (!uinfo)
  742. return -ENOMEM;
  743. uinfo->mem[0].addr = dev->netdev->base_addr;
  744. uinfo->mem[0].internal_addr = dev->regview;
  745. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  746. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  747. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  748. uinfo->mem[1].addr = (unsigned long) cp->status_blk & PAGE_MASK;
  749. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  750. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  751. else
  752. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  753. uinfo->name = "bnx2_cnic";
  754. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  755. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  756. PAGE_MASK;
  757. uinfo->mem[1].size = sizeof(struct host_def_status_block);
  758. uinfo->name = "bnx2x_cnic";
  759. }
  760. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  761. uinfo->mem[2].addr = (unsigned long) cp->l2_ring;
  762. uinfo->mem[2].size = cp->l2_ring_size;
  763. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  764. uinfo->mem[3].addr = (unsigned long) cp->l2_buf;
  765. uinfo->mem[3].size = cp->l2_buf_size;
  766. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  767. uinfo->version = CNIC_MODULE_VERSION;
  768. uinfo->irq = UIO_IRQ_CUSTOM;
  769. uinfo->open = cnic_uio_open;
  770. uinfo->release = cnic_uio_close;
  771. uinfo->priv = dev;
  772. ret = uio_register_device(&dev->pcidev->dev, uinfo);
  773. if (ret) {
  774. kfree(uinfo);
  775. return ret;
  776. }
  777. cp->cnic_uinfo = uinfo;
  778. return 0;
  779. }
  780. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  781. {
  782. struct cnic_local *cp = dev->cnic_priv;
  783. int ret;
  784. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  785. if (ret)
  786. goto error;
  787. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  788. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 1);
  789. if (ret)
  790. goto error;
  791. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  792. ret = cnic_alloc_context(dev);
  793. if (ret)
  794. goto error;
  795. ret = cnic_alloc_l2_rings(dev, 2);
  796. if (ret)
  797. goto error;
  798. ret = cnic_alloc_uio(dev);
  799. if (ret)
  800. goto error;
  801. return 0;
  802. error:
  803. cnic_free_resc(dev);
  804. return ret;
  805. }
  806. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  807. {
  808. struct cnic_local *cp = dev->cnic_priv;
  809. struct cnic_eth_dev *ethdev = cp->ethdev;
  810. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  811. int total_mem, blks, i, cid_space;
  812. if (BNX2X_ISCSI_START_CID < ethdev->starting_cid)
  813. return -EINVAL;
  814. cid_space = MAX_ISCSI_TBL_SZ +
  815. (BNX2X_ISCSI_START_CID - ethdev->starting_cid);
  816. total_mem = BNX2X_CONTEXT_MEM_SIZE * cid_space;
  817. blks = total_mem / ctx_blk_size;
  818. if (total_mem % ctx_blk_size)
  819. blks++;
  820. if (blks > cp->ethdev->ctx_tbl_len)
  821. return -ENOMEM;
  822. cp->ctx_arr = kzalloc(blks * sizeof(struct cnic_ctx), GFP_KERNEL);
  823. if (cp->ctx_arr == NULL)
  824. return -ENOMEM;
  825. cp->ctx_blks = blks;
  826. cp->ctx_blk_size = ctx_blk_size;
  827. if (BNX2X_CHIP_IS_E1H(cp->chip_id))
  828. cp->ctx_align = 0;
  829. else
  830. cp->ctx_align = ctx_blk_size;
  831. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  832. for (i = 0; i < blks; i++) {
  833. cp->ctx_arr[i].ctx =
  834. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  835. &cp->ctx_arr[i].mapping,
  836. GFP_KERNEL);
  837. if (cp->ctx_arr[i].ctx == NULL)
  838. return -ENOMEM;
  839. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  840. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  841. cnic_free_context(dev);
  842. cp->ctx_blk_size += cp->ctx_align;
  843. i = -1;
  844. continue;
  845. }
  846. }
  847. }
  848. return 0;
  849. }
  850. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  851. {
  852. struct cnic_local *cp = dev->cnic_priv;
  853. int i, j, n, ret, pages;
  854. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  855. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  856. GFP_KERNEL);
  857. if (!cp->iscsi_tbl)
  858. goto error;
  859. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  860. MAX_CNIC_L5_CONTEXT, GFP_KERNEL);
  861. if (!cp->ctx_tbl)
  862. goto error;
  863. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  864. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  865. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  866. }
  867. pages = PAGE_ALIGN(MAX_CNIC_L5_CONTEXT * CNIC_KWQ16_DATA_SIZE) /
  868. PAGE_SIZE;
  869. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  870. if (ret)
  871. return -ENOMEM;
  872. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  873. for (i = 0, j = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  874. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  875. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  876. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  877. off;
  878. if ((i % n) == (n - 1))
  879. j++;
  880. }
  881. ret = cnic_alloc_dma(dev, &cp->kcq_info, KCQ_PAGE_CNT, 0);
  882. if (ret)
  883. goto error;
  884. cp->kcq = (struct kcqe **) cp->kcq_info.pg_arr;
  885. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  886. struct bnx2x_bd_chain_next *next =
  887. (struct bnx2x_bd_chain_next *)
  888. &cp->kcq[i][MAX_KCQE_CNT];
  889. int j = i + 1;
  890. if (j >= KCQ_PAGE_CNT)
  891. j = 0;
  892. next->addr_hi = (u64) cp->kcq_info.pg_map_arr[j] >> 32;
  893. next->addr_lo = cp->kcq_info.pg_map_arr[j] & 0xffffffff;
  894. }
  895. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  896. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  897. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  898. if (ret)
  899. goto error;
  900. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  901. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  902. if (ret)
  903. goto error;
  904. ret = cnic_alloc_bnx2x_context(dev);
  905. if (ret)
  906. goto error;
  907. cp->bnx2x_status_blk = cp->status_blk;
  908. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  909. cp->l2_rx_ring_size = 15;
  910. ret = cnic_alloc_l2_rings(dev, 4);
  911. if (ret)
  912. goto error;
  913. ret = cnic_alloc_uio(dev);
  914. if (ret)
  915. goto error;
  916. return 0;
  917. error:
  918. cnic_free_resc(dev);
  919. return -ENOMEM;
  920. }
  921. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  922. {
  923. return cp->max_kwq_idx -
  924. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  925. }
  926. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  927. u32 num_wqes)
  928. {
  929. struct cnic_local *cp = dev->cnic_priv;
  930. struct kwqe *prod_qe;
  931. u16 prod, sw_prod, i;
  932. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  933. return -EAGAIN; /* bnx2 is down */
  934. spin_lock_bh(&cp->cnic_ulp_lock);
  935. if (num_wqes > cnic_kwq_avail(cp) &&
  936. !(cp->cnic_local_flags & CNIC_LCL_FL_KWQ_INIT)) {
  937. spin_unlock_bh(&cp->cnic_ulp_lock);
  938. return -EAGAIN;
  939. }
  940. cp->cnic_local_flags &= ~CNIC_LCL_FL_KWQ_INIT;
  941. prod = cp->kwq_prod_idx;
  942. sw_prod = prod & MAX_KWQ_IDX;
  943. for (i = 0; i < num_wqes; i++) {
  944. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  945. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  946. prod++;
  947. sw_prod = prod & MAX_KWQ_IDX;
  948. }
  949. cp->kwq_prod_idx = prod;
  950. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  951. spin_unlock_bh(&cp->cnic_ulp_lock);
  952. return 0;
  953. }
  954. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  955. union l5cm_specific_data *l5_data)
  956. {
  957. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  958. dma_addr_t map;
  959. map = ctx->kwqe_data_mapping;
  960. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  961. l5_data->phy_address.hi = (u64) map >> 32;
  962. return ctx->kwqe_data;
  963. }
  964. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  965. u32 type, union l5cm_specific_data *l5_data)
  966. {
  967. struct cnic_local *cp = dev->cnic_priv;
  968. struct l5cm_spe kwqe;
  969. struct kwqe_16 *kwq[1];
  970. int ret;
  971. kwqe.hdr.conn_and_cmd_data =
  972. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  973. BNX2X_HW_CID(cid, cp->func)));
  974. kwqe.hdr.type = cpu_to_le16(type);
  975. kwqe.hdr.reserved = 0;
  976. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  977. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  978. kwq[0] = (struct kwqe_16 *) &kwqe;
  979. spin_lock_bh(&cp->cnic_ulp_lock);
  980. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  981. spin_unlock_bh(&cp->cnic_ulp_lock);
  982. if (ret == 1)
  983. return 0;
  984. return -EBUSY;
  985. }
  986. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  987. struct kcqe *cqes[], u32 num_cqes)
  988. {
  989. struct cnic_local *cp = dev->cnic_priv;
  990. struct cnic_ulp_ops *ulp_ops;
  991. rcu_read_lock();
  992. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  993. if (likely(ulp_ops)) {
  994. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  995. cqes, num_cqes);
  996. }
  997. rcu_read_unlock();
  998. }
  999. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1000. {
  1001. struct cnic_local *cp = dev->cnic_priv;
  1002. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1003. int func = cp->func, pages;
  1004. int hq_bds;
  1005. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1006. cp->num_ccells = req1->num_ccells_per_conn;
  1007. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1008. cp->num_iscsi_tasks;
  1009. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1010. BNX2X_ISCSI_R2TQE_SIZE;
  1011. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1012. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1013. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1014. cp->num_cqs = req1->num_cqs;
  1015. if (!dev->max_iscsi_conn)
  1016. return 0;
  1017. /* init Tstorm RAM */
  1018. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1019. req1->rq_num_wqes);
  1020. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1021. PAGE_SIZE);
  1022. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1023. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1024. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1025. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1026. req1->num_tasks_per_conn);
  1027. /* init Ustorm RAM */
  1028. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1029. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(func),
  1030. req1->rq_buffer_size);
  1031. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1032. PAGE_SIZE);
  1033. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1034. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1035. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1036. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1037. req1->num_tasks_per_conn);
  1038. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(func),
  1039. req1->rq_num_wqes);
  1040. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1041. req1->cq_num_wqes);
  1042. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1043. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1044. /* init Xstorm RAM */
  1045. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1046. PAGE_SIZE);
  1047. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1048. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1049. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1050. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1051. req1->num_tasks_per_conn);
  1052. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1053. hq_bds);
  1054. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(func),
  1055. req1->num_tasks_per_conn);
  1056. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(func),
  1057. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1058. /* init Cstorm RAM */
  1059. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(func),
  1060. PAGE_SIZE);
  1061. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1062. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(func), PAGE_SHIFT);
  1063. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1064. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(func),
  1065. req1->num_tasks_per_conn);
  1066. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(func),
  1067. req1->cq_num_wqes);
  1068. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(func),
  1069. hq_bds);
  1070. return 0;
  1071. }
  1072. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1073. {
  1074. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1075. struct cnic_local *cp = dev->cnic_priv;
  1076. int func = cp->func;
  1077. struct iscsi_kcqe kcqe;
  1078. struct kcqe *cqes[1];
  1079. memset(&kcqe, 0, sizeof(kcqe));
  1080. if (!dev->max_iscsi_conn) {
  1081. kcqe.completion_status =
  1082. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1083. goto done;
  1084. }
  1085. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1086. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1087. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1088. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1089. req2->error_bit_map[1]);
  1090. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1091. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1092. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1093. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func), req2->error_bit_map[0]);
  1094. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1095. USTORM_ISCSI_ERROR_BITMAP_OFFSET(func) + 4,
  1096. req2->error_bit_map[1]);
  1097. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1098. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(func), req2->max_cq_sqn);
  1099. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1100. done:
  1101. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1102. cqes[0] = (struct kcqe *) &kcqe;
  1103. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1104. return 0;
  1105. }
  1106. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1107. {
  1108. struct cnic_local *cp = dev->cnic_priv;
  1109. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1110. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1111. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1112. cnic_free_dma(dev, &iscsi->hq_info);
  1113. cnic_free_dma(dev, &iscsi->r2tq_info);
  1114. cnic_free_dma(dev, &iscsi->task_array_info);
  1115. }
  1116. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1117. ctx->cid = 0;
  1118. }
  1119. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1120. {
  1121. u32 cid;
  1122. int ret, pages;
  1123. struct cnic_local *cp = dev->cnic_priv;
  1124. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1125. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1126. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1127. if (cid == -1) {
  1128. ret = -ENOMEM;
  1129. goto error;
  1130. }
  1131. ctx->cid = cid;
  1132. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1133. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1134. if (ret)
  1135. goto error;
  1136. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1137. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1138. if (ret)
  1139. goto error;
  1140. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1141. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1142. if (ret)
  1143. goto error;
  1144. return 0;
  1145. error:
  1146. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1147. return ret;
  1148. }
  1149. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1150. struct regpair *ctx_addr)
  1151. {
  1152. struct cnic_local *cp = dev->cnic_priv;
  1153. struct cnic_eth_dev *ethdev = cp->ethdev;
  1154. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1155. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1156. unsigned long align_off = 0;
  1157. dma_addr_t ctx_map;
  1158. void *ctx;
  1159. if (cp->ctx_align) {
  1160. unsigned long mask = cp->ctx_align - 1;
  1161. if (cp->ctx_arr[blk].mapping & mask)
  1162. align_off = cp->ctx_align -
  1163. (cp->ctx_arr[blk].mapping & mask);
  1164. }
  1165. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1166. (off * BNX2X_CONTEXT_MEM_SIZE);
  1167. ctx = cp->ctx_arr[blk].ctx + align_off +
  1168. (off * BNX2X_CONTEXT_MEM_SIZE);
  1169. if (init)
  1170. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1171. ctx_addr->lo = ctx_map & 0xffffffff;
  1172. ctx_addr->hi = (u64) ctx_map >> 32;
  1173. return ctx;
  1174. }
  1175. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1176. u32 num)
  1177. {
  1178. struct cnic_local *cp = dev->cnic_priv;
  1179. struct iscsi_kwqe_conn_offload1 *req1 =
  1180. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1181. struct iscsi_kwqe_conn_offload2 *req2 =
  1182. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1183. struct iscsi_kwqe_conn_offload3 *req3;
  1184. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1185. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1186. u32 cid = ctx->cid;
  1187. u32 hw_cid = BNX2X_HW_CID(cid, cp->func);
  1188. struct iscsi_context *ictx;
  1189. struct regpair context_addr;
  1190. int i, j, n = 2, n_max;
  1191. ctx->ctx_flags = 0;
  1192. if (!req2->num_additional_wqes)
  1193. return -EINVAL;
  1194. n_max = req2->num_additional_wqes + 2;
  1195. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1196. if (ictx == NULL)
  1197. return -ENOMEM;
  1198. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1199. ictx->xstorm_ag_context.hq_prod = 1;
  1200. ictx->xstorm_st_context.iscsi.first_burst_length =
  1201. ISCSI_DEF_FIRST_BURST_LEN;
  1202. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1203. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1204. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1205. req1->sq_page_table_addr_lo;
  1206. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1207. req1->sq_page_table_addr_hi;
  1208. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1209. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1210. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1211. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1212. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1213. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1214. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1215. iscsi->hq_info.pgtbl[0];
  1216. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1217. iscsi->hq_info.pgtbl[1];
  1218. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1219. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1220. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1221. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1222. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1223. iscsi->r2tq_info.pgtbl[0];
  1224. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1225. iscsi->r2tq_info.pgtbl[1];
  1226. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1227. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1228. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1229. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1230. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1231. BNX2X_ISCSI_PBL_NOT_CACHED;
  1232. ictx->xstorm_st_context.iscsi.flags.flags |=
  1233. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1234. ictx->xstorm_st_context.iscsi.flags.flags |=
  1235. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1236. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1237. /* TSTORM requires the base address of RQ DB & not PTE */
  1238. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1239. req2->rq_page_table_addr_lo & PAGE_MASK;
  1240. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1241. req2->rq_page_table_addr_hi;
  1242. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1243. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1244. ictx->tstorm_st_context.tcp.flags2 |=
  1245. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1246. ictx->timers_context.flags |= ISCSI_TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1247. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1248. req2->rq_page_table_addr_lo;
  1249. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1250. req2->rq_page_table_addr_hi;
  1251. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1252. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1253. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1254. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1255. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1256. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1257. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1258. iscsi->r2tq_info.pgtbl[0];
  1259. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1260. iscsi->r2tq_info.pgtbl[1];
  1261. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1262. req1->cq_page_table_addr_lo;
  1263. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1264. req1->cq_page_table_addr_hi;
  1265. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1266. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1267. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1268. ictx->ustorm_st_context.task_pbe_cache_index =
  1269. BNX2X_ISCSI_PBL_NOT_CACHED;
  1270. ictx->ustorm_st_context.task_pdu_cache_index =
  1271. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1272. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1273. if (j == 3) {
  1274. if (n >= n_max)
  1275. break;
  1276. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1277. j = 0;
  1278. }
  1279. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1280. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1281. req3->qp_first_pte[j].hi;
  1282. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1283. req3->qp_first_pte[j].lo;
  1284. }
  1285. ictx->ustorm_st_context.task_pbl_base.lo =
  1286. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1287. ictx->ustorm_st_context.task_pbl_base.hi =
  1288. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1289. ictx->ustorm_st_context.tce_phy_addr.lo =
  1290. iscsi->task_array_info.pgtbl[0];
  1291. ictx->ustorm_st_context.tce_phy_addr.hi =
  1292. iscsi->task_array_info.pgtbl[1];
  1293. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1294. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1295. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1296. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1297. ISCSI_DEF_MAX_BURST_LEN;
  1298. ictx->ustorm_st_context.negotiated_rx |=
  1299. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1300. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1301. ictx->cstorm_st_context.hq_pbl_base.lo =
  1302. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1303. ictx->cstorm_st_context.hq_pbl_base.hi =
  1304. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1305. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1306. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1307. ictx->cstorm_st_context.task_pbl_base.lo =
  1308. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1309. ictx->cstorm_st_context.task_pbl_base.hi =
  1310. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1311. /* CSTORM and USTORM initialization is different, CSTORM requires
  1312. * CQ DB base & not PTE addr */
  1313. ictx->cstorm_st_context.cq_db_base.lo =
  1314. req1->cq_page_table_addr_lo & PAGE_MASK;
  1315. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1316. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1317. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1318. for (i = 0; i < cp->num_cqs; i++) {
  1319. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1320. ISCSI_INITIAL_SN;
  1321. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1322. ISCSI_INITIAL_SN;
  1323. }
  1324. ictx->xstorm_ag_context.cdu_reserved =
  1325. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1326. ISCSI_CONNECTION_TYPE);
  1327. ictx->ustorm_ag_context.cdu_usage =
  1328. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1329. ISCSI_CONNECTION_TYPE);
  1330. return 0;
  1331. }
  1332. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1333. u32 num, int *work)
  1334. {
  1335. struct iscsi_kwqe_conn_offload1 *req1;
  1336. struct iscsi_kwqe_conn_offload2 *req2;
  1337. struct cnic_local *cp = dev->cnic_priv;
  1338. struct iscsi_kcqe kcqe;
  1339. struct kcqe *cqes[1];
  1340. u32 l5_cid;
  1341. int ret;
  1342. if (num < 2) {
  1343. *work = num;
  1344. return -EINVAL;
  1345. }
  1346. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1347. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1348. if ((num - 2) < req2->num_additional_wqes) {
  1349. *work = num;
  1350. return -EINVAL;
  1351. }
  1352. *work = 2 + req2->num_additional_wqes;;
  1353. l5_cid = req1->iscsi_conn_id;
  1354. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1355. return -EINVAL;
  1356. memset(&kcqe, 0, sizeof(kcqe));
  1357. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1358. kcqe.iscsi_conn_id = l5_cid;
  1359. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1360. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1361. atomic_dec(&cp->iscsi_conn);
  1362. ret = 0;
  1363. goto done;
  1364. }
  1365. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1366. if (ret) {
  1367. atomic_dec(&cp->iscsi_conn);
  1368. ret = 0;
  1369. goto done;
  1370. }
  1371. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1372. if (ret < 0) {
  1373. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1374. atomic_dec(&cp->iscsi_conn);
  1375. goto done;
  1376. }
  1377. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1378. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp->ctx_tbl[l5_cid].cid,
  1379. cp->func);
  1380. done:
  1381. cqes[0] = (struct kcqe *) &kcqe;
  1382. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1383. return ret;
  1384. }
  1385. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1386. {
  1387. struct cnic_local *cp = dev->cnic_priv;
  1388. struct iscsi_kwqe_conn_update *req =
  1389. (struct iscsi_kwqe_conn_update *) kwqe;
  1390. void *data;
  1391. union l5cm_specific_data l5_data;
  1392. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1393. int ret;
  1394. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1395. return -EINVAL;
  1396. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1397. if (!data)
  1398. return -ENOMEM;
  1399. memcpy(data, kwqe, sizeof(struct kwqe));
  1400. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1401. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1402. return ret;
  1403. }
  1404. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1405. {
  1406. struct cnic_local *cp = dev->cnic_priv;
  1407. struct iscsi_kwqe_conn_destroy *req =
  1408. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1409. union l5cm_specific_data l5_data;
  1410. u32 l5_cid = req->reserved0;
  1411. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1412. int ret = 0;
  1413. struct iscsi_kcqe kcqe;
  1414. struct kcqe *cqes[1];
  1415. if (!(ctx->ctx_flags & CTX_FL_OFFLD_START))
  1416. goto skip_cfc_delete;
  1417. while (!time_after(jiffies, ctx->timestamp + (2 * HZ)))
  1418. msleep(250);
  1419. init_waitqueue_head(&ctx->waitq);
  1420. ctx->wait_cond = 0;
  1421. memset(&l5_data, 0, sizeof(l5_data));
  1422. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CFC_DEL,
  1423. req->context_id,
  1424. ETH_CONNECTION_TYPE |
  1425. (1 << SPE_HDR_COMMON_RAMROD_SHIFT),
  1426. &l5_data);
  1427. if (ret == 0)
  1428. wait_event(ctx->waitq, ctx->wait_cond);
  1429. skip_cfc_delete:
  1430. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1431. atomic_dec(&cp->iscsi_conn);
  1432. memset(&kcqe, 0, sizeof(kcqe));
  1433. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1434. kcqe.iscsi_conn_id = l5_cid;
  1435. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1436. kcqe.iscsi_conn_context_id = req->context_id;
  1437. cqes[0] = (struct kcqe *) &kcqe;
  1438. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1439. return ret;
  1440. }
  1441. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1442. struct l4_kwq_connect_req1 *kwqe1,
  1443. struct l4_kwq_connect_req3 *kwqe3,
  1444. struct l5cm_active_conn_buffer *conn_buf)
  1445. {
  1446. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1447. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1448. &conn_buf->xstorm_conn_buffer;
  1449. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1450. &conn_buf->tstorm_conn_buffer;
  1451. struct regpair context_addr;
  1452. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1453. struct in6_addr src_ip, dst_ip;
  1454. int i;
  1455. u32 *addrp;
  1456. addrp = (u32 *) &conn_addr->local_ip_addr;
  1457. for (i = 0; i < 4; i++, addrp++)
  1458. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1459. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1460. for (i = 0; i < 4; i++, addrp++)
  1461. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1462. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1463. xstorm_buf->context_addr.hi = context_addr.hi;
  1464. xstorm_buf->context_addr.lo = context_addr.lo;
  1465. xstorm_buf->mss = 0xffff;
  1466. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1467. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1468. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1469. xstorm_buf->pseudo_header_checksum =
  1470. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1471. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1472. tstorm_buf->params |=
  1473. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1474. if (kwqe3->ka_timeout) {
  1475. tstorm_buf->ka_enable = 1;
  1476. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1477. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1478. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1479. }
  1480. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1481. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1482. tstorm_buf->max_rt_time = 0xffffffff;
  1483. }
  1484. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1485. {
  1486. struct cnic_local *cp = dev->cnic_priv;
  1487. int func = CNIC_FUNC(cp);
  1488. u8 *mac = dev->mac_addr;
  1489. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1490. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(func), mac[0]);
  1491. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1492. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(func), mac[1]);
  1493. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1494. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(func), mac[2]);
  1495. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1496. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(func), mac[3]);
  1497. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1498. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(func), mac[4]);
  1499. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1500. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(func), mac[5]);
  1501. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1502. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func), mac[5]);
  1503. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1504. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1505. mac[4]);
  1506. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1507. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func), mac[3]);
  1508. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1509. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 1,
  1510. mac[2]);
  1511. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1512. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 2,
  1513. mac[1]);
  1514. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1515. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(func) + 3,
  1516. mac[0]);
  1517. }
  1518. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1519. {
  1520. struct cnic_local *cp = dev->cnic_priv;
  1521. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1522. u16 tstorm_flags = 0;
  1523. if (tcp_ts) {
  1524. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1525. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1526. }
  1527. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1528. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), xstorm_flags);
  1529. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1530. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->func), tstorm_flags);
  1531. }
  1532. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1533. u32 num, int *work)
  1534. {
  1535. struct cnic_local *cp = dev->cnic_priv;
  1536. struct l4_kwq_connect_req1 *kwqe1 =
  1537. (struct l4_kwq_connect_req1 *) wqes[0];
  1538. struct l4_kwq_connect_req3 *kwqe3;
  1539. struct l5cm_active_conn_buffer *conn_buf;
  1540. struct l5cm_conn_addr_params *conn_addr;
  1541. union l5cm_specific_data l5_data;
  1542. u32 l5_cid = kwqe1->pg_cid;
  1543. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1544. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1545. int ret;
  1546. if (num < 2) {
  1547. *work = num;
  1548. return -EINVAL;
  1549. }
  1550. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1551. *work = 3;
  1552. else
  1553. *work = 2;
  1554. if (num < *work) {
  1555. *work = num;
  1556. return -EINVAL;
  1557. }
  1558. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1559. printk(KERN_ERR PFX "%s: conn_buf size too big\n",
  1560. dev->netdev->name);
  1561. return -ENOMEM;
  1562. }
  1563. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1564. if (!conn_buf)
  1565. return -ENOMEM;
  1566. memset(conn_buf, 0, sizeof(*conn_buf));
  1567. conn_addr = &conn_buf->conn_addr_buf;
  1568. conn_addr->remote_addr_0 = csk->ha[0];
  1569. conn_addr->remote_addr_1 = csk->ha[1];
  1570. conn_addr->remote_addr_2 = csk->ha[2];
  1571. conn_addr->remote_addr_3 = csk->ha[3];
  1572. conn_addr->remote_addr_4 = csk->ha[4];
  1573. conn_addr->remote_addr_5 = csk->ha[5];
  1574. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1575. struct l4_kwq_connect_req2 *kwqe2 =
  1576. (struct l4_kwq_connect_req2 *) wqes[1];
  1577. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1578. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1579. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1580. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1581. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1582. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1583. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1584. }
  1585. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1586. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1587. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1588. conn_addr->local_tcp_port = kwqe1->src_port;
  1589. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1590. conn_addr->pmtu = kwqe3->pmtu;
  1591. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1592. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1593. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->func), csk->vlan_id);
  1594. cnic_bnx2x_set_tcp_timestamp(dev,
  1595. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1596. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1597. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1598. if (!ret)
  1599. ctx->ctx_flags |= CTX_FL_OFFLD_START;
  1600. return ret;
  1601. }
  1602. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1603. {
  1604. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1605. union l5cm_specific_data l5_data;
  1606. int ret;
  1607. memset(&l5_data, 0, sizeof(l5_data));
  1608. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1609. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1610. return ret;
  1611. }
  1612. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1613. {
  1614. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1615. union l5cm_specific_data l5_data;
  1616. int ret;
  1617. memset(&l5_data, 0, sizeof(l5_data));
  1618. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1619. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1620. return ret;
  1621. }
  1622. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1623. {
  1624. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1625. struct l4_kcq kcqe;
  1626. struct kcqe *cqes[1];
  1627. memset(&kcqe, 0, sizeof(kcqe));
  1628. kcqe.pg_host_opaque = req->host_opaque;
  1629. kcqe.pg_cid = req->host_opaque;
  1630. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1631. cqes[0] = (struct kcqe *) &kcqe;
  1632. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1633. return 0;
  1634. }
  1635. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1636. {
  1637. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1638. struct l4_kcq kcqe;
  1639. struct kcqe *cqes[1];
  1640. memset(&kcqe, 0, sizeof(kcqe));
  1641. kcqe.pg_host_opaque = req->pg_host_opaque;
  1642. kcqe.pg_cid = req->pg_cid;
  1643. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1644. cqes[0] = (struct kcqe *) &kcqe;
  1645. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1646. return 0;
  1647. }
  1648. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1649. u32 num_wqes)
  1650. {
  1651. int i, work, ret;
  1652. u32 opcode;
  1653. struct kwqe *kwqe;
  1654. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1655. return -EAGAIN; /* bnx2 is down */
  1656. for (i = 0; i < num_wqes; ) {
  1657. kwqe = wqes[i];
  1658. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1659. work = 1;
  1660. switch (opcode) {
  1661. case ISCSI_KWQE_OPCODE_INIT1:
  1662. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1663. break;
  1664. case ISCSI_KWQE_OPCODE_INIT2:
  1665. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1666. break;
  1667. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1668. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1669. num_wqes - i, &work);
  1670. break;
  1671. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1672. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1673. break;
  1674. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1675. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1676. break;
  1677. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1678. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1679. &work);
  1680. break;
  1681. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1682. ret = cnic_bnx2x_close(dev, kwqe);
  1683. break;
  1684. case L4_KWQE_OPCODE_VALUE_RESET:
  1685. ret = cnic_bnx2x_reset(dev, kwqe);
  1686. break;
  1687. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1688. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1689. break;
  1690. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1691. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1692. break;
  1693. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1694. ret = 0;
  1695. break;
  1696. default:
  1697. ret = 0;
  1698. printk(KERN_ERR PFX "%s: Unknown type of KWQE(0x%x)\n",
  1699. dev->netdev->name, opcode);
  1700. break;
  1701. }
  1702. if (ret < 0)
  1703. printk(KERN_ERR PFX "%s: KWQE(0x%x) failed\n",
  1704. dev->netdev->name, opcode);
  1705. i += work;
  1706. }
  1707. return 0;
  1708. }
  1709. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1710. {
  1711. struct cnic_local *cp = dev->cnic_priv;
  1712. int i, j;
  1713. i = 0;
  1714. j = 1;
  1715. while (num_cqes) {
  1716. struct cnic_ulp_ops *ulp_ops;
  1717. int ulp_type;
  1718. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1719. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1720. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1721. cnic_kwq_completion(dev, 1);
  1722. while (j < num_cqes) {
  1723. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1724. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1725. break;
  1726. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1727. cnic_kwq_completion(dev, 1);
  1728. j++;
  1729. }
  1730. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1731. ulp_type = CNIC_ULP_RDMA;
  1732. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1733. ulp_type = CNIC_ULP_ISCSI;
  1734. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1735. ulp_type = CNIC_ULP_L4;
  1736. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1737. goto end;
  1738. else {
  1739. printk(KERN_ERR PFX "%s: Unknown type of KCQE(0x%x)\n",
  1740. dev->netdev->name, kcqe_op_flag);
  1741. goto end;
  1742. }
  1743. rcu_read_lock();
  1744. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1745. if (likely(ulp_ops)) {
  1746. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1747. cp->completed_kcq + i, j);
  1748. }
  1749. rcu_read_unlock();
  1750. end:
  1751. num_cqes -= j;
  1752. i += j;
  1753. j = 1;
  1754. }
  1755. return;
  1756. }
  1757. static u16 cnic_bnx2_next_idx(u16 idx)
  1758. {
  1759. return idx + 1;
  1760. }
  1761. static u16 cnic_bnx2_hw_idx(u16 idx)
  1762. {
  1763. return idx;
  1764. }
  1765. static u16 cnic_bnx2x_next_idx(u16 idx)
  1766. {
  1767. idx++;
  1768. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1769. idx++;
  1770. return idx;
  1771. }
  1772. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1773. {
  1774. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1775. idx++;
  1776. return idx;
  1777. }
  1778. static int cnic_get_kcqes(struct cnic_dev *dev, u16 hw_prod, u16 *sw_prod)
  1779. {
  1780. struct cnic_local *cp = dev->cnic_priv;
  1781. u16 i, ri, last;
  1782. struct kcqe *kcqe;
  1783. int kcqe_cnt = 0, last_cnt = 0;
  1784. i = ri = last = *sw_prod;
  1785. ri &= MAX_KCQ_IDX;
  1786. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1787. kcqe = &cp->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1788. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1789. i = cp->next_idx(i);
  1790. ri = i & MAX_KCQ_IDX;
  1791. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1792. last_cnt = kcqe_cnt;
  1793. last = i;
  1794. }
  1795. }
  1796. *sw_prod = last;
  1797. return last_cnt;
  1798. }
  1799. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1800. {
  1801. u16 rx_cons = *cp->rx_cons_ptr;
  1802. u16 tx_cons = *cp->tx_cons_ptr;
  1803. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1804. cp->tx_cons = tx_cons;
  1805. cp->rx_cons = rx_cons;
  1806. uio_event_notify(cp->cnic_uinfo);
  1807. }
  1808. }
  1809. static int cnic_service_bnx2(void *data, void *status_blk)
  1810. {
  1811. struct cnic_dev *dev = data;
  1812. struct status_block *sblk = status_blk;
  1813. struct cnic_local *cp = dev->cnic_priv;
  1814. u32 status_idx = sblk->status_idx;
  1815. u16 hw_prod, sw_prod;
  1816. int kcqe_cnt;
  1817. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1818. return status_idx;
  1819. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1820. hw_prod = sblk->status_completion_producer_index;
  1821. sw_prod = cp->kcq_prod_idx;
  1822. while (sw_prod != hw_prod) {
  1823. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1824. if (kcqe_cnt == 0)
  1825. goto done;
  1826. service_kcqes(dev, kcqe_cnt);
  1827. /* Tell compiler that status_blk fields can change. */
  1828. barrier();
  1829. if (status_idx != sblk->status_idx) {
  1830. status_idx = sblk->status_idx;
  1831. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1832. hw_prod = sblk->status_completion_producer_index;
  1833. } else
  1834. break;
  1835. }
  1836. done:
  1837. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1838. cp->kcq_prod_idx = sw_prod;
  1839. cnic_chk_pkt_rings(cp);
  1840. return status_idx;
  1841. }
  1842. static void cnic_service_bnx2_msix(unsigned long data)
  1843. {
  1844. struct cnic_dev *dev = (struct cnic_dev *) data;
  1845. struct cnic_local *cp = dev->cnic_priv;
  1846. struct status_block_msix *status_blk = cp->bnx2_status_blk;
  1847. u32 status_idx = status_blk->status_idx;
  1848. u16 hw_prod, sw_prod;
  1849. int kcqe_cnt;
  1850. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1851. hw_prod = status_blk->status_completion_producer_index;
  1852. sw_prod = cp->kcq_prod_idx;
  1853. while (sw_prod != hw_prod) {
  1854. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1855. if (kcqe_cnt == 0)
  1856. goto done;
  1857. service_kcqes(dev, kcqe_cnt);
  1858. /* Tell compiler that status_blk fields can change. */
  1859. barrier();
  1860. if (status_idx != status_blk->status_idx) {
  1861. status_idx = status_blk->status_idx;
  1862. cp->kwq_con_idx = status_blk->status_cmd_consumer_index;
  1863. hw_prod = status_blk->status_completion_producer_index;
  1864. } else
  1865. break;
  1866. }
  1867. done:
  1868. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod);
  1869. cp->kcq_prod_idx = sw_prod;
  1870. cnic_chk_pkt_rings(cp);
  1871. cp->last_status_idx = status_idx;
  1872. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1873. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1874. }
  1875. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1876. {
  1877. struct cnic_dev *dev = dev_instance;
  1878. struct cnic_local *cp = dev->cnic_priv;
  1879. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1880. if (cp->ack_int)
  1881. cp->ack_int(dev);
  1882. prefetch(cp->status_blk);
  1883. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1884. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1885. tasklet_schedule(&cp->cnic_irq_task);
  1886. return IRQ_HANDLED;
  1887. }
  1888. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1889. u16 index, u8 op, u8 update)
  1890. {
  1891. struct cnic_local *cp = dev->cnic_priv;
  1892. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1893. COMMAND_REG_INT_ACK);
  1894. struct igu_ack_register igu_ack;
  1895. igu_ack.status_block_index = index;
  1896. igu_ack.sb_id_and_flags =
  1897. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1898. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1899. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1900. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1901. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  1902. }
  1903. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  1904. {
  1905. struct cnic_local *cp = dev->cnic_priv;
  1906. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID, 0,
  1907. IGU_INT_DISABLE, 0);
  1908. }
  1909. static void cnic_service_bnx2x_bh(unsigned long data)
  1910. {
  1911. struct cnic_dev *dev = (struct cnic_dev *) data;
  1912. struct cnic_local *cp = dev->cnic_priv;
  1913. u16 hw_prod, sw_prod;
  1914. struct cstorm_status_block_c *sblk =
  1915. &cp->bnx2x_status_blk->c_status_block;
  1916. u32 status_idx = sblk->status_block_index;
  1917. int kcqe_cnt;
  1918. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1919. return;
  1920. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1921. hw_prod = cp->hw_idx(hw_prod);
  1922. sw_prod = cp->kcq_prod_idx;
  1923. while (sw_prod != hw_prod) {
  1924. kcqe_cnt = cnic_get_kcqes(dev, hw_prod, &sw_prod);
  1925. if (kcqe_cnt == 0)
  1926. goto done;
  1927. service_kcqes(dev, kcqe_cnt);
  1928. /* Tell compiler that sblk fields can change. */
  1929. barrier();
  1930. if (status_idx == sblk->status_block_index)
  1931. break;
  1932. status_idx = sblk->status_block_index;
  1933. hw_prod = sblk->index_values[HC_INDEX_C_ISCSI_EQ_CONS];
  1934. hw_prod = cp->hw_idx(hw_prod);
  1935. }
  1936. done:
  1937. CNIC_WR16(dev, cp->kcq_io_addr, sw_prod + MAX_KCQ_IDX);
  1938. cnic_ack_bnx2x_int(dev, cp->status_blk_num, CSTORM_ID,
  1939. status_idx, IGU_INT_ENABLE, 1);
  1940. cp->kcq_prod_idx = sw_prod;
  1941. return;
  1942. }
  1943. static int cnic_service_bnx2x(void *data, void *status_blk)
  1944. {
  1945. struct cnic_dev *dev = data;
  1946. struct cnic_local *cp = dev->cnic_priv;
  1947. u16 prod = cp->kcq_prod_idx & MAX_KCQ_IDX;
  1948. prefetch(cp->status_blk);
  1949. prefetch(&cp->kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1950. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1951. tasklet_schedule(&cp->cnic_irq_task);
  1952. cnic_chk_pkt_rings(cp);
  1953. return 0;
  1954. }
  1955. static void cnic_ulp_stop(struct cnic_dev *dev)
  1956. {
  1957. struct cnic_local *cp = dev->cnic_priv;
  1958. int if_type;
  1959. if (cp->cnic_uinfo)
  1960. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  1961. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1962. struct cnic_ulp_ops *ulp_ops;
  1963. mutex_lock(&cnic_lock);
  1964. ulp_ops = cp->ulp_ops[if_type];
  1965. if (!ulp_ops) {
  1966. mutex_unlock(&cnic_lock);
  1967. continue;
  1968. }
  1969. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1970. mutex_unlock(&cnic_lock);
  1971. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1972. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  1973. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1974. }
  1975. }
  1976. static void cnic_ulp_start(struct cnic_dev *dev)
  1977. {
  1978. struct cnic_local *cp = dev->cnic_priv;
  1979. int if_type;
  1980. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  1981. struct cnic_ulp_ops *ulp_ops;
  1982. mutex_lock(&cnic_lock);
  1983. ulp_ops = cp->ulp_ops[if_type];
  1984. if (!ulp_ops || !ulp_ops->cnic_start) {
  1985. mutex_unlock(&cnic_lock);
  1986. continue;
  1987. }
  1988. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1989. mutex_unlock(&cnic_lock);
  1990. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  1991. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  1992. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  1993. }
  1994. }
  1995. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  1996. {
  1997. struct cnic_dev *dev = data;
  1998. switch (info->cmd) {
  1999. case CNIC_CTL_STOP_CMD:
  2000. cnic_hold(dev);
  2001. cnic_ulp_stop(dev);
  2002. cnic_stop_hw(dev);
  2003. cnic_put(dev);
  2004. break;
  2005. case CNIC_CTL_START_CMD:
  2006. cnic_hold(dev);
  2007. if (!cnic_start_hw(dev))
  2008. cnic_ulp_start(dev);
  2009. cnic_put(dev);
  2010. break;
  2011. case CNIC_CTL_COMPLETION_CMD: {
  2012. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2013. u32 l5_cid;
  2014. struct cnic_local *cp = dev->cnic_priv;
  2015. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2016. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2017. ctx->wait_cond = 1;
  2018. wake_up(&ctx->waitq);
  2019. }
  2020. break;
  2021. }
  2022. default:
  2023. return -EINVAL;
  2024. }
  2025. return 0;
  2026. }
  2027. static void cnic_ulp_init(struct cnic_dev *dev)
  2028. {
  2029. int i;
  2030. struct cnic_local *cp = dev->cnic_priv;
  2031. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2032. struct cnic_ulp_ops *ulp_ops;
  2033. mutex_lock(&cnic_lock);
  2034. ulp_ops = cnic_ulp_tbl[i];
  2035. if (!ulp_ops || !ulp_ops->cnic_init) {
  2036. mutex_unlock(&cnic_lock);
  2037. continue;
  2038. }
  2039. ulp_get(ulp_ops);
  2040. mutex_unlock(&cnic_lock);
  2041. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2042. ulp_ops->cnic_init(dev);
  2043. ulp_put(ulp_ops);
  2044. }
  2045. }
  2046. static void cnic_ulp_exit(struct cnic_dev *dev)
  2047. {
  2048. int i;
  2049. struct cnic_local *cp = dev->cnic_priv;
  2050. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2051. struct cnic_ulp_ops *ulp_ops;
  2052. mutex_lock(&cnic_lock);
  2053. ulp_ops = cnic_ulp_tbl[i];
  2054. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2055. mutex_unlock(&cnic_lock);
  2056. continue;
  2057. }
  2058. ulp_get(ulp_ops);
  2059. mutex_unlock(&cnic_lock);
  2060. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2061. ulp_ops->cnic_exit(dev);
  2062. ulp_put(ulp_ops);
  2063. }
  2064. }
  2065. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2066. {
  2067. struct cnic_dev *dev = csk->dev;
  2068. struct l4_kwq_offload_pg *l4kwqe;
  2069. struct kwqe *wqes[1];
  2070. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2071. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2072. wqes[0] = (struct kwqe *) l4kwqe;
  2073. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2074. l4kwqe->flags =
  2075. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2076. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2077. l4kwqe->da0 = csk->ha[0];
  2078. l4kwqe->da1 = csk->ha[1];
  2079. l4kwqe->da2 = csk->ha[2];
  2080. l4kwqe->da3 = csk->ha[3];
  2081. l4kwqe->da4 = csk->ha[4];
  2082. l4kwqe->da5 = csk->ha[5];
  2083. l4kwqe->sa0 = dev->mac_addr[0];
  2084. l4kwqe->sa1 = dev->mac_addr[1];
  2085. l4kwqe->sa2 = dev->mac_addr[2];
  2086. l4kwqe->sa3 = dev->mac_addr[3];
  2087. l4kwqe->sa4 = dev->mac_addr[4];
  2088. l4kwqe->sa5 = dev->mac_addr[5];
  2089. l4kwqe->etype = ETH_P_IP;
  2090. l4kwqe->ipid_count = DEF_IPID_COUNT;
  2091. l4kwqe->host_opaque = csk->l5_cid;
  2092. if (csk->vlan_id) {
  2093. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2094. l4kwqe->vlan_tag = csk->vlan_id;
  2095. l4kwqe->l2hdr_nbytes += 4;
  2096. }
  2097. return dev->submit_kwqes(dev, wqes, 1);
  2098. }
  2099. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2100. {
  2101. struct cnic_dev *dev = csk->dev;
  2102. struct l4_kwq_update_pg *l4kwqe;
  2103. struct kwqe *wqes[1];
  2104. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2105. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2106. wqes[0] = (struct kwqe *) l4kwqe;
  2107. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2108. l4kwqe->flags =
  2109. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2110. l4kwqe->pg_cid = csk->pg_cid;
  2111. l4kwqe->da0 = csk->ha[0];
  2112. l4kwqe->da1 = csk->ha[1];
  2113. l4kwqe->da2 = csk->ha[2];
  2114. l4kwqe->da3 = csk->ha[3];
  2115. l4kwqe->da4 = csk->ha[4];
  2116. l4kwqe->da5 = csk->ha[5];
  2117. l4kwqe->pg_host_opaque = csk->l5_cid;
  2118. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2119. return dev->submit_kwqes(dev, wqes, 1);
  2120. }
  2121. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2122. {
  2123. struct cnic_dev *dev = csk->dev;
  2124. struct l4_kwq_upload *l4kwqe;
  2125. struct kwqe *wqes[1];
  2126. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2127. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2128. wqes[0] = (struct kwqe *) l4kwqe;
  2129. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2130. l4kwqe->flags =
  2131. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2132. l4kwqe->cid = csk->pg_cid;
  2133. return dev->submit_kwqes(dev, wqes, 1);
  2134. }
  2135. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2136. {
  2137. struct cnic_dev *dev = csk->dev;
  2138. struct l4_kwq_connect_req1 *l4kwqe1;
  2139. struct l4_kwq_connect_req2 *l4kwqe2;
  2140. struct l4_kwq_connect_req3 *l4kwqe3;
  2141. struct kwqe *wqes[3];
  2142. u8 tcp_flags = 0;
  2143. int num_wqes = 2;
  2144. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2145. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2146. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2147. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2148. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2149. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2150. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2151. l4kwqe3->flags =
  2152. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2153. l4kwqe3->ka_timeout = csk->ka_timeout;
  2154. l4kwqe3->ka_interval = csk->ka_interval;
  2155. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2156. l4kwqe3->tos = csk->tos;
  2157. l4kwqe3->ttl = csk->ttl;
  2158. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2159. l4kwqe3->pmtu = csk->mtu;
  2160. l4kwqe3->rcv_buf = csk->rcv_buf;
  2161. l4kwqe3->snd_buf = csk->snd_buf;
  2162. l4kwqe3->seed = csk->seed;
  2163. wqes[0] = (struct kwqe *) l4kwqe1;
  2164. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2165. wqes[1] = (struct kwqe *) l4kwqe2;
  2166. wqes[2] = (struct kwqe *) l4kwqe3;
  2167. num_wqes = 3;
  2168. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2169. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2170. l4kwqe2->flags =
  2171. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2172. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2173. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2174. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2175. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2176. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2177. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2178. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2179. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2180. sizeof(struct tcphdr);
  2181. } else {
  2182. wqes[1] = (struct kwqe *) l4kwqe3;
  2183. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2184. sizeof(struct tcphdr);
  2185. }
  2186. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2187. l4kwqe1->flags =
  2188. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2189. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2190. l4kwqe1->cid = csk->cid;
  2191. l4kwqe1->pg_cid = csk->pg_cid;
  2192. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2193. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2194. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2195. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2196. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2197. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2198. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2199. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2200. if (csk->tcp_flags & SK_TCP_NAGLE)
  2201. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2202. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2203. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2204. if (csk->tcp_flags & SK_TCP_SACK)
  2205. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2206. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2207. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2208. l4kwqe1->tcp_flags = tcp_flags;
  2209. return dev->submit_kwqes(dev, wqes, num_wqes);
  2210. }
  2211. static int cnic_cm_close_req(struct cnic_sock *csk)
  2212. {
  2213. struct cnic_dev *dev = csk->dev;
  2214. struct l4_kwq_close_req *l4kwqe;
  2215. struct kwqe *wqes[1];
  2216. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2217. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2218. wqes[0] = (struct kwqe *) l4kwqe;
  2219. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2220. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2221. l4kwqe->cid = csk->cid;
  2222. return dev->submit_kwqes(dev, wqes, 1);
  2223. }
  2224. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2225. {
  2226. struct cnic_dev *dev = csk->dev;
  2227. struct l4_kwq_reset_req *l4kwqe;
  2228. struct kwqe *wqes[1];
  2229. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2230. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2231. wqes[0] = (struct kwqe *) l4kwqe;
  2232. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2233. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2234. l4kwqe->cid = csk->cid;
  2235. return dev->submit_kwqes(dev, wqes, 1);
  2236. }
  2237. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2238. u32 l5_cid, struct cnic_sock **csk, void *context)
  2239. {
  2240. struct cnic_local *cp = dev->cnic_priv;
  2241. struct cnic_sock *csk1;
  2242. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2243. return -EINVAL;
  2244. csk1 = &cp->csk_tbl[l5_cid];
  2245. if (atomic_read(&csk1->ref_count))
  2246. return -EAGAIN;
  2247. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2248. return -EBUSY;
  2249. csk1->dev = dev;
  2250. csk1->cid = cid;
  2251. csk1->l5_cid = l5_cid;
  2252. csk1->ulp_type = ulp_type;
  2253. csk1->context = context;
  2254. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2255. csk1->ka_interval = DEF_KA_INTERVAL;
  2256. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2257. csk1->tos = DEF_TOS;
  2258. csk1->ttl = DEF_TTL;
  2259. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2260. csk1->rcv_buf = DEF_RCV_BUF;
  2261. csk1->snd_buf = DEF_SND_BUF;
  2262. csk1->seed = DEF_SEED;
  2263. *csk = csk1;
  2264. return 0;
  2265. }
  2266. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2267. {
  2268. if (csk->src_port) {
  2269. struct cnic_dev *dev = csk->dev;
  2270. struct cnic_local *cp = dev->cnic_priv;
  2271. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2272. csk->src_port = 0;
  2273. }
  2274. }
  2275. static void cnic_close_conn(struct cnic_sock *csk)
  2276. {
  2277. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2278. cnic_cm_upload_pg(csk);
  2279. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2280. }
  2281. cnic_cm_cleanup(csk);
  2282. }
  2283. static int cnic_cm_destroy(struct cnic_sock *csk)
  2284. {
  2285. if (!cnic_in_use(csk))
  2286. return -EINVAL;
  2287. csk_hold(csk);
  2288. clear_bit(SK_F_INUSE, &csk->flags);
  2289. smp_mb__after_clear_bit();
  2290. while (atomic_read(&csk->ref_count) != 1)
  2291. msleep(1);
  2292. cnic_cm_cleanup(csk);
  2293. csk->flags = 0;
  2294. csk_put(csk);
  2295. return 0;
  2296. }
  2297. static inline u16 cnic_get_vlan(struct net_device *dev,
  2298. struct net_device **vlan_dev)
  2299. {
  2300. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2301. *vlan_dev = vlan_dev_real_dev(dev);
  2302. return vlan_dev_vlan_id(dev);
  2303. }
  2304. *vlan_dev = dev;
  2305. return 0;
  2306. }
  2307. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2308. struct dst_entry **dst)
  2309. {
  2310. #if defined(CONFIG_INET)
  2311. struct flowi fl;
  2312. int err;
  2313. struct rtable *rt;
  2314. memset(&fl, 0, sizeof(fl));
  2315. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2316. err = ip_route_output_key(&init_net, &rt, &fl);
  2317. if (!err)
  2318. *dst = &rt->u.dst;
  2319. return err;
  2320. #else
  2321. return -ENETUNREACH;
  2322. #endif
  2323. }
  2324. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2325. struct dst_entry **dst)
  2326. {
  2327. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2328. struct flowi fl;
  2329. memset(&fl, 0, sizeof(fl));
  2330. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2331. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2332. fl.oif = dst_addr->sin6_scope_id;
  2333. *dst = ip6_route_output(&init_net, NULL, &fl);
  2334. if (*dst)
  2335. return 0;
  2336. #endif
  2337. return -ENETUNREACH;
  2338. }
  2339. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2340. int ulp_type)
  2341. {
  2342. struct cnic_dev *dev = NULL;
  2343. struct dst_entry *dst;
  2344. struct net_device *netdev = NULL;
  2345. int err = -ENETUNREACH;
  2346. if (dst_addr->sin_family == AF_INET)
  2347. err = cnic_get_v4_route(dst_addr, &dst);
  2348. else if (dst_addr->sin_family == AF_INET6) {
  2349. struct sockaddr_in6 *dst_addr6 =
  2350. (struct sockaddr_in6 *) dst_addr;
  2351. err = cnic_get_v6_route(dst_addr6, &dst);
  2352. } else
  2353. return NULL;
  2354. if (err)
  2355. return NULL;
  2356. if (!dst->dev)
  2357. goto done;
  2358. cnic_get_vlan(dst->dev, &netdev);
  2359. dev = cnic_from_netdev(netdev);
  2360. done:
  2361. dst_release(dst);
  2362. if (dev)
  2363. cnic_put(dev);
  2364. return dev;
  2365. }
  2366. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2367. {
  2368. struct cnic_dev *dev = csk->dev;
  2369. struct cnic_local *cp = dev->cnic_priv;
  2370. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2371. }
  2372. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2373. {
  2374. struct cnic_dev *dev = csk->dev;
  2375. struct cnic_local *cp = dev->cnic_priv;
  2376. int is_v6, err, rc = -ENETUNREACH;
  2377. struct dst_entry *dst;
  2378. struct net_device *realdev;
  2379. u32 local_port;
  2380. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2381. saddr->remote.v6.sin6_family == AF_INET6)
  2382. is_v6 = 1;
  2383. else if (saddr->local.v4.sin_family == AF_INET &&
  2384. saddr->remote.v4.sin_family == AF_INET)
  2385. is_v6 = 0;
  2386. else
  2387. return -EINVAL;
  2388. clear_bit(SK_F_IPV6, &csk->flags);
  2389. if (is_v6) {
  2390. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2391. set_bit(SK_F_IPV6, &csk->flags);
  2392. err = cnic_get_v6_route(&saddr->remote.v6, &dst);
  2393. if (err)
  2394. return err;
  2395. if (!dst || dst->error || !dst->dev)
  2396. goto err_out;
  2397. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2398. sizeof(struct in6_addr));
  2399. csk->dst_port = saddr->remote.v6.sin6_port;
  2400. local_port = saddr->local.v6.sin6_port;
  2401. #else
  2402. return rc;
  2403. #endif
  2404. } else {
  2405. err = cnic_get_v4_route(&saddr->remote.v4, &dst);
  2406. if (err)
  2407. return err;
  2408. if (!dst || dst->error || !dst->dev)
  2409. goto err_out;
  2410. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2411. csk->dst_port = saddr->remote.v4.sin_port;
  2412. local_port = saddr->local.v4.sin_port;
  2413. }
  2414. csk->vlan_id = cnic_get_vlan(dst->dev, &realdev);
  2415. if (realdev != dev->netdev)
  2416. goto err_out;
  2417. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2418. local_port < CNIC_LOCAL_PORT_MAX) {
  2419. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2420. local_port = 0;
  2421. } else
  2422. local_port = 0;
  2423. if (!local_port) {
  2424. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2425. if (local_port == -1) {
  2426. rc = -ENOMEM;
  2427. goto err_out;
  2428. }
  2429. }
  2430. csk->src_port = local_port;
  2431. csk->mtu = dst_mtu(dst);
  2432. rc = 0;
  2433. err_out:
  2434. dst_release(dst);
  2435. return rc;
  2436. }
  2437. static void cnic_init_csk_state(struct cnic_sock *csk)
  2438. {
  2439. csk->state = 0;
  2440. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2441. clear_bit(SK_F_CLOSING, &csk->flags);
  2442. }
  2443. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2444. {
  2445. int err = 0;
  2446. if (!cnic_in_use(csk))
  2447. return -EINVAL;
  2448. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2449. return -EINVAL;
  2450. cnic_init_csk_state(csk);
  2451. err = cnic_get_route(csk, saddr);
  2452. if (err)
  2453. goto err_out;
  2454. err = cnic_resolve_addr(csk, saddr);
  2455. if (!err)
  2456. return 0;
  2457. err_out:
  2458. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2459. return err;
  2460. }
  2461. static int cnic_cm_abort(struct cnic_sock *csk)
  2462. {
  2463. struct cnic_local *cp = csk->dev->cnic_priv;
  2464. u32 opcode;
  2465. if (!cnic_in_use(csk))
  2466. return -EINVAL;
  2467. if (cnic_abort_prep(csk))
  2468. return cnic_cm_abort_req(csk);
  2469. /* Getting here means that we haven't started connect, or
  2470. * connect was not successful.
  2471. */
  2472. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2473. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2474. opcode = csk->state;
  2475. else
  2476. opcode = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2477. cp->close_conn(csk, opcode);
  2478. return 0;
  2479. }
  2480. static int cnic_cm_close(struct cnic_sock *csk)
  2481. {
  2482. if (!cnic_in_use(csk))
  2483. return -EINVAL;
  2484. if (cnic_close_prep(csk)) {
  2485. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2486. return cnic_cm_close_req(csk);
  2487. }
  2488. return 0;
  2489. }
  2490. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2491. u8 opcode)
  2492. {
  2493. struct cnic_ulp_ops *ulp_ops;
  2494. int ulp_type = csk->ulp_type;
  2495. rcu_read_lock();
  2496. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2497. if (ulp_ops) {
  2498. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2499. ulp_ops->cm_connect_complete(csk);
  2500. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2501. ulp_ops->cm_close_complete(csk);
  2502. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2503. ulp_ops->cm_remote_abort(csk);
  2504. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2505. ulp_ops->cm_abort_complete(csk);
  2506. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2507. ulp_ops->cm_remote_close(csk);
  2508. }
  2509. rcu_read_unlock();
  2510. }
  2511. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2512. {
  2513. if (cnic_offld_prep(csk)) {
  2514. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2515. cnic_cm_update_pg(csk);
  2516. else
  2517. cnic_cm_offload_pg(csk);
  2518. }
  2519. return 0;
  2520. }
  2521. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2522. {
  2523. struct cnic_local *cp = dev->cnic_priv;
  2524. u32 l5_cid = kcqe->pg_host_opaque;
  2525. u8 opcode = kcqe->op_code;
  2526. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2527. csk_hold(csk);
  2528. if (!cnic_in_use(csk))
  2529. goto done;
  2530. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2531. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2532. goto done;
  2533. }
  2534. csk->pg_cid = kcqe->pg_cid;
  2535. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2536. cnic_cm_conn_req(csk);
  2537. done:
  2538. csk_put(csk);
  2539. }
  2540. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2541. {
  2542. struct cnic_local *cp = dev->cnic_priv;
  2543. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2544. u8 opcode = l4kcqe->op_code;
  2545. u32 l5_cid;
  2546. struct cnic_sock *csk;
  2547. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2548. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2549. cnic_cm_process_offld_pg(dev, l4kcqe);
  2550. return;
  2551. }
  2552. l5_cid = l4kcqe->conn_id;
  2553. if (opcode & 0x80)
  2554. l5_cid = l4kcqe->cid;
  2555. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2556. return;
  2557. csk = &cp->csk_tbl[l5_cid];
  2558. csk_hold(csk);
  2559. if (!cnic_in_use(csk)) {
  2560. csk_put(csk);
  2561. return;
  2562. }
  2563. switch (opcode) {
  2564. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2565. if (l4kcqe->status == 0)
  2566. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2567. smp_mb__before_clear_bit();
  2568. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2569. cnic_cm_upcall(cp, csk, opcode);
  2570. break;
  2571. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2572. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags))
  2573. csk->state = opcode;
  2574. /* fall through */
  2575. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2576. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2577. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2578. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2579. cp->close_conn(csk, opcode);
  2580. break;
  2581. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2582. cnic_cm_upcall(cp, csk, opcode);
  2583. break;
  2584. }
  2585. csk_put(csk);
  2586. }
  2587. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2588. {
  2589. struct cnic_dev *dev = data;
  2590. int i;
  2591. for (i = 0; i < num; i++)
  2592. cnic_cm_process_kcqe(dev, kcqe[i]);
  2593. }
  2594. static struct cnic_ulp_ops cm_ulp_ops = {
  2595. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2596. };
  2597. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2598. {
  2599. struct cnic_local *cp = dev->cnic_priv;
  2600. kfree(cp->csk_tbl);
  2601. cp->csk_tbl = NULL;
  2602. cnic_free_id_tbl(&cp->csk_port_tbl);
  2603. }
  2604. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2605. {
  2606. struct cnic_local *cp = dev->cnic_priv;
  2607. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2608. GFP_KERNEL);
  2609. if (!cp->csk_tbl)
  2610. return -ENOMEM;
  2611. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2612. CNIC_LOCAL_PORT_MIN)) {
  2613. cnic_cm_free_mem(dev);
  2614. return -ENOMEM;
  2615. }
  2616. return 0;
  2617. }
  2618. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2619. {
  2620. if ((opcode == csk->state) ||
  2621. (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED &&
  2622. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)) {
  2623. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags))
  2624. return 1;
  2625. }
  2626. return 0;
  2627. }
  2628. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2629. {
  2630. struct cnic_dev *dev = csk->dev;
  2631. struct cnic_local *cp = dev->cnic_priv;
  2632. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2633. if (cnic_ready_to_close(csk, opcode)) {
  2634. cnic_close_conn(csk);
  2635. cnic_cm_upcall(cp, csk, opcode);
  2636. }
  2637. }
  2638. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2639. {
  2640. }
  2641. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2642. {
  2643. u32 seed;
  2644. get_random_bytes(&seed, 4);
  2645. cnic_ctx_wr(dev, 45, 0, seed);
  2646. return 0;
  2647. }
  2648. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2649. {
  2650. struct cnic_dev *dev = csk->dev;
  2651. struct cnic_local *cp = dev->cnic_priv;
  2652. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2653. union l5cm_specific_data l5_data;
  2654. u32 cmd = 0;
  2655. int close_complete = 0;
  2656. switch (opcode) {
  2657. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2658. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2659. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2660. if (cnic_ready_to_close(csk, opcode))
  2661. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2662. break;
  2663. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2664. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2665. break;
  2666. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2667. close_complete = 1;
  2668. break;
  2669. }
  2670. if (cmd) {
  2671. memset(&l5_data, 0, sizeof(l5_data));
  2672. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2673. &l5_data);
  2674. } else if (close_complete) {
  2675. ctx->timestamp = jiffies;
  2676. cnic_close_conn(csk);
  2677. cnic_cm_upcall(cp, csk, csk->state);
  2678. }
  2679. }
  2680. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2681. {
  2682. }
  2683. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2684. {
  2685. struct cnic_local *cp = dev->cnic_priv;
  2686. int func = CNIC_FUNC(cp);
  2687. cnic_init_bnx2x_mac(dev);
  2688. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2689. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2690. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(func), 0);
  2691. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2692. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(func), 1);
  2693. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2694. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(func),
  2695. DEF_MAX_DA_COUNT);
  2696. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2697. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(func), DEF_TTL);
  2698. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2699. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(func), DEF_TOS);
  2700. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2701. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(func), 2);
  2702. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2703. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(func), DEF_SWS_TIMER);
  2704. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(func),
  2705. DEF_MAX_CWND);
  2706. return 0;
  2707. }
  2708. static int cnic_cm_open(struct cnic_dev *dev)
  2709. {
  2710. struct cnic_local *cp = dev->cnic_priv;
  2711. int err;
  2712. err = cnic_cm_alloc_mem(dev);
  2713. if (err)
  2714. return err;
  2715. err = cp->start_cm(dev);
  2716. if (err)
  2717. goto err_out;
  2718. dev->cm_create = cnic_cm_create;
  2719. dev->cm_destroy = cnic_cm_destroy;
  2720. dev->cm_connect = cnic_cm_connect;
  2721. dev->cm_abort = cnic_cm_abort;
  2722. dev->cm_close = cnic_cm_close;
  2723. dev->cm_select_dev = cnic_cm_select_dev;
  2724. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2725. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2726. return 0;
  2727. err_out:
  2728. cnic_cm_free_mem(dev);
  2729. return err;
  2730. }
  2731. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2732. {
  2733. struct cnic_local *cp = dev->cnic_priv;
  2734. int i;
  2735. cp->stop_cm(dev);
  2736. if (!cp->csk_tbl)
  2737. return 0;
  2738. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2739. struct cnic_sock *csk = &cp->csk_tbl[i];
  2740. clear_bit(SK_F_INUSE, &csk->flags);
  2741. cnic_cm_cleanup(csk);
  2742. }
  2743. cnic_cm_free_mem(dev);
  2744. return 0;
  2745. }
  2746. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2747. {
  2748. struct cnic_local *cp = dev->cnic_priv;
  2749. u32 cid_addr;
  2750. int i;
  2751. if (CHIP_NUM(cp) == CHIP_NUM_5709)
  2752. return;
  2753. cid_addr = GET_CID_ADDR(cid);
  2754. for (i = 0; i < CTX_SIZE; i += 4)
  2755. cnic_ctx_wr(dev, cid_addr, i, 0);
  2756. }
  2757. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2758. {
  2759. struct cnic_local *cp = dev->cnic_priv;
  2760. int ret = 0, i;
  2761. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2762. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2763. return 0;
  2764. for (i = 0; i < cp->ctx_blks; i++) {
  2765. int j;
  2766. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2767. u32 val;
  2768. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2769. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2770. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2771. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2772. (u64) cp->ctx_arr[i].mapping >> 32);
  2773. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2774. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2775. for (j = 0; j < 10; j++) {
  2776. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2777. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2778. break;
  2779. udelay(5);
  2780. }
  2781. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2782. ret = -EBUSY;
  2783. break;
  2784. }
  2785. }
  2786. return ret;
  2787. }
  2788. static void cnic_free_irq(struct cnic_dev *dev)
  2789. {
  2790. struct cnic_local *cp = dev->cnic_priv;
  2791. struct cnic_eth_dev *ethdev = cp->ethdev;
  2792. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2793. cp->disable_int_sync(dev);
  2794. tasklet_disable(&cp->cnic_irq_task);
  2795. free_irq(ethdev->irq_arr[0].vector, dev);
  2796. }
  2797. }
  2798. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2799. {
  2800. struct cnic_local *cp = dev->cnic_priv;
  2801. struct cnic_eth_dev *ethdev = cp->ethdev;
  2802. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2803. int err, i = 0;
  2804. int sblk_num = cp->status_blk_num;
  2805. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2806. BNX2_HC_SB_CONFIG_1;
  2807. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2808. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  2809. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  2810. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  2811. cp->bnx2_status_blk = cp->status_blk;
  2812. cp->last_status_idx = cp->bnx2_status_blk->status_idx;
  2813. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  2814. (unsigned long) dev);
  2815. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  2816. "cnic", dev);
  2817. if (err) {
  2818. tasklet_disable(&cp->cnic_irq_task);
  2819. return err;
  2820. }
  2821. while (cp->bnx2_status_blk->status_completion_producer_index &&
  2822. i < 10) {
  2823. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  2824. 1 << (11 + sblk_num));
  2825. udelay(10);
  2826. i++;
  2827. barrier();
  2828. }
  2829. if (cp->bnx2_status_blk->status_completion_producer_index) {
  2830. cnic_free_irq(dev);
  2831. goto failed;
  2832. }
  2833. } else {
  2834. struct status_block *sblk = cp->status_blk;
  2835. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  2836. int i = 0;
  2837. while (sblk->status_completion_producer_index && i < 10) {
  2838. CNIC_WR(dev, BNX2_HC_COMMAND,
  2839. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2840. udelay(10);
  2841. i++;
  2842. barrier();
  2843. }
  2844. if (sblk->status_completion_producer_index)
  2845. goto failed;
  2846. }
  2847. return 0;
  2848. failed:
  2849. printk(KERN_ERR PFX "%s: " "KCQ index not resetting to 0.\n",
  2850. dev->netdev->name);
  2851. return -EBUSY;
  2852. }
  2853. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  2854. {
  2855. struct cnic_local *cp = dev->cnic_priv;
  2856. struct cnic_eth_dev *ethdev = cp->ethdev;
  2857. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2858. return;
  2859. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2860. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2861. }
  2862. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  2863. {
  2864. struct cnic_local *cp = dev->cnic_priv;
  2865. struct cnic_eth_dev *ethdev = cp->ethdev;
  2866. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2867. return;
  2868. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2869. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  2870. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  2871. synchronize_irq(ethdev->irq_arr[0].vector);
  2872. }
  2873. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  2874. {
  2875. struct cnic_local *cp = dev->cnic_priv;
  2876. struct cnic_eth_dev *ethdev = cp->ethdev;
  2877. u32 cid_addr, tx_cid, sb_id;
  2878. u32 val, offset0, offset1, offset2, offset3;
  2879. int i;
  2880. struct tx_bd *txbd;
  2881. dma_addr_t buf_map;
  2882. struct status_block *s_blk = cp->status_blk;
  2883. sb_id = cp->status_blk_num;
  2884. tx_cid = 20;
  2885. cnic_init_context(dev, tx_cid);
  2886. cnic_init_context(dev, tx_cid + 1);
  2887. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  2888. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2889. struct status_block_msix *sblk = cp->status_blk;
  2890. tx_cid = TX_TSS_CID + sb_id - 1;
  2891. cnic_init_context(dev, tx_cid);
  2892. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  2893. (TX_TSS_CID << 7));
  2894. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  2895. }
  2896. cp->tx_cons = *cp->tx_cons_ptr;
  2897. cid_addr = GET_CID_ADDR(tx_cid);
  2898. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  2899. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  2900. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  2901. cnic_ctx_wr(dev, cid_addr2, i, 0);
  2902. offset0 = BNX2_L2CTX_TYPE_XI;
  2903. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  2904. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  2905. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  2906. } else {
  2907. offset0 = BNX2_L2CTX_TYPE;
  2908. offset1 = BNX2_L2CTX_CMD_TYPE;
  2909. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  2910. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  2911. }
  2912. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  2913. cnic_ctx_wr(dev, cid_addr, offset0, val);
  2914. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  2915. cnic_ctx_wr(dev, cid_addr, offset1, val);
  2916. txbd = (struct tx_bd *) cp->l2_ring;
  2917. buf_map = cp->l2_buf_map;
  2918. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  2919. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  2920. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2921. }
  2922. val = (u64) cp->l2_ring_map >> 32;
  2923. cnic_ctx_wr(dev, cid_addr, offset2, val);
  2924. txbd->tx_bd_haddr_hi = val;
  2925. val = (u64) cp->l2_ring_map & 0xffffffff;
  2926. cnic_ctx_wr(dev, cid_addr, offset3, val);
  2927. txbd->tx_bd_haddr_lo = val;
  2928. }
  2929. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  2930. {
  2931. struct cnic_local *cp = dev->cnic_priv;
  2932. struct cnic_eth_dev *ethdev = cp->ethdev;
  2933. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  2934. int i;
  2935. struct rx_bd *rxbd;
  2936. struct status_block *s_blk = cp->status_blk;
  2937. sb_id = cp->status_blk_num;
  2938. cnic_init_context(dev, 2);
  2939. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  2940. coal_reg = BNX2_HC_COMMAND;
  2941. coal_val = CNIC_RD(dev, coal_reg);
  2942. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2943. struct status_block_msix *sblk = cp->status_blk;
  2944. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  2945. coal_reg = BNX2_HC_COALESCE_NOW;
  2946. coal_val = 1 << (11 + sb_id);
  2947. }
  2948. i = 0;
  2949. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  2950. CNIC_WR(dev, coal_reg, coal_val);
  2951. udelay(10);
  2952. i++;
  2953. barrier();
  2954. }
  2955. cp->rx_cons = *cp->rx_cons_ptr;
  2956. cid_addr = GET_CID_ADDR(2);
  2957. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  2958. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  2959. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  2960. if (sb_id == 0)
  2961. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  2962. else
  2963. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  2964. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  2965. rxbd = (struct rx_bd *) (cp->l2_ring + BCM_PAGE_SIZE);
  2966. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  2967. dma_addr_t buf_map;
  2968. int n = (i % cp->l2_rx_ring_size) + 1;
  2969. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  2970. rxbd->rx_bd_len = cp->l2_single_buf_size;
  2971. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  2972. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  2973. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  2974. }
  2975. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  2976. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  2977. rxbd->rx_bd_haddr_hi = val;
  2978. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  2979. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  2980. rxbd->rx_bd_haddr_lo = val;
  2981. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  2982. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  2983. }
  2984. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  2985. {
  2986. struct kwqe *wqes[1], l2kwqe;
  2987. memset(&l2kwqe, 0, sizeof(l2kwqe));
  2988. wqes[0] = &l2kwqe;
  2989. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  2990. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  2991. KWQE_OPCODE_SHIFT) | 2;
  2992. dev->submit_kwqes(dev, wqes, 1);
  2993. }
  2994. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  2995. {
  2996. struct cnic_local *cp = dev->cnic_priv;
  2997. u32 val;
  2998. val = cp->func << 2;
  2999. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3000. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3001. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3002. dev->mac_addr[0] = (u8) (val >> 8);
  3003. dev->mac_addr[1] = (u8) val;
  3004. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3005. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3006. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3007. dev->mac_addr[2] = (u8) (val >> 24);
  3008. dev->mac_addr[3] = (u8) (val >> 16);
  3009. dev->mac_addr[4] = (u8) (val >> 8);
  3010. dev->mac_addr[5] = (u8) val;
  3011. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3012. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3013. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3014. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3015. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3016. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3017. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3018. }
  3019. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3020. {
  3021. struct cnic_local *cp = dev->cnic_priv;
  3022. struct cnic_eth_dev *ethdev = cp->ethdev;
  3023. struct status_block *sblk = cp->status_blk;
  3024. u32 val;
  3025. int err;
  3026. cnic_set_bnx2_mac(dev);
  3027. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3028. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3029. if (BCM_PAGE_BITS > 12)
  3030. val |= (12 - 8) << 4;
  3031. else
  3032. val |= (BCM_PAGE_BITS - 8) << 4;
  3033. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3034. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3035. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3036. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3037. err = cnic_setup_5709_context(dev, 1);
  3038. if (err)
  3039. return err;
  3040. cnic_init_context(dev, KWQ_CID);
  3041. cnic_init_context(dev, KCQ_CID);
  3042. cp->kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3043. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3044. cp->max_kwq_idx = MAX_KWQ_IDX;
  3045. cp->kwq_prod_idx = 0;
  3046. cp->kwq_con_idx = 0;
  3047. cp->cnic_local_flags |= CNIC_LCL_FL_KWQ_INIT;
  3048. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3049. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3050. else
  3051. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3052. /* Initialize the kernel work queue context. */
  3053. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3054. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3055. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3056. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3057. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3058. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3059. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3060. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3061. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3062. val = (u32) cp->kwq_info.pgtbl_map;
  3063. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3064. cp->kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3065. cp->kcq_io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3066. cp->kcq_prod_idx = 0;
  3067. /* Initialize the kernel complete queue context. */
  3068. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3069. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3070. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3071. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3072. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3073. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3074. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3075. val = (u32) ((u64) cp->kcq_info.pgtbl_map >> 32);
  3076. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3077. val = (u32) cp->kcq_info.pgtbl_map;
  3078. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3079. cp->int_num = 0;
  3080. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3081. u32 sb_id = cp->status_blk_num;
  3082. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3083. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3084. cnic_ctx_wr(dev, cp->kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3085. cnic_ctx_wr(dev, cp->kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3086. }
  3087. /* Enable Commnad Scheduler notification when we write to the
  3088. * host producer index of the kernel contexts. */
  3089. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3090. /* Enable Command Scheduler notification when we write to either
  3091. * the Send Queue or Receive Queue producer indexes of the kernel
  3092. * bypass contexts. */
  3093. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3094. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3095. /* Notify COM when the driver post an application buffer. */
  3096. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3097. /* Set the CP and COM doorbells. These two processors polls the
  3098. * doorbell for a non zero value before running. This must be done
  3099. * after setting up the kernel queue contexts. */
  3100. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3101. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3102. cnic_init_bnx2_tx_ring(dev);
  3103. cnic_init_bnx2_rx_ring(dev);
  3104. err = cnic_init_bnx2_irq(dev);
  3105. if (err) {
  3106. printk(KERN_ERR PFX "%s: cnic_init_irq failed\n",
  3107. dev->netdev->name);
  3108. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3109. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3110. return err;
  3111. }
  3112. return 0;
  3113. }
  3114. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3115. {
  3116. struct cnic_local *cp = dev->cnic_priv;
  3117. struct cnic_eth_dev *ethdev = cp->ethdev;
  3118. u32 start_offset = ethdev->ctx_tbl_offset;
  3119. int i;
  3120. for (i = 0; i < cp->ctx_blks; i++) {
  3121. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3122. dma_addr_t map = ctx->mapping;
  3123. if (cp->ctx_align) {
  3124. unsigned long mask = cp->ctx_align - 1;
  3125. map = (map + mask) & ~mask;
  3126. }
  3127. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3128. }
  3129. }
  3130. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3131. {
  3132. struct cnic_local *cp = dev->cnic_priv;
  3133. struct cnic_eth_dev *ethdev = cp->ethdev;
  3134. int err = 0;
  3135. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3136. (unsigned long) dev);
  3137. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3138. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0,
  3139. "cnic", dev);
  3140. if (err)
  3141. tasklet_disable(&cp->cnic_irq_task);
  3142. }
  3143. return err;
  3144. }
  3145. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3146. {
  3147. struct cnic_local *cp = dev->cnic_priv;
  3148. u8 sb_id = cp->status_blk_num;
  3149. int port = CNIC_PORT(cp);
  3150. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3151. CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
  3152. HC_INDEX_C_ISCSI_EQ_CONS),
  3153. 64 / 12);
  3154. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3155. CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
  3156. HC_INDEX_C_ISCSI_EQ_CONS), 0);
  3157. }
  3158. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3159. {
  3160. }
  3161. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev)
  3162. {
  3163. struct cnic_local *cp = dev->cnic_priv;
  3164. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) cp->l2_ring;
  3165. struct eth_context *context;
  3166. struct regpair context_addr;
  3167. dma_addr_t buf_map;
  3168. int func = CNIC_FUNC(cp);
  3169. int port = CNIC_PORT(cp);
  3170. int i;
  3171. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3172. u32 val;
  3173. memset(txbd, 0, BCM_PAGE_SIZE);
  3174. buf_map = cp->l2_buf_map;
  3175. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3176. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3177. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3178. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3179. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3180. reg_bd->addr_hi = start_bd->addr_hi;
  3181. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3182. start_bd->nbytes = cpu_to_le16(0x10);
  3183. start_bd->nbd = cpu_to_le16(3);
  3184. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3185. start_bd->general_data = (UNICAST_ADDRESS <<
  3186. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3187. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3188. }
  3189. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 1, &context_addr);
  3190. val = (u64) cp->l2_ring_map >> 32;
  3191. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3192. context->xstorm_st_context.tx_bd_page_base_hi = val;
  3193. val = (u64) cp->l2_ring_map & 0xffffffff;
  3194. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3195. context->xstorm_st_context.tx_bd_page_base_lo = val;
  3196. context->cstorm_st_context.sb_index_number =
  3197. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS;
  3198. context->cstorm_st_context.status_block_id = BNX2X_DEF_SB_ID;
  3199. context->xstorm_st_context.statistics_data = (cli |
  3200. XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
  3201. context->xstorm_ag_context.cdu_reserved =
  3202. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3203. CDU_REGION_NUMBER_XCM_AG,
  3204. ETH_CONNECTION_TYPE);
  3205. /* reset xstorm per client statistics */
  3206. val = BAR_XSTRORM_INTMEM +
  3207. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3208. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3209. CNIC_WR(dev, val + i * 4, 0);
  3210. cp->tx_cons_ptr =
  3211. &cp->bnx2x_def_status_blk->c_def_status_block.index_values[
  3212. HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS];
  3213. }
  3214. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev)
  3215. {
  3216. struct cnic_local *cp = dev->cnic_priv;
  3217. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (cp->l2_ring +
  3218. BCM_PAGE_SIZE);
  3219. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3220. (cp->l2_ring + (2 * BCM_PAGE_SIZE));
  3221. struct eth_context *context;
  3222. struct regpair context_addr;
  3223. int i;
  3224. int port = CNIC_PORT(cp);
  3225. int func = CNIC_FUNC(cp);
  3226. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3227. u32 val;
  3228. struct tstorm_eth_client_config tstorm_client = {0};
  3229. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3230. dma_addr_t buf_map;
  3231. int n = (i % cp->l2_rx_ring_size) + 1;
  3232. buf_map = cp->l2_buf_map + (n * cp->l2_single_buf_size);
  3233. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3234. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3235. }
  3236. context = cnic_get_bnx2x_ctx(dev, BNX2X_ISCSI_L2_CID, 0, &context_addr);
  3237. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) >> 32;
  3238. rxbd->addr_hi = cpu_to_le32(val);
  3239. context->ustorm_st_context.common.bd_page_base_hi = val;
  3240. val = (u64) (cp->l2_ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3241. rxbd->addr_lo = cpu_to_le32(val);
  3242. context->ustorm_st_context.common.bd_page_base_lo = val;
  3243. context->ustorm_st_context.common.sb_index_numbers =
  3244. BNX2X_ISCSI_RX_SB_INDEX_NUM;
  3245. context->ustorm_st_context.common.clientId = cli;
  3246. context->ustorm_st_context.common.status_block_id = BNX2X_DEF_SB_ID;
  3247. context->ustorm_st_context.common.flags =
  3248. USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
  3249. context->ustorm_st_context.common.statistics_counter_id = cli;
  3250. context->ustorm_st_context.common.mc_alignment_log_size = 0;
  3251. context->ustorm_st_context.common.bd_buff_size =
  3252. cp->l2_single_buf_size;
  3253. context->ustorm_ag_context.cdu_usage =
  3254. CDU_RSRVD_VALUE_TYPE_A(BNX2X_HW_CID(BNX2X_ISCSI_L2_CID, func),
  3255. CDU_REGION_NUMBER_UCM_AG,
  3256. ETH_CONNECTION_TYPE);
  3257. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3258. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3259. rxcqe->addr_hi = cpu_to_le32(val);
  3260. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3261. USTORM_CQE_PAGE_BASE_OFFSET(port, cli) + 4, val);
  3262. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3263. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli) + 4, val);
  3264. val = (u64) (cp->l2_ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3265. rxcqe->addr_lo = cpu_to_le32(val);
  3266. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3267. USTORM_CQE_PAGE_BASE_OFFSET(port, cli), val);
  3268. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3269. USTORM_CQE_PAGE_NEXT_OFFSET(port, cli), val);
  3270. /* client tstorm info */
  3271. tstorm_client.mtu = cp->l2_single_buf_size - 14;
  3272. tstorm_client.config_flags =
  3273. (TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE |
  3274. TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE);
  3275. tstorm_client.statistics_counter_id = cli;
  3276. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3277. TSTORM_CLIENT_CONFIG_OFFSET(port, cli),
  3278. ((u32 *)&tstorm_client)[0]);
  3279. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3280. TSTORM_CLIENT_CONFIG_OFFSET(port, cli) + 4,
  3281. ((u32 *)&tstorm_client)[1]);
  3282. /* reset tstorm per client statistics */
  3283. val = BAR_TSTRORM_INTMEM +
  3284. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3285. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3286. CNIC_WR(dev, val + i * 4, 0);
  3287. /* reset ustorm per client statistics */
  3288. val = BAR_USTRORM_INTMEM +
  3289. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3290. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3291. CNIC_WR(dev, val + i * 4, 0);
  3292. cp->rx_cons_ptr =
  3293. &cp->bnx2x_def_status_blk->u_def_status_block.index_values[
  3294. HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS];
  3295. }
  3296. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3297. {
  3298. struct cnic_local *cp = dev->cnic_priv;
  3299. u32 base, addr, val;
  3300. int port = CNIC_PORT(cp);
  3301. dev->max_iscsi_conn = 0;
  3302. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3303. if (base < 0xa0000 || base >= 0xc0000)
  3304. return;
  3305. addr = BNX2X_SHMEM_ADDR(base,
  3306. dev_info.port_hw_config[port].iscsi_mac_upper);
  3307. val = CNIC_RD(dev, addr);
  3308. dev->mac_addr[0] = (u8) (val >> 8);
  3309. dev->mac_addr[1] = (u8) val;
  3310. addr = BNX2X_SHMEM_ADDR(base,
  3311. dev_info.port_hw_config[port].iscsi_mac_lower);
  3312. val = CNIC_RD(dev, addr);
  3313. dev->mac_addr[2] = (u8) (val >> 24);
  3314. dev->mac_addr[3] = (u8) (val >> 16);
  3315. dev->mac_addr[4] = (u8) (val >> 8);
  3316. dev->mac_addr[5] = (u8) val;
  3317. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3318. val = CNIC_RD(dev, addr);
  3319. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3320. u16 val16;
  3321. addr = BNX2X_SHMEM_ADDR(base,
  3322. drv_lic_key[port].max_iscsi_init_conn);
  3323. val16 = CNIC_RD16(dev, addr);
  3324. if (val16)
  3325. val16 ^= 0x1e1e;
  3326. dev->max_iscsi_conn = val16;
  3327. }
  3328. if (BNX2X_CHIP_IS_E1H(cp->chip_id)) {
  3329. int func = CNIC_FUNC(cp);
  3330. addr = BNX2X_SHMEM_ADDR(base,
  3331. mf_cfg.func_mf_config[func].e1hov_tag);
  3332. val = CNIC_RD(dev, addr);
  3333. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3334. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3335. addr = BNX2X_SHMEM_ADDR(base,
  3336. mf_cfg.func_mf_config[func].config);
  3337. val = CNIC_RD(dev, addr);
  3338. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3339. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3340. dev->max_iscsi_conn = 0;
  3341. }
  3342. }
  3343. }
  3344. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3345. {
  3346. struct cnic_local *cp = dev->cnic_priv;
  3347. int func = CNIC_FUNC(cp), ret, i;
  3348. int port = CNIC_PORT(cp);
  3349. u16 eq_idx;
  3350. u8 sb_id = cp->status_blk_num;
  3351. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3352. BNX2X_ISCSI_START_CID);
  3353. if (ret)
  3354. return -ENOMEM;
  3355. cp->kcq_io_addr = BAR_CSTRORM_INTMEM +
  3356. CSTORM_ISCSI_EQ_PROD_OFFSET(func, 0);
  3357. cp->kcq_prod_idx = 0;
  3358. cnic_get_bnx2x_iscsi_info(dev);
  3359. /* Only 1 EQ */
  3360. CNIC_WR16(dev, cp->kcq_io_addr, MAX_KCQ_IDX);
  3361. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3362. CSTORM_ISCSI_EQ_CONS_OFFSET(func, 0), 0);
  3363. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3364. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0),
  3365. cp->kcq_info.pg_map_arr[1] & 0xffffffff);
  3366. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3367. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(func, 0) + 4,
  3368. (u64) cp->kcq_info.pg_map_arr[1] >> 32);
  3369. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3370. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0),
  3371. cp->kcq_info.pg_map_arr[0] & 0xffffffff);
  3372. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3373. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(func, 0) + 4,
  3374. (u64) cp->kcq_info.pg_map_arr[0] >> 32);
  3375. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3376. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(func, 0), 1);
  3377. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3378. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(func, 0), cp->status_blk_num);
  3379. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3380. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(func, 0),
  3381. HC_INDEX_C_ISCSI_EQ_CONS);
  3382. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3383. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3384. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i),
  3385. cp->conn_buf_info.pgtbl[2 * i]);
  3386. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3387. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(func, i) + 4,
  3388. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3389. }
  3390. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3391. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func),
  3392. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3393. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3394. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(func) + 4,
  3395. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3396. cnic_setup_bnx2x_context(dev);
  3397. eq_idx = CNIC_RD16(dev, BAR_CSTRORM_INTMEM +
  3398. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3399. offsetof(struct cstorm_status_block_c,
  3400. index_values[HC_INDEX_C_ISCSI_EQ_CONS]));
  3401. if (eq_idx != 0) {
  3402. printk(KERN_ERR PFX "%s: EQ cons index %x != 0\n",
  3403. dev->netdev->name, eq_idx);
  3404. return -EBUSY;
  3405. }
  3406. ret = cnic_init_bnx2x_irq(dev);
  3407. if (ret)
  3408. return ret;
  3409. cnic_init_bnx2x_tx_ring(dev);
  3410. cnic_init_bnx2x_rx_ring(dev);
  3411. return 0;
  3412. }
  3413. static void cnic_init_rings(struct cnic_dev *dev)
  3414. {
  3415. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3416. cnic_init_bnx2_tx_ring(dev);
  3417. cnic_init_bnx2_rx_ring(dev);
  3418. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3419. struct cnic_local *cp = dev->cnic_priv;
  3420. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3421. union l5cm_specific_data l5_data;
  3422. struct ustorm_eth_rx_producers rx_prods = {0};
  3423. u32 off, i;
  3424. rx_prods.bd_prod = 0;
  3425. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3426. barrier();
  3427. off = BAR_USTRORM_INTMEM +
  3428. USTORM_RX_PRODS_OFFSET(CNIC_PORT(cp), cli);
  3429. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3430. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3431. cnic_init_bnx2x_tx_ring(dev);
  3432. cnic_init_bnx2x_rx_ring(dev);
  3433. l5_data.phy_address.lo = cli;
  3434. l5_data.phy_address.hi = 0;
  3435. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3436. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3437. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3438. }
  3439. }
  3440. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3441. {
  3442. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3443. cnic_shutdown_bnx2_rx_ring(dev);
  3444. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3445. struct cnic_local *cp = dev->cnic_priv;
  3446. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3447. union l5cm_specific_data l5_data;
  3448. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3449. l5_data.phy_address.lo = cli;
  3450. l5_data.phy_address.hi = 0;
  3451. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3452. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3453. msleep(10);
  3454. }
  3455. }
  3456. static int cnic_register_netdev(struct cnic_dev *dev)
  3457. {
  3458. struct cnic_local *cp = dev->cnic_priv;
  3459. struct cnic_eth_dev *ethdev = cp->ethdev;
  3460. int err;
  3461. if (!ethdev)
  3462. return -ENODEV;
  3463. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3464. return 0;
  3465. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3466. if (err)
  3467. printk(KERN_ERR PFX "%s: register_cnic failed\n",
  3468. dev->netdev->name);
  3469. return err;
  3470. }
  3471. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3472. {
  3473. struct cnic_local *cp = dev->cnic_priv;
  3474. struct cnic_eth_dev *ethdev = cp->ethdev;
  3475. if (!ethdev)
  3476. return;
  3477. ethdev->drv_unregister_cnic(dev->netdev);
  3478. }
  3479. static int cnic_start_hw(struct cnic_dev *dev)
  3480. {
  3481. struct cnic_local *cp = dev->cnic_priv;
  3482. struct cnic_eth_dev *ethdev = cp->ethdev;
  3483. int err;
  3484. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3485. return -EALREADY;
  3486. dev->regview = ethdev->io_base;
  3487. cp->chip_id = ethdev->chip_id;
  3488. pci_dev_get(dev->pcidev);
  3489. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3490. cp->status_blk = ethdev->irq_arr[0].status_blk;
  3491. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3492. err = cp->alloc_resc(dev);
  3493. if (err) {
  3494. printk(KERN_ERR PFX "%s: allocate resource failure\n",
  3495. dev->netdev->name);
  3496. goto err1;
  3497. }
  3498. err = cp->start_hw(dev);
  3499. if (err)
  3500. goto err1;
  3501. err = cnic_cm_open(dev);
  3502. if (err)
  3503. goto err1;
  3504. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3505. cp->enable_int(dev);
  3506. return 0;
  3507. err1:
  3508. cp->free_resc(dev);
  3509. pci_dev_put(dev->pcidev);
  3510. return err;
  3511. }
  3512. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3513. {
  3514. cnic_disable_bnx2_int_sync(dev);
  3515. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3516. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3517. cnic_init_context(dev, KWQ_CID);
  3518. cnic_init_context(dev, KCQ_CID);
  3519. cnic_setup_5709_context(dev, 0);
  3520. cnic_free_irq(dev);
  3521. cnic_free_resc(dev);
  3522. }
  3523. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3524. {
  3525. struct cnic_local *cp = dev->cnic_priv;
  3526. u8 sb_id = cp->status_blk_num;
  3527. int port = CNIC_PORT(cp);
  3528. cnic_free_irq(dev);
  3529. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3530. CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id) +
  3531. offsetof(struct cstorm_status_block_c,
  3532. index_values[HC_INDEX_C_ISCSI_EQ_CONS]),
  3533. 0);
  3534. cnic_free_resc(dev);
  3535. }
  3536. static void cnic_stop_hw(struct cnic_dev *dev)
  3537. {
  3538. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3539. struct cnic_local *cp = dev->cnic_priv;
  3540. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3541. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3542. synchronize_rcu();
  3543. cnic_cm_shutdown(dev);
  3544. cp->stop_hw(dev);
  3545. pci_dev_put(dev->pcidev);
  3546. }
  3547. }
  3548. static void cnic_free_dev(struct cnic_dev *dev)
  3549. {
  3550. int i = 0;
  3551. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3552. msleep(100);
  3553. i++;
  3554. }
  3555. if (atomic_read(&dev->ref_count) != 0)
  3556. printk(KERN_ERR PFX "%s: Failed waiting for ref count to go"
  3557. " to zero.\n", dev->netdev->name);
  3558. printk(KERN_INFO PFX "Removed CNIC device: %s\n", dev->netdev->name);
  3559. dev_put(dev->netdev);
  3560. kfree(dev);
  3561. }
  3562. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3563. struct pci_dev *pdev)
  3564. {
  3565. struct cnic_dev *cdev;
  3566. struct cnic_local *cp;
  3567. int alloc_size;
  3568. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3569. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3570. if (cdev == NULL) {
  3571. printk(KERN_ERR PFX "%s: allocate dev struct failure\n",
  3572. dev->name);
  3573. return NULL;
  3574. }
  3575. cdev->netdev = dev;
  3576. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3577. cdev->register_device = cnic_register_device;
  3578. cdev->unregister_device = cnic_unregister_device;
  3579. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3580. cp = cdev->cnic_priv;
  3581. cp->dev = cdev;
  3582. cp->uio_dev = -1;
  3583. cp->l2_single_buf_size = 0x400;
  3584. cp->l2_rx_ring_size = 3;
  3585. spin_lock_init(&cp->cnic_ulp_lock);
  3586. printk(KERN_INFO PFX "Added CNIC device: %s\n", dev->name);
  3587. return cdev;
  3588. }
  3589. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3590. {
  3591. struct pci_dev *pdev;
  3592. struct cnic_dev *cdev;
  3593. struct cnic_local *cp;
  3594. struct cnic_eth_dev *ethdev = NULL;
  3595. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3596. probe = symbol_get(bnx2_cnic_probe);
  3597. if (probe) {
  3598. ethdev = (*probe)(dev);
  3599. symbol_put(bnx2_cnic_probe);
  3600. }
  3601. if (!ethdev)
  3602. return NULL;
  3603. pdev = ethdev->pdev;
  3604. if (!pdev)
  3605. return NULL;
  3606. dev_hold(dev);
  3607. pci_dev_get(pdev);
  3608. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3609. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3610. u8 rev;
  3611. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3612. if (rev < 0x10) {
  3613. pci_dev_put(pdev);
  3614. goto cnic_err;
  3615. }
  3616. }
  3617. pci_dev_put(pdev);
  3618. cdev = cnic_alloc_dev(dev, pdev);
  3619. if (cdev == NULL)
  3620. goto cnic_err;
  3621. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3622. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3623. cp = cdev->cnic_priv;
  3624. cp->ethdev = ethdev;
  3625. cdev->pcidev = pdev;
  3626. cp->cnic_ops = &cnic_bnx2_ops;
  3627. cp->start_hw = cnic_start_bnx2_hw;
  3628. cp->stop_hw = cnic_stop_bnx2_hw;
  3629. cp->setup_pgtbl = cnic_setup_page_tbl;
  3630. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3631. cp->free_resc = cnic_free_resc;
  3632. cp->start_cm = cnic_cm_init_bnx2_hw;
  3633. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3634. cp->enable_int = cnic_enable_bnx2_int;
  3635. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3636. cp->close_conn = cnic_close_bnx2_conn;
  3637. cp->next_idx = cnic_bnx2_next_idx;
  3638. cp->hw_idx = cnic_bnx2_hw_idx;
  3639. return cdev;
  3640. cnic_err:
  3641. dev_put(dev);
  3642. return NULL;
  3643. }
  3644. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3645. {
  3646. struct pci_dev *pdev;
  3647. struct cnic_dev *cdev;
  3648. struct cnic_local *cp;
  3649. struct cnic_eth_dev *ethdev = NULL;
  3650. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3651. probe = symbol_get(bnx2x_cnic_probe);
  3652. if (probe) {
  3653. ethdev = (*probe)(dev);
  3654. symbol_put(bnx2x_cnic_probe);
  3655. }
  3656. if (!ethdev)
  3657. return NULL;
  3658. pdev = ethdev->pdev;
  3659. if (!pdev)
  3660. return NULL;
  3661. dev_hold(dev);
  3662. cdev = cnic_alloc_dev(dev, pdev);
  3663. if (cdev == NULL) {
  3664. dev_put(dev);
  3665. return NULL;
  3666. }
  3667. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3668. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3669. cp = cdev->cnic_priv;
  3670. cp->ethdev = ethdev;
  3671. cdev->pcidev = pdev;
  3672. cp->cnic_ops = &cnic_bnx2x_ops;
  3673. cp->start_hw = cnic_start_bnx2x_hw;
  3674. cp->stop_hw = cnic_stop_bnx2x_hw;
  3675. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3676. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3677. cp->free_resc = cnic_free_resc;
  3678. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3679. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3680. cp->enable_int = cnic_enable_bnx2x_int;
  3681. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3682. cp->ack_int = cnic_ack_bnx2x_msix;
  3683. cp->close_conn = cnic_close_bnx2x_conn;
  3684. cp->next_idx = cnic_bnx2x_next_idx;
  3685. cp->hw_idx = cnic_bnx2x_hw_idx;
  3686. return cdev;
  3687. }
  3688. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3689. {
  3690. struct ethtool_drvinfo drvinfo;
  3691. struct cnic_dev *cdev = NULL;
  3692. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3693. memset(&drvinfo, 0, sizeof(drvinfo));
  3694. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3695. if (!strcmp(drvinfo.driver, "bnx2"))
  3696. cdev = init_bnx2_cnic(dev);
  3697. if (!strcmp(drvinfo.driver, "bnx2x"))
  3698. cdev = init_bnx2x_cnic(dev);
  3699. if (cdev) {
  3700. write_lock(&cnic_dev_lock);
  3701. list_add(&cdev->list, &cnic_dev_list);
  3702. write_unlock(&cnic_dev_lock);
  3703. }
  3704. }
  3705. return cdev;
  3706. }
  3707. /**
  3708. * netdev event handler
  3709. */
  3710. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3711. void *ptr)
  3712. {
  3713. struct net_device *netdev = ptr;
  3714. struct cnic_dev *dev;
  3715. int if_type;
  3716. int new_dev = 0;
  3717. dev = cnic_from_netdev(netdev);
  3718. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3719. /* Check for the hot-plug device */
  3720. dev = is_cnic_dev(netdev);
  3721. if (dev) {
  3722. new_dev = 1;
  3723. cnic_hold(dev);
  3724. }
  3725. }
  3726. if (dev) {
  3727. struct cnic_local *cp = dev->cnic_priv;
  3728. if (new_dev)
  3729. cnic_ulp_init(dev);
  3730. else if (event == NETDEV_UNREGISTER)
  3731. cnic_ulp_exit(dev);
  3732. if (event == NETDEV_UP) {
  3733. if (cnic_register_netdev(dev) != 0) {
  3734. cnic_put(dev);
  3735. goto done;
  3736. }
  3737. if (!cnic_start_hw(dev))
  3738. cnic_ulp_start(dev);
  3739. }
  3740. rcu_read_lock();
  3741. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  3742. struct cnic_ulp_ops *ulp_ops;
  3743. void *ctx;
  3744. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  3745. if (!ulp_ops || !ulp_ops->indicate_netevent)
  3746. continue;
  3747. ctx = cp->ulp_handle[if_type];
  3748. ulp_ops->indicate_netevent(ctx, event);
  3749. }
  3750. rcu_read_unlock();
  3751. if (event == NETDEV_GOING_DOWN) {
  3752. cnic_ulp_stop(dev);
  3753. cnic_stop_hw(dev);
  3754. cnic_unregister_netdev(dev);
  3755. } else if (event == NETDEV_UNREGISTER) {
  3756. write_lock(&cnic_dev_lock);
  3757. list_del_init(&dev->list);
  3758. write_unlock(&cnic_dev_lock);
  3759. cnic_put(dev);
  3760. cnic_free_dev(dev);
  3761. goto done;
  3762. }
  3763. cnic_put(dev);
  3764. }
  3765. done:
  3766. return NOTIFY_DONE;
  3767. }
  3768. static struct notifier_block cnic_netdev_notifier = {
  3769. .notifier_call = cnic_netdev_event
  3770. };
  3771. static void cnic_release(void)
  3772. {
  3773. struct cnic_dev *dev;
  3774. while (!list_empty(&cnic_dev_list)) {
  3775. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  3776. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3777. cnic_ulp_stop(dev);
  3778. cnic_stop_hw(dev);
  3779. }
  3780. cnic_ulp_exit(dev);
  3781. cnic_unregister_netdev(dev);
  3782. list_del_init(&dev->list);
  3783. cnic_free_dev(dev);
  3784. }
  3785. }
  3786. static int __init cnic_init(void)
  3787. {
  3788. int rc = 0;
  3789. printk(KERN_INFO "%s", version);
  3790. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  3791. if (rc) {
  3792. cnic_release();
  3793. return rc;
  3794. }
  3795. return 0;
  3796. }
  3797. static void __exit cnic_exit(void)
  3798. {
  3799. unregister_netdevice_notifier(&cnic_netdev_notifier);
  3800. cnic_release();
  3801. return;
  3802. }
  3803. module_init(cnic_init);
  3804. module_exit(cnic_exit);