intel_sprite.c 29 KB

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  1. /*
  2. * Copyright © 2011 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21. * SOFTWARE.
  22. *
  23. * Authors:
  24. * Jesse Barnes <jbarnes@virtuousgeek.org>
  25. *
  26. * New plane/sprite handling.
  27. *
  28. * The older chips had a separate interface for programming plane related
  29. * registers; newer ones are much simpler and we can use the new DRM plane
  30. * support.
  31. */
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_fourcc.h>
  35. #include <drm/drm_rect.h>
  36. #include "intel_drv.h"
  37. #include <drm/i915_drm.h>
  38. #include "i915_drv.h"
  39. static void
  40. vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
  41. struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  42. unsigned int crtc_w, unsigned int crtc_h,
  43. uint32_t x, uint32_t y,
  44. uint32_t src_w, uint32_t src_h)
  45. {
  46. struct drm_device *dev = dplane->dev;
  47. struct drm_i915_private *dev_priv = dev->dev_private;
  48. struct intel_plane *intel_plane = to_intel_plane(dplane);
  49. int pipe = intel_plane->pipe;
  50. int plane = intel_plane->plane;
  51. u32 sprctl;
  52. unsigned long sprsurf_offset, linear_offset;
  53. int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  54. sprctl = I915_READ(SPCNTR(pipe, plane));
  55. /* Mask out pixel format bits in case we change it */
  56. sprctl &= ~SP_PIXFORMAT_MASK;
  57. sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
  58. sprctl &= ~SP_TILED;
  59. switch (fb->pixel_format) {
  60. case DRM_FORMAT_YUYV:
  61. sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
  62. break;
  63. case DRM_FORMAT_YVYU:
  64. sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
  65. break;
  66. case DRM_FORMAT_UYVY:
  67. sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
  68. break;
  69. case DRM_FORMAT_VYUY:
  70. sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
  71. break;
  72. case DRM_FORMAT_RGB565:
  73. sprctl |= SP_FORMAT_BGR565;
  74. break;
  75. case DRM_FORMAT_XRGB8888:
  76. sprctl |= SP_FORMAT_BGRX8888;
  77. break;
  78. case DRM_FORMAT_ARGB8888:
  79. sprctl |= SP_FORMAT_BGRA8888;
  80. break;
  81. case DRM_FORMAT_XBGR2101010:
  82. sprctl |= SP_FORMAT_RGBX1010102;
  83. break;
  84. case DRM_FORMAT_ABGR2101010:
  85. sprctl |= SP_FORMAT_RGBA1010102;
  86. break;
  87. case DRM_FORMAT_XBGR8888:
  88. sprctl |= SP_FORMAT_RGBX8888;
  89. break;
  90. case DRM_FORMAT_ABGR8888:
  91. sprctl |= SP_FORMAT_RGBA8888;
  92. break;
  93. default:
  94. /*
  95. * If we get here one of the upper layers failed to filter
  96. * out the unsupported plane formats
  97. */
  98. BUG();
  99. break;
  100. }
  101. if (obj->tiling_mode != I915_TILING_NONE)
  102. sprctl |= SP_TILED;
  103. sprctl |= SP_ENABLE;
  104. /* Sizes are 0 based */
  105. src_w--;
  106. src_h--;
  107. crtc_w--;
  108. crtc_h--;
  109. intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
  110. I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
  111. I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
  112. linear_offset = y * fb->pitches[0] + x * pixel_size;
  113. sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
  114. obj->tiling_mode,
  115. pixel_size,
  116. fb->pitches[0]);
  117. linear_offset -= sprsurf_offset;
  118. if (obj->tiling_mode != I915_TILING_NONE)
  119. I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
  120. else
  121. I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
  122. I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
  123. I915_WRITE(SPCNTR(pipe, plane), sprctl);
  124. I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
  125. sprsurf_offset);
  126. POSTING_READ(SPSURF(pipe, plane));
  127. }
  128. static void
  129. vlv_disable_plane(struct drm_plane *dplane)
  130. {
  131. struct drm_device *dev = dplane->dev;
  132. struct drm_i915_private *dev_priv = dev->dev_private;
  133. struct intel_plane *intel_plane = to_intel_plane(dplane);
  134. int pipe = intel_plane->pipe;
  135. int plane = intel_plane->plane;
  136. I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
  137. ~SP_ENABLE);
  138. /* Activate double buffered register update */
  139. I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);
  140. POSTING_READ(SPSURF(pipe, plane));
  141. }
  142. static int
  143. vlv_update_colorkey(struct drm_plane *dplane,
  144. struct drm_intel_sprite_colorkey *key)
  145. {
  146. struct drm_device *dev = dplane->dev;
  147. struct drm_i915_private *dev_priv = dev->dev_private;
  148. struct intel_plane *intel_plane = to_intel_plane(dplane);
  149. int pipe = intel_plane->pipe;
  150. int plane = intel_plane->plane;
  151. u32 sprctl;
  152. if (key->flags & I915_SET_COLORKEY_DESTINATION)
  153. return -EINVAL;
  154. I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
  155. I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
  156. I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
  157. sprctl = I915_READ(SPCNTR(pipe, plane));
  158. sprctl &= ~SP_SOURCE_KEY;
  159. if (key->flags & I915_SET_COLORKEY_SOURCE)
  160. sprctl |= SP_SOURCE_KEY;
  161. I915_WRITE(SPCNTR(pipe, plane), sprctl);
  162. POSTING_READ(SPKEYMSK(pipe, plane));
  163. return 0;
  164. }
  165. static void
  166. vlv_get_colorkey(struct drm_plane *dplane,
  167. struct drm_intel_sprite_colorkey *key)
  168. {
  169. struct drm_device *dev = dplane->dev;
  170. struct drm_i915_private *dev_priv = dev->dev_private;
  171. struct intel_plane *intel_plane = to_intel_plane(dplane);
  172. int pipe = intel_plane->pipe;
  173. int plane = intel_plane->plane;
  174. u32 sprctl;
  175. key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
  176. key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
  177. key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
  178. sprctl = I915_READ(SPCNTR(pipe, plane));
  179. if (sprctl & SP_SOURCE_KEY)
  180. key->flags = I915_SET_COLORKEY_SOURCE;
  181. else
  182. key->flags = I915_SET_COLORKEY_NONE;
  183. }
  184. static void
  185. ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
  186. struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  187. unsigned int crtc_w, unsigned int crtc_h,
  188. uint32_t x, uint32_t y,
  189. uint32_t src_w, uint32_t src_h)
  190. {
  191. struct drm_device *dev = plane->dev;
  192. struct drm_i915_private *dev_priv = dev->dev_private;
  193. struct intel_plane *intel_plane = to_intel_plane(plane);
  194. int pipe = intel_plane->pipe;
  195. u32 sprctl, sprscale = 0;
  196. unsigned long sprsurf_offset, linear_offset;
  197. int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  198. bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;
  199. sprctl = I915_READ(SPRCTL(pipe));
  200. /* Mask out pixel format bits in case we change it */
  201. sprctl &= ~SPRITE_PIXFORMAT_MASK;
  202. sprctl &= ~SPRITE_RGB_ORDER_RGBX;
  203. sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
  204. sprctl &= ~SPRITE_TILED;
  205. switch (fb->pixel_format) {
  206. case DRM_FORMAT_XBGR8888:
  207. sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  208. break;
  209. case DRM_FORMAT_XRGB8888:
  210. sprctl |= SPRITE_FORMAT_RGBX888;
  211. break;
  212. case DRM_FORMAT_YUYV:
  213. sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  214. break;
  215. case DRM_FORMAT_YVYU:
  216. sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  217. break;
  218. case DRM_FORMAT_UYVY:
  219. sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  220. break;
  221. case DRM_FORMAT_VYUY:
  222. sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  223. break;
  224. default:
  225. BUG();
  226. }
  227. if (obj->tiling_mode != I915_TILING_NONE)
  228. sprctl |= SPRITE_TILED;
  229. /* must disable */
  230. sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  231. sprctl |= SPRITE_ENABLE;
  232. if (IS_HASWELL(dev))
  233. sprctl |= SPRITE_PIPE_CSC_ENABLE;
  234. /* Sizes are 0 based */
  235. src_w--;
  236. src_h--;
  237. crtc_w--;
  238. crtc_h--;
  239. intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
  240. /*
  241. * IVB workaround: must disable low power watermarks for at least
  242. * one frame before enabling scaling. LP watermarks can be re-enabled
  243. * when scaling is disabled.
  244. */
  245. if (crtc_w != src_w || crtc_h != src_h) {
  246. dev_priv->sprite_scaling_enabled |= 1 << pipe;
  247. if (!scaling_was_enabled) {
  248. intel_update_watermarks(dev);
  249. intel_wait_for_vblank(dev, pipe);
  250. }
  251. sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
  252. } else
  253. dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
  254. I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
  255. I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
  256. linear_offset = y * fb->pitches[0] + x * pixel_size;
  257. sprsurf_offset =
  258. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  259. pixel_size, fb->pitches[0]);
  260. linear_offset -= sprsurf_offset;
  261. /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
  262. * register */
  263. if (IS_HASWELL(dev))
  264. I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
  265. else if (obj->tiling_mode != I915_TILING_NONE)
  266. I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
  267. else
  268. I915_WRITE(SPRLINOFF(pipe), linear_offset);
  269. I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
  270. if (intel_plane->can_scale)
  271. I915_WRITE(SPRSCALE(pipe), sprscale);
  272. I915_WRITE(SPRCTL(pipe), sprctl);
  273. I915_MODIFY_DISPBASE(SPRSURF(pipe),
  274. i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
  275. POSTING_READ(SPRSURF(pipe));
  276. /* potentially re-enable LP watermarks */
  277. if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
  278. intel_update_watermarks(dev);
  279. }
  280. static void
  281. ivb_disable_plane(struct drm_plane *plane)
  282. {
  283. struct drm_device *dev = plane->dev;
  284. struct drm_i915_private *dev_priv = dev->dev_private;
  285. struct intel_plane *intel_plane = to_intel_plane(plane);
  286. int pipe = intel_plane->pipe;
  287. bool scaling_was_enabled = dev_priv->sprite_scaling_enabled;
  288. I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
  289. /* Can't leave the scaler enabled... */
  290. if (intel_plane->can_scale)
  291. I915_WRITE(SPRSCALE(pipe), 0);
  292. /* Activate double buffered register update */
  293. I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
  294. POSTING_READ(SPRSURF(pipe));
  295. dev_priv->sprite_scaling_enabled &= ~(1 << pipe);
  296. intel_update_sprite_watermarks(dev, pipe, 0, 0, false);
  297. /* potentially re-enable LP watermarks */
  298. if (scaling_was_enabled && !dev_priv->sprite_scaling_enabled)
  299. intel_update_watermarks(dev);
  300. }
  301. static int
  302. ivb_update_colorkey(struct drm_plane *plane,
  303. struct drm_intel_sprite_colorkey *key)
  304. {
  305. struct drm_device *dev = plane->dev;
  306. struct drm_i915_private *dev_priv = dev->dev_private;
  307. struct intel_plane *intel_plane;
  308. u32 sprctl;
  309. int ret = 0;
  310. intel_plane = to_intel_plane(plane);
  311. I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
  312. I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
  313. I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
  314. sprctl = I915_READ(SPRCTL(intel_plane->pipe));
  315. sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
  316. if (key->flags & I915_SET_COLORKEY_DESTINATION)
  317. sprctl |= SPRITE_DEST_KEY;
  318. else if (key->flags & I915_SET_COLORKEY_SOURCE)
  319. sprctl |= SPRITE_SOURCE_KEY;
  320. I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
  321. POSTING_READ(SPRKEYMSK(intel_plane->pipe));
  322. return ret;
  323. }
  324. static void
  325. ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
  326. {
  327. struct drm_device *dev = plane->dev;
  328. struct drm_i915_private *dev_priv = dev->dev_private;
  329. struct intel_plane *intel_plane;
  330. u32 sprctl;
  331. intel_plane = to_intel_plane(plane);
  332. key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
  333. key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
  334. key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
  335. key->flags = 0;
  336. sprctl = I915_READ(SPRCTL(intel_plane->pipe));
  337. if (sprctl & SPRITE_DEST_KEY)
  338. key->flags = I915_SET_COLORKEY_DESTINATION;
  339. else if (sprctl & SPRITE_SOURCE_KEY)
  340. key->flags = I915_SET_COLORKEY_SOURCE;
  341. else
  342. key->flags = I915_SET_COLORKEY_NONE;
  343. }
  344. static void
  345. ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
  346. struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  347. unsigned int crtc_w, unsigned int crtc_h,
  348. uint32_t x, uint32_t y,
  349. uint32_t src_w, uint32_t src_h)
  350. {
  351. struct drm_device *dev = plane->dev;
  352. struct drm_i915_private *dev_priv = dev->dev_private;
  353. struct intel_plane *intel_plane = to_intel_plane(plane);
  354. int pipe = intel_plane->pipe;
  355. unsigned long dvssurf_offset, linear_offset;
  356. u32 dvscntr, dvsscale;
  357. int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  358. dvscntr = I915_READ(DVSCNTR(pipe));
  359. /* Mask out pixel format bits in case we change it */
  360. dvscntr &= ~DVS_PIXFORMAT_MASK;
  361. dvscntr &= ~DVS_RGB_ORDER_XBGR;
  362. dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
  363. dvscntr &= ~DVS_TILED;
  364. switch (fb->pixel_format) {
  365. case DRM_FORMAT_XBGR8888:
  366. dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
  367. break;
  368. case DRM_FORMAT_XRGB8888:
  369. dvscntr |= DVS_FORMAT_RGBX888;
  370. break;
  371. case DRM_FORMAT_YUYV:
  372. dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
  373. break;
  374. case DRM_FORMAT_YVYU:
  375. dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
  376. break;
  377. case DRM_FORMAT_UYVY:
  378. dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
  379. break;
  380. case DRM_FORMAT_VYUY:
  381. dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
  382. break;
  383. default:
  384. BUG();
  385. }
  386. if (obj->tiling_mode != I915_TILING_NONE)
  387. dvscntr |= DVS_TILED;
  388. if (IS_GEN6(dev))
  389. dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
  390. dvscntr |= DVS_ENABLE;
  391. /* Sizes are 0 based */
  392. src_w--;
  393. src_h--;
  394. crtc_w--;
  395. crtc_h--;
  396. intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size, true);
  397. dvsscale = 0;
  398. if (IS_GEN5(dev) || crtc_w != src_w || crtc_h != src_h)
  399. dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
  400. I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
  401. I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
  402. linear_offset = y * fb->pitches[0] + x * pixel_size;
  403. dvssurf_offset =
  404. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  405. pixel_size, fb->pitches[0]);
  406. linear_offset -= dvssurf_offset;
  407. if (obj->tiling_mode != I915_TILING_NONE)
  408. I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
  409. else
  410. I915_WRITE(DVSLINOFF(pipe), linear_offset);
  411. I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
  412. I915_WRITE(DVSSCALE(pipe), dvsscale);
  413. I915_WRITE(DVSCNTR(pipe), dvscntr);
  414. I915_MODIFY_DISPBASE(DVSSURF(pipe),
  415. i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
  416. POSTING_READ(DVSSURF(pipe));
  417. }
  418. static void
  419. ilk_disable_plane(struct drm_plane *plane)
  420. {
  421. struct drm_device *dev = plane->dev;
  422. struct drm_i915_private *dev_priv = dev->dev_private;
  423. struct intel_plane *intel_plane = to_intel_plane(plane);
  424. int pipe = intel_plane->pipe;
  425. I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
  426. /* Disable the scaler */
  427. I915_WRITE(DVSSCALE(pipe), 0);
  428. /* Flush double buffered register updates */
  429. I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);
  430. POSTING_READ(DVSSURF(pipe));
  431. }
  432. static void
  433. intel_enable_primary(struct drm_crtc *crtc)
  434. {
  435. struct drm_device *dev = crtc->dev;
  436. struct drm_i915_private *dev_priv = dev->dev_private;
  437. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  438. int reg = DSPCNTR(intel_crtc->plane);
  439. if (!intel_crtc->primary_disabled)
  440. return;
  441. intel_crtc->primary_disabled = false;
  442. intel_update_fbc(dev);
  443. I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
  444. }
  445. static void
  446. intel_disable_primary(struct drm_crtc *crtc)
  447. {
  448. struct drm_device *dev = crtc->dev;
  449. struct drm_i915_private *dev_priv = dev->dev_private;
  450. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  451. int reg = DSPCNTR(intel_crtc->plane);
  452. if (intel_crtc->primary_disabled)
  453. return;
  454. I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
  455. intel_crtc->primary_disabled = true;
  456. intel_update_fbc(dev);
  457. }
  458. static int
  459. ilk_update_colorkey(struct drm_plane *plane,
  460. struct drm_intel_sprite_colorkey *key)
  461. {
  462. struct drm_device *dev = plane->dev;
  463. struct drm_i915_private *dev_priv = dev->dev_private;
  464. struct intel_plane *intel_plane;
  465. u32 dvscntr;
  466. int ret = 0;
  467. intel_plane = to_intel_plane(plane);
  468. I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
  469. I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
  470. I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
  471. dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
  472. dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
  473. if (key->flags & I915_SET_COLORKEY_DESTINATION)
  474. dvscntr |= DVS_DEST_KEY;
  475. else if (key->flags & I915_SET_COLORKEY_SOURCE)
  476. dvscntr |= DVS_SOURCE_KEY;
  477. I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
  478. POSTING_READ(DVSKEYMSK(intel_plane->pipe));
  479. return ret;
  480. }
  481. static void
  482. ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
  483. {
  484. struct drm_device *dev = plane->dev;
  485. struct drm_i915_private *dev_priv = dev->dev_private;
  486. struct intel_plane *intel_plane;
  487. u32 dvscntr;
  488. intel_plane = to_intel_plane(plane);
  489. key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
  490. key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
  491. key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
  492. key->flags = 0;
  493. dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
  494. if (dvscntr & DVS_DEST_KEY)
  495. key->flags = I915_SET_COLORKEY_DESTINATION;
  496. else if (dvscntr & DVS_SOURCE_KEY)
  497. key->flags = I915_SET_COLORKEY_SOURCE;
  498. else
  499. key->flags = I915_SET_COLORKEY_NONE;
  500. }
  501. static bool
  502. format_is_yuv(uint32_t format)
  503. {
  504. switch (format) {
  505. case DRM_FORMAT_YUYV:
  506. case DRM_FORMAT_UYVY:
  507. case DRM_FORMAT_VYUY:
  508. case DRM_FORMAT_YVYU:
  509. return true;
  510. default:
  511. return false;
  512. }
  513. }
  514. static int
  515. intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
  516. struct drm_framebuffer *fb, int crtc_x, int crtc_y,
  517. unsigned int crtc_w, unsigned int crtc_h,
  518. uint32_t src_x, uint32_t src_y,
  519. uint32_t src_w, uint32_t src_h)
  520. {
  521. struct drm_device *dev = plane->dev;
  522. struct drm_i915_private *dev_priv = dev->dev_private;
  523. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  524. struct intel_plane *intel_plane = to_intel_plane(plane);
  525. struct intel_framebuffer *intel_fb;
  526. struct drm_i915_gem_object *obj, *old_obj;
  527. int pipe = intel_plane->pipe;
  528. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  529. pipe);
  530. int ret = 0;
  531. bool disable_primary = false;
  532. bool visible;
  533. int hscale, vscale;
  534. int max_scale, min_scale;
  535. int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
  536. struct drm_rect src = {
  537. /* sample coordinates in 16.16 fixed point */
  538. .x1 = src_x,
  539. .x2 = src_x + src_w,
  540. .y1 = src_y,
  541. .y2 = src_y + src_h,
  542. };
  543. struct drm_rect dst = {
  544. /* integer pixels */
  545. .x1 = crtc_x,
  546. .x2 = crtc_x + crtc_w,
  547. .y1 = crtc_y,
  548. .y2 = crtc_y + crtc_h,
  549. };
  550. const struct drm_rect clip = {
  551. .x2 = crtc->mode.hdisplay,
  552. .y2 = crtc->mode.vdisplay,
  553. };
  554. intel_fb = to_intel_framebuffer(fb);
  555. obj = intel_fb->obj;
  556. old_obj = intel_plane->obj;
  557. intel_plane->crtc_x = crtc_x;
  558. intel_plane->crtc_y = crtc_y;
  559. intel_plane->crtc_w = crtc_w;
  560. intel_plane->crtc_h = crtc_h;
  561. intel_plane->src_x = src_x;
  562. intel_plane->src_y = src_y;
  563. intel_plane->src_w = src_w;
  564. intel_plane->src_h = src_h;
  565. /* Pipe must be running... */
  566. if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) {
  567. DRM_DEBUG_KMS("Pipe disabled\n");
  568. return -EINVAL;
  569. }
  570. /* Don't modify another pipe's plane */
  571. if (intel_plane->pipe != intel_crtc->pipe) {
  572. DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
  573. return -EINVAL;
  574. }
  575. /* FIXME check all gen limits */
  576. if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
  577. DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
  578. return -EINVAL;
  579. }
  580. /* Sprite planes can be linear or x-tiled surfaces */
  581. switch (obj->tiling_mode) {
  582. case I915_TILING_NONE:
  583. case I915_TILING_X:
  584. break;
  585. default:
  586. DRM_DEBUG_KMS("Unsupported tiling mode\n");
  587. return -EINVAL;
  588. }
  589. /*
  590. * FIXME the following code does a bunch of fuzzy adjustments to the
  591. * coordinates and sizes. We probably need some way to decide whether
  592. * more strict checking should be done instead.
  593. */
  594. max_scale = intel_plane->max_downscale << 16;
  595. min_scale = intel_plane->can_scale ? 1 : (1 << 16);
  596. hscale = drm_rect_calc_hscale_relaxed(&src, &dst, min_scale, max_scale);
  597. BUG_ON(hscale < 0);
  598. vscale = drm_rect_calc_vscale_relaxed(&src, &dst, min_scale, max_scale);
  599. BUG_ON(vscale < 0);
  600. visible = drm_rect_clip_scaled(&src, &dst, &clip, hscale, vscale);
  601. crtc_x = dst.x1;
  602. crtc_y = dst.y1;
  603. crtc_w = drm_rect_width(&dst);
  604. crtc_h = drm_rect_height(&dst);
  605. if (visible) {
  606. /* check again in case clipping clamped the results */
  607. hscale = drm_rect_calc_hscale(&src, &dst, min_scale, max_scale);
  608. if (hscale < 0) {
  609. DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
  610. drm_rect_debug_print(&src, true);
  611. drm_rect_debug_print(&dst, false);
  612. return hscale;
  613. }
  614. vscale = drm_rect_calc_vscale(&src, &dst, min_scale, max_scale);
  615. if (vscale < 0) {
  616. DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
  617. drm_rect_debug_print(&src, true);
  618. drm_rect_debug_print(&dst, false);
  619. return vscale;
  620. }
  621. /* Make the source viewport size an exact multiple of the scaling factors. */
  622. drm_rect_adjust_size(&src,
  623. drm_rect_width(&dst) * hscale - drm_rect_width(&src),
  624. drm_rect_height(&dst) * vscale - drm_rect_height(&src));
  625. /* sanity check to make sure the src viewport wasn't enlarged */
  626. WARN_ON(src.x1 < (int) src_x ||
  627. src.y1 < (int) src_y ||
  628. src.x2 > (int) (src_x + src_w) ||
  629. src.y2 > (int) (src_y + src_h));
  630. /*
  631. * Hardware doesn't handle subpixel coordinates.
  632. * Adjust to (macro)pixel boundary, but be careful not to
  633. * increase the source viewport size, because that could
  634. * push the downscaling factor out of bounds.
  635. */
  636. src_x = src.x1 >> 16;
  637. src_w = drm_rect_width(&src) >> 16;
  638. src_y = src.y1 >> 16;
  639. src_h = drm_rect_height(&src) >> 16;
  640. if (format_is_yuv(fb->pixel_format)) {
  641. src_x &= ~1;
  642. src_w &= ~1;
  643. /*
  644. * Must keep src and dst the
  645. * same if we can't scale.
  646. */
  647. if (!intel_plane->can_scale)
  648. crtc_w &= ~1;
  649. if (crtc_w == 0)
  650. visible = false;
  651. }
  652. }
  653. /* Check size restrictions when scaling */
  654. if (visible && (src_w != crtc_w || src_h != crtc_h)) {
  655. unsigned int width_bytes;
  656. WARN_ON(!intel_plane->can_scale);
  657. /* FIXME interlacing min height is 6 */
  658. if (crtc_w < 3 || crtc_h < 3)
  659. visible = false;
  660. if (src_w < 3 || src_h < 3)
  661. visible = false;
  662. width_bytes = ((src_x * pixel_size) & 63) + src_w * pixel_size;
  663. if (src_w > 2048 || src_h > 2048 ||
  664. width_bytes > 4096 || fb->pitches[0] > 4096) {
  665. DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
  666. return -EINVAL;
  667. }
  668. }
  669. dst.x1 = crtc_x;
  670. dst.x2 = crtc_x + crtc_w;
  671. dst.y1 = crtc_y;
  672. dst.y2 = crtc_y + crtc_h;
  673. /*
  674. * If the sprite is completely covering the primary plane,
  675. * we can disable the primary and save power.
  676. */
  677. disable_primary = drm_rect_equals(&dst, &clip);
  678. WARN_ON(disable_primary && !visible);
  679. mutex_lock(&dev->struct_mutex);
  680. /* Note that this will apply the VT-d workaround for scanouts,
  681. * which is more restrictive than required for sprites. (The
  682. * primary plane requires 256KiB alignment with 64 PTE padding,
  683. * the sprite planes only require 128KiB alignment and 32 PTE padding.
  684. */
  685. ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
  686. if (ret)
  687. goto out_unlock;
  688. intel_plane->obj = obj;
  689. /*
  690. * Be sure to re-enable the primary before the sprite is no longer
  691. * covering it fully.
  692. */
  693. if (!disable_primary)
  694. intel_enable_primary(crtc);
  695. if (visible)
  696. intel_plane->update_plane(plane, fb, obj,
  697. crtc_x, crtc_y, crtc_w, crtc_h,
  698. src_x, src_y, src_w, src_h);
  699. else
  700. intel_plane->disable_plane(plane);
  701. if (disable_primary)
  702. intel_disable_primary(crtc);
  703. /* Unpin old obj after new one is active to avoid ugliness */
  704. if (old_obj) {
  705. /*
  706. * It's fairly common to simply update the position of
  707. * an existing object. In that case, we don't need to
  708. * wait for vblank to avoid ugliness, we only need to
  709. * do the pin & ref bookkeeping.
  710. */
  711. if (old_obj != obj) {
  712. mutex_unlock(&dev->struct_mutex);
  713. intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
  714. mutex_lock(&dev->struct_mutex);
  715. }
  716. intel_unpin_fb_obj(old_obj);
  717. }
  718. out_unlock:
  719. mutex_unlock(&dev->struct_mutex);
  720. return ret;
  721. }
  722. static int
  723. intel_disable_plane(struct drm_plane *plane)
  724. {
  725. struct drm_device *dev = plane->dev;
  726. struct intel_plane *intel_plane = to_intel_plane(plane);
  727. int ret = 0;
  728. if (plane->crtc)
  729. intel_enable_primary(plane->crtc);
  730. intel_plane->disable_plane(plane);
  731. if (!intel_plane->obj)
  732. goto out;
  733. intel_wait_for_vblank(dev, intel_plane->pipe);
  734. mutex_lock(&dev->struct_mutex);
  735. intel_unpin_fb_obj(intel_plane->obj);
  736. intel_plane->obj = NULL;
  737. mutex_unlock(&dev->struct_mutex);
  738. out:
  739. return ret;
  740. }
  741. static void intel_destroy_plane(struct drm_plane *plane)
  742. {
  743. struct intel_plane *intel_plane = to_intel_plane(plane);
  744. intel_disable_plane(plane);
  745. drm_plane_cleanup(plane);
  746. kfree(intel_plane);
  747. }
  748. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  749. struct drm_file *file_priv)
  750. {
  751. struct drm_intel_sprite_colorkey *set = data;
  752. struct drm_mode_object *obj;
  753. struct drm_plane *plane;
  754. struct intel_plane *intel_plane;
  755. int ret = 0;
  756. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  757. return -ENODEV;
  758. /* Make sure we don't try to enable both src & dest simultaneously */
  759. if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
  760. return -EINVAL;
  761. drm_modeset_lock_all(dev);
  762. obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
  763. if (!obj) {
  764. ret = -EINVAL;
  765. goto out_unlock;
  766. }
  767. plane = obj_to_plane(obj);
  768. intel_plane = to_intel_plane(plane);
  769. ret = intel_plane->update_colorkey(plane, set);
  770. out_unlock:
  771. drm_modeset_unlock_all(dev);
  772. return ret;
  773. }
  774. int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
  775. struct drm_file *file_priv)
  776. {
  777. struct drm_intel_sprite_colorkey *get = data;
  778. struct drm_mode_object *obj;
  779. struct drm_plane *plane;
  780. struct intel_plane *intel_plane;
  781. int ret = 0;
  782. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  783. return -ENODEV;
  784. drm_modeset_lock_all(dev);
  785. obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
  786. if (!obj) {
  787. ret = -EINVAL;
  788. goto out_unlock;
  789. }
  790. plane = obj_to_plane(obj);
  791. intel_plane = to_intel_plane(plane);
  792. intel_plane->get_colorkey(plane, get);
  793. out_unlock:
  794. drm_modeset_unlock_all(dev);
  795. return ret;
  796. }
  797. void intel_plane_restore(struct drm_plane *plane)
  798. {
  799. struct intel_plane *intel_plane = to_intel_plane(plane);
  800. if (!plane->crtc || !plane->fb)
  801. return;
  802. intel_update_plane(plane, plane->crtc, plane->fb,
  803. intel_plane->crtc_x, intel_plane->crtc_y,
  804. intel_plane->crtc_w, intel_plane->crtc_h,
  805. intel_plane->src_x, intel_plane->src_y,
  806. intel_plane->src_w, intel_plane->src_h);
  807. }
  808. void intel_plane_disable(struct drm_plane *plane)
  809. {
  810. if (!plane->crtc || !plane->fb)
  811. return;
  812. intel_disable_plane(plane);
  813. }
  814. static const struct drm_plane_funcs intel_plane_funcs = {
  815. .update_plane = intel_update_plane,
  816. .disable_plane = intel_disable_plane,
  817. .destroy = intel_destroy_plane,
  818. };
  819. static uint32_t ilk_plane_formats[] = {
  820. DRM_FORMAT_XRGB8888,
  821. DRM_FORMAT_YUYV,
  822. DRM_FORMAT_YVYU,
  823. DRM_FORMAT_UYVY,
  824. DRM_FORMAT_VYUY,
  825. };
  826. static uint32_t snb_plane_formats[] = {
  827. DRM_FORMAT_XBGR8888,
  828. DRM_FORMAT_XRGB8888,
  829. DRM_FORMAT_YUYV,
  830. DRM_FORMAT_YVYU,
  831. DRM_FORMAT_UYVY,
  832. DRM_FORMAT_VYUY,
  833. };
  834. static uint32_t vlv_plane_formats[] = {
  835. DRM_FORMAT_RGB565,
  836. DRM_FORMAT_ABGR8888,
  837. DRM_FORMAT_ARGB8888,
  838. DRM_FORMAT_XBGR8888,
  839. DRM_FORMAT_XRGB8888,
  840. DRM_FORMAT_XBGR2101010,
  841. DRM_FORMAT_ABGR2101010,
  842. DRM_FORMAT_YUYV,
  843. DRM_FORMAT_YVYU,
  844. DRM_FORMAT_UYVY,
  845. DRM_FORMAT_VYUY,
  846. };
  847. int
  848. intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
  849. {
  850. struct intel_plane *intel_plane;
  851. unsigned long possible_crtcs;
  852. const uint32_t *plane_formats;
  853. int num_plane_formats;
  854. int ret;
  855. if (INTEL_INFO(dev)->gen < 5)
  856. return -ENODEV;
  857. intel_plane = kzalloc(sizeof(struct intel_plane), GFP_KERNEL);
  858. if (!intel_plane)
  859. return -ENOMEM;
  860. switch (INTEL_INFO(dev)->gen) {
  861. case 5:
  862. case 6:
  863. intel_plane->can_scale = true;
  864. intel_plane->max_downscale = 16;
  865. intel_plane->update_plane = ilk_update_plane;
  866. intel_plane->disable_plane = ilk_disable_plane;
  867. intel_plane->update_colorkey = ilk_update_colorkey;
  868. intel_plane->get_colorkey = ilk_get_colorkey;
  869. if (IS_GEN6(dev)) {
  870. plane_formats = snb_plane_formats;
  871. num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  872. } else {
  873. plane_formats = ilk_plane_formats;
  874. num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
  875. }
  876. break;
  877. case 7:
  878. if (IS_IVYBRIDGE(dev)) {
  879. intel_plane->can_scale = true;
  880. intel_plane->max_downscale = 2;
  881. } else {
  882. intel_plane->can_scale = false;
  883. intel_plane->max_downscale = 1;
  884. }
  885. if (IS_VALLEYVIEW(dev)) {
  886. intel_plane->update_plane = vlv_update_plane;
  887. intel_plane->disable_plane = vlv_disable_plane;
  888. intel_plane->update_colorkey = vlv_update_colorkey;
  889. intel_plane->get_colorkey = vlv_get_colorkey;
  890. plane_formats = vlv_plane_formats;
  891. num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
  892. } else {
  893. intel_plane->update_plane = ivb_update_plane;
  894. intel_plane->disable_plane = ivb_disable_plane;
  895. intel_plane->update_colorkey = ivb_update_colorkey;
  896. intel_plane->get_colorkey = ivb_get_colorkey;
  897. plane_formats = snb_plane_formats;
  898. num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  899. }
  900. break;
  901. default:
  902. kfree(intel_plane);
  903. return -ENODEV;
  904. }
  905. intel_plane->pipe = pipe;
  906. intel_plane->plane = plane;
  907. possible_crtcs = (1 << pipe);
  908. ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
  909. &intel_plane_funcs,
  910. plane_formats, num_plane_formats,
  911. false);
  912. if (ret)
  913. kfree(intel_plane);
  914. return ret;
  915. }