intel_sdvo.c 90 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * intel_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. bool rgb_quant_range_selectable;
  110. /**
  111. * This is set if we detect output of sdvo device as LVDS and
  112. * have a valid fixed mode to use with the panel.
  113. */
  114. bool is_lvds;
  115. /**
  116. * This is sdvo fixed pannel mode pointer
  117. */
  118. struct drm_display_mode *sdvo_lvds_fixed_mode;
  119. /* DDC bus used by this SDVO encoder */
  120. uint8_t ddc_bus;
  121. /*
  122. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  123. */
  124. uint8_t dtd_sdvo_flags;
  125. };
  126. struct intel_sdvo_connector {
  127. struct intel_connector base;
  128. /* Mark the type of connector */
  129. uint16_t output_flag;
  130. enum hdmi_force_audio force_audio;
  131. /* This contains all current supported TV format */
  132. u8 tv_format_supported[TV_FORMAT_NUM];
  133. int format_supported_num;
  134. struct drm_property *tv_format;
  135. /* add the property for the SDVO-TV */
  136. struct drm_property *left;
  137. struct drm_property *right;
  138. struct drm_property *top;
  139. struct drm_property *bottom;
  140. struct drm_property *hpos;
  141. struct drm_property *vpos;
  142. struct drm_property *contrast;
  143. struct drm_property *saturation;
  144. struct drm_property *hue;
  145. struct drm_property *sharpness;
  146. struct drm_property *flicker_filter;
  147. struct drm_property *flicker_filter_adaptive;
  148. struct drm_property *flicker_filter_2d;
  149. struct drm_property *tv_chroma_filter;
  150. struct drm_property *tv_luma_filter;
  151. struct drm_property *dot_crawl;
  152. /* add the property for the SDVO-TV/LVDS */
  153. struct drm_property *brightness;
  154. /* Add variable to record current setting for the above property */
  155. u32 left_margin, right_margin, top_margin, bottom_margin;
  156. /* this is to get the range of margin.*/
  157. u32 max_hscan, max_vscan;
  158. u32 max_hpos, cur_hpos;
  159. u32 max_vpos, cur_vpos;
  160. u32 cur_brightness, max_brightness;
  161. u32 cur_contrast, max_contrast;
  162. u32 cur_saturation, max_saturation;
  163. u32 cur_hue, max_hue;
  164. u32 cur_sharpness, max_sharpness;
  165. u32 cur_flicker_filter, max_flicker_filter;
  166. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  167. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  168. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  169. u32 cur_tv_luma_filter, max_tv_luma_filter;
  170. u32 cur_dot_crawl, max_dot_crawl;
  171. };
  172. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  173. {
  174. return container_of(encoder, struct intel_sdvo, base.base);
  175. }
  176. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  177. {
  178. return container_of(intel_attached_encoder(connector),
  179. struct intel_sdvo, base);
  180. }
  181. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  182. {
  183. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  184. }
  185. static bool
  186. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  187. static bool
  188. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  189. struct intel_sdvo_connector *intel_sdvo_connector,
  190. int type);
  191. static bool
  192. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  193. struct intel_sdvo_connector *intel_sdvo_connector);
  194. /**
  195. * Writes the SDVOB or SDVOC with the given value, but always writes both
  196. * SDVOB and SDVOC to work around apparent hardware issues (according to
  197. * comments in the BIOS).
  198. */
  199. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  200. {
  201. struct drm_device *dev = intel_sdvo->base.base.dev;
  202. struct drm_i915_private *dev_priv = dev->dev_private;
  203. u32 bval = val, cval = val;
  204. int i;
  205. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  206. I915_WRITE(intel_sdvo->sdvo_reg, val);
  207. I915_READ(intel_sdvo->sdvo_reg);
  208. return;
  209. }
  210. if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
  211. cval = I915_READ(GEN3_SDVOC);
  212. else
  213. bval = I915_READ(GEN3_SDVOB);
  214. /*
  215. * Write the registers twice for luck. Sometimes,
  216. * writing them only once doesn't appear to 'stick'.
  217. * The BIOS does this too. Yay, magic
  218. */
  219. for (i = 0; i < 2; i++)
  220. {
  221. I915_WRITE(GEN3_SDVOB, bval);
  222. I915_READ(GEN3_SDVOB);
  223. I915_WRITE(GEN3_SDVOC, cval);
  224. I915_READ(GEN3_SDVOC);
  225. }
  226. }
  227. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  228. {
  229. struct i2c_msg msgs[] = {
  230. {
  231. .addr = intel_sdvo->slave_addr,
  232. .flags = 0,
  233. .len = 1,
  234. .buf = &addr,
  235. },
  236. {
  237. .addr = intel_sdvo->slave_addr,
  238. .flags = I2C_M_RD,
  239. .len = 1,
  240. .buf = ch,
  241. }
  242. };
  243. int ret;
  244. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  245. return true;
  246. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  247. return false;
  248. }
  249. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  250. /** Mapping of command numbers to names, for debug output */
  251. static const struct _sdvo_cmd_name {
  252. u8 cmd;
  253. const char *name;
  254. } sdvo_cmd_names[] = {
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  298. /* Add the op code for SDVO enhancements */
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  343. /* HDMI op code */
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  363. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  364. };
  365. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  366. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  367. const void *args, int args_len)
  368. {
  369. int i;
  370. DRM_DEBUG_KMS("%s: W: %02X ",
  371. SDVO_NAME(intel_sdvo), cmd);
  372. for (i = 0; i < args_len; i++)
  373. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  374. for (; i < 8; i++)
  375. DRM_LOG_KMS(" ");
  376. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  377. if (cmd == sdvo_cmd_names[i].cmd) {
  378. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  379. break;
  380. }
  381. }
  382. if (i == ARRAY_SIZE(sdvo_cmd_names))
  383. DRM_LOG_KMS("(%02X)", cmd);
  384. DRM_LOG_KMS("\n");
  385. }
  386. static const char *cmd_status_names[] = {
  387. "Power on",
  388. "Success",
  389. "Not supported",
  390. "Invalid arg",
  391. "Pending",
  392. "Target not specified",
  393. "Scaling not supported"
  394. };
  395. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  396. const void *args, int args_len)
  397. {
  398. u8 *buf, status;
  399. struct i2c_msg *msgs;
  400. int i, ret = true;
  401. /* Would be simpler to allocate both in one go ? */
  402. buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
  403. if (!buf)
  404. return false;
  405. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  406. if (!msgs) {
  407. kfree(buf);
  408. return false;
  409. }
  410. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  411. for (i = 0; i < args_len; i++) {
  412. msgs[i].addr = intel_sdvo->slave_addr;
  413. msgs[i].flags = 0;
  414. msgs[i].len = 2;
  415. msgs[i].buf = buf + 2 *i;
  416. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  417. buf[2*i + 1] = ((u8*)args)[i];
  418. }
  419. msgs[i].addr = intel_sdvo->slave_addr;
  420. msgs[i].flags = 0;
  421. msgs[i].len = 2;
  422. msgs[i].buf = buf + 2*i;
  423. buf[2*i + 0] = SDVO_I2C_OPCODE;
  424. buf[2*i + 1] = cmd;
  425. /* the following two are to read the response */
  426. status = SDVO_I2C_CMD_STATUS;
  427. msgs[i+1].addr = intel_sdvo->slave_addr;
  428. msgs[i+1].flags = 0;
  429. msgs[i+1].len = 1;
  430. msgs[i+1].buf = &status;
  431. msgs[i+2].addr = intel_sdvo->slave_addr;
  432. msgs[i+2].flags = I2C_M_RD;
  433. msgs[i+2].len = 1;
  434. msgs[i+2].buf = &status;
  435. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  436. if (ret < 0) {
  437. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  438. ret = false;
  439. goto out;
  440. }
  441. if (ret != i+3) {
  442. /* failure in I2C transfer */
  443. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  444. ret = false;
  445. }
  446. out:
  447. kfree(msgs);
  448. kfree(buf);
  449. return ret;
  450. }
  451. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  452. void *response, int response_len)
  453. {
  454. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  455. u8 status;
  456. int i;
  457. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  458. /*
  459. * The documentation states that all commands will be
  460. * processed within 15µs, and that we need only poll
  461. * the status byte a maximum of 3 times in order for the
  462. * command to be complete.
  463. *
  464. * Check 5 times in case the hardware failed to read the docs.
  465. *
  466. * Also beware that the first response by many devices is to
  467. * reply PENDING and stall for time. TVs are notorious for
  468. * requiring longer than specified to complete their replies.
  469. * Originally (in the DDX long ago), the delay was only ever 15ms
  470. * with an additional delay of 30ms applied for TVs added later after
  471. * many experiments. To accommodate both sets of delays, we do a
  472. * sequence of slow checks if the device is falling behind and fails
  473. * to reply within 5*15µs.
  474. */
  475. if (!intel_sdvo_read_byte(intel_sdvo,
  476. SDVO_I2C_CMD_STATUS,
  477. &status))
  478. goto log_fail;
  479. while (status == SDVO_CMD_STATUS_PENDING && --retry) {
  480. if (retry < 10)
  481. msleep(15);
  482. else
  483. udelay(15);
  484. if (!intel_sdvo_read_byte(intel_sdvo,
  485. SDVO_I2C_CMD_STATUS,
  486. &status))
  487. goto log_fail;
  488. }
  489. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  490. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  491. else
  492. DRM_LOG_KMS("(??? %d)", status);
  493. if (status != SDVO_CMD_STATUS_SUCCESS)
  494. goto log_fail;
  495. /* Read the command response */
  496. for (i = 0; i < response_len; i++) {
  497. if (!intel_sdvo_read_byte(intel_sdvo,
  498. SDVO_I2C_RETURN_0 + i,
  499. &((u8 *)response)[i]))
  500. goto log_fail;
  501. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  502. }
  503. DRM_LOG_KMS("\n");
  504. return true;
  505. log_fail:
  506. DRM_LOG_KMS("... failed\n");
  507. return false;
  508. }
  509. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  510. {
  511. if (mode->clock >= 100000)
  512. return 1;
  513. else if (mode->clock >= 50000)
  514. return 2;
  515. else
  516. return 4;
  517. }
  518. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  519. u8 ddc_bus)
  520. {
  521. /* This must be the immediately preceding write before the i2c xfer */
  522. return intel_sdvo_write_cmd(intel_sdvo,
  523. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  524. &ddc_bus, 1);
  525. }
  526. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  527. {
  528. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  529. return false;
  530. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  531. }
  532. static bool
  533. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  534. {
  535. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  536. return false;
  537. return intel_sdvo_read_response(intel_sdvo, value, len);
  538. }
  539. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  540. {
  541. struct intel_sdvo_set_target_input_args targets = {0};
  542. return intel_sdvo_set_value(intel_sdvo,
  543. SDVO_CMD_SET_TARGET_INPUT,
  544. &targets, sizeof(targets));
  545. }
  546. /**
  547. * Return whether each input is trained.
  548. *
  549. * This function is making an assumption about the layout of the response,
  550. * which should be checked against the docs.
  551. */
  552. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  553. {
  554. struct intel_sdvo_get_trained_inputs_response response;
  555. BUILD_BUG_ON(sizeof(response) != 1);
  556. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  557. &response, sizeof(response)))
  558. return false;
  559. *input_1 = response.input0_trained;
  560. *input_2 = response.input1_trained;
  561. return true;
  562. }
  563. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  564. u16 outputs)
  565. {
  566. return intel_sdvo_set_value(intel_sdvo,
  567. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  568. &outputs, sizeof(outputs));
  569. }
  570. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  571. u16 *outputs)
  572. {
  573. return intel_sdvo_get_value(intel_sdvo,
  574. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  575. outputs, sizeof(*outputs));
  576. }
  577. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  578. int mode)
  579. {
  580. u8 state = SDVO_ENCODER_STATE_ON;
  581. switch (mode) {
  582. case DRM_MODE_DPMS_ON:
  583. state = SDVO_ENCODER_STATE_ON;
  584. break;
  585. case DRM_MODE_DPMS_STANDBY:
  586. state = SDVO_ENCODER_STATE_STANDBY;
  587. break;
  588. case DRM_MODE_DPMS_SUSPEND:
  589. state = SDVO_ENCODER_STATE_SUSPEND;
  590. break;
  591. case DRM_MODE_DPMS_OFF:
  592. state = SDVO_ENCODER_STATE_OFF;
  593. break;
  594. }
  595. return intel_sdvo_set_value(intel_sdvo,
  596. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  597. }
  598. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  599. int *clock_min,
  600. int *clock_max)
  601. {
  602. struct intel_sdvo_pixel_clock_range clocks;
  603. BUILD_BUG_ON(sizeof(clocks) != 4);
  604. if (!intel_sdvo_get_value(intel_sdvo,
  605. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  606. &clocks, sizeof(clocks)))
  607. return false;
  608. /* Convert the values from units of 10 kHz to kHz. */
  609. *clock_min = clocks.min * 10;
  610. *clock_max = clocks.max * 10;
  611. return true;
  612. }
  613. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  614. u16 outputs)
  615. {
  616. return intel_sdvo_set_value(intel_sdvo,
  617. SDVO_CMD_SET_TARGET_OUTPUT,
  618. &outputs, sizeof(outputs));
  619. }
  620. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  621. struct intel_sdvo_dtd *dtd)
  622. {
  623. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  624. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  625. }
  626. static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  627. struct intel_sdvo_dtd *dtd)
  628. {
  629. return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  630. intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  631. }
  632. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  633. struct intel_sdvo_dtd *dtd)
  634. {
  635. return intel_sdvo_set_timing(intel_sdvo,
  636. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  637. }
  638. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  639. struct intel_sdvo_dtd *dtd)
  640. {
  641. return intel_sdvo_set_timing(intel_sdvo,
  642. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  643. }
  644. static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
  645. struct intel_sdvo_dtd *dtd)
  646. {
  647. return intel_sdvo_get_timing(intel_sdvo,
  648. SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
  649. }
  650. static bool
  651. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  652. uint16_t clock,
  653. uint16_t width,
  654. uint16_t height)
  655. {
  656. struct intel_sdvo_preferred_input_timing_args args;
  657. memset(&args, 0, sizeof(args));
  658. args.clock = clock;
  659. args.width = width;
  660. args.height = height;
  661. args.interlace = 0;
  662. if (intel_sdvo->is_lvds &&
  663. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  664. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  665. args.scaled = 1;
  666. return intel_sdvo_set_value(intel_sdvo,
  667. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  668. &args, sizeof(args));
  669. }
  670. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  671. struct intel_sdvo_dtd *dtd)
  672. {
  673. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  674. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  675. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  676. &dtd->part1, sizeof(dtd->part1)) &&
  677. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  678. &dtd->part2, sizeof(dtd->part2));
  679. }
  680. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  681. {
  682. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  683. }
  684. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  685. const struct drm_display_mode *mode)
  686. {
  687. uint16_t width, height;
  688. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  689. uint16_t h_sync_offset, v_sync_offset;
  690. int mode_clock;
  691. width = mode->hdisplay;
  692. height = mode->vdisplay;
  693. /* do some mode translations */
  694. h_blank_len = mode->htotal - mode->hdisplay;
  695. h_sync_len = mode->hsync_end - mode->hsync_start;
  696. v_blank_len = mode->vtotal - mode->vdisplay;
  697. v_sync_len = mode->vsync_end - mode->vsync_start;
  698. h_sync_offset = mode->hsync_start - mode->hdisplay;
  699. v_sync_offset = mode->vsync_start - mode->vdisplay;
  700. mode_clock = mode->clock;
  701. mode_clock /= 10;
  702. dtd->part1.clock = mode_clock;
  703. dtd->part1.h_active = width & 0xff;
  704. dtd->part1.h_blank = h_blank_len & 0xff;
  705. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  706. ((h_blank_len >> 8) & 0xf);
  707. dtd->part1.v_active = height & 0xff;
  708. dtd->part1.v_blank = v_blank_len & 0xff;
  709. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  710. ((v_blank_len >> 8) & 0xf);
  711. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  712. dtd->part2.h_sync_width = h_sync_len & 0xff;
  713. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  714. (v_sync_len & 0xf);
  715. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  716. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  717. ((v_sync_len & 0x30) >> 4);
  718. dtd->part2.dtd_flags = 0x18;
  719. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  720. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  721. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  722. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  723. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  724. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  725. dtd->part2.sdvo_flags = 0;
  726. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  727. dtd->part2.reserved = 0;
  728. }
  729. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  730. const struct intel_sdvo_dtd *dtd)
  731. {
  732. mode->hdisplay = dtd->part1.h_active;
  733. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  734. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  735. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  736. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  737. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  738. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  739. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  740. mode->vdisplay = dtd->part1.v_active;
  741. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  742. mode->vsync_start = mode->vdisplay;
  743. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  744. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  745. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  746. mode->vsync_end = mode->vsync_start +
  747. (dtd->part2.v_sync_off_width & 0xf);
  748. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  749. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  750. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  751. mode->clock = dtd->part1.clock * 10;
  752. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  753. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  754. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  755. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  756. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  757. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  758. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  759. }
  760. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  761. {
  762. struct intel_sdvo_encode encode;
  763. BUILD_BUG_ON(sizeof(encode) != 2);
  764. return intel_sdvo_get_value(intel_sdvo,
  765. SDVO_CMD_GET_SUPP_ENCODE,
  766. &encode, sizeof(encode));
  767. }
  768. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  769. uint8_t mode)
  770. {
  771. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  772. }
  773. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  774. uint8_t mode)
  775. {
  776. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  777. }
  778. #if 0
  779. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  780. {
  781. int i, j;
  782. uint8_t set_buf_index[2];
  783. uint8_t av_split;
  784. uint8_t buf_size;
  785. uint8_t buf[48];
  786. uint8_t *pos;
  787. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  788. for (i = 0; i <= av_split; i++) {
  789. set_buf_index[0] = i; set_buf_index[1] = 0;
  790. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  791. set_buf_index, 2);
  792. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  793. intel_sdvo_read_response(encoder, &buf_size, 1);
  794. pos = buf;
  795. for (j = 0; j <= buf_size; j += 8) {
  796. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  797. NULL, 0);
  798. intel_sdvo_read_response(encoder, pos, 8);
  799. pos += 8;
  800. }
  801. }
  802. }
  803. #endif
  804. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  805. unsigned if_index, uint8_t tx_rate,
  806. uint8_t *data, unsigned length)
  807. {
  808. uint8_t set_buf_index[2] = { if_index, 0 };
  809. uint8_t hbuf_size, tmp[8];
  810. int i;
  811. if (!intel_sdvo_set_value(intel_sdvo,
  812. SDVO_CMD_SET_HBUF_INDEX,
  813. set_buf_index, 2))
  814. return false;
  815. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  816. &hbuf_size, 1))
  817. return false;
  818. /* Buffer size is 0 based, hooray! */
  819. hbuf_size++;
  820. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  821. if_index, length, hbuf_size);
  822. for (i = 0; i < hbuf_size; i += 8) {
  823. memset(tmp, 0, 8);
  824. if (i < length)
  825. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  826. if (!intel_sdvo_set_value(intel_sdvo,
  827. SDVO_CMD_SET_HBUF_DATA,
  828. tmp, 8))
  829. return false;
  830. }
  831. return intel_sdvo_set_value(intel_sdvo,
  832. SDVO_CMD_SET_HBUF_TXRATE,
  833. &tx_rate, 1);
  834. }
  835. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  836. const struct drm_display_mode *adjusted_mode)
  837. {
  838. struct dip_infoframe avi_if = {
  839. .type = DIP_TYPE_AVI,
  840. .ver = DIP_VERSION_AVI,
  841. .len = DIP_LEN_AVI,
  842. };
  843. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  844. struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
  845. if (intel_sdvo->rgb_quant_range_selectable) {
  846. if (intel_crtc->config.limited_color_range)
  847. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
  848. else
  849. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
  850. }
  851. avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
  852. intel_dip_infoframe_csum(&avi_if);
  853. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  854. * we must not send the ecc field, either. */
  855. memcpy(sdvo_data, &avi_if, 3);
  856. sdvo_data[3] = avi_if.checksum;
  857. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  858. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  859. SDVO_HBUF_TX_VSYNC,
  860. sdvo_data, sizeof(sdvo_data));
  861. }
  862. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  863. {
  864. struct intel_sdvo_tv_format format;
  865. uint32_t format_map;
  866. format_map = 1 << intel_sdvo->tv_format_index;
  867. memset(&format, 0, sizeof(format));
  868. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  869. BUILD_BUG_ON(sizeof(format) != 6);
  870. return intel_sdvo_set_value(intel_sdvo,
  871. SDVO_CMD_SET_TV_FORMAT,
  872. &format, sizeof(format));
  873. }
  874. static bool
  875. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  876. const struct drm_display_mode *mode)
  877. {
  878. struct intel_sdvo_dtd output_dtd;
  879. if (!intel_sdvo_set_target_output(intel_sdvo,
  880. intel_sdvo->attached_output))
  881. return false;
  882. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  883. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  884. return false;
  885. return true;
  886. }
  887. /* Asks the sdvo controller for the preferred input mode given the output mode.
  888. * Unfortunately we have to set up the full output mode to do that. */
  889. static bool
  890. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  891. const struct drm_display_mode *mode,
  892. struct drm_display_mode *adjusted_mode)
  893. {
  894. struct intel_sdvo_dtd input_dtd;
  895. /* Reset the input timing to the screen. Assume always input 0. */
  896. if (!intel_sdvo_set_target_input(intel_sdvo))
  897. return false;
  898. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  899. mode->clock / 10,
  900. mode->hdisplay,
  901. mode->vdisplay))
  902. return false;
  903. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  904. &input_dtd))
  905. return false;
  906. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  907. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  908. return true;
  909. }
  910. static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
  911. {
  912. unsigned dotclock = pipe_config->adjusted_mode.clock;
  913. struct dpll *clock = &pipe_config->dpll;
  914. /* SDVO TV has fixed PLL values depend on its clock range,
  915. this mirrors vbios setting. */
  916. if (dotclock >= 100000 && dotclock < 140500) {
  917. clock->p1 = 2;
  918. clock->p2 = 10;
  919. clock->n = 3;
  920. clock->m1 = 16;
  921. clock->m2 = 8;
  922. } else if (dotclock >= 140500 && dotclock <= 200000) {
  923. clock->p1 = 1;
  924. clock->p2 = 10;
  925. clock->n = 6;
  926. clock->m1 = 12;
  927. clock->m2 = 8;
  928. } else {
  929. WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
  930. }
  931. pipe_config->clock_set = true;
  932. }
  933. static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
  934. struct intel_crtc_config *pipe_config)
  935. {
  936. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  937. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  938. struct drm_display_mode *mode = &pipe_config->requested_mode;
  939. DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
  940. pipe_config->pipe_bpp = 8*3;
  941. if (HAS_PCH_SPLIT(encoder->base.dev))
  942. pipe_config->has_pch_encoder = true;
  943. /* We need to construct preferred input timings based on our
  944. * output timings. To do that, we have to set the output
  945. * timings, even though this isn't really the right place in
  946. * the sequence to do it. Oh well.
  947. */
  948. if (intel_sdvo->is_tv) {
  949. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  950. return false;
  951. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  952. mode,
  953. adjusted_mode);
  954. pipe_config->sdvo_tv_clock = true;
  955. } else if (intel_sdvo->is_lvds) {
  956. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  957. intel_sdvo->sdvo_lvds_fixed_mode))
  958. return false;
  959. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  960. mode,
  961. adjusted_mode);
  962. }
  963. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  964. * SDVO device will factor out the multiplier during mode_set.
  965. */
  966. pipe_config->pixel_multiplier =
  967. intel_sdvo_get_pixel_multiplier(adjusted_mode);
  968. adjusted_mode->clock *= pipe_config->pixel_multiplier;
  969. if (intel_sdvo->color_range_auto) {
  970. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  971. /* FIXME: This bit is only valid when using TMDS encoding and 8
  972. * bit per color mode. */
  973. if (intel_sdvo->has_hdmi_monitor &&
  974. drm_match_cea_mode(adjusted_mode) > 1)
  975. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  976. else
  977. intel_sdvo->color_range = 0;
  978. }
  979. if (intel_sdvo->color_range)
  980. pipe_config->limited_color_range = true;
  981. /* Clock computation needs to happen after pixel multiplier. */
  982. if (intel_sdvo->is_tv)
  983. i9xx_adjust_sdvo_tv_clock(pipe_config);
  984. return true;
  985. }
  986. static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
  987. {
  988. struct drm_device *dev = intel_encoder->base.dev;
  989. struct drm_i915_private *dev_priv = dev->dev_private;
  990. struct drm_crtc *crtc = intel_encoder->base.crtc;
  991. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  992. struct drm_display_mode *adjusted_mode =
  993. &intel_crtc->config.adjusted_mode;
  994. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  995. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
  996. u32 sdvox;
  997. struct intel_sdvo_in_out_map in_out;
  998. struct intel_sdvo_dtd input_dtd, output_dtd;
  999. int rate;
  1000. if (!mode)
  1001. return;
  1002. /* First, set the input mapping for the first input to our controlled
  1003. * output. This is only correct if we're a single-input device, in
  1004. * which case the first input is the output from the appropriate SDVO
  1005. * channel on the motherboard. In a two-input device, the first input
  1006. * will be SDVOB and the second SDVOC.
  1007. */
  1008. in_out.in0 = intel_sdvo->attached_output;
  1009. in_out.in1 = 0;
  1010. intel_sdvo_set_value(intel_sdvo,
  1011. SDVO_CMD_SET_IN_OUT_MAP,
  1012. &in_out, sizeof(in_out));
  1013. /* Set the output timings to the screen */
  1014. if (!intel_sdvo_set_target_output(intel_sdvo,
  1015. intel_sdvo->attached_output))
  1016. return;
  1017. /* lvds has a special fixed output timing. */
  1018. if (intel_sdvo->is_lvds)
  1019. intel_sdvo_get_dtd_from_mode(&output_dtd,
  1020. intel_sdvo->sdvo_lvds_fixed_mode);
  1021. else
  1022. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  1023. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  1024. DRM_INFO("Setting output timings on %s failed\n",
  1025. SDVO_NAME(intel_sdvo));
  1026. /* Set the input timing to the screen. Assume always input 0. */
  1027. if (!intel_sdvo_set_target_input(intel_sdvo))
  1028. return;
  1029. if (intel_sdvo->has_hdmi_monitor) {
  1030. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  1031. intel_sdvo_set_colorimetry(intel_sdvo,
  1032. SDVO_COLORIMETRY_RGB256);
  1033. intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
  1034. } else
  1035. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  1036. if (intel_sdvo->is_tv &&
  1037. !intel_sdvo_set_tv_format(intel_sdvo))
  1038. return;
  1039. /* We have tried to get input timing in mode_fixup, and filled into
  1040. * adjusted_mode.
  1041. */
  1042. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  1043. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  1044. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  1045. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1046. DRM_INFO("Setting input timings on %s failed\n",
  1047. SDVO_NAME(intel_sdvo));
  1048. switch (intel_crtc->config.pixel_multiplier) {
  1049. default:
  1050. WARN(1, "unknown pixel mutlipler specified\n");
  1051. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1052. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1053. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1054. }
  1055. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1056. return;
  1057. /* Set the SDVO control regs. */
  1058. if (INTEL_INFO(dev)->gen >= 4) {
  1059. /* The real mode polarity is set by the SDVO commands, using
  1060. * struct intel_sdvo_dtd. */
  1061. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1062. if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
  1063. sdvox |= intel_sdvo->color_range;
  1064. if (INTEL_INFO(dev)->gen < 5)
  1065. sdvox |= SDVO_BORDER_ENABLE;
  1066. } else {
  1067. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1068. switch (intel_sdvo->sdvo_reg) {
  1069. case GEN3_SDVOB:
  1070. sdvox &= SDVOB_PRESERVE_MASK;
  1071. break;
  1072. case GEN3_SDVOC:
  1073. sdvox &= SDVOC_PRESERVE_MASK;
  1074. break;
  1075. }
  1076. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1077. }
  1078. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1079. sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
  1080. else
  1081. sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1082. if (intel_sdvo->has_hdmi_audio)
  1083. sdvox |= SDVO_AUDIO_ENABLE;
  1084. if (INTEL_INFO(dev)->gen >= 4) {
  1085. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1086. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1087. /* done in crtc_mode_set as it lives inside the dpll register */
  1088. } else {
  1089. sdvox |= (intel_crtc->config.pixel_multiplier - 1)
  1090. << SDVO_PORT_MULTIPLY_SHIFT;
  1091. }
  1092. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1093. INTEL_INFO(dev)->gen < 5)
  1094. sdvox |= SDVO_STALL_SELECT;
  1095. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1096. }
  1097. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1098. {
  1099. struct intel_sdvo_connector *intel_sdvo_connector =
  1100. to_intel_sdvo_connector(&connector->base);
  1101. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1102. u16 active_outputs = 0;
  1103. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1104. if (active_outputs & intel_sdvo_connector->output_flag)
  1105. return true;
  1106. else
  1107. return false;
  1108. }
  1109. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1110. enum pipe *pipe)
  1111. {
  1112. struct drm_device *dev = encoder->base.dev;
  1113. struct drm_i915_private *dev_priv = dev->dev_private;
  1114. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1115. u16 active_outputs = 0;
  1116. u32 tmp;
  1117. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1118. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1119. if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
  1120. return false;
  1121. if (HAS_PCH_CPT(dev))
  1122. *pipe = PORT_TO_PIPE_CPT(tmp);
  1123. else
  1124. *pipe = PORT_TO_PIPE(tmp);
  1125. return true;
  1126. }
  1127. static void intel_sdvo_get_config(struct intel_encoder *encoder,
  1128. struct intel_crtc_config *pipe_config)
  1129. {
  1130. struct drm_device *dev = encoder->base.dev;
  1131. struct drm_i915_private *dev_priv = dev->dev_private;
  1132. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1133. struct intel_sdvo_dtd dtd;
  1134. int encoder_pixel_multiplier = 0;
  1135. u32 flags = 0, sdvox;
  1136. u8 val;
  1137. bool ret;
  1138. ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
  1139. if (!ret) {
  1140. /* Some sdvo encoders are not spec compliant and don't
  1141. * implement the mandatory get_timings function. */
  1142. DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
  1143. pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
  1144. } else {
  1145. if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  1146. flags |= DRM_MODE_FLAG_PHSYNC;
  1147. else
  1148. flags |= DRM_MODE_FLAG_NHSYNC;
  1149. if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  1150. flags |= DRM_MODE_FLAG_PVSYNC;
  1151. else
  1152. flags |= DRM_MODE_FLAG_NVSYNC;
  1153. }
  1154. pipe_config->adjusted_mode.flags |= flags;
  1155. /*
  1156. * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
  1157. * the sdvo port register, on all other platforms it is part of the dpll
  1158. * state. Since the general pipe state readout happens before the
  1159. * encoder->get_config we so already have a valid pixel multplier on all
  1160. * other platfroms.
  1161. */
  1162. if (IS_I915G(dev) || IS_I915GM(dev)) {
  1163. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1164. pipe_config->pixel_multiplier =
  1165. ((sdvox & SDVO_PORT_MULTIPLY_MASK)
  1166. >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
  1167. }
  1168. /* Cross check the port pixel multiplier with the sdvo encoder state. */
  1169. if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
  1170. &val, 1)) {
  1171. switch (val) {
  1172. case SDVO_CLOCK_RATE_MULT_1X:
  1173. encoder_pixel_multiplier = 1;
  1174. break;
  1175. case SDVO_CLOCK_RATE_MULT_2X:
  1176. encoder_pixel_multiplier = 2;
  1177. break;
  1178. case SDVO_CLOCK_RATE_MULT_4X:
  1179. encoder_pixel_multiplier = 4;
  1180. break;
  1181. }
  1182. }
  1183. WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
  1184. "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
  1185. pipe_config->pixel_multiplier, encoder_pixel_multiplier);
  1186. }
  1187. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1188. {
  1189. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1190. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1191. u32 temp;
  1192. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1193. if (0)
  1194. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1195. DRM_MODE_DPMS_OFF);
  1196. temp = I915_READ(intel_sdvo->sdvo_reg);
  1197. if ((temp & SDVO_ENABLE) != 0) {
  1198. /* HW workaround for IBX, we need to move the port to
  1199. * transcoder A before disabling it. */
  1200. if (HAS_PCH_IBX(encoder->base.dev)) {
  1201. struct drm_crtc *crtc = encoder->base.crtc;
  1202. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1203. if (temp & SDVO_PIPE_B_SELECT) {
  1204. temp &= ~SDVO_PIPE_B_SELECT;
  1205. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1206. POSTING_READ(intel_sdvo->sdvo_reg);
  1207. /* Again we need to write this twice. */
  1208. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1209. POSTING_READ(intel_sdvo->sdvo_reg);
  1210. /* Transcoder selection bits only update
  1211. * effectively on vblank. */
  1212. if (crtc)
  1213. intel_wait_for_vblank(encoder->base.dev, pipe);
  1214. else
  1215. msleep(50);
  1216. }
  1217. }
  1218. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1219. }
  1220. }
  1221. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1222. {
  1223. struct drm_device *dev = encoder->base.dev;
  1224. struct drm_i915_private *dev_priv = dev->dev_private;
  1225. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1226. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1227. u32 temp;
  1228. bool input1, input2;
  1229. int i;
  1230. u8 status;
  1231. temp = I915_READ(intel_sdvo->sdvo_reg);
  1232. if ((temp & SDVO_ENABLE) == 0) {
  1233. /* HW workaround for IBX, we need to move the port
  1234. * to transcoder A before disabling it, so restore it here. */
  1235. if (HAS_PCH_IBX(dev))
  1236. temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1237. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1238. }
  1239. for (i = 0; i < 2; i++)
  1240. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1241. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1242. /* Warn if the device reported failure to sync.
  1243. * A lot of SDVO devices fail to notify of sync, but it's
  1244. * a given it the status is a success, we succeeded.
  1245. */
  1246. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1247. DRM_DEBUG_KMS("First %s output reported failure to "
  1248. "sync\n", SDVO_NAME(intel_sdvo));
  1249. }
  1250. if (0)
  1251. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1252. DRM_MODE_DPMS_ON);
  1253. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1254. }
  1255. /* Special dpms function to support cloning between dvo/sdvo/crt. */
  1256. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1257. {
  1258. struct drm_crtc *crtc;
  1259. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1260. /* dvo supports only 2 dpms states. */
  1261. if (mode != DRM_MODE_DPMS_ON)
  1262. mode = DRM_MODE_DPMS_OFF;
  1263. if (mode == connector->dpms)
  1264. return;
  1265. connector->dpms = mode;
  1266. /* Only need to change hw state when actually enabled */
  1267. crtc = intel_sdvo->base.base.crtc;
  1268. if (!crtc) {
  1269. intel_sdvo->base.connectors_active = false;
  1270. return;
  1271. }
  1272. /* We set active outputs manually below in case pipe dpms doesn't change
  1273. * due to cloning. */
  1274. if (mode != DRM_MODE_DPMS_ON) {
  1275. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1276. if (0)
  1277. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1278. intel_sdvo->base.connectors_active = false;
  1279. intel_crtc_update_dpms(crtc);
  1280. } else {
  1281. intel_sdvo->base.connectors_active = true;
  1282. intel_crtc_update_dpms(crtc);
  1283. if (0)
  1284. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1285. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1286. }
  1287. intel_modeset_check_state(connector->dev);
  1288. }
  1289. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1290. struct drm_display_mode *mode)
  1291. {
  1292. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1293. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1294. return MODE_NO_DBLESCAN;
  1295. if (intel_sdvo->pixel_clock_min > mode->clock)
  1296. return MODE_CLOCK_LOW;
  1297. if (intel_sdvo->pixel_clock_max < mode->clock)
  1298. return MODE_CLOCK_HIGH;
  1299. if (intel_sdvo->is_lvds) {
  1300. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1301. return MODE_PANEL;
  1302. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1303. return MODE_PANEL;
  1304. }
  1305. return MODE_OK;
  1306. }
  1307. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1308. {
  1309. BUILD_BUG_ON(sizeof(*caps) != 8);
  1310. if (!intel_sdvo_get_value(intel_sdvo,
  1311. SDVO_CMD_GET_DEVICE_CAPS,
  1312. caps, sizeof(*caps)))
  1313. return false;
  1314. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1315. " vendor_id: %d\n"
  1316. " device_id: %d\n"
  1317. " device_rev_id: %d\n"
  1318. " sdvo_version_major: %d\n"
  1319. " sdvo_version_minor: %d\n"
  1320. " sdvo_inputs_mask: %d\n"
  1321. " smooth_scaling: %d\n"
  1322. " sharp_scaling: %d\n"
  1323. " up_scaling: %d\n"
  1324. " down_scaling: %d\n"
  1325. " stall_support: %d\n"
  1326. " output_flags: %d\n",
  1327. caps->vendor_id,
  1328. caps->device_id,
  1329. caps->device_rev_id,
  1330. caps->sdvo_version_major,
  1331. caps->sdvo_version_minor,
  1332. caps->sdvo_inputs_mask,
  1333. caps->smooth_scaling,
  1334. caps->sharp_scaling,
  1335. caps->up_scaling,
  1336. caps->down_scaling,
  1337. caps->stall_support,
  1338. caps->output_flags);
  1339. return true;
  1340. }
  1341. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1342. {
  1343. struct drm_device *dev = intel_sdvo->base.base.dev;
  1344. uint16_t hotplug;
  1345. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1346. * on the line. */
  1347. if (IS_I945G(dev) || IS_I945GM(dev))
  1348. return 0;
  1349. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1350. &hotplug, sizeof(hotplug)))
  1351. return 0;
  1352. return hotplug;
  1353. }
  1354. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1355. {
  1356. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1357. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1358. &intel_sdvo->hotplug_active, 2);
  1359. }
  1360. static bool
  1361. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1362. {
  1363. /* Is there more than one type of output? */
  1364. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1365. }
  1366. static struct edid *
  1367. intel_sdvo_get_edid(struct drm_connector *connector)
  1368. {
  1369. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1370. return drm_get_edid(connector, &sdvo->ddc);
  1371. }
  1372. /* Mac mini hack -- use the same DDC as the analog connector */
  1373. static struct edid *
  1374. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1375. {
  1376. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1377. return drm_get_edid(connector,
  1378. intel_gmbus_get_adapter(dev_priv,
  1379. dev_priv->vbt.crt_ddc_pin));
  1380. }
  1381. static enum drm_connector_status
  1382. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1383. {
  1384. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1385. enum drm_connector_status status;
  1386. struct edid *edid;
  1387. edid = intel_sdvo_get_edid(connector);
  1388. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1389. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1390. /*
  1391. * Don't use the 1 as the argument of DDC bus switch to get
  1392. * the EDID. It is used for SDVO SPD ROM.
  1393. */
  1394. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1395. intel_sdvo->ddc_bus = ddc;
  1396. edid = intel_sdvo_get_edid(connector);
  1397. if (edid)
  1398. break;
  1399. }
  1400. /*
  1401. * If we found the EDID on the other bus,
  1402. * assume that is the correct DDC bus.
  1403. */
  1404. if (edid == NULL)
  1405. intel_sdvo->ddc_bus = saved_ddc;
  1406. }
  1407. /*
  1408. * When there is no edid and no monitor is connected with VGA
  1409. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1410. */
  1411. if (edid == NULL)
  1412. edid = intel_sdvo_get_analog_edid(connector);
  1413. status = connector_status_unknown;
  1414. if (edid != NULL) {
  1415. /* DDC bus is shared, match EDID to connector type */
  1416. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1417. status = connector_status_connected;
  1418. if (intel_sdvo->is_hdmi) {
  1419. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1420. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1421. intel_sdvo->rgb_quant_range_selectable =
  1422. drm_rgb_quant_range_selectable(edid);
  1423. }
  1424. } else
  1425. status = connector_status_disconnected;
  1426. kfree(edid);
  1427. }
  1428. if (status == connector_status_connected) {
  1429. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1430. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1431. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1432. }
  1433. return status;
  1434. }
  1435. static bool
  1436. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1437. struct edid *edid)
  1438. {
  1439. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1440. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1441. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1442. connector_is_digital, monitor_is_digital);
  1443. return connector_is_digital == monitor_is_digital;
  1444. }
  1445. static enum drm_connector_status
  1446. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1447. {
  1448. uint16_t response;
  1449. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1450. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1451. enum drm_connector_status ret;
  1452. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  1453. connector->base.id, drm_get_connector_name(connector));
  1454. if (!intel_sdvo_get_value(intel_sdvo,
  1455. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1456. &response, 2))
  1457. return connector_status_unknown;
  1458. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1459. response & 0xff, response >> 8,
  1460. intel_sdvo_connector->output_flag);
  1461. if (response == 0)
  1462. return connector_status_disconnected;
  1463. intel_sdvo->attached_output = response;
  1464. intel_sdvo->has_hdmi_monitor = false;
  1465. intel_sdvo->has_hdmi_audio = false;
  1466. intel_sdvo->rgb_quant_range_selectable = false;
  1467. if ((intel_sdvo_connector->output_flag & response) == 0)
  1468. ret = connector_status_disconnected;
  1469. else if (IS_TMDS(intel_sdvo_connector))
  1470. ret = intel_sdvo_tmds_sink_detect(connector);
  1471. else {
  1472. struct edid *edid;
  1473. /* if we have an edid check it matches the connection */
  1474. edid = intel_sdvo_get_edid(connector);
  1475. if (edid == NULL)
  1476. edid = intel_sdvo_get_analog_edid(connector);
  1477. if (edid != NULL) {
  1478. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1479. edid))
  1480. ret = connector_status_connected;
  1481. else
  1482. ret = connector_status_disconnected;
  1483. kfree(edid);
  1484. } else
  1485. ret = connector_status_connected;
  1486. }
  1487. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1488. if (ret == connector_status_connected) {
  1489. intel_sdvo->is_tv = false;
  1490. intel_sdvo->is_lvds = false;
  1491. if (response & SDVO_TV_MASK)
  1492. intel_sdvo->is_tv = true;
  1493. if (response & SDVO_LVDS_MASK)
  1494. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1495. }
  1496. return ret;
  1497. }
  1498. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1499. {
  1500. struct edid *edid;
  1501. /* set the bus switch and get the modes */
  1502. edid = intel_sdvo_get_edid(connector);
  1503. /*
  1504. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1505. * link between analog and digital outputs. So, if the regular SDVO
  1506. * DDC fails, check to see if the analog output is disconnected, in
  1507. * which case we'll look there for the digital DDC data.
  1508. */
  1509. if (edid == NULL)
  1510. edid = intel_sdvo_get_analog_edid(connector);
  1511. if (edid != NULL) {
  1512. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1513. edid)) {
  1514. drm_mode_connector_update_edid_property(connector, edid);
  1515. drm_add_edid_modes(connector, edid);
  1516. }
  1517. kfree(edid);
  1518. }
  1519. }
  1520. /*
  1521. * Set of SDVO TV modes.
  1522. * Note! This is in reply order (see loop in get_tv_modes).
  1523. * XXX: all 60Hz refresh?
  1524. */
  1525. static const struct drm_display_mode sdvo_tv_modes[] = {
  1526. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1527. 416, 0, 200, 201, 232, 233, 0,
  1528. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1529. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1530. 416, 0, 240, 241, 272, 273, 0,
  1531. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1532. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1533. 496, 0, 300, 301, 332, 333, 0,
  1534. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1535. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1536. 736, 0, 350, 351, 382, 383, 0,
  1537. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1538. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1539. 736, 0, 400, 401, 432, 433, 0,
  1540. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1541. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1542. 736, 0, 480, 481, 512, 513, 0,
  1543. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1544. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1545. 800, 0, 480, 481, 512, 513, 0,
  1546. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1547. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1548. 800, 0, 576, 577, 608, 609, 0,
  1549. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1550. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1551. 816, 0, 350, 351, 382, 383, 0,
  1552. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1553. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1554. 816, 0, 400, 401, 432, 433, 0,
  1555. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1556. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1557. 816, 0, 480, 481, 512, 513, 0,
  1558. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1559. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1560. 816, 0, 540, 541, 572, 573, 0,
  1561. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1562. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1563. 816, 0, 576, 577, 608, 609, 0,
  1564. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1565. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1566. 864, 0, 576, 577, 608, 609, 0,
  1567. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1568. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1569. 896, 0, 600, 601, 632, 633, 0,
  1570. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1571. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1572. 928, 0, 624, 625, 656, 657, 0,
  1573. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1574. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1575. 1016, 0, 766, 767, 798, 799, 0,
  1576. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1577. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1578. 1120, 0, 768, 769, 800, 801, 0,
  1579. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1580. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1581. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1582. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1583. };
  1584. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1585. {
  1586. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1587. struct intel_sdvo_sdtv_resolution_request tv_res;
  1588. uint32_t reply = 0, format_map = 0;
  1589. int i;
  1590. /* Read the list of supported input resolutions for the selected TV
  1591. * format.
  1592. */
  1593. format_map = 1 << intel_sdvo->tv_format_index;
  1594. memcpy(&tv_res, &format_map,
  1595. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1596. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1597. return;
  1598. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1599. if (!intel_sdvo_write_cmd(intel_sdvo,
  1600. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1601. &tv_res, sizeof(tv_res)))
  1602. return;
  1603. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1604. return;
  1605. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1606. if (reply & (1 << i)) {
  1607. struct drm_display_mode *nmode;
  1608. nmode = drm_mode_duplicate(connector->dev,
  1609. &sdvo_tv_modes[i]);
  1610. if (nmode)
  1611. drm_mode_probed_add(connector, nmode);
  1612. }
  1613. }
  1614. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1615. {
  1616. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1617. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1618. struct drm_display_mode *newmode;
  1619. /*
  1620. * Fetch modes from VBT. For SDVO prefer the VBT mode since some
  1621. * SDVO->LVDS transcoders can't cope with the EDID mode.
  1622. */
  1623. if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
  1624. newmode = drm_mode_duplicate(connector->dev,
  1625. dev_priv->vbt.sdvo_lvds_vbt_mode);
  1626. if (newmode != NULL) {
  1627. /* Guarantee the mode is preferred */
  1628. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1629. DRM_MODE_TYPE_DRIVER);
  1630. drm_mode_probed_add(connector, newmode);
  1631. }
  1632. }
  1633. /*
  1634. * Attempt to get the mode list from DDC.
  1635. * Assume that the preferred modes are
  1636. * arranged in priority order.
  1637. */
  1638. intel_ddc_get_modes(connector, &intel_sdvo->ddc);
  1639. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1640. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1641. intel_sdvo->sdvo_lvds_fixed_mode =
  1642. drm_mode_duplicate(connector->dev, newmode);
  1643. intel_sdvo->is_lvds = true;
  1644. break;
  1645. }
  1646. }
  1647. }
  1648. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1649. {
  1650. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1651. if (IS_TV(intel_sdvo_connector))
  1652. intel_sdvo_get_tv_modes(connector);
  1653. else if (IS_LVDS(intel_sdvo_connector))
  1654. intel_sdvo_get_lvds_modes(connector);
  1655. else
  1656. intel_sdvo_get_ddc_modes(connector);
  1657. return !list_empty(&connector->probed_modes);
  1658. }
  1659. static void
  1660. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1661. {
  1662. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1663. struct drm_device *dev = connector->dev;
  1664. if (intel_sdvo_connector->left)
  1665. drm_property_destroy(dev, intel_sdvo_connector->left);
  1666. if (intel_sdvo_connector->right)
  1667. drm_property_destroy(dev, intel_sdvo_connector->right);
  1668. if (intel_sdvo_connector->top)
  1669. drm_property_destroy(dev, intel_sdvo_connector->top);
  1670. if (intel_sdvo_connector->bottom)
  1671. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1672. if (intel_sdvo_connector->hpos)
  1673. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1674. if (intel_sdvo_connector->vpos)
  1675. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1676. if (intel_sdvo_connector->saturation)
  1677. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1678. if (intel_sdvo_connector->contrast)
  1679. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1680. if (intel_sdvo_connector->hue)
  1681. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1682. if (intel_sdvo_connector->sharpness)
  1683. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1684. if (intel_sdvo_connector->flicker_filter)
  1685. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1686. if (intel_sdvo_connector->flicker_filter_2d)
  1687. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1688. if (intel_sdvo_connector->flicker_filter_adaptive)
  1689. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1690. if (intel_sdvo_connector->tv_luma_filter)
  1691. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1692. if (intel_sdvo_connector->tv_chroma_filter)
  1693. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1694. if (intel_sdvo_connector->dot_crawl)
  1695. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1696. if (intel_sdvo_connector->brightness)
  1697. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1698. }
  1699. static void intel_sdvo_destroy(struct drm_connector *connector)
  1700. {
  1701. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1702. if (intel_sdvo_connector->tv_format)
  1703. drm_property_destroy(connector->dev,
  1704. intel_sdvo_connector->tv_format);
  1705. intel_sdvo_destroy_enhance_property(connector);
  1706. drm_sysfs_connector_remove(connector);
  1707. drm_connector_cleanup(connector);
  1708. kfree(intel_sdvo_connector);
  1709. }
  1710. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1711. {
  1712. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1713. struct edid *edid;
  1714. bool has_audio = false;
  1715. if (!intel_sdvo->is_hdmi)
  1716. return false;
  1717. edid = intel_sdvo_get_edid(connector);
  1718. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1719. has_audio = drm_detect_monitor_audio(edid);
  1720. kfree(edid);
  1721. return has_audio;
  1722. }
  1723. static int
  1724. intel_sdvo_set_property(struct drm_connector *connector,
  1725. struct drm_property *property,
  1726. uint64_t val)
  1727. {
  1728. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1729. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1730. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1731. uint16_t temp_value;
  1732. uint8_t cmd;
  1733. int ret;
  1734. ret = drm_object_property_set_value(&connector->base, property, val);
  1735. if (ret)
  1736. return ret;
  1737. if (property == dev_priv->force_audio_property) {
  1738. int i = val;
  1739. bool has_audio;
  1740. if (i == intel_sdvo_connector->force_audio)
  1741. return 0;
  1742. intel_sdvo_connector->force_audio = i;
  1743. if (i == HDMI_AUDIO_AUTO)
  1744. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1745. else
  1746. has_audio = (i == HDMI_AUDIO_ON);
  1747. if (has_audio == intel_sdvo->has_hdmi_audio)
  1748. return 0;
  1749. intel_sdvo->has_hdmi_audio = has_audio;
  1750. goto done;
  1751. }
  1752. if (property == dev_priv->broadcast_rgb_property) {
  1753. bool old_auto = intel_sdvo->color_range_auto;
  1754. uint32_t old_range = intel_sdvo->color_range;
  1755. switch (val) {
  1756. case INTEL_BROADCAST_RGB_AUTO:
  1757. intel_sdvo->color_range_auto = true;
  1758. break;
  1759. case INTEL_BROADCAST_RGB_FULL:
  1760. intel_sdvo->color_range_auto = false;
  1761. intel_sdvo->color_range = 0;
  1762. break;
  1763. case INTEL_BROADCAST_RGB_LIMITED:
  1764. intel_sdvo->color_range_auto = false;
  1765. /* FIXME: this bit is only valid when using TMDS
  1766. * encoding and 8 bit per color mode. */
  1767. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  1768. break;
  1769. default:
  1770. return -EINVAL;
  1771. }
  1772. if (old_auto == intel_sdvo->color_range_auto &&
  1773. old_range == intel_sdvo->color_range)
  1774. return 0;
  1775. goto done;
  1776. }
  1777. #define CHECK_PROPERTY(name, NAME) \
  1778. if (intel_sdvo_connector->name == property) { \
  1779. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1780. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1781. cmd = SDVO_CMD_SET_##NAME; \
  1782. intel_sdvo_connector->cur_##name = temp_value; \
  1783. goto set_value; \
  1784. }
  1785. if (property == intel_sdvo_connector->tv_format) {
  1786. if (val >= TV_FORMAT_NUM)
  1787. return -EINVAL;
  1788. if (intel_sdvo->tv_format_index ==
  1789. intel_sdvo_connector->tv_format_supported[val])
  1790. return 0;
  1791. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1792. goto done;
  1793. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1794. temp_value = val;
  1795. if (intel_sdvo_connector->left == property) {
  1796. drm_object_property_set_value(&connector->base,
  1797. intel_sdvo_connector->right, val);
  1798. if (intel_sdvo_connector->left_margin == temp_value)
  1799. return 0;
  1800. intel_sdvo_connector->left_margin = temp_value;
  1801. intel_sdvo_connector->right_margin = temp_value;
  1802. temp_value = intel_sdvo_connector->max_hscan -
  1803. intel_sdvo_connector->left_margin;
  1804. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1805. goto set_value;
  1806. } else if (intel_sdvo_connector->right == property) {
  1807. drm_object_property_set_value(&connector->base,
  1808. intel_sdvo_connector->left, val);
  1809. if (intel_sdvo_connector->right_margin == temp_value)
  1810. return 0;
  1811. intel_sdvo_connector->left_margin = temp_value;
  1812. intel_sdvo_connector->right_margin = temp_value;
  1813. temp_value = intel_sdvo_connector->max_hscan -
  1814. intel_sdvo_connector->left_margin;
  1815. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1816. goto set_value;
  1817. } else if (intel_sdvo_connector->top == property) {
  1818. drm_object_property_set_value(&connector->base,
  1819. intel_sdvo_connector->bottom, val);
  1820. if (intel_sdvo_connector->top_margin == temp_value)
  1821. return 0;
  1822. intel_sdvo_connector->top_margin = temp_value;
  1823. intel_sdvo_connector->bottom_margin = temp_value;
  1824. temp_value = intel_sdvo_connector->max_vscan -
  1825. intel_sdvo_connector->top_margin;
  1826. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1827. goto set_value;
  1828. } else if (intel_sdvo_connector->bottom == property) {
  1829. drm_object_property_set_value(&connector->base,
  1830. intel_sdvo_connector->top, val);
  1831. if (intel_sdvo_connector->bottom_margin == temp_value)
  1832. return 0;
  1833. intel_sdvo_connector->top_margin = temp_value;
  1834. intel_sdvo_connector->bottom_margin = temp_value;
  1835. temp_value = intel_sdvo_connector->max_vscan -
  1836. intel_sdvo_connector->top_margin;
  1837. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1838. goto set_value;
  1839. }
  1840. CHECK_PROPERTY(hpos, HPOS)
  1841. CHECK_PROPERTY(vpos, VPOS)
  1842. CHECK_PROPERTY(saturation, SATURATION)
  1843. CHECK_PROPERTY(contrast, CONTRAST)
  1844. CHECK_PROPERTY(hue, HUE)
  1845. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1846. CHECK_PROPERTY(sharpness, SHARPNESS)
  1847. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1848. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1849. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1850. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1851. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1852. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1853. }
  1854. return -EINVAL; /* unknown property */
  1855. set_value:
  1856. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1857. return -EIO;
  1858. done:
  1859. if (intel_sdvo->base.base.crtc)
  1860. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1861. return 0;
  1862. #undef CHECK_PROPERTY
  1863. }
  1864. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1865. .dpms = intel_sdvo_dpms,
  1866. .detect = intel_sdvo_detect,
  1867. .fill_modes = drm_helper_probe_single_connector_modes,
  1868. .set_property = intel_sdvo_set_property,
  1869. .destroy = intel_sdvo_destroy,
  1870. };
  1871. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1872. .get_modes = intel_sdvo_get_modes,
  1873. .mode_valid = intel_sdvo_mode_valid,
  1874. .best_encoder = intel_best_encoder,
  1875. };
  1876. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1877. {
  1878. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1879. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1880. drm_mode_destroy(encoder->dev,
  1881. intel_sdvo->sdvo_lvds_fixed_mode);
  1882. i2c_del_adapter(&intel_sdvo->ddc);
  1883. intel_encoder_destroy(encoder);
  1884. }
  1885. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1886. .destroy = intel_sdvo_enc_destroy,
  1887. };
  1888. static void
  1889. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1890. {
  1891. uint16_t mask = 0;
  1892. unsigned int num_bits;
  1893. /* Make a mask of outputs less than or equal to our own priority in the
  1894. * list.
  1895. */
  1896. switch (sdvo->controlled_output) {
  1897. case SDVO_OUTPUT_LVDS1:
  1898. mask |= SDVO_OUTPUT_LVDS1;
  1899. case SDVO_OUTPUT_LVDS0:
  1900. mask |= SDVO_OUTPUT_LVDS0;
  1901. case SDVO_OUTPUT_TMDS1:
  1902. mask |= SDVO_OUTPUT_TMDS1;
  1903. case SDVO_OUTPUT_TMDS0:
  1904. mask |= SDVO_OUTPUT_TMDS0;
  1905. case SDVO_OUTPUT_RGB1:
  1906. mask |= SDVO_OUTPUT_RGB1;
  1907. case SDVO_OUTPUT_RGB0:
  1908. mask |= SDVO_OUTPUT_RGB0;
  1909. break;
  1910. }
  1911. /* Count bits to find what number we are in the priority list. */
  1912. mask &= sdvo->caps.output_flags;
  1913. num_bits = hweight16(mask);
  1914. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1915. if (num_bits > 3)
  1916. num_bits = 3;
  1917. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1918. sdvo->ddc_bus = 1 << num_bits;
  1919. }
  1920. /**
  1921. * Choose the appropriate DDC bus for control bus switch command for this
  1922. * SDVO output based on the controlled output.
  1923. *
  1924. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1925. * outputs, then LVDS outputs.
  1926. */
  1927. static void
  1928. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1929. struct intel_sdvo *sdvo, u32 reg)
  1930. {
  1931. struct sdvo_device_mapping *mapping;
  1932. if (sdvo->is_sdvob)
  1933. mapping = &(dev_priv->sdvo_mappings[0]);
  1934. else
  1935. mapping = &(dev_priv->sdvo_mappings[1]);
  1936. if (mapping->initialized)
  1937. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1938. else
  1939. intel_sdvo_guess_ddc_bus(sdvo);
  1940. }
  1941. static void
  1942. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1943. struct intel_sdvo *sdvo, u32 reg)
  1944. {
  1945. struct sdvo_device_mapping *mapping;
  1946. u8 pin;
  1947. if (sdvo->is_sdvob)
  1948. mapping = &dev_priv->sdvo_mappings[0];
  1949. else
  1950. mapping = &dev_priv->sdvo_mappings[1];
  1951. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1952. pin = mapping->i2c_pin;
  1953. else
  1954. pin = GMBUS_PORT_DPB;
  1955. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1956. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1957. * our code totally fails once we start using gmbus. Hence fall back to
  1958. * bit banging for now. */
  1959. intel_gmbus_force_bit(sdvo->i2c, true);
  1960. }
  1961. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  1962. static void
  1963. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  1964. {
  1965. intel_gmbus_force_bit(sdvo->i2c, false);
  1966. }
  1967. static bool
  1968. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1969. {
  1970. return intel_sdvo_check_supp_encode(intel_sdvo);
  1971. }
  1972. static u8
  1973. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1974. {
  1975. struct drm_i915_private *dev_priv = dev->dev_private;
  1976. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1977. if (sdvo->is_sdvob) {
  1978. my_mapping = &dev_priv->sdvo_mappings[0];
  1979. other_mapping = &dev_priv->sdvo_mappings[1];
  1980. } else {
  1981. my_mapping = &dev_priv->sdvo_mappings[1];
  1982. other_mapping = &dev_priv->sdvo_mappings[0];
  1983. }
  1984. /* If the BIOS described our SDVO device, take advantage of it. */
  1985. if (my_mapping->slave_addr)
  1986. return my_mapping->slave_addr;
  1987. /* If the BIOS only described a different SDVO device, use the
  1988. * address that it isn't using.
  1989. */
  1990. if (other_mapping->slave_addr) {
  1991. if (other_mapping->slave_addr == 0x70)
  1992. return 0x72;
  1993. else
  1994. return 0x70;
  1995. }
  1996. /* No SDVO device info is found for another DVO port,
  1997. * so use mapping assumption we had before BIOS parsing.
  1998. */
  1999. if (sdvo->is_sdvob)
  2000. return 0x70;
  2001. else
  2002. return 0x72;
  2003. }
  2004. static void
  2005. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  2006. struct intel_sdvo *encoder)
  2007. {
  2008. drm_connector_init(encoder->base.base.dev,
  2009. &connector->base.base,
  2010. &intel_sdvo_connector_funcs,
  2011. connector->base.base.connector_type);
  2012. drm_connector_helper_add(&connector->base.base,
  2013. &intel_sdvo_connector_helper_funcs);
  2014. connector->base.base.interlace_allowed = 1;
  2015. connector->base.base.doublescan_allowed = 0;
  2016. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  2017. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  2018. intel_connector_attach_encoder(&connector->base, &encoder->base);
  2019. drm_sysfs_connector_add(&connector->base.base);
  2020. }
  2021. static void
  2022. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  2023. struct intel_sdvo_connector *connector)
  2024. {
  2025. struct drm_device *dev = connector->base.base.dev;
  2026. intel_attach_force_audio_property(&connector->base.base);
  2027. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  2028. intel_attach_broadcast_rgb_property(&connector->base.base);
  2029. intel_sdvo->color_range_auto = true;
  2030. }
  2031. }
  2032. static bool
  2033. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  2034. {
  2035. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2036. struct drm_connector *connector;
  2037. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2038. struct intel_connector *intel_connector;
  2039. struct intel_sdvo_connector *intel_sdvo_connector;
  2040. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2041. if (!intel_sdvo_connector)
  2042. return false;
  2043. if (device == 0) {
  2044. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  2045. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  2046. } else if (device == 1) {
  2047. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  2048. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  2049. }
  2050. intel_connector = &intel_sdvo_connector->base;
  2051. connector = &intel_connector->base;
  2052. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  2053. intel_sdvo_connector->output_flag) {
  2054. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  2055. /* Some SDVO devices have one-shot hotplug interrupts.
  2056. * Ensure that they get re-enabled when an interrupt happens.
  2057. */
  2058. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  2059. intel_sdvo_enable_hotplug(intel_encoder);
  2060. } else {
  2061. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  2062. }
  2063. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  2064. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  2065. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  2066. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  2067. intel_sdvo->is_hdmi = true;
  2068. }
  2069. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2070. if (intel_sdvo->is_hdmi)
  2071. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  2072. return true;
  2073. }
  2074. static bool
  2075. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  2076. {
  2077. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2078. struct drm_connector *connector;
  2079. struct intel_connector *intel_connector;
  2080. struct intel_sdvo_connector *intel_sdvo_connector;
  2081. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2082. if (!intel_sdvo_connector)
  2083. return false;
  2084. intel_connector = &intel_sdvo_connector->base;
  2085. connector = &intel_connector->base;
  2086. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  2087. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  2088. intel_sdvo->controlled_output |= type;
  2089. intel_sdvo_connector->output_flag = type;
  2090. intel_sdvo->is_tv = true;
  2091. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2092. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  2093. goto err;
  2094. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2095. goto err;
  2096. return true;
  2097. err:
  2098. intel_sdvo_destroy(connector);
  2099. return false;
  2100. }
  2101. static bool
  2102. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  2103. {
  2104. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2105. struct drm_connector *connector;
  2106. struct intel_connector *intel_connector;
  2107. struct intel_sdvo_connector *intel_sdvo_connector;
  2108. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2109. if (!intel_sdvo_connector)
  2110. return false;
  2111. intel_connector = &intel_sdvo_connector->base;
  2112. connector = &intel_connector->base;
  2113. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  2114. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  2115. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  2116. if (device == 0) {
  2117. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2118. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2119. } else if (device == 1) {
  2120. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2121. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2122. }
  2123. intel_sdvo_connector_init(intel_sdvo_connector,
  2124. intel_sdvo);
  2125. return true;
  2126. }
  2127. static bool
  2128. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2129. {
  2130. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2131. struct drm_connector *connector;
  2132. struct intel_connector *intel_connector;
  2133. struct intel_sdvo_connector *intel_sdvo_connector;
  2134. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2135. if (!intel_sdvo_connector)
  2136. return false;
  2137. intel_connector = &intel_sdvo_connector->base;
  2138. connector = &intel_connector->base;
  2139. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2140. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2141. if (device == 0) {
  2142. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2143. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2144. } else if (device == 1) {
  2145. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2146. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2147. }
  2148. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2149. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2150. goto err;
  2151. return true;
  2152. err:
  2153. intel_sdvo_destroy(connector);
  2154. return false;
  2155. }
  2156. static bool
  2157. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2158. {
  2159. intel_sdvo->is_tv = false;
  2160. intel_sdvo->is_lvds = false;
  2161. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2162. if (flags & SDVO_OUTPUT_TMDS0)
  2163. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2164. return false;
  2165. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2166. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2167. return false;
  2168. /* TV has no XXX1 function block */
  2169. if (flags & SDVO_OUTPUT_SVID0)
  2170. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2171. return false;
  2172. if (flags & SDVO_OUTPUT_CVBS0)
  2173. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2174. return false;
  2175. if (flags & SDVO_OUTPUT_YPRPB0)
  2176. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2177. return false;
  2178. if (flags & SDVO_OUTPUT_RGB0)
  2179. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2180. return false;
  2181. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2182. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2183. return false;
  2184. if (flags & SDVO_OUTPUT_LVDS0)
  2185. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2186. return false;
  2187. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2188. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2189. return false;
  2190. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2191. unsigned char bytes[2];
  2192. intel_sdvo->controlled_output = 0;
  2193. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2194. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2195. SDVO_NAME(intel_sdvo),
  2196. bytes[0], bytes[1]);
  2197. return false;
  2198. }
  2199. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2200. return true;
  2201. }
  2202. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2203. {
  2204. struct drm_device *dev = intel_sdvo->base.base.dev;
  2205. struct drm_connector *connector, *tmp;
  2206. list_for_each_entry_safe(connector, tmp,
  2207. &dev->mode_config.connector_list, head) {
  2208. if (intel_attached_encoder(connector) == &intel_sdvo->base)
  2209. intel_sdvo_destroy(connector);
  2210. }
  2211. }
  2212. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2213. struct intel_sdvo_connector *intel_sdvo_connector,
  2214. int type)
  2215. {
  2216. struct drm_device *dev = intel_sdvo->base.base.dev;
  2217. struct intel_sdvo_tv_format format;
  2218. uint32_t format_map, i;
  2219. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2220. return false;
  2221. BUILD_BUG_ON(sizeof(format) != 6);
  2222. if (!intel_sdvo_get_value(intel_sdvo,
  2223. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2224. &format, sizeof(format)))
  2225. return false;
  2226. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2227. if (format_map == 0)
  2228. return false;
  2229. intel_sdvo_connector->format_supported_num = 0;
  2230. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2231. if (format_map & (1 << i))
  2232. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2233. intel_sdvo_connector->tv_format =
  2234. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2235. "mode", intel_sdvo_connector->format_supported_num);
  2236. if (!intel_sdvo_connector->tv_format)
  2237. return false;
  2238. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2239. drm_property_add_enum(
  2240. intel_sdvo_connector->tv_format, i,
  2241. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2242. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2243. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2244. intel_sdvo_connector->tv_format, 0);
  2245. return true;
  2246. }
  2247. #define ENHANCEMENT(name, NAME) do { \
  2248. if (enhancements.name) { \
  2249. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2250. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2251. return false; \
  2252. intel_sdvo_connector->max_##name = data_value[0]; \
  2253. intel_sdvo_connector->cur_##name = response; \
  2254. intel_sdvo_connector->name = \
  2255. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2256. if (!intel_sdvo_connector->name) return false; \
  2257. drm_object_attach_property(&connector->base, \
  2258. intel_sdvo_connector->name, \
  2259. intel_sdvo_connector->cur_##name); \
  2260. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2261. data_value[0], data_value[1], response); \
  2262. } \
  2263. } while (0)
  2264. static bool
  2265. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2266. struct intel_sdvo_connector *intel_sdvo_connector,
  2267. struct intel_sdvo_enhancements_reply enhancements)
  2268. {
  2269. struct drm_device *dev = intel_sdvo->base.base.dev;
  2270. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2271. uint16_t response, data_value[2];
  2272. /* when horizontal overscan is supported, Add the left/right property */
  2273. if (enhancements.overscan_h) {
  2274. if (!intel_sdvo_get_value(intel_sdvo,
  2275. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2276. &data_value, 4))
  2277. return false;
  2278. if (!intel_sdvo_get_value(intel_sdvo,
  2279. SDVO_CMD_GET_OVERSCAN_H,
  2280. &response, 2))
  2281. return false;
  2282. intel_sdvo_connector->max_hscan = data_value[0];
  2283. intel_sdvo_connector->left_margin = data_value[0] - response;
  2284. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2285. intel_sdvo_connector->left =
  2286. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2287. if (!intel_sdvo_connector->left)
  2288. return false;
  2289. drm_object_attach_property(&connector->base,
  2290. intel_sdvo_connector->left,
  2291. intel_sdvo_connector->left_margin);
  2292. intel_sdvo_connector->right =
  2293. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2294. if (!intel_sdvo_connector->right)
  2295. return false;
  2296. drm_object_attach_property(&connector->base,
  2297. intel_sdvo_connector->right,
  2298. intel_sdvo_connector->right_margin);
  2299. DRM_DEBUG_KMS("h_overscan: max %d, "
  2300. "default %d, current %d\n",
  2301. data_value[0], data_value[1], response);
  2302. }
  2303. if (enhancements.overscan_v) {
  2304. if (!intel_sdvo_get_value(intel_sdvo,
  2305. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2306. &data_value, 4))
  2307. return false;
  2308. if (!intel_sdvo_get_value(intel_sdvo,
  2309. SDVO_CMD_GET_OVERSCAN_V,
  2310. &response, 2))
  2311. return false;
  2312. intel_sdvo_connector->max_vscan = data_value[0];
  2313. intel_sdvo_connector->top_margin = data_value[0] - response;
  2314. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2315. intel_sdvo_connector->top =
  2316. drm_property_create_range(dev, 0,
  2317. "top_margin", 0, data_value[0]);
  2318. if (!intel_sdvo_connector->top)
  2319. return false;
  2320. drm_object_attach_property(&connector->base,
  2321. intel_sdvo_connector->top,
  2322. intel_sdvo_connector->top_margin);
  2323. intel_sdvo_connector->bottom =
  2324. drm_property_create_range(dev, 0,
  2325. "bottom_margin", 0, data_value[0]);
  2326. if (!intel_sdvo_connector->bottom)
  2327. return false;
  2328. drm_object_attach_property(&connector->base,
  2329. intel_sdvo_connector->bottom,
  2330. intel_sdvo_connector->bottom_margin);
  2331. DRM_DEBUG_KMS("v_overscan: max %d, "
  2332. "default %d, current %d\n",
  2333. data_value[0], data_value[1], response);
  2334. }
  2335. ENHANCEMENT(hpos, HPOS);
  2336. ENHANCEMENT(vpos, VPOS);
  2337. ENHANCEMENT(saturation, SATURATION);
  2338. ENHANCEMENT(contrast, CONTRAST);
  2339. ENHANCEMENT(hue, HUE);
  2340. ENHANCEMENT(sharpness, SHARPNESS);
  2341. ENHANCEMENT(brightness, BRIGHTNESS);
  2342. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2343. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2344. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2345. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2346. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2347. if (enhancements.dot_crawl) {
  2348. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2349. return false;
  2350. intel_sdvo_connector->max_dot_crawl = 1;
  2351. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2352. intel_sdvo_connector->dot_crawl =
  2353. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2354. if (!intel_sdvo_connector->dot_crawl)
  2355. return false;
  2356. drm_object_attach_property(&connector->base,
  2357. intel_sdvo_connector->dot_crawl,
  2358. intel_sdvo_connector->cur_dot_crawl);
  2359. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2360. }
  2361. return true;
  2362. }
  2363. static bool
  2364. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2365. struct intel_sdvo_connector *intel_sdvo_connector,
  2366. struct intel_sdvo_enhancements_reply enhancements)
  2367. {
  2368. struct drm_device *dev = intel_sdvo->base.base.dev;
  2369. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2370. uint16_t response, data_value[2];
  2371. ENHANCEMENT(brightness, BRIGHTNESS);
  2372. return true;
  2373. }
  2374. #undef ENHANCEMENT
  2375. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2376. struct intel_sdvo_connector *intel_sdvo_connector)
  2377. {
  2378. union {
  2379. struct intel_sdvo_enhancements_reply reply;
  2380. uint16_t response;
  2381. } enhancements;
  2382. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2383. enhancements.response = 0;
  2384. intel_sdvo_get_value(intel_sdvo,
  2385. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2386. &enhancements, sizeof(enhancements));
  2387. if (enhancements.response == 0) {
  2388. DRM_DEBUG_KMS("No enhancement is supported\n");
  2389. return true;
  2390. }
  2391. if (IS_TV(intel_sdvo_connector))
  2392. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2393. else if (IS_LVDS(intel_sdvo_connector))
  2394. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2395. else
  2396. return true;
  2397. }
  2398. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2399. struct i2c_msg *msgs,
  2400. int num)
  2401. {
  2402. struct intel_sdvo *sdvo = adapter->algo_data;
  2403. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2404. return -EIO;
  2405. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2406. }
  2407. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2408. {
  2409. struct intel_sdvo *sdvo = adapter->algo_data;
  2410. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2411. }
  2412. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2413. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2414. .functionality = intel_sdvo_ddc_proxy_func
  2415. };
  2416. static bool
  2417. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2418. struct drm_device *dev)
  2419. {
  2420. sdvo->ddc.owner = THIS_MODULE;
  2421. sdvo->ddc.class = I2C_CLASS_DDC;
  2422. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2423. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2424. sdvo->ddc.algo_data = sdvo;
  2425. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2426. return i2c_add_adapter(&sdvo->ddc) == 0;
  2427. }
  2428. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2429. {
  2430. struct drm_i915_private *dev_priv = dev->dev_private;
  2431. struct intel_encoder *intel_encoder;
  2432. struct intel_sdvo *intel_sdvo;
  2433. int i;
  2434. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2435. if (!intel_sdvo)
  2436. return false;
  2437. intel_sdvo->sdvo_reg = sdvo_reg;
  2438. intel_sdvo->is_sdvob = is_sdvob;
  2439. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2440. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2441. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2442. goto err_i2c_bus;
  2443. /* encoder type will be decided later */
  2444. intel_encoder = &intel_sdvo->base;
  2445. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2446. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2447. /* Read the regs to test if we can talk to the device */
  2448. for (i = 0; i < 0x40; i++) {
  2449. u8 byte;
  2450. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2451. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2452. SDVO_NAME(intel_sdvo));
  2453. goto err;
  2454. }
  2455. }
  2456. intel_encoder->compute_config = intel_sdvo_compute_config;
  2457. intel_encoder->disable = intel_disable_sdvo;
  2458. intel_encoder->mode_set = intel_sdvo_mode_set;
  2459. intel_encoder->enable = intel_enable_sdvo;
  2460. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2461. intel_encoder->get_config = intel_sdvo_get_config;
  2462. /* In default case sdvo lvds is false */
  2463. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2464. goto err;
  2465. if (intel_sdvo_output_setup(intel_sdvo,
  2466. intel_sdvo->caps.output_flags) != true) {
  2467. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2468. SDVO_NAME(intel_sdvo));
  2469. /* Output_setup can leave behind connectors! */
  2470. goto err_output;
  2471. }
  2472. /* Only enable the hotplug irq if we need it, to work around noisy
  2473. * hotplug lines.
  2474. */
  2475. if (intel_sdvo->hotplug_active) {
  2476. intel_encoder->hpd_pin =
  2477. intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
  2478. }
  2479. /*
  2480. * Cloning SDVO with anything is often impossible, since the SDVO
  2481. * encoder can request a special input timing mode. And even if that's
  2482. * not the case we have evidence that cloning a plain unscaled mode with
  2483. * VGA doesn't really work. Furthermore the cloning flags are way too
  2484. * simplistic anyway to express such constraints, so just give up on
  2485. * cloning for SDVO encoders.
  2486. */
  2487. intel_sdvo->base.cloneable = false;
  2488. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2489. /* Set the input timing to the screen. Assume always input 0. */
  2490. if (!intel_sdvo_set_target_input(intel_sdvo))
  2491. goto err_output;
  2492. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2493. &intel_sdvo->pixel_clock_min,
  2494. &intel_sdvo->pixel_clock_max))
  2495. goto err_output;
  2496. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2497. "clock range %dMHz - %dMHz, "
  2498. "input 1: %c, input 2: %c, "
  2499. "output 1: %c, output 2: %c\n",
  2500. SDVO_NAME(intel_sdvo),
  2501. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2502. intel_sdvo->caps.device_rev_id,
  2503. intel_sdvo->pixel_clock_min / 1000,
  2504. intel_sdvo->pixel_clock_max / 1000,
  2505. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2506. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2507. /* check currently supported outputs */
  2508. intel_sdvo->caps.output_flags &
  2509. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2510. intel_sdvo->caps.output_flags &
  2511. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2512. return true;
  2513. err_output:
  2514. intel_sdvo_output_cleanup(intel_sdvo);
  2515. err:
  2516. drm_encoder_cleanup(&intel_encoder->base);
  2517. i2c_del_adapter(&intel_sdvo->ddc);
  2518. err_i2c_bus:
  2519. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2520. kfree(intel_sdvo);
  2521. return false;
  2522. }