intel_panel.c 20 KB

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  1. /*
  2. * Copyright © 2006-2010 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. * Chris Wilson <chris@chris-wilson.co.uk>
  29. */
  30. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31. #include <linux/moduleparam.h>
  32. #include "intel_drv.h"
  33. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  34. void
  35. intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
  36. struct drm_display_mode *adjusted_mode)
  37. {
  38. adjusted_mode->hdisplay = fixed_mode->hdisplay;
  39. adjusted_mode->hsync_start = fixed_mode->hsync_start;
  40. adjusted_mode->hsync_end = fixed_mode->hsync_end;
  41. adjusted_mode->htotal = fixed_mode->htotal;
  42. adjusted_mode->vdisplay = fixed_mode->vdisplay;
  43. adjusted_mode->vsync_start = fixed_mode->vsync_start;
  44. adjusted_mode->vsync_end = fixed_mode->vsync_end;
  45. adjusted_mode->vtotal = fixed_mode->vtotal;
  46. adjusted_mode->clock = fixed_mode->clock;
  47. }
  48. /* adjusted_mode has been preset to be the panel's fixed mode */
  49. void
  50. intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
  51. struct intel_crtc_config *pipe_config,
  52. int fitting_mode)
  53. {
  54. struct drm_display_mode *mode, *adjusted_mode;
  55. int x, y, width, height;
  56. mode = &pipe_config->requested_mode;
  57. adjusted_mode = &pipe_config->adjusted_mode;
  58. x = y = width = height = 0;
  59. /* Native modes don't need fitting */
  60. if (adjusted_mode->hdisplay == mode->hdisplay &&
  61. adjusted_mode->vdisplay == mode->vdisplay)
  62. goto done;
  63. switch (fitting_mode) {
  64. case DRM_MODE_SCALE_CENTER:
  65. width = mode->hdisplay;
  66. height = mode->vdisplay;
  67. x = (adjusted_mode->hdisplay - width + 1)/2;
  68. y = (adjusted_mode->vdisplay - height + 1)/2;
  69. break;
  70. case DRM_MODE_SCALE_ASPECT:
  71. /* Scale but preserve the aspect ratio */
  72. {
  73. u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
  74. u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
  75. if (scaled_width > scaled_height) { /* pillar */
  76. width = scaled_height / mode->vdisplay;
  77. if (width & 1)
  78. width++;
  79. x = (adjusted_mode->hdisplay - width + 1) / 2;
  80. y = 0;
  81. height = adjusted_mode->vdisplay;
  82. } else if (scaled_width < scaled_height) { /* letter */
  83. height = scaled_width / mode->hdisplay;
  84. if (height & 1)
  85. height++;
  86. y = (adjusted_mode->vdisplay - height + 1) / 2;
  87. x = 0;
  88. width = adjusted_mode->hdisplay;
  89. } else {
  90. x = y = 0;
  91. width = adjusted_mode->hdisplay;
  92. height = adjusted_mode->vdisplay;
  93. }
  94. }
  95. break;
  96. case DRM_MODE_SCALE_FULLSCREEN:
  97. x = y = 0;
  98. width = adjusted_mode->hdisplay;
  99. height = adjusted_mode->vdisplay;
  100. break;
  101. default:
  102. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  103. return;
  104. }
  105. done:
  106. pipe_config->pch_pfit.pos = (x << 16) | y;
  107. pipe_config->pch_pfit.size = (width << 16) | height;
  108. }
  109. static void
  110. centre_horizontally(struct drm_display_mode *mode,
  111. int width)
  112. {
  113. u32 border, sync_pos, blank_width, sync_width;
  114. /* keep the hsync and hblank widths constant */
  115. sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
  116. blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
  117. sync_pos = (blank_width - sync_width + 1) / 2;
  118. border = (mode->hdisplay - width + 1) / 2;
  119. border += border & 1; /* make the border even */
  120. mode->crtc_hdisplay = width;
  121. mode->crtc_hblank_start = width + border;
  122. mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
  123. mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
  124. mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
  125. }
  126. static void
  127. centre_vertically(struct drm_display_mode *mode,
  128. int height)
  129. {
  130. u32 border, sync_pos, blank_width, sync_width;
  131. /* keep the vsync and vblank widths constant */
  132. sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
  133. blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
  134. sync_pos = (blank_width - sync_width + 1) / 2;
  135. border = (mode->vdisplay - height + 1) / 2;
  136. mode->crtc_vdisplay = height;
  137. mode->crtc_vblank_start = height + border;
  138. mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
  139. mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
  140. mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
  141. }
  142. static inline u32 panel_fitter_scaling(u32 source, u32 target)
  143. {
  144. /*
  145. * Floating point operation is not supported. So the FACTOR
  146. * is defined, which can avoid the floating point computation
  147. * when calculating the panel ratio.
  148. */
  149. #define ACCURACY 12
  150. #define FACTOR (1 << ACCURACY)
  151. u32 ratio = source * FACTOR / target;
  152. return (FACTOR * ratio + FACTOR/2) / FACTOR;
  153. }
  154. void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
  155. struct intel_crtc_config *pipe_config,
  156. int fitting_mode)
  157. {
  158. struct drm_device *dev = intel_crtc->base.dev;
  159. u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
  160. struct drm_display_mode *mode, *adjusted_mode;
  161. mode = &pipe_config->requested_mode;
  162. adjusted_mode = &pipe_config->adjusted_mode;
  163. /* Native modes don't need fitting */
  164. if (adjusted_mode->hdisplay == mode->hdisplay &&
  165. adjusted_mode->vdisplay == mode->vdisplay)
  166. goto out;
  167. drm_mode_set_crtcinfo(adjusted_mode, 0);
  168. pipe_config->timings_set = true;
  169. switch (fitting_mode) {
  170. case DRM_MODE_SCALE_CENTER:
  171. /*
  172. * For centered modes, we have to calculate border widths &
  173. * heights and modify the values programmed into the CRTC.
  174. */
  175. centre_horizontally(adjusted_mode, mode->hdisplay);
  176. centre_vertically(adjusted_mode, mode->vdisplay);
  177. border = LVDS_BORDER_ENABLE;
  178. break;
  179. case DRM_MODE_SCALE_ASPECT:
  180. /* Scale but preserve the aspect ratio */
  181. if (INTEL_INFO(dev)->gen >= 4) {
  182. u32 scaled_width = adjusted_mode->hdisplay *
  183. mode->vdisplay;
  184. u32 scaled_height = mode->hdisplay *
  185. adjusted_mode->vdisplay;
  186. /* 965+ is easy, it does everything in hw */
  187. if (scaled_width > scaled_height)
  188. pfit_control |= PFIT_ENABLE |
  189. PFIT_SCALING_PILLAR;
  190. else if (scaled_width < scaled_height)
  191. pfit_control |= PFIT_ENABLE |
  192. PFIT_SCALING_LETTER;
  193. else if (adjusted_mode->hdisplay != mode->hdisplay)
  194. pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
  195. } else {
  196. u32 scaled_width = adjusted_mode->hdisplay *
  197. mode->vdisplay;
  198. u32 scaled_height = mode->hdisplay *
  199. adjusted_mode->vdisplay;
  200. /*
  201. * For earlier chips we have to calculate the scaling
  202. * ratio by hand and program it into the
  203. * PFIT_PGM_RATIO register
  204. */
  205. if (scaled_width > scaled_height) { /* pillar */
  206. centre_horizontally(adjusted_mode,
  207. scaled_height /
  208. mode->vdisplay);
  209. border = LVDS_BORDER_ENABLE;
  210. if (mode->vdisplay != adjusted_mode->vdisplay) {
  211. u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
  212. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  213. bits << PFIT_VERT_SCALE_SHIFT);
  214. pfit_control |= (PFIT_ENABLE |
  215. VERT_INTERP_BILINEAR |
  216. HORIZ_INTERP_BILINEAR);
  217. }
  218. } else if (scaled_width < scaled_height) { /* letter */
  219. centre_vertically(adjusted_mode,
  220. scaled_width /
  221. mode->hdisplay);
  222. border = LVDS_BORDER_ENABLE;
  223. if (mode->hdisplay != adjusted_mode->hdisplay) {
  224. u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
  225. pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  226. bits << PFIT_VERT_SCALE_SHIFT);
  227. pfit_control |= (PFIT_ENABLE |
  228. VERT_INTERP_BILINEAR |
  229. HORIZ_INTERP_BILINEAR);
  230. }
  231. } else {
  232. /* Aspects match, Let hw scale both directions */
  233. pfit_control |= (PFIT_ENABLE |
  234. VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  235. VERT_INTERP_BILINEAR |
  236. HORIZ_INTERP_BILINEAR);
  237. }
  238. }
  239. break;
  240. case DRM_MODE_SCALE_FULLSCREEN:
  241. /*
  242. * Full scaling, even if it changes the aspect ratio.
  243. * Fortunately this is all done for us in hw.
  244. */
  245. if (mode->vdisplay != adjusted_mode->vdisplay ||
  246. mode->hdisplay != adjusted_mode->hdisplay) {
  247. pfit_control |= PFIT_ENABLE;
  248. if (INTEL_INFO(dev)->gen >= 4)
  249. pfit_control |= PFIT_SCALING_AUTO;
  250. else
  251. pfit_control |= (VERT_AUTO_SCALE |
  252. VERT_INTERP_BILINEAR |
  253. HORIZ_AUTO_SCALE |
  254. HORIZ_INTERP_BILINEAR);
  255. }
  256. break;
  257. default:
  258. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  259. return;
  260. }
  261. /* 965+ wants fuzzy fitting */
  262. /* FIXME: handle multiple panels by failing gracefully */
  263. if (INTEL_INFO(dev)->gen >= 4)
  264. pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
  265. PFIT_FILTER_FUZZY);
  266. out:
  267. if ((pfit_control & PFIT_ENABLE) == 0) {
  268. pfit_control = 0;
  269. pfit_pgm_ratios = 0;
  270. }
  271. /* Make sure pre-965 set dither correctly for 18bpp panels. */
  272. if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
  273. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  274. pipe_config->gmch_pfit.control = pfit_control;
  275. pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
  276. pipe_config->gmch_pfit.lvds_border_bits = border;
  277. }
  278. static int is_backlight_combination_mode(struct drm_device *dev)
  279. {
  280. struct drm_i915_private *dev_priv = dev->dev_private;
  281. if (INTEL_INFO(dev)->gen >= 4)
  282. return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
  283. if (IS_GEN2(dev))
  284. return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
  285. return 0;
  286. }
  287. /* XXX: query mode clock or hardware clock and program max PWM appropriately
  288. * when it's 0.
  289. */
  290. static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
  291. {
  292. struct drm_i915_private *dev_priv = dev->dev_private;
  293. u32 val;
  294. WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
  295. /* Restore the CTL value if it lost, e.g. GPU reset */
  296. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  297. val = I915_READ(BLC_PWM_PCH_CTL2);
  298. if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
  299. dev_priv->regfile.saveBLC_PWM_CTL2 = val;
  300. } else if (val == 0) {
  301. val = dev_priv->regfile.saveBLC_PWM_CTL2;
  302. I915_WRITE(BLC_PWM_PCH_CTL2, val);
  303. }
  304. } else {
  305. val = I915_READ(BLC_PWM_CTL);
  306. if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
  307. dev_priv->regfile.saveBLC_PWM_CTL = val;
  308. if (INTEL_INFO(dev)->gen >= 4)
  309. dev_priv->regfile.saveBLC_PWM_CTL2 =
  310. I915_READ(BLC_PWM_CTL2);
  311. } else if (val == 0) {
  312. val = dev_priv->regfile.saveBLC_PWM_CTL;
  313. I915_WRITE(BLC_PWM_CTL, val);
  314. if (INTEL_INFO(dev)->gen >= 4)
  315. I915_WRITE(BLC_PWM_CTL2,
  316. dev_priv->regfile.saveBLC_PWM_CTL2);
  317. }
  318. }
  319. return val;
  320. }
  321. static u32 intel_panel_get_max_backlight(struct drm_device *dev)
  322. {
  323. u32 max;
  324. max = i915_read_blc_pwm_ctl(dev);
  325. if (HAS_PCH_SPLIT(dev)) {
  326. max >>= 16;
  327. } else {
  328. if (INTEL_INFO(dev)->gen < 4)
  329. max >>= 17;
  330. else
  331. max >>= 16;
  332. if (is_backlight_combination_mode(dev))
  333. max *= 0xff;
  334. }
  335. DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
  336. return max;
  337. }
  338. static int i915_panel_invert_brightness;
  339. MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
  340. "(-1 force normal, 0 machine defaults, 1 force inversion), please "
  341. "report PCI device ID, subsystem vendor and subsystem device ID "
  342. "to dri-devel@lists.freedesktop.org, if your machine needs it. "
  343. "It will then be included in an upcoming module version.");
  344. module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
  345. static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
  346. {
  347. struct drm_i915_private *dev_priv = dev->dev_private;
  348. if (i915_panel_invert_brightness < 0)
  349. return val;
  350. if (i915_panel_invert_brightness > 0 ||
  351. dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
  352. u32 max = intel_panel_get_max_backlight(dev);
  353. if (max)
  354. return max - val;
  355. }
  356. return val;
  357. }
  358. static u32 intel_panel_get_backlight(struct drm_device *dev)
  359. {
  360. struct drm_i915_private *dev_priv = dev->dev_private;
  361. u32 val;
  362. unsigned long flags;
  363. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  364. if (HAS_PCH_SPLIT(dev)) {
  365. val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  366. } else {
  367. val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  368. if (INTEL_INFO(dev)->gen < 4)
  369. val >>= 1;
  370. if (is_backlight_combination_mode(dev)) {
  371. u8 lbpc;
  372. pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
  373. val *= lbpc;
  374. }
  375. }
  376. val = intel_panel_compute_brightness(dev, val);
  377. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  378. DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
  379. return val;
  380. }
  381. static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
  382. {
  383. struct drm_i915_private *dev_priv = dev->dev_private;
  384. u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  385. I915_WRITE(BLC_PWM_CPU_CTL, val | level);
  386. }
  387. static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
  388. {
  389. struct drm_i915_private *dev_priv = dev->dev_private;
  390. u32 tmp;
  391. DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
  392. level = intel_panel_compute_brightness(dev, level);
  393. if (HAS_PCH_SPLIT(dev))
  394. return intel_pch_panel_set_backlight(dev, level);
  395. if (is_backlight_combination_mode(dev)) {
  396. u32 max = intel_panel_get_max_backlight(dev);
  397. u8 lbpc;
  398. /* we're screwed, but keep behaviour backwards compatible */
  399. if (!max)
  400. max = 1;
  401. lbpc = level * 0xfe / max + 1;
  402. level /= lbpc;
  403. pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
  404. }
  405. tmp = I915_READ(BLC_PWM_CTL);
  406. if (INTEL_INFO(dev)->gen < 4)
  407. level <<= 1;
  408. tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  409. I915_WRITE(BLC_PWM_CTL, tmp | level);
  410. }
  411. /* set backlight brightness to level in range [0..max] */
  412. void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
  413. {
  414. struct drm_i915_private *dev_priv = dev->dev_private;
  415. u32 freq;
  416. unsigned long flags;
  417. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  418. freq = intel_panel_get_max_backlight(dev);
  419. if (!freq) {
  420. /* we are screwed, bail out */
  421. goto out;
  422. }
  423. /* scale to hardware */
  424. level = level * freq / max;
  425. dev_priv->backlight.level = level;
  426. if (dev_priv->backlight.device)
  427. dev_priv->backlight.device->props.brightness = level;
  428. if (dev_priv->backlight.enabled)
  429. intel_panel_actually_set_backlight(dev, level);
  430. out:
  431. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  432. }
  433. void intel_panel_disable_backlight(struct drm_device *dev)
  434. {
  435. struct drm_i915_private *dev_priv = dev->dev_private;
  436. unsigned long flags;
  437. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  438. dev_priv->backlight.enabled = false;
  439. intel_panel_actually_set_backlight(dev, 0);
  440. if (INTEL_INFO(dev)->gen >= 4) {
  441. uint32_t reg, tmp;
  442. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  443. I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
  444. if (HAS_PCH_SPLIT(dev)) {
  445. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  446. tmp &= ~BLM_PCH_PWM_ENABLE;
  447. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  448. }
  449. }
  450. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  451. }
  452. void intel_panel_enable_backlight(struct drm_device *dev,
  453. enum pipe pipe)
  454. {
  455. struct drm_i915_private *dev_priv = dev->dev_private;
  456. enum transcoder cpu_transcoder =
  457. intel_pipe_to_cpu_transcoder(dev_priv, pipe);
  458. unsigned long flags;
  459. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  460. if (dev_priv->backlight.level == 0) {
  461. dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
  462. if (dev_priv->backlight.device)
  463. dev_priv->backlight.device->props.brightness =
  464. dev_priv->backlight.level;
  465. }
  466. if (INTEL_INFO(dev)->gen >= 4) {
  467. uint32_t reg, tmp;
  468. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  469. tmp = I915_READ(reg);
  470. /* Note that this can also get called through dpms changes. And
  471. * we don't track the backlight dpms state, hence check whether
  472. * we have to do anything first. */
  473. if (tmp & BLM_PWM_ENABLE)
  474. goto set_level;
  475. if (INTEL_INFO(dev)->num_pipes == 3)
  476. tmp &= ~BLM_PIPE_SELECT_IVB;
  477. else
  478. tmp &= ~BLM_PIPE_SELECT;
  479. if (cpu_transcoder == TRANSCODER_EDP)
  480. tmp |= BLM_TRANSCODER_EDP;
  481. else
  482. tmp |= BLM_PIPE(cpu_transcoder);
  483. tmp &= ~BLM_PWM_ENABLE;
  484. I915_WRITE(reg, tmp);
  485. POSTING_READ(reg);
  486. I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
  487. if (HAS_PCH_SPLIT(dev) &&
  488. !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
  489. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  490. tmp |= BLM_PCH_PWM_ENABLE;
  491. tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
  492. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  493. }
  494. }
  495. set_level:
  496. /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
  497. * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
  498. * registers are set.
  499. */
  500. dev_priv->backlight.enabled = true;
  501. intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
  502. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  503. }
  504. static void intel_panel_init_backlight(struct drm_device *dev)
  505. {
  506. struct drm_i915_private *dev_priv = dev->dev_private;
  507. dev_priv->backlight.level = intel_panel_get_backlight(dev);
  508. dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
  509. }
  510. enum drm_connector_status
  511. intel_panel_detect(struct drm_device *dev)
  512. {
  513. struct drm_i915_private *dev_priv = dev->dev_private;
  514. /* Assume that the BIOS does not lie through the OpRegion... */
  515. if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
  516. return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
  517. connector_status_connected :
  518. connector_status_disconnected;
  519. }
  520. switch (i915_panel_ignore_lid) {
  521. case -2:
  522. return connector_status_connected;
  523. case -1:
  524. return connector_status_disconnected;
  525. default:
  526. return connector_status_unknown;
  527. }
  528. }
  529. #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
  530. static int intel_panel_update_status(struct backlight_device *bd)
  531. {
  532. struct drm_device *dev = bl_get_data(bd);
  533. intel_panel_set_backlight(dev, bd->props.brightness,
  534. bd->props.max_brightness);
  535. return 0;
  536. }
  537. static int intel_panel_get_brightness(struct backlight_device *bd)
  538. {
  539. struct drm_device *dev = bl_get_data(bd);
  540. return intel_panel_get_backlight(dev);
  541. }
  542. static const struct backlight_ops intel_panel_bl_ops = {
  543. .update_status = intel_panel_update_status,
  544. .get_brightness = intel_panel_get_brightness,
  545. };
  546. int intel_panel_setup_backlight(struct drm_connector *connector)
  547. {
  548. struct drm_device *dev = connector->dev;
  549. struct drm_i915_private *dev_priv = dev->dev_private;
  550. struct backlight_properties props;
  551. unsigned long flags;
  552. intel_panel_init_backlight(dev);
  553. if (WARN_ON(dev_priv->backlight.device))
  554. return -ENODEV;
  555. memset(&props, 0, sizeof(props));
  556. props.type = BACKLIGHT_RAW;
  557. props.brightness = dev_priv->backlight.level;
  558. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  559. props.max_brightness = intel_panel_get_max_backlight(dev);
  560. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  561. if (props.max_brightness == 0) {
  562. DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
  563. return -ENODEV;
  564. }
  565. dev_priv->backlight.device =
  566. backlight_device_register("intel_backlight",
  567. &connector->kdev, dev,
  568. &intel_panel_bl_ops, &props);
  569. if (IS_ERR(dev_priv->backlight.device)) {
  570. DRM_ERROR("Failed to register backlight: %ld\n",
  571. PTR_ERR(dev_priv->backlight.device));
  572. dev_priv->backlight.device = NULL;
  573. return -ENODEV;
  574. }
  575. return 0;
  576. }
  577. void intel_panel_destroy_backlight(struct drm_device *dev)
  578. {
  579. struct drm_i915_private *dev_priv = dev->dev_private;
  580. if (dev_priv->backlight.device) {
  581. backlight_device_unregister(dev_priv->backlight.device);
  582. dev_priv->backlight.device = NULL;
  583. }
  584. }
  585. #else
  586. int intel_panel_setup_backlight(struct drm_connector *connector)
  587. {
  588. intel_panel_init_backlight(connector->dev);
  589. return 0;
  590. }
  591. void intel_panel_destroy_backlight(struct drm_device *dev)
  592. {
  593. return;
  594. }
  595. #endif
  596. int intel_panel_init(struct intel_panel *panel,
  597. struct drm_display_mode *fixed_mode)
  598. {
  599. panel->fixed_mode = fixed_mode;
  600. return 0;
  601. }
  602. void intel_panel_fini(struct intel_panel *panel)
  603. {
  604. struct intel_connector *intel_connector =
  605. container_of(panel, struct intel_connector, panel);
  606. if (panel->fixed_mode)
  607. drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
  608. }