intel_hdmi.c 36 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2009 Intel Corporation
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Jesse Barnes <jesse.barnes@intel.com>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <drm/drmP.h>
  32. #include <drm/drm_crtc.h>
  33. #include <drm/drm_edid.h>
  34. #include "intel_drv.h"
  35. #include <drm/i915_drm.h>
  36. #include "i915_drv.h"
  37. static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  38. {
  39. return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  40. }
  41. static void
  42. assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  43. {
  44. struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  45. struct drm_i915_private *dev_priv = dev->dev_private;
  46. uint32_t enabled_bits;
  47. enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  48. WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  49. "HDMI port enabled, expecting disabled\n");
  50. }
  51. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  52. {
  53. struct intel_digital_port *intel_dig_port =
  54. container_of(encoder, struct intel_digital_port, base.base);
  55. return &intel_dig_port->hdmi;
  56. }
  57. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  58. {
  59. return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  60. }
  61. void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  62. {
  63. uint8_t *data = (uint8_t *)frame;
  64. uint8_t sum = 0;
  65. unsigned i;
  66. frame->checksum = 0;
  67. frame->ecc = 0;
  68. for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  69. sum += data[i];
  70. frame->checksum = 0x100 - sum;
  71. }
  72. static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  73. {
  74. switch (frame->type) {
  75. case DIP_TYPE_AVI:
  76. return VIDEO_DIP_SELECT_AVI;
  77. case DIP_TYPE_SPD:
  78. return VIDEO_DIP_SELECT_SPD;
  79. default:
  80. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  81. return 0;
  82. }
  83. }
  84. static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  85. {
  86. switch (frame->type) {
  87. case DIP_TYPE_AVI:
  88. return VIDEO_DIP_ENABLE_AVI;
  89. case DIP_TYPE_SPD:
  90. return VIDEO_DIP_ENABLE_SPD;
  91. default:
  92. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  93. return 0;
  94. }
  95. }
  96. static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
  97. {
  98. switch (frame->type) {
  99. case DIP_TYPE_AVI:
  100. return VIDEO_DIP_ENABLE_AVI_HSW;
  101. case DIP_TYPE_SPD:
  102. return VIDEO_DIP_ENABLE_SPD_HSW;
  103. default:
  104. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  105. return 0;
  106. }
  107. }
  108. static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
  109. enum transcoder cpu_transcoder)
  110. {
  111. switch (frame->type) {
  112. case DIP_TYPE_AVI:
  113. return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
  114. case DIP_TYPE_SPD:
  115. return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
  116. default:
  117. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  118. return 0;
  119. }
  120. }
  121. static void g4x_write_infoframe(struct drm_encoder *encoder,
  122. struct dip_infoframe *frame)
  123. {
  124. uint32_t *data = (uint32_t *)frame;
  125. struct drm_device *dev = encoder->dev;
  126. struct drm_i915_private *dev_priv = dev->dev_private;
  127. u32 val = I915_READ(VIDEO_DIP_CTL);
  128. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  129. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  130. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  131. val |= g4x_infoframe_index(frame);
  132. val &= ~g4x_infoframe_enable(frame);
  133. I915_WRITE(VIDEO_DIP_CTL, val);
  134. mmiowb();
  135. for (i = 0; i < len; i += 4) {
  136. I915_WRITE(VIDEO_DIP_DATA, *data);
  137. data++;
  138. }
  139. /* Write every possible data byte to force correct ECC calculation. */
  140. for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  141. I915_WRITE(VIDEO_DIP_DATA, 0);
  142. mmiowb();
  143. val |= g4x_infoframe_enable(frame);
  144. val &= ~VIDEO_DIP_FREQ_MASK;
  145. val |= VIDEO_DIP_FREQ_VSYNC;
  146. I915_WRITE(VIDEO_DIP_CTL, val);
  147. POSTING_READ(VIDEO_DIP_CTL);
  148. }
  149. static void ibx_write_infoframe(struct drm_encoder *encoder,
  150. struct dip_infoframe *frame)
  151. {
  152. uint32_t *data = (uint32_t *)frame;
  153. struct drm_device *dev = encoder->dev;
  154. struct drm_i915_private *dev_priv = dev->dev_private;
  155. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  156. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  157. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  158. u32 val = I915_READ(reg);
  159. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  160. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  161. val |= g4x_infoframe_index(frame);
  162. val &= ~g4x_infoframe_enable(frame);
  163. I915_WRITE(reg, val);
  164. mmiowb();
  165. for (i = 0; i < len; i += 4) {
  166. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  167. data++;
  168. }
  169. /* Write every possible data byte to force correct ECC calculation. */
  170. for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  171. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  172. mmiowb();
  173. val |= g4x_infoframe_enable(frame);
  174. val &= ~VIDEO_DIP_FREQ_MASK;
  175. val |= VIDEO_DIP_FREQ_VSYNC;
  176. I915_WRITE(reg, val);
  177. POSTING_READ(reg);
  178. }
  179. static void cpt_write_infoframe(struct drm_encoder *encoder,
  180. struct dip_infoframe *frame)
  181. {
  182. uint32_t *data = (uint32_t *)frame;
  183. struct drm_device *dev = encoder->dev;
  184. struct drm_i915_private *dev_priv = dev->dev_private;
  185. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  186. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  187. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  188. u32 val = I915_READ(reg);
  189. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  190. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  191. val |= g4x_infoframe_index(frame);
  192. /* The DIP control register spec says that we need to update the AVI
  193. * infoframe without clearing its enable bit */
  194. if (frame->type != DIP_TYPE_AVI)
  195. val &= ~g4x_infoframe_enable(frame);
  196. I915_WRITE(reg, val);
  197. mmiowb();
  198. for (i = 0; i < len; i += 4) {
  199. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  200. data++;
  201. }
  202. /* Write every possible data byte to force correct ECC calculation. */
  203. for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  204. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  205. mmiowb();
  206. val |= g4x_infoframe_enable(frame);
  207. val &= ~VIDEO_DIP_FREQ_MASK;
  208. val |= VIDEO_DIP_FREQ_VSYNC;
  209. I915_WRITE(reg, val);
  210. POSTING_READ(reg);
  211. }
  212. static void vlv_write_infoframe(struct drm_encoder *encoder,
  213. struct dip_infoframe *frame)
  214. {
  215. uint32_t *data = (uint32_t *)frame;
  216. struct drm_device *dev = encoder->dev;
  217. struct drm_i915_private *dev_priv = dev->dev_private;
  218. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  219. int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  220. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  221. u32 val = I915_READ(reg);
  222. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  223. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  224. val |= g4x_infoframe_index(frame);
  225. val &= ~g4x_infoframe_enable(frame);
  226. I915_WRITE(reg, val);
  227. mmiowb();
  228. for (i = 0; i < len; i += 4) {
  229. I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  230. data++;
  231. }
  232. /* Write every possible data byte to force correct ECC calculation. */
  233. for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  234. I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
  235. mmiowb();
  236. val |= g4x_infoframe_enable(frame);
  237. val &= ~VIDEO_DIP_FREQ_MASK;
  238. val |= VIDEO_DIP_FREQ_VSYNC;
  239. I915_WRITE(reg, val);
  240. POSTING_READ(reg);
  241. }
  242. static void hsw_write_infoframe(struct drm_encoder *encoder,
  243. struct dip_infoframe *frame)
  244. {
  245. uint32_t *data = (uint32_t *)frame;
  246. struct drm_device *dev = encoder->dev;
  247. struct drm_i915_private *dev_priv = dev->dev_private;
  248. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  249. u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
  250. u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
  251. unsigned int i, len = DIP_HEADER_SIZE + frame->len;
  252. u32 val = I915_READ(ctl_reg);
  253. if (data_reg == 0)
  254. return;
  255. val &= ~hsw_infoframe_enable(frame);
  256. I915_WRITE(ctl_reg, val);
  257. mmiowb();
  258. for (i = 0; i < len; i += 4) {
  259. I915_WRITE(data_reg + i, *data);
  260. data++;
  261. }
  262. /* Write every possible data byte to force correct ECC calculation. */
  263. for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  264. I915_WRITE(data_reg + i, 0);
  265. mmiowb();
  266. val |= hsw_infoframe_enable(frame);
  267. I915_WRITE(ctl_reg, val);
  268. POSTING_READ(ctl_reg);
  269. }
  270. static void intel_set_infoframe(struct drm_encoder *encoder,
  271. struct dip_infoframe *frame)
  272. {
  273. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  274. intel_dip_infoframe_csum(frame);
  275. intel_hdmi->write_infoframe(encoder, frame);
  276. }
  277. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  278. struct drm_display_mode *adjusted_mode)
  279. {
  280. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  281. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  282. struct dip_infoframe avi_if = {
  283. .type = DIP_TYPE_AVI,
  284. .ver = DIP_VERSION_AVI,
  285. .len = DIP_LEN_AVI,
  286. };
  287. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  288. avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
  289. if (intel_hdmi->rgb_quant_range_selectable) {
  290. if (intel_crtc->config.limited_color_range)
  291. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
  292. else
  293. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
  294. }
  295. avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
  296. intel_set_infoframe(encoder, &avi_if);
  297. }
  298. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  299. {
  300. struct dip_infoframe spd_if;
  301. memset(&spd_if, 0, sizeof(spd_if));
  302. spd_if.type = DIP_TYPE_SPD;
  303. spd_if.ver = DIP_VERSION_SPD;
  304. spd_if.len = DIP_LEN_SPD;
  305. strcpy(spd_if.body.spd.vn, "Intel");
  306. strcpy(spd_if.body.spd.pd, "Integrated gfx");
  307. spd_if.body.spd.sdi = DIP_SPD_PC;
  308. intel_set_infoframe(encoder, &spd_if);
  309. }
  310. static void g4x_set_infoframes(struct drm_encoder *encoder,
  311. struct drm_display_mode *adjusted_mode)
  312. {
  313. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  314. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  315. struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  316. u32 reg = VIDEO_DIP_CTL;
  317. u32 val = I915_READ(reg);
  318. u32 port;
  319. assert_hdmi_port_disabled(intel_hdmi);
  320. /* If the registers were not initialized yet, they might be zeroes,
  321. * which means we're selecting the AVI DIP and we're setting its
  322. * frequency to once. This seems to really confuse the HW and make
  323. * things stop working (the register spec says the AVI always needs to
  324. * be sent every VSync). So here we avoid writing to the register more
  325. * than we need and also explicitly select the AVI DIP and explicitly
  326. * set its frequency to every VSync. Avoiding to write it twice seems to
  327. * be enough to solve the problem, but being defensive shouldn't hurt us
  328. * either. */
  329. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  330. if (!intel_hdmi->has_hdmi_sink) {
  331. if (!(val & VIDEO_DIP_ENABLE))
  332. return;
  333. val &= ~VIDEO_DIP_ENABLE;
  334. I915_WRITE(reg, val);
  335. POSTING_READ(reg);
  336. return;
  337. }
  338. switch (intel_dig_port->port) {
  339. case PORT_B:
  340. port = VIDEO_DIP_PORT_B;
  341. break;
  342. case PORT_C:
  343. port = VIDEO_DIP_PORT_C;
  344. break;
  345. default:
  346. BUG();
  347. return;
  348. }
  349. if (port != (val & VIDEO_DIP_PORT_MASK)) {
  350. if (val & VIDEO_DIP_ENABLE) {
  351. val &= ~VIDEO_DIP_ENABLE;
  352. I915_WRITE(reg, val);
  353. POSTING_READ(reg);
  354. }
  355. val &= ~VIDEO_DIP_PORT_MASK;
  356. val |= port;
  357. }
  358. val |= VIDEO_DIP_ENABLE;
  359. val &= ~VIDEO_DIP_ENABLE_VENDOR;
  360. I915_WRITE(reg, val);
  361. POSTING_READ(reg);
  362. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  363. intel_hdmi_set_spd_infoframe(encoder);
  364. }
  365. static void ibx_set_infoframes(struct drm_encoder *encoder,
  366. struct drm_display_mode *adjusted_mode)
  367. {
  368. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  369. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  370. struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
  371. struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  372. u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  373. u32 val = I915_READ(reg);
  374. u32 port;
  375. assert_hdmi_port_disabled(intel_hdmi);
  376. /* See the big comment in g4x_set_infoframes() */
  377. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  378. if (!intel_hdmi->has_hdmi_sink) {
  379. if (!(val & VIDEO_DIP_ENABLE))
  380. return;
  381. val &= ~VIDEO_DIP_ENABLE;
  382. I915_WRITE(reg, val);
  383. POSTING_READ(reg);
  384. return;
  385. }
  386. switch (intel_dig_port->port) {
  387. case PORT_B:
  388. port = VIDEO_DIP_PORT_B;
  389. break;
  390. case PORT_C:
  391. port = VIDEO_DIP_PORT_C;
  392. break;
  393. case PORT_D:
  394. port = VIDEO_DIP_PORT_D;
  395. break;
  396. default:
  397. BUG();
  398. return;
  399. }
  400. if (port != (val & VIDEO_DIP_PORT_MASK)) {
  401. if (val & VIDEO_DIP_ENABLE) {
  402. val &= ~VIDEO_DIP_ENABLE;
  403. I915_WRITE(reg, val);
  404. POSTING_READ(reg);
  405. }
  406. val &= ~VIDEO_DIP_PORT_MASK;
  407. val |= port;
  408. }
  409. val |= VIDEO_DIP_ENABLE;
  410. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  411. VIDEO_DIP_ENABLE_GCP);
  412. I915_WRITE(reg, val);
  413. POSTING_READ(reg);
  414. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  415. intel_hdmi_set_spd_infoframe(encoder);
  416. }
  417. static void cpt_set_infoframes(struct drm_encoder *encoder,
  418. struct drm_display_mode *adjusted_mode)
  419. {
  420. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  421. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  422. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  423. u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  424. u32 val = I915_READ(reg);
  425. assert_hdmi_port_disabled(intel_hdmi);
  426. /* See the big comment in g4x_set_infoframes() */
  427. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  428. if (!intel_hdmi->has_hdmi_sink) {
  429. if (!(val & VIDEO_DIP_ENABLE))
  430. return;
  431. val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
  432. I915_WRITE(reg, val);
  433. POSTING_READ(reg);
  434. return;
  435. }
  436. /* Set both together, unset both together: see the spec. */
  437. val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  438. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  439. VIDEO_DIP_ENABLE_GCP);
  440. I915_WRITE(reg, val);
  441. POSTING_READ(reg);
  442. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  443. intel_hdmi_set_spd_infoframe(encoder);
  444. }
  445. static void vlv_set_infoframes(struct drm_encoder *encoder,
  446. struct drm_display_mode *adjusted_mode)
  447. {
  448. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  449. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  450. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  451. u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  452. u32 val = I915_READ(reg);
  453. assert_hdmi_port_disabled(intel_hdmi);
  454. /* See the big comment in g4x_set_infoframes() */
  455. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  456. if (!intel_hdmi->has_hdmi_sink) {
  457. if (!(val & VIDEO_DIP_ENABLE))
  458. return;
  459. val &= ~VIDEO_DIP_ENABLE;
  460. I915_WRITE(reg, val);
  461. POSTING_READ(reg);
  462. return;
  463. }
  464. val |= VIDEO_DIP_ENABLE;
  465. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  466. VIDEO_DIP_ENABLE_GCP);
  467. I915_WRITE(reg, val);
  468. POSTING_READ(reg);
  469. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  470. intel_hdmi_set_spd_infoframe(encoder);
  471. }
  472. static void hsw_set_infoframes(struct drm_encoder *encoder,
  473. struct drm_display_mode *adjusted_mode)
  474. {
  475. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  476. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  477. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  478. u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
  479. u32 val = I915_READ(reg);
  480. assert_hdmi_port_disabled(intel_hdmi);
  481. if (!intel_hdmi->has_hdmi_sink) {
  482. I915_WRITE(reg, 0);
  483. POSTING_READ(reg);
  484. return;
  485. }
  486. val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
  487. VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
  488. I915_WRITE(reg, val);
  489. POSTING_READ(reg);
  490. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  491. intel_hdmi_set_spd_infoframe(encoder);
  492. }
  493. static void intel_hdmi_mode_set(struct drm_encoder *encoder,
  494. struct drm_display_mode *mode,
  495. struct drm_display_mode *adjusted_mode)
  496. {
  497. struct drm_device *dev = encoder->dev;
  498. struct drm_i915_private *dev_priv = dev->dev_private;
  499. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  500. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  501. u32 hdmi_val;
  502. hdmi_val = SDVO_ENCODING_HDMI;
  503. if (!HAS_PCH_SPLIT(dev))
  504. hdmi_val |= intel_hdmi->color_range;
  505. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  506. hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
  507. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  508. hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
  509. if (intel_crtc->config.pipe_bpp > 24)
  510. hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
  511. else
  512. hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
  513. /* Required on CPT */
  514. if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  515. hdmi_val |= HDMI_MODE_SELECT_HDMI;
  516. if (intel_hdmi->has_audio) {
  517. DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  518. pipe_name(intel_crtc->pipe));
  519. hdmi_val |= SDVO_AUDIO_ENABLE;
  520. hdmi_val |= HDMI_MODE_SELECT_HDMI;
  521. intel_write_eld(encoder, adjusted_mode);
  522. }
  523. if (HAS_PCH_CPT(dev))
  524. hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
  525. else
  526. hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe);
  527. I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
  528. POSTING_READ(intel_hdmi->hdmi_reg);
  529. intel_hdmi->set_infoframes(encoder, adjusted_mode);
  530. }
  531. static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  532. enum pipe *pipe)
  533. {
  534. struct drm_device *dev = encoder->base.dev;
  535. struct drm_i915_private *dev_priv = dev->dev_private;
  536. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  537. u32 tmp;
  538. tmp = I915_READ(intel_hdmi->hdmi_reg);
  539. if (!(tmp & SDVO_ENABLE))
  540. return false;
  541. if (HAS_PCH_CPT(dev))
  542. *pipe = PORT_TO_PIPE_CPT(tmp);
  543. else
  544. *pipe = PORT_TO_PIPE(tmp);
  545. return true;
  546. }
  547. static void intel_hdmi_get_config(struct intel_encoder *encoder,
  548. struct intel_crtc_config *pipe_config)
  549. {
  550. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  551. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  552. u32 tmp, flags = 0;
  553. tmp = I915_READ(intel_hdmi->hdmi_reg);
  554. if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
  555. flags |= DRM_MODE_FLAG_PHSYNC;
  556. else
  557. flags |= DRM_MODE_FLAG_NHSYNC;
  558. if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
  559. flags |= DRM_MODE_FLAG_PVSYNC;
  560. else
  561. flags |= DRM_MODE_FLAG_NVSYNC;
  562. pipe_config->adjusted_mode.flags |= flags;
  563. }
  564. static void intel_enable_hdmi(struct intel_encoder *encoder)
  565. {
  566. struct drm_device *dev = encoder->base.dev;
  567. struct drm_i915_private *dev_priv = dev->dev_private;
  568. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  569. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  570. u32 temp;
  571. u32 enable_bits = SDVO_ENABLE;
  572. if (intel_hdmi->has_audio)
  573. enable_bits |= SDVO_AUDIO_ENABLE;
  574. temp = I915_READ(intel_hdmi->hdmi_reg);
  575. /* HW workaround for IBX, we need to move the port to transcoder A
  576. * before disabling it, so restore the transcoder select bit here. */
  577. if (HAS_PCH_IBX(dev))
  578. enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
  579. /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  580. * we do this anyway which shows more stable in testing.
  581. */
  582. if (HAS_PCH_SPLIT(dev)) {
  583. I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
  584. POSTING_READ(intel_hdmi->hdmi_reg);
  585. }
  586. temp |= enable_bits;
  587. I915_WRITE(intel_hdmi->hdmi_reg, temp);
  588. POSTING_READ(intel_hdmi->hdmi_reg);
  589. /* HW workaround, need to write this twice for issue that may result
  590. * in first write getting masked.
  591. */
  592. if (HAS_PCH_SPLIT(dev)) {
  593. I915_WRITE(intel_hdmi->hdmi_reg, temp);
  594. POSTING_READ(intel_hdmi->hdmi_reg);
  595. }
  596. if (IS_VALLEYVIEW(dev)) {
  597. struct intel_digital_port *dport =
  598. enc_to_dig_port(&encoder->base);
  599. int channel = vlv_dport_to_channel(dport);
  600. vlv_wait_port_ready(dev_priv, channel);
  601. }
  602. }
  603. static void intel_disable_hdmi(struct intel_encoder *encoder)
  604. {
  605. struct drm_device *dev = encoder->base.dev;
  606. struct drm_i915_private *dev_priv = dev->dev_private;
  607. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  608. u32 temp;
  609. u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
  610. temp = I915_READ(intel_hdmi->hdmi_reg);
  611. /* HW workaround for IBX, we need to move the port to transcoder A
  612. * before disabling it. */
  613. if (HAS_PCH_IBX(dev)) {
  614. struct drm_crtc *crtc = encoder->base.crtc;
  615. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  616. if (temp & SDVO_PIPE_B_SELECT) {
  617. temp &= ~SDVO_PIPE_B_SELECT;
  618. I915_WRITE(intel_hdmi->hdmi_reg, temp);
  619. POSTING_READ(intel_hdmi->hdmi_reg);
  620. /* Again we need to write this twice. */
  621. I915_WRITE(intel_hdmi->hdmi_reg, temp);
  622. POSTING_READ(intel_hdmi->hdmi_reg);
  623. /* Transcoder selection bits only update
  624. * effectively on vblank. */
  625. if (crtc)
  626. intel_wait_for_vblank(dev, pipe);
  627. else
  628. msleep(50);
  629. }
  630. }
  631. /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  632. * we do this anyway which shows more stable in testing.
  633. */
  634. if (HAS_PCH_SPLIT(dev)) {
  635. I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
  636. POSTING_READ(intel_hdmi->hdmi_reg);
  637. }
  638. temp &= ~enable_bits;
  639. I915_WRITE(intel_hdmi->hdmi_reg, temp);
  640. POSTING_READ(intel_hdmi->hdmi_reg);
  641. /* HW workaround, need to write this twice for issue that may result
  642. * in first write getting masked.
  643. */
  644. if (HAS_PCH_SPLIT(dev)) {
  645. I915_WRITE(intel_hdmi->hdmi_reg, temp);
  646. POSTING_READ(intel_hdmi->hdmi_reg);
  647. }
  648. }
  649. static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
  650. {
  651. struct drm_device *dev = intel_hdmi_to_dev(hdmi);
  652. if (IS_G4X(dev))
  653. return 165000;
  654. else if (IS_HASWELL(dev))
  655. return 300000;
  656. else
  657. return 225000;
  658. }
  659. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  660. struct drm_display_mode *mode)
  661. {
  662. if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
  663. return MODE_CLOCK_HIGH;
  664. if (mode->clock < 20000)
  665. return MODE_CLOCK_LOW;
  666. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  667. return MODE_NO_DBLESCAN;
  668. return MODE_OK;
  669. }
  670. bool intel_hdmi_compute_config(struct intel_encoder *encoder,
  671. struct intel_crtc_config *pipe_config)
  672. {
  673. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  674. struct drm_device *dev = encoder->base.dev;
  675. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  676. int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
  677. int portclock_limit = hdmi_portclock_limit(intel_hdmi);
  678. int desired_bpp;
  679. if (intel_hdmi->color_range_auto) {
  680. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  681. if (intel_hdmi->has_hdmi_sink &&
  682. drm_match_cea_mode(adjusted_mode) > 1)
  683. intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
  684. else
  685. intel_hdmi->color_range = 0;
  686. }
  687. if (intel_hdmi->color_range)
  688. pipe_config->limited_color_range = true;
  689. if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
  690. pipe_config->has_pch_encoder = true;
  691. /*
  692. * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  693. * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
  694. * outputs. We also need to check that the higher clock still fits
  695. * within limits.
  696. */
  697. if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
  698. && HAS_PCH_SPLIT(dev)) {
  699. DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
  700. desired_bpp = 12*3;
  701. /* Need to adjust the port link by 1.5x for 12bpc. */
  702. pipe_config->port_clock = clock_12bpc;
  703. } else {
  704. DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
  705. desired_bpp = 8*3;
  706. }
  707. if (!pipe_config->bw_constrained) {
  708. DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
  709. pipe_config->pipe_bpp = desired_bpp;
  710. }
  711. if (adjusted_mode->clock > portclock_limit) {
  712. DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
  713. return false;
  714. }
  715. return true;
  716. }
  717. static enum drm_connector_status
  718. intel_hdmi_detect(struct drm_connector *connector, bool force)
  719. {
  720. struct drm_device *dev = connector->dev;
  721. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  722. struct intel_digital_port *intel_dig_port =
  723. hdmi_to_dig_port(intel_hdmi);
  724. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  725. struct drm_i915_private *dev_priv = dev->dev_private;
  726. struct edid *edid;
  727. enum drm_connector_status status = connector_status_disconnected;
  728. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  729. connector->base.id, drm_get_connector_name(connector));
  730. intel_hdmi->has_hdmi_sink = false;
  731. intel_hdmi->has_audio = false;
  732. intel_hdmi->rgb_quant_range_selectable = false;
  733. edid = drm_get_edid(connector,
  734. intel_gmbus_get_adapter(dev_priv,
  735. intel_hdmi->ddc_bus));
  736. if (edid) {
  737. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  738. status = connector_status_connected;
  739. if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  740. intel_hdmi->has_hdmi_sink =
  741. drm_detect_hdmi_monitor(edid);
  742. intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  743. intel_hdmi->rgb_quant_range_selectable =
  744. drm_rgb_quant_range_selectable(edid);
  745. }
  746. kfree(edid);
  747. }
  748. if (status == connector_status_connected) {
  749. if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  750. intel_hdmi->has_audio =
  751. (intel_hdmi->force_audio == HDMI_AUDIO_ON);
  752. intel_encoder->type = INTEL_OUTPUT_HDMI;
  753. }
  754. return status;
  755. }
  756. static int intel_hdmi_get_modes(struct drm_connector *connector)
  757. {
  758. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  759. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  760. /* We should parse the EDID data and find out if it's an HDMI sink so
  761. * we can send audio to it.
  762. */
  763. return intel_ddc_get_modes(connector,
  764. intel_gmbus_get_adapter(dev_priv,
  765. intel_hdmi->ddc_bus));
  766. }
  767. static bool
  768. intel_hdmi_detect_audio(struct drm_connector *connector)
  769. {
  770. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  771. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  772. struct edid *edid;
  773. bool has_audio = false;
  774. edid = drm_get_edid(connector,
  775. intel_gmbus_get_adapter(dev_priv,
  776. intel_hdmi->ddc_bus));
  777. if (edid) {
  778. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  779. has_audio = drm_detect_monitor_audio(edid);
  780. kfree(edid);
  781. }
  782. return has_audio;
  783. }
  784. static int
  785. intel_hdmi_set_property(struct drm_connector *connector,
  786. struct drm_property *property,
  787. uint64_t val)
  788. {
  789. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  790. struct intel_digital_port *intel_dig_port =
  791. hdmi_to_dig_port(intel_hdmi);
  792. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  793. int ret;
  794. ret = drm_object_property_set_value(&connector->base, property, val);
  795. if (ret)
  796. return ret;
  797. if (property == dev_priv->force_audio_property) {
  798. enum hdmi_force_audio i = val;
  799. bool has_audio;
  800. if (i == intel_hdmi->force_audio)
  801. return 0;
  802. intel_hdmi->force_audio = i;
  803. if (i == HDMI_AUDIO_AUTO)
  804. has_audio = intel_hdmi_detect_audio(connector);
  805. else
  806. has_audio = (i == HDMI_AUDIO_ON);
  807. if (i == HDMI_AUDIO_OFF_DVI)
  808. intel_hdmi->has_hdmi_sink = 0;
  809. intel_hdmi->has_audio = has_audio;
  810. goto done;
  811. }
  812. if (property == dev_priv->broadcast_rgb_property) {
  813. bool old_auto = intel_hdmi->color_range_auto;
  814. uint32_t old_range = intel_hdmi->color_range;
  815. switch (val) {
  816. case INTEL_BROADCAST_RGB_AUTO:
  817. intel_hdmi->color_range_auto = true;
  818. break;
  819. case INTEL_BROADCAST_RGB_FULL:
  820. intel_hdmi->color_range_auto = false;
  821. intel_hdmi->color_range = 0;
  822. break;
  823. case INTEL_BROADCAST_RGB_LIMITED:
  824. intel_hdmi->color_range_auto = false;
  825. intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
  826. break;
  827. default:
  828. return -EINVAL;
  829. }
  830. if (old_auto == intel_hdmi->color_range_auto &&
  831. old_range == intel_hdmi->color_range)
  832. return 0;
  833. goto done;
  834. }
  835. return -EINVAL;
  836. done:
  837. if (intel_dig_port->base.base.crtc)
  838. intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
  839. return 0;
  840. }
  841. static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
  842. {
  843. struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  844. struct drm_device *dev = encoder->base.dev;
  845. struct drm_i915_private *dev_priv = dev->dev_private;
  846. struct intel_crtc *intel_crtc =
  847. to_intel_crtc(encoder->base.crtc);
  848. int port = vlv_dport_to_channel(dport);
  849. int pipe = intel_crtc->pipe;
  850. u32 val;
  851. if (!IS_VALLEYVIEW(dev))
  852. return;
  853. /* Enable clock channels for this port */
  854. val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
  855. val = 0;
  856. if (pipe)
  857. val |= (1<<21);
  858. else
  859. val &= ~(1<<21);
  860. val |= 0x001000c4;
  861. vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
  862. /* HDMI 1.0V-2dB */
  863. vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
  864. vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
  865. 0x2b245f5f);
  866. vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
  867. 0x5578b83a);
  868. vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
  869. 0x0c782040);
  870. vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
  871. 0x2b247878);
  872. vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
  873. vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
  874. 0x00002000);
  875. vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
  876. DPIO_TX_OCALINIT_EN);
  877. /* Program lane clock */
  878. vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
  879. 0x00760018);
  880. vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
  881. 0x00400888);
  882. }
  883. static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
  884. {
  885. struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  886. struct drm_device *dev = encoder->base.dev;
  887. struct drm_i915_private *dev_priv = dev->dev_private;
  888. int port = vlv_dport_to_channel(dport);
  889. if (!IS_VALLEYVIEW(dev))
  890. return;
  891. /* Program Tx lane resets to default */
  892. vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
  893. DPIO_PCS_TX_LANE2_RESET |
  894. DPIO_PCS_TX_LANE1_RESET);
  895. vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
  896. DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
  897. DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
  898. (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
  899. DPIO_PCS_CLK_SOFT_RESET);
  900. /* Fix up inter-pair skew failure */
  901. vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
  902. vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
  903. vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
  904. vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
  905. 0x00002000);
  906. vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
  907. DPIO_TX_OCALINIT_EN);
  908. }
  909. static void intel_hdmi_post_disable(struct intel_encoder *encoder)
  910. {
  911. struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
  912. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  913. int port = vlv_dport_to_channel(dport);
  914. /* Reset lanes to avoid HDMI flicker (VLV w/a) */
  915. mutex_lock(&dev_priv->dpio_lock);
  916. vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
  917. vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
  918. mutex_unlock(&dev_priv->dpio_lock);
  919. }
  920. static void intel_hdmi_destroy(struct drm_connector *connector)
  921. {
  922. drm_sysfs_connector_remove(connector);
  923. drm_connector_cleanup(connector);
  924. kfree(connector);
  925. }
  926. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
  927. .mode_set = intel_hdmi_mode_set,
  928. };
  929. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  930. .dpms = intel_connector_dpms,
  931. .detect = intel_hdmi_detect,
  932. .fill_modes = drm_helper_probe_single_connector_modes,
  933. .set_property = intel_hdmi_set_property,
  934. .destroy = intel_hdmi_destroy,
  935. };
  936. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  937. .get_modes = intel_hdmi_get_modes,
  938. .mode_valid = intel_hdmi_mode_valid,
  939. .best_encoder = intel_best_encoder,
  940. };
  941. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  942. .destroy = intel_encoder_destroy,
  943. };
  944. static void
  945. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  946. {
  947. intel_attach_force_audio_property(connector);
  948. intel_attach_broadcast_rgb_property(connector);
  949. intel_hdmi->color_range_auto = true;
  950. }
  951. void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
  952. struct intel_connector *intel_connector)
  953. {
  954. struct drm_connector *connector = &intel_connector->base;
  955. struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
  956. struct intel_encoder *intel_encoder = &intel_dig_port->base;
  957. struct drm_device *dev = intel_encoder->base.dev;
  958. struct drm_i915_private *dev_priv = dev->dev_private;
  959. enum port port = intel_dig_port->port;
  960. drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  961. DRM_MODE_CONNECTOR_HDMIA);
  962. drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  963. connector->interlace_allowed = 1;
  964. connector->doublescan_allowed = 0;
  965. switch (port) {
  966. case PORT_B:
  967. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  968. intel_encoder->hpd_pin = HPD_PORT_B;
  969. break;
  970. case PORT_C:
  971. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  972. intel_encoder->hpd_pin = HPD_PORT_C;
  973. break;
  974. case PORT_D:
  975. intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  976. intel_encoder->hpd_pin = HPD_PORT_D;
  977. break;
  978. case PORT_A:
  979. intel_encoder->hpd_pin = HPD_PORT_A;
  980. /* Internal port only for eDP. */
  981. default:
  982. BUG();
  983. }
  984. if (IS_VALLEYVIEW(dev)) {
  985. intel_hdmi->write_infoframe = vlv_write_infoframe;
  986. intel_hdmi->set_infoframes = vlv_set_infoframes;
  987. } else if (!HAS_PCH_SPLIT(dev)) {
  988. intel_hdmi->write_infoframe = g4x_write_infoframe;
  989. intel_hdmi->set_infoframes = g4x_set_infoframes;
  990. } else if (HAS_DDI(dev)) {
  991. intel_hdmi->write_infoframe = hsw_write_infoframe;
  992. intel_hdmi->set_infoframes = hsw_set_infoframes;
  993. } else if (HAS_PCH_IBX(dev)) {
  994. intel_hdmi->write_infoframe = ibx_write_infoframe;
  995. intel_hdmi->set_infoframes = ibx_set_infoframes;
  996. } else {
  997. intel_hdmi->write_infoframe = cpt_write_infoframe;
  998. intel_hdmi->set_infoframes = cpt_set_infoframes;
  999. }
  1000. if (HAS_DDI(dev))
  1001. intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
  1002. else
  1003. intel_connector->get_hw_state = intel_connector_get_hw_state;
  1004. intel_hdmi_add_properties(intel_hdmi, connector);
  1005. intel_connector_attach_encoder(intel_connector, intel_encoder);
  1006. drm_sysfs_connector_add(connector);
  1007. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  1008. * 0xd. Failure to do so will result in spurious interrupts being
  1009. * generated on the port when a cable is not attached.
  1010. */
  1011. if (IS_G4X(dev) && !IS_GM45(dev)) {
  1012. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  1013. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  1014. }
  1015. }
  1016. void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
  1017. {
  1018. struct intel_digital_port *intel_dig_port;
  1019. struct intel_encoder *intel_encoder;
  1020. struct drm_encoder *encoder;
  1021. struct intel_connector *intel_connector;
  1022. intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
  1023. if (!intel_dig_port)
  1024. return;
  1025. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  1026. if (!intel_connector) {
  1027. kfree(intel_dig_port);
  1028. return;
  1029. }
  1030. intel_encoder = &intel_dig_port->base;
  1031. encoder = &intel_encoder->base;
  1032. drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  1033. DRM_MODE_ENCODER_TMDS);
  1034. drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
  1035. intel_encoder->compute_config = intel_hdmi_compute_config;
  1036. intel_encoder->enable = intel_enable_hdmi;
  1037. intel_encoder->disable = intel_disable_hdmi;
  1038. intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
  1039. intel_encoder->get_config = intel_hdmi_get_config;
  1040. if (IS_VALLEYVIEW(dev)) {
  1041. intel_encoder->pre_enable = intel_hdmi_pre_enable;
  1042. intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
  1043. intel_encoder->post_disable = intel_hdmi_post_disable;
  1044. }
  1045. intel_encoder->type = INTEL_OUTPUT_HDMI;
  1046. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  1047. intel_encoder->cloneable = false;
  1048. intel_dig_port->port = port;
  1049. intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
  1050. intel_dig_port->dp.output_reg = 0;
  1051. intel_hdmi_init_connector(intel_dig_port, intel_connector);
  1052. }