intel_display.c 286 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include <drm/drm_dp_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <linux/dma_remapping.h>
  42. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  43. static void intel_increase_pllclock(struct drm_crtc *crtc);
  44. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  46. struct intel_crtc_config *pipe_config);
  47. static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  48. struct intel_crtc_config *pipe_config);
  49. typedef struct {
  50. int min, max;
  51. } intel_range_t;
  52. typedef struct {
  53. int dot_limit;
  54. int p2_slow, p2_fast;
  55. } intel_p2_t;
  56. #define INTEL_P2_NUM 2
  57. typedef struct intel_limit intel_limit_t;
  58. struct intel_limit {
  59. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  60. intel_p2_t p2;
  61. };
  62. /* FDI */
  63. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  64. int
  65. intel_pch_rawclk(struct drm_device *dev)
  66. {
  67. struct drm_i915_private *dev_priv = dev->dev_private;
  68. WARN_ON(!HAS_PCH_SPLIT(dev));
  69. return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  70. }
  71. static inline u32 /* units of 100MHz */
  72. intel_fdi_link_freq(struct drm_device *dev)
  73. {
  74. if (IS_GEN5(dev)) {
  75. struct drm_i915_private *dev_priv = dev->dev_private;
  76. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  77. } else
  78. return 27;
  79. }
  80. static const intel_limit_t intel_limits_i8xx_dac = {
  81. .dot = { .min = 25000, .max = 350000 },
  82. .vco = { .min = 930000, .max = 1400000 },
  83. .n = { .min = 3, .max = 16 },
  84. .m = { .min = 96, .max = 140 },
  85. .m1 = { .min = 18, .max = 26 },
  86. .m2 = { .min = 6, .max = 16 },
  87. .p = { .min = 4, .max = 128 },
  88. .p1 = { .min = 2, .max = 33 },
  89. .p2 = { .dot_limit = 165000,
  90. .p2_slow = 4, .p2_fast = 2 },
  91. };
  92. static const intel_limit_t intel_limits_i8xx_dvo = {
  93. .dot = { .min = 25000, .max = 350000 },
  94. .vco = { .min = 930000, .max = 1400000 },
  95. .n = { .min = 3, .max = 16 },
  96. .m = { .min = 96, .max = 140 },
  97. .m1 = { .min = 18, .max = 26 },
  98. .m2 = { .min = 6, .max = 16 },
  99. .p = { .min = 4, .max = 128 },
  100. .p1 = { .min = 2, .max = 33 },
  101. .p2 = { .dot_limit = 165000,
  102. .p2_slow = 4, .p2_fast = 4 },
  103. };
  104. static const intel_limit_t intel_limits_i8xx_lvds = {
  105. .dot = { .min = 25000, .max = 350000 },
  106. .vco = { .min = 930000, .max = 1400000 },
  107. .n = { .min = 3, .max = 16 },
  108. .m = { .min = 96, .max = 140 },
  109. .m1 = { .min = 18, .max = 26 },
  110. .m2 = { .min = 6, .max = 16 },
  111. .p = { .min = 4, .max = 128 },
  112. .p1 = { .min = 1, .max = 6 },
  113. .p2 = { .dot_limit = 165000,
  114. .p2_slow = 14, .p2_fast = 7 },
  115. };
  116. static const intel_limit_t intel_limits_i9xx_sdvo = {
  117. .dot = { .min = 20000, .max = 400000 },
  118. .vco = { .min = 1400000, .max = 2800000 },
  119. .n = { .min = 1, .max = 6 },
  120. .m = { .min = 70, .max = 120 },
  121. .m1 = { .min = 8, .max = 18 },
  122. .m2 = { .min = 3, .max = 7 },
  123. .p = { .min = 5, .max = 80 },
  124. .p1 = { .min = 1, .max = 8 },
  125. .p2 = { .dot_limit = 200000,
  126. .p2_slow = 10, .p2_fast = 5 },
  127. };
  128. static const intel_limit_t intel_limits_i9xx_lvds = {
  129. .dot = { .min = 20000, .max = 400000 },
  130. .vco = { .min = 1400000, .max = 2800000 },
  131. .n = { .min = 1, .max = 6 },
  132. .m = { .min = 70, .max = 120 },
  133. .m1 = { .min = 8, .max = 18 },
  134. .m2 = { .min = 3, .max = 7 },
  135. .p = { .min = 7, .max = 98 },
  136. .p1 = { .min = 1, .max = 8 },
  137. .p2 = { .dot_limit = 112000,
  138. .p2_slow = 14, .p2_fast = 7 },
  139. };
  140. static const intel_limit_t intel_limits_g4x_sdvo = {
  141. .dot = { .min = 25000, .max = 270000 },
  142. .vco = { .min = 1750000, .max = 3500000},
  143. .n = { .min = 1, .max = 4 },
  144. .m = { .min = 104, .max = 138 },
  145. .m1 = { .min = 17, .max = 23 },
  146. .m2 = { .min = 5, .max = 11 },
  147. .p = { .min = 10, .max = 30 },
  148. .p1 = { .min = 1, .max = 3},
  149. .p2 = { .dot_limit = 270000,
  150. .p2_slow = 10,
  151. .p2_fast = 10
  152. },
  153. };
  154. static const intel_limit_t intel_limits_g4x_hdmi = {
  155. .dot = { .min = 22000, .max = 400000 },
  156. .vco = { .min = 1750000, .max = 3500000},
  157. .n = { .min = 1, .max = 4 },
  158. .m = { .min = 104, .max = 138 },
  159. .m1 = { .min = 16, .max = 23 },
  160. .m2 = { .min = 5, .max = 11 },
  161. .p = { .min = 5, .max = 80 },
  162. .p1 = { .min = 1, .max = 8},
  163. .p2 = { .dot_limit = 165000,
  164. .p2_slow = 10, .p2_fast = 5 },
  165. };
  166. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  167. .dot = { .min = 20000, .max = 115000 },
  168. .vco = { .min = 1750000, .max = 3500000 },
  169. .n = { .min = 1, .max = 3 },
  170. .m = { .min = 104, .max = 138 },
  171. .m1 = { .min = 17, .max = 23 },
  172. .m2 = { .min = 5, .max = 11 },
  173. .p = { .min = 28, .max = 112 },
  174. .p1 = { .min = 2, .max = 8 },
  175. .p2 = { .dot_limit = 0,
  176. .p2_slow = 14, .p2_fast = 14
  177. },
  178. };
  179. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  180. .dot = { .min = 80000, .max = 224000 },
  181. .vco = { .min = 1750000, .max = 3500000 },
  182. .n = { .min = 1, .max = 3 },
  183. .m = { .min = 104, .max = 138 },
  184. .m1 = { .min = 17, .max = 23 },
  185. .m2 = { .min = 5, .max = 11 },
  186. .p = { .min = 14, .max = 42 },
  187. .p1 = { .min = 2, .max = 6 },
  188. .p2 = { .dot_limit = 0,
  189. .p2_slow = 7, .p2_fast = 7
  190. },
  191. };
  192. static const intel_limit_t intel_limits_pineview_sdvo = {
  193. .dot = { .min = 20000, .max = 400000},
  194. .vco = { .min = 1700000, .max = 3500000 },
  195. /* Pineview's Ncounter is a ring counter */
  196. .n = { .min = 3, .max = 6 },
  197. .m = { .min = 2, .max = 256 },
  198. /* Pineview only has one combined m divider, which we treat as m2. */
  199. .m1 = { .min = 0, .max = 0 },
  200. .m2 = { .min = 0, .max = 254 },
  201. .p = { .min = 5, .max = 80 },
  202. .p1 = { .min = 1, .max = 8 },
  203. .p2 = { .dot_limit = 200000,
  204. .p2_slow = 10, .p2_fast = 5 },
  205. };
  206. static const intel_limit_t intel_limits_pineview_lvds = {
  207. .dot = { .min = 20000, .max = 400000 },
  208. .vco = { .min = 1700000, .max = 3500000 },
  209. .n = { .min = 3, .max = 6 },
  210. .m = { .min = 2, .max = 256 },
  211. .m1 = { .min = 0, .max = 0 },
  212. .m2 = { .min = 0, .max = 254 },
  213. .p = { .min = 7, .max = 112 },
  214. .p1 = { .min = 1, .max = 8 },
  215. .p2 = { .dot_limit = 112000,
  216. .p2_slow = 14, .p2_fast = 14 },
  217. };
  218. /* Ironlake / Sandybridge
  219. *
  220. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  221. * the range value for them is (actual_value - 2).
  222. */
  223. static const intel_limit_t intel_limits_ironlake_dac = {
  224. .dot = { .min = 25000, .max = 350000 },
  225. .vco = { .min = 1760000, .max = 3510000 },
  226. .n = { .min = 1, .max = 5 },
  227. .m = { .min = 79, .max = 127 },
  228. .m1 = { .min = 12, .max = 22 },
  229. .m2 = { .min = 5, .max = 9 },
  230. .p = { .min = 5, .max = 80 },
  231. .p1 = { .min = 1, .max = 8 },
  232. .p2 = { .dot_limit = 225000,
  233. .p2_slow = 10, .p2_fast = 5 },
  234. };
  235. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  236. .dot = { .min = 25000, .max = 350000 },
  237. .vco = { .min = 1760000, .max = 3510000 },
  238. .n = { .min = 1, .max = 3 },
  239. .m = { .min = 79, .max = 118 },
  240. .m1 = { .min = 12, .max = 22 },
  241. .m2 = { .min = 5, .max = 9 },
  242. .p = { .min = 28, .max = 112 },
  243. .p1 = { .min = 2, .max = 8 },
  244. .p2 = { .dot_limit = 225000,
  245. .p2_slow = 14, .p2_fast = 14 },
  246. };
  247. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  248. .dot = { .min = 25000, .max = 350000 },
  249. .vco = { .min = 1760000, .max = 3510000 },
  250. .n = { .min = 1, .max = 3 },
  251. .m = { .min = 79, .max = 127 },
  252. .m1 = { .min = 12, .max = 22 },
  253. .m2 = { .min = 5, .max = 9 },
  254. .p = { .min = 14, .max = 56 },
  255. .p1 = { .min = 2, .max = 8 },
  256. .p2 = { .dot_limit = 225000,
  257. .p2_slow = 7, .p2_fast = 7 },
  258. };
  259. /* LVDS 100mhz refclk limits. */
  260. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  261. .dot = { .min = 25000, .max = 350000 },
  262. .vco = { .min = 1760000, .max = 3510000 },
  263. .n = { .min = 1, .max = 2 },
  264. .m = { .min = 79, .max = 126 },
  265. .m1 = { .min = 12, .max = 22 },
  266. .m2 = { .min = 5, .max = 9 },
  267. .p = { .min = 28, .max = 112 },
  268. .p1 = { .min = 2, .max = 8 },
  269. .p2 = { .dot_limit = 225000,
  270. .p2_slow = 14, .p2_fast = 14 },
  271. };
  272. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  273. .dot = { .min = 25000, .max = 350000 },
  274. .vco = { .min = 1760000, .max = 3510000 },
  275. .n = { .min = 1, .max = 3 },
  276. .m = { .min = 79, .max = 126 },
  277. .m1 = { .min = 12, .max = 22 },
  278. .m2 = { .min = 5, .max = 9 },
  279. .p = { .min = 14, .max = 42 },
  280. .p1 = { .min = 2, .max = 6 },
  281. .p2 = { .dot_limit = 225000,
  282. .p2_slow = 7, .p2_fast = 7 },
  283. };
  284. static const intel_limit_t intel_limits_vlv_dac = {
  285. .dot = { .min = 25000, .max = 270000 },
  286. .vco = { .min = 4000000, .max = 6000000 },
  287. .n = { .min = 1, .max = 7 },
  288. .m = { .min = 22, .max = 450 }, /* guess */
  289. .m1 = { .min = 2, .max = 3 },
  290. .m2 = { .min = 11, .max = 156 },
  291. .p = { .min = 10, .max = 30 },
  292. .p1 = { .min = 1, .max = 3 },
  293. .p2 = { .dot_limit = 270000,
  294. .p2_slow = 2, .p2_fast = 20 },
  295. };
  296. static const intel_limit_t intel_limits_vlv_hdmi = {
  297. .dot = { .min = 25000, .max = 270000 },
  298. .vco = { .min = 4000000, .max = 6000000 },
  299. .n = { .min = 1, .max = 7 },
  300. .m = { .min = 60, .max = 300 }, /* guess */
  301. .m1 = { .min = 2, .max = 3 },
  302. .m2 = { .min = 11, .max = 156 },
  303. .p = { .min = 10, .max = 30 },
  304. .p1 = { .min = 2, .max = 3 },
  305. .p2 = { .dot_limit = 270000,
  306. .p2_slow = 2, .p2_fast = 20 },
  307. };
  308. static const intel_limit_t intel_limits_vlv_dp = {
  309. .dot = { .min = 25000, .max = 270000 },
  310. .vco = { .min = 4000000, .max = 6000000 },
  311. .n = { .min = 1, .max = 7 },
  312. .m = { .min = 22, .max = 450 },
  313. .m1 = { .min = 2, .max = 3 },
  314. .m2 = { .min = 11, .max = 156 },
  315. .p = { .min = 10, .max = 30 },
  316. .p1 = { .min = 1, .max = 3 },
  317. .p2 = { .dot_limit = 270000,
  318. .p2_slow = 2, .p2_fast = 20 },
  319. };
  320. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  321. int refclk)
  322. {
  323. struct drm_device *dev = crtc->dev;
  324. const intel_limit_t *limit;
  325. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  326. if (intel_is_dual_link_lvds(dev)) {
  327. if (refclk == 100000)
  328. limit = &intel_limits_ironlake_dual_lvds_100m;
  329. else
  330. limit = &intel_limits_ironlake_dual_lvds;
  331. } else {
  332. if (refclk == 100000)
  333. limit = &intel_limits_ironlake_single_lvds_100m;
  334. else
  335. limit = &intel_limits_ironlake_single_lvds;
  336. }
  337. } else
  338. limit = &intel_limits_ironlake_dac;
  339. return limit;
  340. }
  341. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  342. {
  343. struct drm_device *dev = crtc->dev;
  344. const intel_limit_t *limit;
  345. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  346. if (intel_is_dual_link_lvds(dev))
  347. limit = &intel_limits_g4x_dual_channel_lvds;
  348. else
  349. limit = &intel_limits_g4x_single_channel_lvds;
  350. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  351. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  352. limit = &intel_limits_g4x_hdmi;
  353. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  354. limit = &intel_limits_g4x_sdvo;
  355. } else /* The option is for other outputs */
  356. limit = &intel_limits_i9xx_sdvo;
  357. return limit;
  358. }
  359. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  360. {
  361. struct drm_device *dev = crtc->dev;
  362. const intel_limit_t *limit;
  363. if (HAS_PCH_SPLIT(dev))
  364. limit = intel_ironlake_limit(crtc, refclk);
  365. else if (IS_G4X(dev)) {
  366. limit = intel_g4x_limit(crtc);
  367. } else if (IS_PINEVIEW(dev)) {
  368. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  369. limit = &intel_limits_pineview_lvds;
  370. else
  371. limit = &intel_limits_pineview_sdvo;
  372. } else if (IS_VALLEYVIEW(dev)) {
  373. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  374. limit = &intel_limits_vlv_dac;
  375. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  376. limit = &intel_limits_vlv_hdmi;
  377. else
  378. limit = &intel_limits_vlv_dp;
  379. } else if (!IS_GEN2(dev)) {
  380. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  381. limit = &intel_limits_i9xx_lvds;
  382. else
  383. limit = &intel_limits_i9xx_sdvo;
  384. } else {
  385. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  386. limit = &intel_limits_i8xx_lvds;
  387. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
  388. limit = &intel_limits_i8xx_dvo;
  389. else
  390. limit = &intel_limits_i8xx_dac;
  391. }
  392. return limit;
  393. }
  394. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  395. static void pineview_clock(int refclk, intel_clock_t *clock)
  396. {
  397. clock->m = clock->m2 + 2;
  398. clock->p = clock->p1 * clock->p2;
  399. clock->vco = refclk * clock->m / clock->n;
  400. clock->dot = clock->vco / clock->p;
  401. }
  402. static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
  403. {
  404. return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
  405. }
  406. static void i9xx_clock(int refclk, intel_clock_t *clock)
  407. {
  408. clock->m = i9xx_dpll_compute_m(clock);
  409. clock->p = clock->p1 * clock->p2;
  410. clock->vco = refclk * clock->m / (clock->n + 2);
  411. clock->dot = clock->vco / clock->p;
  412. }
  413. /**
  414. * Returns whether any output on the specified pipe is of the specified type
  415. */
  416. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  417. {
  418. struct drm_device *dev = crtc->dev;
  419. struct intel_encoder *encoder;
  420. for_each_encoder_on_crtc(dev, crtc, encoder)
  421. if (encoder->type == type)
  422. return true;
  423. return false;
  424. }
  425. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  426. /**
  427. * Returns whether the given set of divisors are valid for a given refclk with
  428. * the given connectors.
  429. */
  430. static bool intel_PLL_is_valid(struct drm_device *dev,
  431. const intel_limit_t *limit,
  432. const intel_clock_t *clock)
  433. {
  434. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  435. INTELPllInvalid("p1 out of range\n");
  436. if (clock->p < limit->p.min || limit->p.max < clock->p)
  437. INTELPllInvalid("p out of range\n");
  438. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  439. INTELPllInvalid("m2 out of range\n");
  440. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  441. INTELPllInvalid("m1 out of range\n");
  442. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  443. INTELPllInvalid("m1 <= m2\n");
  444. if (clock->m < limit->m.min || limit->m.max < clock->m)
  445. INTELPllInvalid("m out of range\n");
  446. if (clock->n < limit->n.min || limit->n.max < clock->n)
  447. INTELPllInvalid("n out of range\n");
  448. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  449. INTELPllInvalid("vco out of range\n");
  450. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  451. * connector, etc., rather than just a single range.
  452. */
  453. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  454. INTELPllInvalid("dot out of range\n");
  455. return true;
  456. }
  457. static bool
  458. i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  459. int target, int refclk, intel_clock_t *match_clock,
  460. intel_clock_t *best_clock)
  461. {
  462. struct drm_device *dev = crtc->dev;
  463. intel_clock_t clock;
  464. int err = target;
  465. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  466. /*
  467. * For LVDS just rely on its current settings for dual-channel.
  468. * We haven't figured out how to reliably set up different
  469. * single/dual channel state, if we even can.
  470. */
  471. if (intel_is_dual_link_lvds(dev))
  472. clock.p2 = limit->p2.p2_fast;
  473. else
  474. clock.p2 = limit->p2.p2_slow;
  475. } else {
  476. if (target < limit->p2.dot_limit)
  477. clock.p2 = limit->p2.p2_slow;
  478. else
  479. clock.p2 = limit->p2.p2_fast;
  480. }
  481. memset(best_clock, 0, sizeof(*best_clock));
  482. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  483. clock.m1++) {
  484. for (clock.m2 = limit->m2.min;
  485. clock.m2 <= limit->m2.max; clock.m2++) {
  486. if (clock.m2 >= clock.m1)
  487. break;
  488. for (clock.n = limit->n.min;
  489. clock.n <= limit->n.max; clock.n++) {
  490. for (clock.p1 = limit->p1.min;
  491. clock.p1 <= limit->p1.max; clock.p1++) {
  492. int this_err;
  493. i9xx_clock(refclk, &clock);
  494. if (!intel_PLL_is_valid(dev, limit,
  495. &clock))
  496. continue;
  497. if (match_clock &&
  498. clock.p != match_clock->p)
  499. continue;
  500. this_err = abs(clock.dot - target);
  501. if (this_err < err) {
  502. *best_clock = clock;
  503. err = this_err;
  504. }
  505. }
  506. }
  507. }
  508. }
  509. return (err != target);
  510. }
  511. static bool
  512. pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  513. int target, int refclk, intel_clock_t *match_clock,
  514. intel_clock_t *best_clock)
  515. {
  516. struct drm_device *dev = crtc->dev;
  517. intel_clock_t clock;
  518. int err = target;
  519. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  520. /*
  521. * For LVDS just rely on its current settings for dual-channel.
  522. * We haven't figured out how to reliably set up different
  523. * single/dual channel state, if we even can.
  524. */
  525. if (intel_is_dual_link_lvds(dev))
  526. clock.p2 = limit->p2.p2_fast;
  527. else
  528. clock.p2 = limit->p2.p2_slow;
  529. } else {
  530. if (target < limit->p2.dot_limit)
  531. clock.p2 = limit->p2.p2_slow;
  532. else
  533. clock.p2 = limit->p2.p2_fast;
  534. }
  535. memset(best_clock, 0, sizeof(*best_clock));
  536. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  537. clock.m1++) {
  538. for (clock.m2 = limit->m2.min;
  539. clock.m2 <= limit->m2.max; clock.m2++) {
  540. for (clock.n = limit->n.min;
  541. clock.n <= limit->n.max; clock.n++) {
  542. for (clock.p1 = limit->p1.min;
  543. clock.p1 <= limit->p1.max; clock.p1++) {
  544. int this_err;
  545. pineview_clock(refclk, &clock);
  546. if (!intel_PLL_is_valid(dev, limit,
  547. &clock))
  548. continue;
  549. if (match_clock &&
  550. clock.p != match_clock->p)
  551. continue;
  552. this_err = abs(clock.dot - target);
  553. if (this_err < err) {
  554. *best_clock = clock;
  555. err = this_err;
  556. }
  557. }
  558. }
  559. }
  560. }
  561. return (err != target);
  562. }
  563. static bool
  564. g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  565. int target, int refclk, intel_clock_t *match_clock,
  566. intel_clock_t *best_clock)
  567. {
  568. struct drm_device *dev = crtc->dev;
  569. intel_clock_t clock;
  570. int max_n;
  571. bool found;
  572. /* approximately equals target * 0.00585 */
  573. int err_most = (target >> 8) + (target >> 9);
  574. found = false;
  575. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  576. if (intel_is_dual_link_lvds(dev))
  577. clock.p2 = limit->p2.p2_fast;
  578. else
  579. clock.p2 = limit->p2.p2_slow;
  580. } else {
  581. if (target < limit->p2.dot_limit)
  582. clock.p2 = limit->p2.p2_slow;
  583. else
  584. clock.p2 = limit->p2.p2_fast;
  585. }
  586. memset(best_clock, 0, sizeof(*best_clock));
  587. max_n = limit->n.max;
  588. /* based on hardware requirement, prefer smaller n to precision */
  589. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  590. /* based on hardware requirement, prefere larger m1,m2 */
  591. for (clock.m1 = limit->m1.max;
  592. clock.m1 >= limit->m1.min; clock.m1--) {
  593. for (clock.m2 = limit->m2.max;
  594. clock.m2 >= limit->m2.min; clock.m2--) {
  595. for (clock.p1 = limit->p1.max;
  596. clock.p1 >= limit->p1.min; clock.p1--) {
  597. int this_err;
  598. i9xx_clock(refclk, &clock);
  599. if (!intel_PLL_is_valid(dev, limit,
  600. &clock))
  601. continue;
  602. this_err = abs(clock.dot - target);
  603. if (this_err < err_most) {
  604. *best_clock = clock;
  605. err_most = this_err;
  606. max_n = clock.n;
  607. found = true;
  608. }
  609. }
  610. }
  611. }
  612. }
  613. return found;
  614. }
  615. static bool
  616. vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
  617. int target, int refclk, intel_clock_t *match_clock,
  618. intel_clock_t *best_clock)
  619. {
  620. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  621. u32 m, n, fastclk;
  622. u32 updrate, minupdate, fracbits, p;
  623. unsigned long bestppm, ppm, absppm;
  624. int dotclk, flag;
  625. flag = 0;
  626. dotclk = target * 1000;
  627. bestppm = 1000000;
  628. ppm = absppm = 0;
  629. fastclk = dotclk / (2*100);
  630. updrate = 0;
  631. minupdate = 19200;
  632. fracbits = 1;
  633. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  634. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  635. /* based on hardware requirement, prefer smaller n to precision */
  636. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  637. updrate = refclk / n;
  638. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  639. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  640. if (p2 > 10)
  641. p2 = p2 - 1;
  642. p = p1 * p2;
  643. /* based on hardware requirement, prefer bigger m1,m2 values */
  644. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  645. m2 = (((2*(fastclk * p * n / m1 )) +
  646. refclk) / (2*refclk));
  647. m = m1 * m2;
  648. vco = updrate * m;
  649. if (vco >= limit->vco.min && vco < limit->vco.max) {
  650. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  651. absppm = (ppm > 0) ? ppm : (-ppm);
  652. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  653. bestppm = 0;
  654. flag = 1;
  655. }
  656. if (absppm < bestppm - 10) {
  657. bestppm = absppm;
  658. flag = 1;
  659. }
  660. if (flag) {
  661. bestn = n;
  662. bestm1 = m1;
  663. bestm2 = m2;
  664. bestp1 = p1;
  665. bestp2 = p2;
  666. flag = 0;
  667. }
  668. }
  669. }
  670. }
  671. }
  672. }
  673. best_clock->n = bestn;
  674. best_clock->m1 = bestm1;
  675. best_clock->m2 = bestm2;
  676. best_clock->p1 = bestp1;
  677. best_clock->p2 = bestp2;
  678. return true;
  679. }
  680. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  681. enum pipe pipe)
  682. {
  683. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  684. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  685. return intel_crtc->config.cpu_transcoder;
  686. }
  687. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  688. {
  689. struct drm_i915_private *dev_priv = dev->dev_private;
  690. u32 frame, frame_reg = PIPEFRAME(pipe);
  691. frame = I915_READ(frame_reg);
  692. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  693. DRM_DEBUG_KMS("vblank wait timed out\n");
  694. }
  695. /**
  696. * intel_wait_for_vblank - wait for vblank on a given pipe
  697. * @dev: drm device
  698. * @pipe: pipe to wait for
  699. *
  700. * Wait for vblank to occur on a given pipe. Needed for various bits of
  701. * mode setting code.
  702. */
  703. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  704. {
  705. struct drm_i915_private *dev_priv = dev->dev_private;
  706. int pipestat_reg = PIPESTAT(pipe);
  707. if (INTEL_INFO(dev)->gen >= 5) {
  708. ironlake_wait_for_vblank(dev, pipe);
  709. return;
  710. }
  711. /* Clear existing vblank status. Note this will clear any other
  712. * sticky status fields as well.
  713. *
  714. * This races with i915_driver_irq_handler() with the result
  715. * that either function could miss a vblank event. Here it is not
  716. * fatal, as we will either wait upon the next vblank interrupt or
  717. * timeout. Generally speaking intel_wait_for_vblank() is only
  718. * called during modeset at which time the GPU should be idle and
  719. * should *not* be performing page flips and thus not waiting on
  720. * vblanks...
  721. * Currently, the result of us stealing a vblank from the irq
  722. * handler is that a single frame will be skipped during swapbuffers.
  723. */
  724. I915_WRITE(pipestat_reg,
  725. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  726. /* Wait for vblank interrupt bit to set */
  727. if (wait_for(I915_READ(pipestat_reg) &
  728. PIPE_VBLANK_INTERRUPT_STATUS,
  729. 50))
  730. DRM_DEBUG_KMS("vblank wait timed out\n");
  731. }
  732. /*
  733. * intel_wait_for_pipe_off - wait for pipe to turn off
  734. * @dev: drm device
  735. * @pipe: pipe to wait for
  736. *
  737. * After disabling a pipe, we can't wait for vblank in the usual way,
  738. * spinning on the vblank interrupt status bit, since we won't actually
  739. * see an interrupt when the pipe is disabled.
  740. *
  741. * On Gen4 and above:
  742. * wait for the pipe register state bit to turn off
  743. *
  744. * Otherwise:
  745. * wait for the display line value to settle (it usually
  746. * ends up stopping at the start of the next frame).
  747. *
  748. */
  749. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  750. {
  751. struct drm_i915_private *dev_priv = dev->dev_private;
  752. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  753. pipe);
  754. if (INTEL_INFO(dev)->gen >= 4) {
  755. int reg = PIPECONF(cpu_transcoder);
  756. /* Wait for the Pipe State to go off */
  757. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  758. 100))
  759. WARN(1, "pipe_off wait timed out\n");
  760. } else {
  761. u32 last_line, line_mask;
  762. int reg = PIPEDSL(pipe);
  763. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  764. if (IS_GEN2(dev))
  765. line_mask = DSL_LINEMASK_GEN2;
  766. else
  767. line_mask = DSL_LINEMASK_GEN3;
  768. /* Wait for the display line to settle */
  769. do {
  770. last_line = I915_READ(reg) & line_mask;
  771. mdelay(5);
  772. } while (((I915_READ(reg) & line_mask) != last_line) &&
  773. time_after(timeout, jiffies));
  774. if (time_after(jiffies, timeout))
  775. WARN(1, "pipe_off wait timed out\n");
  776. }
  777. }
  778. /*
  779. * ibx_digital_port_connected - is the specified port connected?
  780. * @dev_priv: i915 private structure
  781. * @port: the port to test
  782. *
  783. * Returns true if @port is connected, false otherwise.
  784. */
  785. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  786. struct intel_digital_port *port)
  787. {
  788. u32 bit;
  789. if (HAS_PCH_IBX(dev_priv->dev)) {
  790. switch(port->port) {
  791. case PORT_B:
  792. bit = SDE_PORTB_HOTPLUG;
  793. break;
  794. case PORT_C:
  795. bit = SDE_PORTC_HOTPLUG;
  796. break;
  797. case PORT_D:
  798. bit = SDE_PORTD_HOTPLUG;
  799. break;
  800. default:
  801. return true;
  802. }
  803. } else {
  804. switch(port->port) {
  805. case PORT_B:
  806. bit = SDE_PORTB_HOTPLUG_CPT;
  807. break;
  808. case PORT_C:
  809. bit = SDE_PORTC_HOTPLUG_CPT;
  810. break;
  811. case PORT_D:
  812. bit = SDE_PORTD_HOTPLUG_CPT;
  813. break;
  814. default:
  815. return true;
  816. }
  817. }
  818. return I915_READ(SDEISR) & bit;
  819. }
  820. static const char *state_string(bool enabled)
  821. {
  822. return enabled ? "on" : "off";
  823. }
  824. /* Only for pre-ILK configs */
  825. void assert_pll(struct drm_i915_private *dev_priv,
  826. enum pipe pipe, bool state)
  827. {
  828. int reg;
  829. u32 val;
  830. bool cur_state;
  831. reg = DPLL(pipe);
  832. val = I915_READ(reg);
  833. cur_state = !!(val & DPLL_VCO_ENABLE);
  834. WARN(cur_state != state,
  835. "PLL state assertion failure (expected %s, current %s)\n",
  836. state_string(state), state_string(cur_state));
  837. }
  838. struct intel_shared_dpll *
  839. intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
  840. {
  841. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  842. if (crtc->config.shared_dpll < 0)
  843. return NULL;
  844. return &dev_priv->shared_dplls[crtc->config.shared_dpll];
  845. }
  846. /* For ILK+ */
  847. void assert_shared_dpll(struct drm_i915_private *dev_priv,
  848. struct intel_shared_dpll *pll,
  849. bool state)
  850. {
  851. bool cur_state;
  852. struct intel_dpll_hw_state hw_state;
  853. if (HAS_PCH_LPT(dev_priv->dev)) {
  854. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  855. return;
  856. }
  857. if (WARN (!pll,
  858. "asserting DPLL %s with no DPLL\n", state_string(state)))
  859. return;
  860. cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
  861. WARN(cur_state != state,
  862. "%s assertion failure (expected %s, current %s)\n",
  863. pll->name, state_string(state), state_string(cur_state));
  864. }
  865. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  866. enum pipe pipe, bool state)
  867. {
  868. int reg;
  869. u32 val;
  870. bool cur_state;
  871. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  872. pipe);
  873. if (HAS_DDI(dev_priv->dev)) {
  874. /* DDI does not have a specific FDI_TX register */
  875. reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  876. val = I915_READ(reg);
  877. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  878. } else {
  879. reg = FDI_TX_CTL(pipe);
  880. val = I915_READ(reg);
  881. cur_state = !!(val & FDI_TX_ENABLE);
  882. }
  883. WARN(cur_state != state,
  884. "FDI TX state assertion failure (expected %s, current %s)\n",
  885. state_string(state), state_string(cur_state));
  886. }
  887. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  888. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  889. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  890. enum pipe pipe, bool state)
  891. {
  892. int reg;
  893. u32 val;
  894. bool cur_state;
  895. reg = FDI_RX_CTL(pipe);
  896. val = I915_READ(reg);
  897. cur_state = !!(val & FDI_RX_ENABLE);
  898. WARN(cur_state != state,
  899. "FDI RX state assertion failure (expected %s, current %s)\n",
  900. state_string(state), state_string(cur_state));
  901. }
  902. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  903. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  904. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  905. enum pipe pipe)
  906. {
  907. int reg;
  908. u32 val;
  909. /* ILK FDI PLL is always enabled */
  910. if (dev_priv->info->gen == 5)
  911. return;
  912. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  913. if (HAS_DDI(dev_priv->dev))
  914. return;
  915. reg = FDI_TX_CTL(pipe);
  916. val = I915_READ(reg);
  917. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  918. }
  919. void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
  920. enum pipe pipe, bool state)
  921. {
  922. int reg;
  923. u32 val;
  924. bool cur_state;
  925. reg = FDI_RX_CTL(pipe);
  926. val = I915_READ(reg);
  927. cur_state = !!(val & FDI_RX_PLL_ENABLE);
  928. WARN(cur_state != state,
  929. "FDI RX PLL assertion failure (expected %s, current %s)\n",
  930. state_string(state), state_string(cur_state));
  931. }
  932. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  933. enum pipe pipe)
  934. {
  935. int pp_reg, lvds_reg;
  936. u32 val;
  937. enum pipe panel_pipe = PIPE_A;
  938. bool locked = true;
  939. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  940. pp_reg = PCH_PP_CONTROL;
  941. lvds_reg = PCH_LVDS;
  942. } else {
  943. pp_reg = PP_CONTROL;
  944. lvds_reg = LVDS;
  945. }
  946. val = I915_READ(pp_reg);
  947. if (!(val & PANEL_POWER_ON) ||
  948. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  949. locked = false;
  950. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  951. panel_pipe = PIPE_B;
  952. WARN(panel_pipe == pipe && locked,
  953. "panel assertion failure, pipe %c regs locked\n",
  954. pipe_name(pipe));
  955. }
  956. void assert_pipe(struct drm_i915_private *dev_priv,
  957. enum pipe pipe, bool state)
  958. {
  959. int reg;
  960. u32 val;
  961. bool cur_state;
  962. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  963. pipe);
  964. /* if we need the pipe A quirk it must be always on */
  965. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  966. state = true;
  967. if (!intel_display_power_enabled(dev_priv->dev,
  968. POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
  969. cur_state = false;
  970. } else {
  971. reg = PIPECONF(cpu_transcoder);
  972. val = I915_READ(reg);
  973. cur_state = !!(val & PIPECONF_ENABLE);
  974. }
  975. WARN(cur_state != state,
  976. "pipe %c assertion failure (expected %s, current %s)\n",
  977. pipe_name(pipe), state_string(state), state_string(cur_state));
  978. }
  979. static void assert_plane(struct drm_i915_private *dev_priv,
  980. enum plane plane, bool state)
  981. {
  982. int reg;
  983. u32 val;
  984. bool cur_state;
  985. reg = DSPCNTR(plane);
  986. val = I915_READ(reg);
  987. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  988. WARN(cur_state != state,
  989. "plane %c assertion failure (expected %s, current %s)\n",
  990. plane_name(plane), state_string(state), state_string(cur_state));
  991. }
  992. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  993. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  994. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  995. enum pipe pipe)
  996. {
  997. struct drm_device *dev = dev_priv->dev;
  998. int reg, i;
  999. u32 val;
  1000. int cur_pipe;
  1001. /* Primary planes are fixed to pipes on gen4+ */
  1002. if (INTEL_INFO(dev)->gen >= 4) {
  1003. reg = DSPCNTR(pipe);
  1004. val = I915_READ(reg);
  1005. WARN((val & DISPLAY_PLANE_ENABLE),
  1006. "plane %c assertion failure, should be disabled but not\n",
  1007. plane_name(pipe));
  1008. return;
  1009. }
  1010. /* Need to check both planes against the pipe */
  1011. for_each_pipe(i) {
  1012. reg = DSPCNTR(i);
  1013. val = I915_READ(reg);
  1014. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1015. DISPPLANE_SEL_PIPE_SHIFT;
  1016. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1017. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1018. plane_name(i), pipe_name(pipe));
  1019. }
  1020. }
  1021. static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
  1022. enum pipe pipe)
  1023. {
  1024. struct drm_device *dev = dev_priv->dev;
  1025. int reg, i;
  1026. u32 val;
  1027. if (IS_VALLEYVIEW(dev)) {
  1028. for (i = 0; i < dev_priv->num_plane; i++) {
  1029. reg = SPCNTR(pipe, i);
  1030. val = I915_READ(reg);
  1031. WARN((val & SP_ENABLE),
  1032. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1033. sprite_name(pipe, i), pipe_name(pipe));
  1034. }
  1035. } else if (INTEL_INFO(dev)->gen >= 7) {
  1036. reg = SPRCTL(pipe);
  1037. val = I915_READ(reg);
  1038. WARN((val & SPRITE_ENABLE),
  1039. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1040. plane_name(pipe), pipe_name(pipe));
  1041. } else if (INTEL_INFO(dev)->gen >= 5) {
  1042. reg = DVSCNTR(pipe);
  1043. val = I915_READ(reg);
  1044. WARN((val & DVS_ENABLE),
  1045. "sprite %c assertion failure, should be off on pipe %c but is still active\n",
  1046. plane_name(pipe), pipe_name(pipe));
  1047. }
  1048. }
  1049. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1050. {
  1051. u32 val;
  1052. bool enabled;
  1053. if (HAS_PCH_LPT(dev_priv->dev)) {
  1054. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1055. return;
  1056. }
  1057. val = I915_READ(PCH_DREF_CONTROL);
  1058. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1059. DREF_SUPERSPREAD_SOURCE_MASK));
  1060. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1061. }
  1062. static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
  1063. enum pipe pipe)
  1064. {
  1065. int reg;
  1066. u32 val;
  1067. bool enabled;
  1068. reg = PCH_TRANSCONF(pipe);
  1069. val = I915_READ(reg);
  1070. enabled = !!(val & TRANS_ENABLE);
  1071. WARN(enabled,
  1072. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1073. pipe_name(pipe));
  1074. }
  1075. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1076. enum pipe pipe, u32 port_sel, u32 val)
  1077. {
  1078. if ((val & DP_PORT_EN) == 0)
  1079. return false;
  1080. if (HAS_PCH_CPT(dev_priv->dev)) {
  1081. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1082. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1083. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1084. return false;
  1085. } else {
  1086. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1087. return false;
  1088. }
  1089. return true;
  1090. }
  1091. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1092. enum pipe pipe, u32 val)
  1093. {
  1094. if ((val & SDVO_ENABLE) == 0)
  1095. return false;
  1096. if (HAS_PCH_CPT(dev_priv->dev)) {
  1097. if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
  1098. return false;
  1099. } else {
  1100. if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
  1101. return false;
  1102. }
  1103. return true;
  1104. }
  1105. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1106. enum pipe pipe, u32 val)
  1107. {
  1108. if ((val & LVDS_PORT_EN) == 0)
  1109. return false;
  1110. if (HAS_PCH_CPT(dev_priv->dev)) {
  1111. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1112. return false;
  1113. } else {
  1114. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1115. return false;
  1116. }
  1117. return true;
  1118. }
  1119. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1120. enum pipe pipe, u32 val)
  1121. {
  1122. if ((val & ADPA_DAC_ENABLE) == 0)
  1123. return false;
  1124. if (HAS_PCH_CPT(dev_priv->dev)) {
  1125. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1126. return false;
  1127. } else {
  1128. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1129. return false;
  1130. }
  1131. return true;
  1132. }
  1133. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1134. enum pipe pipe, int reg, u32 port_sel)
  1135. {
  1136. u32 val = I915_READ(reg);
  1137. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1138. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1139. reg, pipe_name(pipe));
  1140. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1141. && (val & DP_PIPEB_SELECT),
  1142. "IBX PCH dp port still using transcoder B\n");
  1143. }
  1144. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1145. enum pipe pipe, int reg)
  1146. {
  1147. u32 val = I915_READ(reg);
  1148. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1149. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1150. reg, pipe_name(pipe));
  1151. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
  1152. && (val & SDVO_PIPE_B_SELECT),
  1153. "IBX PCH hdmi port still using transcoder B\n");
  1154. }
  1155. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1156. enum pipe pipe)
  1157. {
  1158. int reg;
  1159. u32 val;
  1160. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1161. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1162. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1163. reg = PCH_ADPA;
  1164. val = I915_READ(reg);
  1165. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1166. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1167. pipe_name(pipe));
  1168. reg = PCH_LVDS;
  1169. val = I915_READ(reg);
  1170. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1171. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1172. pipe_name(pipe));
  1173. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
  1174. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
  1175. assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
  1176. }
  1177. static void vlv_enable_pll(struct intel_crtc *crtc)
  1178. {
  1179. struct drm_device *dev = crtc->base.dev;
  1180. struct drm_i915_private *dev_priv = dev->dev_private;
  1181. int reg = DPLL(crtc->pipe);
  1182. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1183. assert_pipe_disabled(dev_priv, crtc->pipe);
  1184. /* No really, not for ILK+ */
  1185. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
  1186. /* PLL is protected by panel, make sure we can write it */
  1187. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1188. assert_panel_unlocked(dev_priv, crtc->pipe);
  1189. I915_WRITE(reg, dpll);
  1190. POSTING_READ(reg);
  1191. udelay(150);
  1192. if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  1193. DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
  1194. I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
  1195. POSTING_READ(DPLL_MD(crtc->pipe));
  1196. /* We do this three times for luck */
  1197. I915_WRITE(reg, dpll);
  1198. POSTING_READ(reg);
  1199. udelay(150); /* wait for warmup */
  1200. I915_WRITE(reg, dpll);
  1201. POSTING_READ(reg);
  1202. udelay(150); /* wait for warmup */
  1203. I915_WRITE(reg, dpll);
  1204. POSTING_READ(reg);
  1205. udelay(150); /* wait for warmup */
  1206. }
  1207. static void i9xx_enable_pll(struct intel_crtc *crtc)
  1208. {
  1209. struct drm_device *dev = crtc->base.dev;
  1210. struct drm_i915_private *dev_priv = dev->dev_private;
  1211. int reg = DPLL(crtc->pipe);
  1212. u32 dpll = crtc->config.dpll_hw_state.dpll;
  1213. assert_pipe_disabled(dev_priv, crtc->pipe);
  1214. /* No really, not for ILK+ */
  1215. BUG_ON(dev_priv->info->gen >= 5);
  1216. /* PLL is protected by panel, make sure we can write it */
  1217. if (IS_MOBILE(dev) && !IS_I830(dev))
  1218. assert_panel_unlocked(dev_priv, crtc->pipe);
  1219. I915_WRITE(reg, dpll);
  1220. /* Wait for the clocks to stabilize. */
  1221. POSTING_READ(reg);
  1222. udelay(150);
  1223. if (INTEL_INFO(dev)->gen >= 4) {
  1224. I915_WRITE(DPLL_MD(crtc->pipe),
  1225. crtc->config.dpll_hw_state.dpll_md);
  1226. } else {
  1227. /* The pixel multiplier can only be updated once the
  1228. * DPLL is enabled and the clocks are stable.
  1229. *
  1230. * So write it again.
  1231. */
  1232. I915_WRITE(reg, dpll);
  1233. }
  1234. /* We do this three times for luck */
  1235. I915_WRITE(reg, dpll);
  1236. POSTING_READ(reg);
  1237. udelay(150); /* wait for warmup */
  1238. I915_WRITE(reg, dpll);
  1239. POSTING_READ(reg);
  1240. udelay(150); /* wait for warmup */
  1241. I915_WRITE(reg, dpll);
  1242. POSTING_READ(reg);
  1243. udelay(150); /* wait for warmup */
  1244. }
  1245. /**
  1246. * i9xx_disable_pll - disable a PLL
  1247. * @dev_priv: i915 private structure
  1248. * @pipe: pipe PLL to disable
  1249. *
  1250. * Disable the PLL for @pipe, making sure the pipe is off first.
  1251. *
  1252. * Note! This is for pre-ILK only.
  1253. */
  1254. static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1255. {
  1256. /* Don't disable pipe A or pipe A PLLs if needed */
  1257. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1258. return;
  1259. /* Make sure the pipe isn't still relying on us */
  1260. assert_pipe_disabled(dev_priv, pipe);
  1261. I915_WRITE(DPLL(pipe), 0);
  1262. POSTING_READ(DPLL(pipe));
  1263. }
  1264. void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
  1265. {
  1266. u32 port_mask;
  1267. if (!port)
  1268. port_mask = DPLL_PORTB_READY_MASK;
  1269. else
  1270. port_mask = DPLL_PORTC_READY_MASK;
  1271. if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
  1272. WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
  1273. 'B' + port, I915_READ(DPLL(0)));
  1274. }
  1275. /**
  1276. * ironlake_enable_shared_dpll - enable PCH PLL
  1277. * @dev_priv: i915 private structure
  1278. * @pipe: pipe PLL to enable
  1279. *
  1280. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1281. * drives the transcoder clock.
  1282. */
  1283. static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
  1284. {
  1285. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1286. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1287. /* PCH PLLs only available on ILK, SNB and IVB */
  1288. BUG_ON(dev_priv->info->gen < 5);
  1289. if (WARN_ON(pll == NULL))
  1290. return;
  1291. if (WARN_ON(pll->refcount == 0))
  1292. return;
  1293. DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
  1294. pll->name, pll->active, pll->on,
  1295. crtc->base.base.id);
  1296. if (pll->active++) {
  1297. WARN_ON(!pll->on);
  1298. assert_shared_dpll_enabled(dev_priv, pll);
  1299. return;
  1300. }
  1301. WARN_ON(pll->on);
  1302. DRM_DEBUG_KMS("enabling %s\n", pll->name);
  1303. pll->enable(dev_priv, pll);
  1304. pll->on = true;
  1305. }
  1306. static void intel_disable_shared_dpll(struct intel_crtc *crtc)
  1307. {
  1308. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  1309. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  1310. /* PCH only available on ILK+ */
  1311. BUG_ON(dev_priv->info->gen < 5);
  1312. if (WARN_ON(pll == NULL))
  1313. return;
  1314. if (WARN_ON(pll->refcount == 0))
  1315. return;
  1316. DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
  1317. pll->name, pll->active, pll->on,
  1318. crtc->base.base.id);
  1319. if (WARN_ON(pll->active == 0)) {
  1320. assert_shared_dpll_disabled(dev_priv, pll);
  1321. return;
  1322. }
  1323. assert_shared_dpll_enabled(dev_priv, pll);
  1324. WARN_ON(!pll->on);
  1325. if (--pll->active)
  1326. return;
  1327. DRM_DEBUG_KMS("disabling %s\n", pll->name);
  1328. pll->disable(dev_priv, pll);
  1329. pll->on = false;
  1330. }
  1331. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1332. enum pipe pipe)
  1333. {
  1334. struct drm_device *dev = dev_priv->dev;
  1335. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1336. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1337. uint32_t reg, val, pipeconf_val;
  1338. /* PCH only available on ILK+ */
  1339. BUG_ON(dev_priv->info->gen < 5);
  1340. /* Make sure PCH DPLL is enabled */
  1341. assert_shared_dpll_enabled(dev_priv,
  1342. intel_crtc_to_shared_dpll(intel_crtc));
  1343. /* FDI must be feeding us bits for PCH ports */
  1344. assert_fdi_tx_enabled(dev_priv, pipe);
  1345. assert_fdi_rx_enabled(dev_priv, pipe);
  1346. if (HAS_PCH_CPT(dev)) {
  1347. /* Workaround: Set the timing override bit before enabling the
  1348. * pch transcoder. */
  1349. reg = TRANS_CHICKEN2(pipe);
  1350. val = I915_READ(reg);
  1351. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1352. I915_WRITE(reg, val);
  1353. }
  1354. reg = PCH_TRANSCONF(pipe);
  1355. val = I915_READ(reg);
  1356. pipeconf_val = I915_READ(PIPECONF(pipe));
  1357. if (HAS_PCH_IBX(dev_priv->dev)) {
  1358. /*
  1359. * make the BPC in transcoder be consistent with
  1360. * that in pipeconf reg.
  1361. */
  1362. val &= ~PIPECONF_BPC_MASK;
  1363. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1364. }
  1365. val &= ~TRANS_INTERLACE_MASK;
  1366. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1367. if (HAS_PCH_IBX(dev_priv->dev) &&
  1368. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1369. val |= TRANS_LEGACY_INTERLACED_ILK;
  1370. else
  1371. val |= TRANS_INTERLACED;
  1372. else
  1373. val |= TRANS_PROGRESSIVE;
  1374. I915_WRITE(reg, val | TRANS_ENABLE);
  1375. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1376. DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
  1377. }
  1378. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1379. enum transcoder cpu_transcoder)
  1380. {
  1381. u32 val, pipeconf_val;
  1382. /* PCH only available on ILK+ */
  1383. BUG_ON(dev_priv->info->gen < 5);
  1384. /* FDI must be feeding us bits for PCH ports */
  1385. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1386. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1387. /* Workaround: set timing override bit. */
  1388. val = I915_READ(_TRANSA_CHICKEN2);
  1389. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1390. I915_WRITE(_TRANSA_CHICKEN2, val);
  1391. val = TRANS_ENABLE;
  1392. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1393. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1394. PIPECONF_INTERLACED_ILK)
  1395. val |= TRANS_INTERLACED;
  1396. else
  1397. val |= TRANS_PROGRESSIVE;
  1398. I915_WRITE(LPT_TRANSCONF, val);
  1399. if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
  1400. DRM_ERROR("Failed to enable PCH transcoder\n");
  1401. }
  1402. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1403. enum pipe pipe)
  1404. {
  1405. struct drm_device *dev = dev_priv->dev;
  1406. uint32_t reg, val;
  1407. /* FDI relies on the transcoder */
  1408. assert_fdi_tx_disabled(dev_priv, pipe);
  1409. assert_fdi_rx_disabled(dev_priv, pipe);
  1410. /* Ports must be off as well */
  1411. assert_pch_ports_disabled(dev_priv, pipe);
  1412. reg = PCH_TRANSCONF(pipe);
  1413. val = I915_READ(reg);
  1414. val &= ~TRANS_ENABLE;
  1415. I915_WRITE(reg, val);
  1416. /* wait for PCH transcoder off, transcoder state */
  1417. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1418. DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
  1419. if (!HAS_PCH_IBX(dev)) {
  1420. /* Workaround: Clear the timing override chicken bit again. */
  1421. reg = TRANS_CHICKEN2(pipe);
  1422. val = I915_READ(reg);
  1423. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1424. I915_WRITE(reg, val);
  1425. }
  1426. }
  1427. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1428. {
  1429. u32 val;
  1430. val = I915_READ(LPT_TRANSCONF);
  1431. val &= ~TRANS_ENABLE;
  1432. I915_WRITE(LPT_TRANSCONF, val);
  1433. /* wait for PCH transcoder off, transcoder state */
  1434. if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
  1435. DRM_ERROR("Failed to disable PCH transcoder\n");
  1436. /* Workaround: clear timing override bit. */
  1437. val = I915_READ(_TRANSA_CHICKEN2);
  1438. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1439. I915_WRITE(_TRANSA_CHICKEN2, val);
  1440. }
  1441. /**
  1442. * intel_enable_pipe - enable a pipe, asserting requirements
  1443. * @dev_priv: i915 private structure
  1444. * @pipe: pipe to enable
  1445. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1446. *
  1447. * Enable @pipe, making sure that various hardware specific requirements
  1448. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1449. *
  1450. * @pipe should be %PIPE_A or %PIPE_B.
  1451. *
  1452. * Will wait until the pipe is actually running (i.e. first vblank) before
  1453. * returning.
  1454. */
  1455. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1456. bool pch_port)
  1457. {
  1458. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1459. pipe);
  1460. enum pipe pch_transcoder;
  1461. int reg;
  1462. u32 val;
  1463. assert_planes_disabled(dev_priv, pipe);
  1464. assert_sprites_disabled(dev_priv, pipe);
  1465. if (HAS_PCH_LPT(dev_priv->dev))
  1466. pch_transcoder = TRANSCODER_A;
  1467. else
  1468. pch_transcoder = pipe;
  1469. /*
  1470. * A pipe without a PLL won't actually be able to drive bits from
  1471. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1472. * need the check.
  1473. */
  1474. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1475. assert_pll_enabled(dev_priv, pipe);
  1476. else {
  1477. if (pch_port) {
  1478. /* if driving the PCH, we need FDI enabled */
  1479. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1480. assert_fdi_tx_pll_enabled(dev_priv,
  1481. (enum pipe) cpu_transcoder);
  1482. }
  1483. /* FIXME: assert CPU port conditions for SNB+ */
  1484. }
  1485. reg = PIPECONF(cpu_transcoder);
  1486. val = I915_READ(reg);
  1487. if (val & PIPECONF_ENABLE)
  1488. return;
  1489. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1490. intel_wait_for_vblank(dev_priv->dev, pipe);
  1491. }
  1492. /**
  1493. * intel_disable_pipe - disable a pipe, asserting requirements
  1494. * @dev_priv: i915 private structure
  1495. * @pipe: pipe to disable
  1496. *
  1497. * Disable @pipe, making sure that various hardware specific requirements
  1498. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1499. *
  1500. * @pipe should be %PIPE_A or %PIPE_B.
  1501. *
  1502. * Will wait until the pipe has shut down before returning.
  1503. */
  1504. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1505. enum pipe pipe)
  1506. {
  1507. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1508. pipe);
  1509. int reg;
  1510. u32 val;
  1511. /*
  1512. * Make sure planes won't keep trying to pump pixels to us,
  1513. * or we might hang the display.
  1514. */
  1515. assert_planes_disabled(dev_priv, pipe);
  1516. assert_sprites_disabled(dev_priv, pipe);
  1517. /* Don't disable pipe A or pipe A PLLs if needed */
  1518. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1519. return;
  1520. reg = PIPECONF(cpu_transcoder);
  1521. val = I915_READ(reg);
  1522. if ((val & PIPECONF_ENABLE) == 0)
  1523. return;
  1524. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1525. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1526. }
  1527. /*
  1528. * Plane regs are double buffered, going from enabled->disabled needs a
  1529. * trigger in order to latch. The display address reg provides this.
  1530. */
  1531. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1532. enum plane plane)
  1533. {
  1534. if (dev_priv->info->gen >= 4)
  1535. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1536. else
  1537. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1538. }
  1539. /**
  1540. * intel_enable_plane - enable a display plane on a given pipe
  1541. * @dev_priv: i915 private structure
  1542. * @plane: plane to enable
  1543. * @pipe: pipe being fed
  1544. *
  1545. * Enable @plane on @pipe, making sure that @pipe is running first.
  1546. */
  1547. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1548. enum plane plane, enum pipe pipe)
  1549. {
  1550. int reg;
  1551. u32 val;
  1552. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1553. assert_pipe_enabled(dev_priv, pipe);
  1554. reg = DSPCNTR(plane);
  1555. val = I915_READ(reg);
  1556. if (val & DISPLAY_PLANE_ENABLE)
  1557. return;
  1558. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1559. intel_flush_display_plane(dev_priv, plane);
  1560. intel_wait_for_vblank(dev_priv->dev, pipe);
  1561. }
  1562. /**
  1563. * intel_disable_plane - disable a display plane
  1564. * @dev_priv: i915 private structure
  1565. * @plane: plane to disable
  1566. * @pipe: pipe consuming the data
  1567. *
  1568. * Disable @plane; should be an independent operation.
  1569. */
  1570. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1571. enum plane plane, enum pipe pipe)
  1572. {
  1573. int reg;
  1574. u32 val;
  1575. reg = DSPCNTR(plane);
  1576. val = I915_READ(reg);
  1577. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1578. return;
  1579. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1580. intel_flush_display_plane(dev_priv, plane);
  1581. intel_wait_for_vblank(dev_priv->dev, pipe);
  1582. }
  1583. static bool need_vtd_wa(struct drm_device *dev)
  1584. {
  1585. #ifdef CONFIG_INTEL_IOMMU
  1586. if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
  1587. return true;
  1588. #endif
  1589. return false;
  1590. }
  1591. int
  1592. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1593. struct drm_i915_gem_object *obj,
  1594. struct intel_ring_buffer *pipelined)
  1595. {
  1596. struct drm_i915_private *dev_priv = dev->dev_private;
  1597. u32 alignment;
  1598. int ret;
  1599. switch (obj->tiling_mode) {
  1600. case I915_TILING_NONE:
  1601. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1602. alignment = 128 * 1024;
  1603. else if (INTEL_INFO(dev)->gen >= 4)
  1604. alignment = 4 * 1024;
  1605. else
  1606. alignment = 64 * 1024;
  1607. break;
  1608. case I915_TILING_X:
  1609. /* pin() will align the object as required by fence */
  1610. alignment = 0;
  1611. break;
  1612. case I915_TILING_Y:
  1613. /* Despite that we check this in framebuffer_init userspace can
  1614. * screw us over and change the tiling after the fact. Only
  1615. * pinned buffers can't change their tiling. */
  1616. DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
  1617. return -EINVAL;
  1618. default:
  1619. BUG();
  1620. }
  1621. /* Note that the w/a also requires 64 PTE of padding following the
  1622. * bo. We currently fill all unused PTE with the shadow page and so
  1623. * we should always have valid PTE following the scanout preventing
  1624. * the VT-d warning.
  1625. */
  1626. if (need_vtd_wa(dev) && alignment < 256 * 1024)
  1627. alignment = 256 * 1024;
  1628. dev_priv->mm.interruptible = false;
  1629. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1630. if (ret)
  1631. goto err_interruptible;
  1632. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1633. * fence, whereas 965+ only requires a fence if using
  1634. * framebuffer compression. For simplicity, we always install
  1635. * a fence as the cost is not that onerous.
  1636. */
  1637. ret = i915_gem_object_get_fence(obj);
  1638. if (ret)
  1639. goto err_unpin;
  1640. i915_gem_object_pin_fence(obj);
  1641. dev_priv->mm.interruptible = true;
  1642. return 0;
  1643. err_unpin:
  1644. i915_gem_object_unpin(obj);
  1645. err_interruptible:
  1646. dev_priv->mm.interruptible = true;
  1647. return ret;
  1648. }
  1649. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1650. {
  1651. i915_gem_object_unpin_fence(obj);
  1652. i915_gem_object_unpin(obj);
  1653. }
  1654. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1655. * is assumed to be a power-of-two. */
  1656. unsigned long intel_gen4_compute_page_offset(int *x, int *y,
  1657. unsigned int tiling_mode,
  1658. unsigned int cpp,
  1659. unsigned int pitch)
  1660. {
  1661. if (tiling_mode != I915_TILING_NONE) {
  1662. unsigned int tile_rows, tiles;
  1663. tile_rows = *y / 8;
  1664. *y %= 8;
  1665. tiles = *x / (512/cpp);
  1666. *x %= 512/cpp;
  1667. return tile_rows * pitch * 8 + tiles * 4096;
  1668. } else {
  1669. unsigned int offset;
  1670. offset = *y * pitch + *x * cpp;
  1671. *y = 0;
  1672. *x = (offset & 4095) / cpp;
  1673. return offset & -4096;
  1674. }
  1675. }
  1676. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1677. int x, int y)
  1678. {
  1679. struct drm_device *dev = crtc->dev;
  1680. struct drm_i915_private *dev_priv = dev->dev_private;
  1681. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1682. struct intel_framebuffer *intel_fb;
  1683. struct drm_i915_gem_object *obj;
  1684. int plane = intel_crtc->plane;
  1685. unsigned long linear_offset;
  1686. u32 dspcntr;
  1687. u32 reg;
  1688. switch (plane) {
  1689. case 0:
  1690. case 1:
  1691. break;
  1692. default:
  1693. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1694. return -EINVAL;
  1695. }
  1696. intel_fb = to_intel_framebuffer(fb);
  1697. obj = intel_fb->obj;
  1698. reg = DSPCNTR(plane);
  1699. dspcntr = I915_READ(reg);
  1700. /* Mask out pixel format bits in case we change it */
  1701. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1702. switch (fb->pixel_format) {
  1703. case DRM_FORMAT_C8:
  1704. dspcntr |= DISPPLANE_8BPP;
  1705. break;
  1706. case DRM_FORMAT_XRGB1555:
  1707. case DRM_FORMAT_ARGB1555:
  1708. dspcntr |= DISPPLANE_BGRX555;
  1709. break;
  1710. case DRM_FORMAT_RGB565:
  1711. dspcntr |= DISPPLANE_BGRX565;
  1712. break;
  1713. case DRM_FORMAT_XRGB8888:
  1714. case DRM_FORMAT_ARGB8888:
  1715. dspcntr |= DISPPLANE_BGRX888;
  1716. break;
  1717. case DRM_FORMAT_XBGR8888:
  1718. case DRM_FORMAT_ABGR8888:
  1719. dspcntr |= DISPPLANE_RGBX888;
  1720. break;
  1721. case DRM_FORMAT_XRGB2101010:
  1722. case DRM_FORMAT_ARGB2101010:
  1723. dspcntr |= DISPPLANE_BGRX101010;
  1724. break;
  1725. case DRM_FORMAT_XBGR2101010:
  1726. case DRM_FORMAT_ABGR2101010:
  1727. dspcntr |= DISPPLANE_RGBX101010;
  1728. break;
  1729. default:
  1730. BUG();
  1731. }
  1732. if (INTEL_INFO(dev)->gen >= 4) {
  1733. if (obj->tiling_mode != I915_TILING_NONE)
  1734. dspcntr |= DISPPLANE_TILED;
  1735. else
  1736. dspcntr &= ~DISPPLANE_TILED;
  1737. }
  1738. if (IS_G4X(dev))
  1739. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1740. I915_WRITE(reg, dspcntr);
  1741. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1742. if (INTEL_INFO(dev)->gen >= 4) {
  1743. intel_crtc->dspaddr_offset =
  1744. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1745. fb->bits_per_pixel / 8,
  1746. fb->pitches[0]);
  1747. linear_offset -= intel_crtc->dspaddr_offset;
  1748. } else {
  1749. intel_crtc->dspaddr_offset = linear_offset;
  1750. }
  1751. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1752. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1753. fb->pitches[0]);
  1754. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1755. if (INTEL_INFO(dev)->gen >= 4) {
  1756. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1757. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1758. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1759. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1760. } else
  1761. I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
  1762. POSTING_READ(reg);
  1763. return 0;
  1764. }
  1765. static int ironlake_update_plane(struct drm_crtc *crtc,
  1766. struct drm_framebuffer *fb, int x, int y)
  1767. {
  1768. struct drm_device *dev = crtc->dev;
  1769. struct drm_i915_private *dev_priv = dev->dev_private;
  1770. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1771. struct intel_framebuffer *intel_fb;
  1772. struct drm_i915_gem_object *obj;
  1773. int plane = intel_crtc->plane;
  1774. unsigned long linear_offset;
  1775. u32 dspcntr;
  1776. u32 reg;
  1777. switch (plane) {
  1778. case 0:
  1779. case 1:
  1780. case 2:
  1781. break;
  1782. default:
  1783. DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
  1784. return -EINVAL;
  1785. }
  1786. intel_fb = to_intel_framebuffer(fb);
  1787. obj = intel_fb->obj;
  1788. reg = DSPCNTR(plane);
  1789. dspcntr = I915_READ(reg);
  1790. /* Mask out pixel format bits in case we change it */
  1791. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1792. switch (fb->pixel_format) {
  1793. case DRM_FORMAT_C8:
  1794. dspcntr |= DISPPLANE_8BPP;
  1795. break;
  1796. case DRM_FORMAT_RGB565:
  1797. dspcntr |= DISPPLANE_BGRX565;
  1798. break;
  1799. case DRM_FORMAT_XRGB8888:
  1800. case DRM_FORMAT_ARGB8888:
  1801. dspcntr |= DISPPLANE_BGRX888;
  1802. break;
  1803. case DRM_FORMAT_XBGR8888:
  1804. case DRM_FORMAT_ABGR8888:
  1805. dspcntr |= DISPPLANE_RGBX888;
  1806. break;
  1807. case DRM_FORMAT_XRGB2101010:
  1808. case DRM_FORMAT_ARGB2101010:
  1809. dspcntr |= DISPPLANE_BGRX101010;
  1810. break;
  1811. case DRM_FORMAT_XBGR2101010:
  1812. case DRM_FORMAT_ABGR2101010:
  1813. dspcntr |= DISPPLANE_RGBX101010;
  1814. break;
  1815. default:
  1816. BUG();
  1817. }
  1818. if (obj->tiling_mode != I915_TILING_NONE)
  1819. dspcntr |= DISPPLANE_TILED;
  1820. else
  1821. dspcntr &= ~DISPPLANE_TILED;
  1822. /* must disable */
  1823. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1824. I915_WRITE(reg, dspcntr);
  1825. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1826. intel_crtc->dspaddr_offset =
  1827. intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
  1828. fb->bits_per_pixel / 8,
  1829. fb->pitches[0]);
  1830. linear_offset -= intel_crtc->dspaddr_offset;
  1831. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1832. i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
  1833. fb->pitches[0]);
  1834. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1835. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1836. i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  1837. if (IS_HASWELL(dev)) {
  1838. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  1839. } else {
  1840. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1841. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1842. }
  1843. POSTING_READ(reg);
  1844. return 0;
  1845. }
  1846. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1847. static int
  1848. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1849. int x, int y, enum mode_set_atomic state)
  1850. {
  1851. struct drm_device *dev = crtc->dev;
  1852. struct drm_i915_private *dev_priv = dev->dev_private;
  1853. if (dev_priv->display.disable_fbc)
  1854. dev_priv->display.disable_fbc(dev);
  1855. intel_increase_pllclock(crtc);
  1856. return dev_priv->display.update_plane(crtc, fb, x, y);
  1857. }
  1858. void intel_display_handle_reset(struct drm_device *dev)
  1859. {
  1860. struct drm_i915_private *dev_priv = dev->dev_private;
  1861. struct drm_crtc *crtc;
  1862. /*
  1863. * Flips in the rings have been nuked by the reset,
  1864. * so complete all pending flips so that user space
  1865. * will get its events and not get stuck.
  1866. *
  1867. * Also update the base address of all primary
  1868. * planes to the the last fb to make sure we're
  1869. * showing the correct fb after a reset.
  1870. *
  1871. * Need to make two loops over the crtcs so that we
  1872. * don't try to grab a crtc mutex before the
  1873. * pending_flip_queue really got woken up.
  1874. */
  1875. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1876. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1877. enum plane plane = intel_crtc->plane;
  1878. intel_prepare_page_flip(dev, plane);
  1879. intel_finish_page_flip_plane(dev, plane);
  1880. }
  1881. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1882. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1883. mutex_lock(&crtc->mutex);
  1884. if (intel_crtc->active)
  1885. dev_priv->display.update_plane(crtc, crtc->fb,
  1886. crtc->x, crtc->y);
  1887. mutex_unlock(&crtc->mutex);
  1888. }
  1889. }
  1890. static int
  1891. intel_finish_fb(struct drm_framebuffer *old_fb)
  1892. {
  1893. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1894. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1895. bool was_interruptible = dev_priv->mm.interruptible;
  1896. int ret;
  1897. /* Big Hammer, we also need to ensure that any pending
  1898. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1899. * current scanout is retired before unpinning the old
  1900. * framebuffer.
  1901. *
  1902. * This should only fail upon a hung GPU, in which case we
  1903. * can safely continue.
  1904. */
  1905. dev_priv->mm.interruptible = false;
  1906. ret = i915_gem_object_finish_gpu(obj);
  1907. dev_priv->mm.interruptible = was_interruptible;
  1908. return ret;
  1909. }
  1910. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  1911. {
  1912. struct drm_device *dev = crtc->dev;
  1913. struct drm_i915_master_private *master_priv;
  1914. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1915. if (!dev->primary->master)
  1916. return;
  1917. master_priv = dev->primary->master->driver_priv;
  1918. if (!master_priv->sarea_priv)
  1919. return;
  1920. switch (intel_crtc->pipe) {
  1921. case 0:
  1922. master_priv->sarea_priv->pipeA_x = x;
  1923. master_priv->sarea_priv->pipeA_y = y;
  1924. break;
  1925. case 1:
  1926. master_priv->sarea_priv->pipeB_x = x;
  1927. master_priv->sarea_priv->pipeB_y = y;
  1928. break;
  1929. default:
  1930. break;
  1931. }
  1932. }
  1933. static int
  1934. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1935. struct drm_framebuffer *fb)
  1936. {
  1937. struct drm_device *dev = crtc->dev;
  1938. struct drm_i915_private *dev_priv = dev->dev_private;
  1939. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1940. struct drm_framebuffer *old_fb;
  1941. int ret;
  1942. /* no fb bound */
  1943. if (!fb) {
  1944. DRM_ERROR("No FB bound\n");
  1945. return 0;
  1946. }
  1947. if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
  1948. DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
  1949. plane_name(intel_crtc->plane),
  1950. INTEL_INFO(dev)->num_pipes);
  1951. return -EINVAL;
  1952. }
  1953. mutex_lock(&dev->struct_mutex);
  1954. ret = intel_pin_and_fence_fb_obj(dev,
  1955. to_intel_framebuffer(fb)->obj,
  1956. NULL);
  1957. if (ret != 0) {
  1958. mutex_unlock(&dev->struct_mutex);
  1959. DRM_ERROR("pin & fence failed\n");
  1960. return ret;
  1961. }
  1962. /* Update pipe size and adjust fitter if needed */
  1963. if (i915_fastboot) {
  1964. I915_WRITE(PIPESRC(intel_crtc->pipe),
  1965. ((crtc->mode.hdisplay - 1) << 16) |
  1966. (crtc->mode.vdisplay - 1));
  1967. if (!intel_crtc->config.pch_pfit.size &&
  1968. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  1969. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  1970. I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
  1971. I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
  1972. I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
  1973. }
  1974. }
  1975. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  1976. if (ret) {
  1977. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  1978. mutex_unlock(&dev->struct_mutex);
  1979. DRM_ERROR("failed to update base address\n");
  1980. return ret;
  1981. }
  1982. old_fb = crtc->fb;
  1983. crtc->fb = fb;
  1984. crtc->x = x;
  1985. crtc->y = y;
  1986. if (old_fb) {
  1987. if (intel_crtc->active && old_fb != fb)
  1988. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1989. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  1990. }
  1991. intel_update_fbc(dev);
  1992. intel_edp_psr_update(dev);
  1993. mutex_unlock(&dev->struct_mutex);
  1994. intel_crtc_update_sarea_pos(crtc, x, y);
  1995. return 0;
  1996. }
  1997. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  1998. {
  1999. struct drm_device *dev = crtc->dev;
  2000. struct drm_i915_private *dev_priv = dev->dev_private;
  2001. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2002. int pipe = intel_crtc->pipe;
  2003. u32 reg, temp;
  2004. /* enable normal train */
  2005. reg = FDI_TX_CTL(pipe);
  2006. temp = I915_READ(reg);
  2007. if (IS_IVYBRIDGE(dev)) {
  2008. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2009. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2010. } else {
  2011. temp &= ~FDI_LINK_TRAIN_NONE;
  2012. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2013. }
  2014. I915_WRITE(reg, temp);
  2015. reg = FDI_RX_CTL(pipe);
  2016. temp = I915_READ(reg);
  2017. if (HAS_PCH_CPT(dev)) {
  2018. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2019. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2020. } else {
  2021. temp &= ~FDI_LINK_TRAIN_NONE;
  2022. temp |= FDI_LINK_TRAIN_NONE;
  2023. }
  2024. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2025. /* wait one idle pattern time */
  2026. POSTING_READ(reg);
  2027. udelay(1000);
  2028. /* IVB wants error correction enabled */
  2029. if (IS_IVYBRIDGE(dev))
  2030. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2031. FDI_FE_ERRC_ENABLE);
  2032. }
  2033. static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
  2034. {
  2035. return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
  2036. }
  2037. static void ivb_modeset_global_resources(struct drm_device *dev)
  2038. {
  2039. struct drm_i915_private *dev_priv = dev->dev_private;
  2040. struct intel_crtc *pipe_B_crtc =
  2041. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2042. struct intel_crtc *pipe_C_crtc =
  2043. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2044. uint32_t temp;
  2045. /*
  2046. * When everything is off disable fdi C so that we could enable fdi B
  2047. * with all lanes. Note that we don't care about enabled pipes without
  2048. * an enabled pch encoder.
  2049. */
  2050. if (!pipe_has_enabled_pch(pipe_B_crtc) &&
  2051. !pipe_has_enabled_pch(pipe_C_crtc)) {
  2052. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2053. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2054. temp = I915_READ(SOUTH_CHICKEN1);
  2055. temp &= ~FDI_BC_BIFURCATION_SELECT;
  2056. DRM_DEBUG_KMS("disabling fdi C rx\n");
  2057. I915_WRITE(SOUTH_CHICKEN1, temp);
  2058. }
  2059. }
  2060. /* The FDI link training functions for ILK/Ibexpeak. */
  2061. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2062. {
  2063. struct drm_device *dev = crtc->dev;
  2064. struct drm_i915_private *dev_priv = dev->dev_private;
  2065. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2066. int pipe = intel_crtc->pipe;
  2067. int plane = intel_crtc->plane;
  2068. u32 reg, temp, tries;
  2069. /* FDI needs bits from pipe & plane first */
  2070. assert_pipe_enabled(dev_priv, pipe);
  2071. assert_plane_enabled(dev_priv, plane);
  2072. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2073. for train result */
  2074. reg = FDI_RX_IMR(pipe);
  2075. temp = I915_READ(reg);
  2076. temp &= ~FDI_RX_SYMBOL_LOCK;
  2077. temp &= ~FDI_RX_BIT_LOCK;
  2078. I915_WRITE(reg, temp);
  2079. I915_READ(reg);
  2080. udelay(150);
  2081. /* enable CPU FDI TX and PCH FDI RX */
  2082. reg = FDI_TX_CTL(pipe);
  2083. temp = I915_READ(reg);
  2084. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2085. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2086. temp &= ~FDI_LINK_TRAIN_NONE;
  2087. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2088. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2089. reg = FDI_RX_CTL(pipe);
  2090. temp = I915_READ(reg);
  2091. temp &= ~FDI_LINK_TRAIN_NONE;
  2092. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2093. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2094. POSTING_READ(reg);
  2095. udelay(150);
  2096. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2097. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2098. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2099. FDI_RX_PHASE_SYNC_POINTER_EN);
  2100. reg = FDI_RX_IIR(pipe);
  2101. for (tries = 0; tries < 5; tries++) {
  2102. temp = I915_READ(reg);
  2103. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2104. if ((temp & FDI_RX_BIT_LOCK)) {
  2105. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2106. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2107. break;
  2108. }
  2109. }
  2110. if (tries == 5)
  2111. DRM_ERROR("FDI train 1 fail!\n");
  2112. /* Train 2 */
  2113. reg = FDI_TX_CTL(pipe);
  2114. temp = I915_READ(reg);
  2115. temp &= ~FDI_LINK_TRAIN_NONE;
  2116. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2117. I915_WRITE(reg, temp);
  2118. reg = FDI_RX_CTL(pipe);
  2119. temp = I915_READ(reg);
  2120. temp &= ~FDI_LINK_TRAIN_NONE;
  2121. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2122. I915_WRITE(reg, temp);
  2123. POSTING_READ(reg);
  2124. udelay(150);
  2125. reg = FDI_RX_IIR(pipe);
  2126. for (tries = 0; tries < 5; tries++) {
  2127. temp = I915_READ(reg);
  2128. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2129. if (temp & FDI_RX_SYMBOL_LOCK) {
  2130. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2131. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2132. break;
  2133. }
  2134. }
  2135. if (tries == 5)
  2136. DRM_ERROR("FDI train 2 fail!\n");
  2137. DRM_DEBUG_KMS("FDI train done\n");
  2138. }
  2139. static const int snb_b_fdi_train_param[] = {
  2140. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2141. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2142. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2143. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2144. };
  2145. /* The FDI link training functions for SNB/Cougarpoint. */
  2146. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2147. {
  2148. struct drm_device *dev = crtc->dev;
  2149. struct drm_i915_private *dev_priv = dev->dev_private;
  2150. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2151. int pipe = intel_crtc->pipe;
  2152. u32 reg, temp, i, retry;
  2153. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2154. for train result */
  2155. reg = FDI_RX_IMR(pipe);
  2156. temp = I915_READ(reg);
  2157. temp &= ~FDI_RX_SYMBOL_LOCK;
  2158. temp &= ~FDI_RX_BIT_LOCK;
  2159. I915_WRITE(reg, temp);
  2160. POSTING_READ(reg);
  2161. udelay(150);
  2162. /* enable CPU FDI TX and PCH FDI RX */
  2163. reg = FDI_TX_CTL(pipe);
  2164. temp = I915_READ(reg);
  2165. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2166. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2167. temp &= ~FDI_LINK_TRAIN_NONE;
  2168. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2169. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2170. /* SNB-B */
  2171. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2172. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2173. I915_WRITE(FDI_RX_MISC(pipe),
  2174. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2175. reg = FDI_RX_CTL(pipe);
  2176. temp = I915_READ(reg);
  2177. if (HAS_PCH_CPT(dev)) {
  2178. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2179. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2180. } else {
  2181. temp &= ~FDI_LINK_TRAIN_NONE;
  2182. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2183. }
  2184. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2185. POSTING_READ(reg);
  2186. udelay(150);
  2187. for (i = 0; i < 4; i++) {
  2188. reg = FDI_TX_CTL(pipe);
  2189. temp = I915_READ(reg);
  2190. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2191. temp |= snb_b_fdi_train_param[i];
  2192. I915_WRITE(reg, temp);
  2193. POSTING_READ(reg);
  2194. udelay(500);
  2195. for (retry = 0; retry < 5; retry++) {
  2196. reg = FDI_RX_IIR(pipe);
  2197. temp = I915_READ(reg);
  2198. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2199. if (temp & FDI_RX_BIT_LOCK) {
  2200. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2201. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2202. break;
  2203. }
  2204. udelay(50);
  2205. }
  2206. if (retry < 5)
  2207. break;
  2208. }
  2209. if (i == 4)
  2210. DRM_ERROR("FDI train 1 fail!\n");
  2211. /* Train 2 */
  2212. reg = FDI_TX_CTL(pipe);
  2213. temp = I915_READ(reg);
  2214. temp &= ~FDI_LINK_TRAIN_NONE;
  2215. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2216. if (IS_GEN6(dev)) {
  2217. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2218. /* SNB-B */
  2219. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2220. }
  2221. I915_WRITE(reg, temp);
  2222. reg = FDI_RX_CTL(pipe);
  2223. temp = I915_READ(reg);
  2224. if (HAS_PCH_CPT(dev)) {
  2225. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2226. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2227. } else {
  2228. temp &= ~FDI_LINK_TRAIN_NONE;
  2229. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2230. }
  2231. I915_WRITE(reg, temp);
  2232. POSTING_READ(reg);
  2233. udelay(150);
  2234. for (i = 0; i < 4; i++) {
  2235. reg = FDI_TX_CTL(pipe);
  2236. temp = I915_READ(reg);
  2237. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2238. temp |= snb_b_fdi_train_param[i];
  2239. I915_WRITE(reg, temp);
  2240. POSTING_READ(reg);
  2241. udelay(500);
  2242. for (retry = 0; retry < 5; retry++) {
  2243. reg = FDI_RX_IIR(pipe);
  2244. temp = I915_READ(reg);
  2245. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2246. if (temp & FDI_RX_SYMBOL_LOCK) {
  2247. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2248. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2249. break;
  2250. }
  2251. udelay(50);
  2252. }
  2253. if (retry < 5)
  2254. break;
  2255. }
  2256. if (i == 4)
  2257. DRM_ERROR("FDI train 2 fail!\n");
  2258. DRM_DEBUG_KMS("FDI train done.\n");
  2259. }
  2260. /* Manual link training for Ivy Bridge A0 parts */
  2261. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2262. {
  2263. struct drm_device *dev = crtc->dev;
  2264. struct drm_i915_private *dev_priv = dev->dev_private;
  2265. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2266. int pipe = intel_crtc->pipe;
  2267. u32 reg, temp, i;
  2268. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2269. for train result */
  2270. reg = FDI_RX_IMR(pipe);
  2271. temp = I915_READ(reg);
  2272. temp &= ~FDI_RX_SYMBOL_LOCK;
  2273. temp &= ~FDI_RX_BIT_LOCK;
  2274. I915_WRITE(reg, temp);
  2275. POSTING_READ(reg);
  2276. udelay(150);
  2277. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2278. I915_READ(FDI_RX_IIR(pipe)));
  2279. /* enable CPU FDI TX and PCH FDI RX */
  2280. reg = FDI_TX_CTL(pipe);
  2281. temp = I915_READ(reg);
  2282. temp &= ~FDI_DP_PORT_WIDTH_MASK;
  2283. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2284. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2285. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2286. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2287. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2288. temp |= FDI_COMPOSITE_SYNC;
  2289. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2290. I915_WRITE(FDI_RX_MISC(pipe),
  2291. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2292. reg = FDI_RX_CTL(pipe);
  2293. temp = I915_READ(reg);
  2294. temp &= ~FDI_LINK_TRAIN_AUTO;
  2295. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2296. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2297. temp |= FDI_COMPOSITE_SYNC;
  2298. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2299. POSTING_READ(reg);
  2300. udelay(150);
  2301. for (i = 0; i < 4; i++) {
  2302. reg = FDI_TX_CTL(pipe);
  2303. temp = I915_READ(reg);
  2304. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2305. temp |= snb_b_fdi_train_param[i];
  2306. I915_WRITE(reg, temp);
  2307. POSTING_READ(reg);
  2308. udelay(500);
  2309. reg = FDI_RX_IIR(pipe);
  2310. temp = I915_READ(reg);
  2311. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2312. if (temp & FDI_RX_BIT_LOCK ||
  2313. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2314. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2315. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
  2316. break;
  2317. }
  2318. }
  2319. if (i == 4)
  2320. DRM_ERROR("FDI train 1 fail!\n");
  2321. /* Train 2 */
  2322. reg = FDI_TX_CTL(pipe);
  2323. temp = I915_READ(reg);
  2324. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2325. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2326. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2327. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2328. I915_WRITE(reg, temp);
  2329. reg = FDI_RX_CTL(pipe);
  2330. temp = I915_READ(reg);
  2331. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2332. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2333. I915_WRITE(reg, temp);
  2334. POSTING_READ(reg);
  2335. udelay(150);
  2336. for (i = 0; i < 4; i++) {
  2337. reg = FDI_TX_CTL(pipe);
  2338. temp = I915_READ(reg);
  2339. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2340. temp |= snb_b_fdi_train_param[i];
  2341. I915_WRITE(reg, temp);
  2342. POSTING_READ(reg);
  2343. udelay(500);
  2344. reg = FDI_RX_IIR(pipe);
  2345. temp = I915_READ(reg);
  2346. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2347. if (temp & FDI_RX_SYMBOL_LOCK) {
  2348. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2349. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
  2350. break;
  2351. }
  2352. }
  2353. if (i == 4)
  2354. DRM_ERROR("FDI train 2 fail!\n");
  2355. DRM_DEBUG_KMS("FDI train done.\n");
  2356. }
  2357. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2358. {
  2359. struct drm_device *dev = intel_crtc->base.dev;
  2360. struct drm_i915_private *dev_priv = dev->dev_private;
  2361. int pipe = intel_crtc->pipe;
  2362. u32 reg, temp;
  2363. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2364. reg = FDI_RX_CTL(pipe);
  2365. temp = I915_READ(reg);
  2366. temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
  2367. temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
  2368. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2369. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2370. POSTING_READ(reg);
  2371. udelay(200);
  2372. /* Switch from Rawclk to PCDclk */
  2373. temp = I915_READ(reg);
  2374. I915_WRITE(reg, temp | FDI_PCDCLK);
  2375. POSTING_READ(reg);
  2376. udelay(200);
  2377. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2378. reg = FDI_TX_CTL(pipe);
  2379. temp = I915_READ(reg);
  2380. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2381. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2382. POSTING_READ(reg);
  2383. udelay(100);
  2384. }
  2385. }
  2386. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2387. {
  2388. struct drm_device *dev = intel_crtc->base.dev;
  2389. struct drm_i915_private *dev_priv = dev->dev_private;
  2390. int pipe = intel_crtc->pipe;
  2391. u32 reg, temp;
  2392. /* Switch from PCDclk to Rawclk */
  2393. reg = FDI_RX_CTL(pipe);
  2394. temp = I915_READ(reg);
  2395. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2396. /* Disable CPU FDI TX PLL */
  2397. reg = FDI_TX_CTL(pipe);
  2398. temp = I915_READ(reg);
  2399. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2400. POSTING_READ(reg);
  2401. udelay(100);
  2402. reg = FDI_RX_CTL(pipe);
  2403. temp = I915_READ(reg);
  2404. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2405. /* Wait for the clocks to turn off. */
  2406. POSTING_READ(reg);
  2407. udelay(100);
  2408. }
  2409. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2410. {
  2411. struct drm_device *dev = crtc->dev;
  2412. struct drm_i915_private *dev_priv = dev->dev_private;
  2413. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2414. int pipe = intel_crtc->pipe;
  2415. u32 reg, temp;
  2416. /* disable CPU FDI tx and PCH FDI rx */
  2417. reg = FDI_TX_CTL(pipe);
  2418. temp = I915_READ(reg);
  2419. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2420. POSTING_READ(reg);
  2421. reg = FDI_RX_CTL(pipe);
  2422. temp = I915_READ(reg);
  2423. temp &= ~(0x7 << 16);
  2424. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2425. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2426. POSTING_READ(reg);
  2427. udelay(100);
  2428. /* Ironlake workaround, disable clock pointer after downing FDI */
  2429. if (HAS_PCH_IBX(dev)) {
  2430. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2431. }
  2432. /* still set train pattern 1 */
  2433. reg = FDI_TX_CTL(pipe);
  2434. temp = I915_READ(reg);
  2435. temp &= ~FDI_LINK_TRAIN_NONE;
  2436. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2437. I915_WRITE(reg, temp);
  2438. reg = FDI_RX_CTL(pipe);
  2439. temp = I915_READ(reg);
  2440. if (HAS_PCH_CPT(dev)) {
  2441. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2442. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2443. } else {
  2444. temp &= ~FDI_LINK_TRAIN_NONE;
  2445. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2446. }
  2447. /* BPC in FDI rx is consistent with that in PIPECONF */
  2448. temp &= ~(0x07 << 16);
  2449. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2450. I915_WRITE(reg, temp);
  2451. POSTING_READ(reg);
  2452. udelay(100);
  2453. }
  2454. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2455. {
  2456. struct drm_device *dev = crtc->dev;
  2457. struct drm_i915_private *dev_priv = dev->dev_private;
  2458. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2459. unsigned long flags;
  2460. bool pending;
  2461. if (i915_reset_in_progress(&dev_priv->gpu_error) ||
  2462. intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
  2463. return false;
  2464. spin_lock_irqsave(&dev->event_lock, flags);
  2465. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2466. spin_unlock_irqrestore(&dev->event_lock, flags);
  2467. return pending;
  2468. }
  2469. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2470. {
  2471. struct drm_device *dev = crtc->dev;
  2472. struct drm_i915_private *dev_priv = dev->dev_private;
  2473. if (crtc->fb == NULL)
  2474. return;
  2475. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2476. wait_event(dev_priv->pending_flip_queue,
  2477. !intel_crtc_has_pending_flip(crtc));
  2478. mutex_lock(&dev->struct_mutex);
  2479. intel_finish_fb(crtc->fb);
  2480. mutex_unlock(&dev->struct_mutex);
  2481. }
  2482. /* Program iCLKIP clock to the desired frequency */
  2483. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2484. {
  2485. struct drm_device *dev = crtc->dev;
  2486. struct drm_i915_private *dev_priv = dev->dev_private;
  2487. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2488. u32 temp;
  2489. mutex_lock(&dev_priv->dpio_lock);
  2490. /* It is necessary to ungate the pixclk gate prior to programming
  2491. * the divisors, and gate it back when it is done.
  2492. */
  2493. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2494. /* Disable SSCCTL */
  2495. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2496. intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2497. SBI_SSCCTL_DISABLE,
  2498. SBI_ICLK);
  2499. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2500. if (crtc->mode.clock == 20000) {
  2501. auxdiv = 1;
  2502. divsel = 0x41;
  2503. phaseinc = 0x20;
  2504. } else {
  2505. /* The iCLK virtual clock root frequency is in MHz,
  2506. * but the crtc->mode.clock in in KHz. To get the divisors,
  2507. * it is necessary to divide one by another, so we
  2508. * convert the virtual clock precision to KHz here for higher
  2509. * precision.
  2510. */
  2511. u32 iclk_virtual_root_freq = 172800 * 1000;
  2512. u32 iclk_pi_range = 64;
  2513. u32 desired_divisor, msb_divisor_value, pi_value;
  2514. desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
  2515. msb_divisor_value = desired_divisor / iclk_pi_range;
  2516. pi_value = desired_divisor % iclk_pi_range;
  2517. auxdiv = 0;
  2518. divsel = msb_divisor_value - 2;
  2519. phaseinc = pi_value;
  2520. }
  2521. /* This should not happen with any sane values */
  2522. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2523. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2524. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2525. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2526. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2527. crtc->mode.clock,
  2528. auxdiv,
  2529. divsel,
  2530. phasedir,
  2531. phaseinc);
  2532. /* Program SSCDIVINTPHASE6 */
  2533. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2534. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2535. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2536. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2537. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2538. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2539. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2540. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2541. /* Program SSCAUXDIV */
  2542. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2543. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2544. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2545. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2546. /* Enable modulator and associated divider */
  2547. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2548. temp &= ~SBI_SSCCTL_DISABLE;
  2549. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2550. /* Wait for initialization time */
  2551. udelay(24);
  2552. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2553. mutex_unlock(&dev_priv->dpio_lock);
  2554. }
  2555. static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
  2556. enum pipe pch_transcoder)
  2557. {
  2558. struct drm_device *dev = crtc->base.dev;
  2559. struct drm_i915_private *dev_priv = dev->dev_private;
  2560. enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
  2561. I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
  2562. I915_READ(HTOTAL(cpu_transcoder)));
  2563. I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
  2564. I915_READ(HBLANK(cpu_transcoder)));
  2565. I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
  2566. I915_READ(HSYNC(cpu_transcoder)));
  2567. I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
  2568. I915_READ(VTOTAL(cpu_transcoder)));
  2569. I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
  2570. I915_READ(VBLANK(cpu_transcoder)));
  2571. I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
  2572. I915_READ(VSYNC(cpu_transcoder)));
  2573. I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
  2574. I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2575. }
  2576. /*
  2577. * Enable PCH resources required for PCH ports:
  2578. * - PCH PLLs
  2579. * - FDI training & RX/TX
  2580. * - update transcoder timings
  2581. * - DP transcoding bits
  2582. * - transcoder
  2583. */
  2584. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2585. {
  2586. struct drm_device *dev = crtc->dev;
  2587. struct drm_i915_private *dev_priv = dev->dev_private;
  2588. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2589. int pipe = intel_crtc->pipe;
  2590. u32 reg, temp;
  2591. assert_pch_transcoder_disabled(dev_priv, pipe);
  2592. /* Write the TU size bits before fdi link training, so that error
  2593. * detection works. */
  2594. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2595. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2596. /* For PCH output, training FDI link */
  2597. dev_priv->display.fdi_link_train(crtc);
  2598. /* We need to program the right clock selection before writing the pixel
  2599. * mutliplier into the DPLL. */
  2600. if (HAS_PCH_CPT(dev)) {
  2601. u32 sel;
  2602. temp = I915_READ(PCH_DPLL_SEL);
  2603. temp |= TRANS_DPLL_ENABLE(pipe);
  2604. sel = TRANS_DPLLB_SEL(pipe);
  2605. if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
  2606. temp |= sel;
  2607. else
  2608. temp &= ~sel;
  2609. I915_WRITE(PCH_DPLL_SEL, temp);
  2610. }
  2611. /* XXX: pch pll's can be enabled any time before we enable the PCH
  2612. * transcoder, and we actually should do this to not upset any PCH
  2613. * transcoder that already use the clock when we share it.
  2614. *
  2615. * Note that enable_shared_dpll tries to do the right thing, but
  2616. * get_shared_dpll unconditionally resets the pll - we need that to have
  2617. * the right LVDS enable sequence. */
  2618. ironlake_enable_shared_dpll(intel_crtc);
  2619. /* set transcoder timing, panel must allow it */
  2620. assert_panel_unlocked(dev_priv, pipe);
  2621. ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
  2622. intel_fdi_normal_train(crtc);
  2623. /* For PCH DP, enable TRANS_DP_CTL */
  2624. if (HAS_PCH_CPT(dev) &&
  2625. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2626. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2627. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  2628. reg = TRANS_DP_CTL(pipe);
  2629. temp = I915_READ(reg);
  2630. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2631. TRANS_DP_SYNC_MASK |
  2632. TRANS_DP_BPC_MASK);
  2633. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2634. TRANS_DP_ENH_FRAMING);
  2635. temp |= bpc << 9; /* same format but at 11:9 */
  2636. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2637. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2638. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2639. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2640. switch (intel_trans_dp_port_sel(crtc)) {
  2641. case PCH_DP_B:
  2642. temp |= TRANS_DP_PORT_SEL_B;
  2643. break;
  2644. case PCH_DP_C:
  2645. temp |= TRANS_DP_PORT_SEL_C;
  2646. break;
  2647. case PCH_DP_D:
  2648. temp |= TRANS_DP_PORT_SEL_D;
  2649. break;
  2650. default:
  2651. BUG();
  2652. }
  2653. I915_WRITE(reg, temp);
  2654. }
  2655. ironlake_enable_pch_transcoder(dev_priv, pipe);
  2656. }
  2657. static void lpt_pch_enable(struct drm_crtc *crtc)
  2658. {
  2659. struct drm_device *dev = crtc->dev;
  2660. struct drm_i915_private *dev_priv = dev->dev_private;
  2661. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2662. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  2663. assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
  2664. lpt_program_iclkip(crtc);
  2665. /* Set transcoder timing. */
  2666. ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
  2667. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  2668. }
  2669. static void intel_put_shared_dpll(struct intel_crtc *crtc)
  2670. {
  2671. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2672. if (pll == NULL)
  2673. return;
  2674. if (pll->refcount == 0) {
  2675. WARN(1, "bad %s refcount\n", pll->name);
  2676. return;
  2677. }
  2678. if (--pll->refcount == 0) {
  2679. WARN_ON(pll->on);
  2680. WARN_ON(pll->active);
  2681. }
  2682. crtc->config.shared_dpll = DPLL_ID_PRIVATE;
  2683. }
  2684. static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
  2685. {
  2686. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2687. struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
  2688. enum intel_dpll_id i;
  2689. if (pll) {
  2690. DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
  2691. crtc->base.base.id, pll->name);
  2692. intel_put_shared_dpll(crtc);
  2693. }
  2694. if (HAS_PCH_IBX(dev_priv->dev)) {
  2695. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2696. i = (enum intel_dpll_id) crtc->pipe;
  2697. pll = &dev_priv->shared_dplls[i];
  2698. DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
  2699. crtc->base.base.id, pll->name);
  2700. goto found;
  2701. }
  2702. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2703. pll = &dev_priv->shared_dplls[i];
  2704. /* Only want to check enabled timings first */
  2705. if (pll->refcount == 0)
  2706. continue;
  2707. if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
  2708. sizeof(pll->hw_state)) == 0) {
  2709. DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
  2710. crtc->base.base.id,
  2711. pll->name, pll->refcount, pll->active);
  2712. goto found;
  2713. }
  2714. }
  2715. /* Ok no matching timings, maybe there's a free one? */
  2716. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  2717. pll = &dev_priv->shared_dplls[i];
  2718. if (pll->refcount == 0) {
  2719. DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
  2720. crtc->base.base.id, pll->name);
  2721. goto found;
  2722. }
  2723. }
  2724. return NULL;
  2725. found:
  2726. crtc->config.shared_dpll = i;
  2727. DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
  2728. pipe_name(crtc->pipe));
  2729. if (pll->active == 0) {
  2730. memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
  2731. sizeof(pll->hw_state));
  2732. DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
  2733. WARN_ON(pll->on);
  2734. assert_shared_dpll_disabled(dev_priv, pll);
  2735. pll->mode_set(dev_priv, pll);
  2736. }
  2737. pll->refcount++;
  2738. return pll;
  2739. }
  2740. static void cpt_verify_modeset(struct drm_device *dev, int pipe)
  2741. {
  2742. struct drm_i915_private *dev_priv = dev->dev_private;
  2743. int dslreg = PIPEDSL(pipe);
  2744. u32 temp;
  2745. temp = I915_READ(dslreg);
  2746. udelay(500);
  2747. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2748. if (wait_for(I915_READ(dslreg) != temp, 5))
  2749. DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
  2750. }
  2751. }
  2752. static void ironlake_pfit_enable(struct intel_crtc *crtc)
  2753. {
  2754. struct drm_device *dev = crtc->base.dev;
  2755. struct drm_i915_private *dev_priv = dev->dev_private;
  2756. int pipe = crtc->pipe;
  2757. if (crtc->config.pch_pfit.size) {
  2758. /* Force use of hard-coded filter coefficients
  2759. * as some pre-programmed values are broken,
  2760. * e.g. x201.
  2761. */
  2762. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
  2763. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2764. PF_PIPE_SEL_IVB(pipe));
  2765. else
  2766. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2767. I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
  2768. I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
  2769. }
  2770. }
  2771. static void intel_enable_planes(struct drm_crtc *crtc)
  2772. {
  2773. struct drm_device *dev = crtc->dev;
  2774. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2775. struct intel_plane *intel_plane;
  2776. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2777. if (intel_plane->pipe == pipe)
  2778. intel_plane_restore(&intel_plane->base);
  2779. }
  2780. static void intel_disable_planes(struct drm_crtc *crtc)
  2781. {
  2782. struct drm_device *dev = crtc->dev;
  2783. enum pipe pipe = to_intel_crtc(crtc)->pipe;
  2784. struct intel_plane *intel_plane;
  2785. list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
  2786. if (intel_plane->pipe == pipe)
  2787. intel_plane_disable(&intel_plane->base);
  2788. }
  2789. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2790. {
  2791. struct drm_device *dev = crtc->dev;
  2792. struct drm_i915_private *dev_priv = dev->dev_private;
  2793. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2794. struct intel_encoder *encoder;
  2795. int pipe = intel_crtc->pipe;
  2796. int plane = intel_crtc->plane;
  2797. WARN_ON(!crtc->enabled);
  2798. if (intel_crtc->active)
  2799. return;
  2800. intel_crtc->active = true;
  2801. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2802. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  2803. intel_update_watermarks(dev);
  2804. for_each_encoder_on_crtc(dev, crtc, encoder)
  2805. if (encoder->pre_enable)
  2806. encoder->pre_enable(encoder);
  2807. if (intel_crtc->config.has_pch_encoder) {
  2808. /* Note: FDI PLL enabling _must_ be done before we enable the
  2809. * cpu pipes, hence this is separate from all the other fdi/pch
  2810. * enabling. */
  2811. ironlake_fdi_pll_enable(intel_crtc);
  2812. } else {
  2813. assert_fdi_tx_disabled(dev_priv, pipe);
  2814. assert_fdi_rx_disabled(dev_priv, pipe);
  2815. }
  2816. ironlake_pfit_enable(intel_crtc);
  2817. /*
  2818. * On ILK+ LUT must be loaded before the pipe is running but with
  2819. * clocks enabled
  2820. */
  2821. intel_crtc_load_lut(crtc);
  2822. intel_enable_pipe(dev_priv, pipe,
  2823. intel_crtc->config.has_pch_encoder);
  2824. intel_enable_plane(dev_priv, plane, pipe);
  2825. intel_enable_planes(crtc);
  2826. intel_crtc_update_cursor(crtc, true);
  2827. if (intel_crtc->config.has_pch_encoder)
  2828. ironlake_pch_enable(crtc);
  2829. mutex_lock(&dev->struct_mutex);
  2830. intel_update_fbc(dev);
  2831. mutex_unlock(&dev->struct_mutex);
  2832. for_each_encoder_on_crtc(dev, crtc, encoder)
  2833. encoder->enable(encoder);
  2834. if (HAS_PCH_CPT(dev))
  2835. cpt_verify_modeset(dev, intel_crtc->pipe);
  2836. /*
  2837. * There seems to be a race in PCH platform hw (at least on some
  2838. * outputs) where an enabled pipe still completes any pageflip right
  2839. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2840. * as the first vblank happend, everything works as expected. Hence just
  2841. * wait for one vblank before returning to avoid strange things
  2842. * happening.
  2843. */
  2844. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2845. }
  2846. /* IPS only exists on ULT machines and is tied to pipe A. */
  2847. static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
  2848. {
  2849. return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
  2850. }
  2851. static void hsw_enable_ips(struct intel_crtc *crtc)
  2852. {
  2853. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  2854. if (!crtc->config.ips_enabled)
  2855. return;
  2856. /* We can only enable IPS after we enable a plane and wait for a vblank.
  2857. * We guarantee that the plane is enabled by calling intel_enable_ips
  2858. * only after intel_enable_plane. And intel_enable_plane already waits
  2859. * for a vblank, so all we need to do here is to enable the IPS bit. */
  2860. assert_plane_enabled(dev_priv, crtc->plane);
  2861. I915_WRITE(IPS_CTL, IPS_ENABLE);
  2862. }
  2863. static void hsw_disable_ips(struct intel_crtc *crtc)
  2864. {
  2865. struct drm_device *dev = crtc->base.dev;
  2866. struct drm_i915_private *dev_priv = dev->dev_private;
  2867. if (!crtc->config.ips_enabled)
  2868. return;
  2869. assert_plane_enabled(dev_priv, crtc->plane);
  2870. I915_WRITE(IPS_CTL, 0);
  2871. /* We need to wait for a vblank before we can disable the plane. */
  2872. intel_wait_for_vblank(dev, crtc->pipe);
  2873. }
  2874. static void haswell_crtc_enable(struct drm_crtc *crtc)
  2875. {
  2876. struct drm_device *dev = crtc->dev;
  2877. struct drm_i915_private *dev_priv = dev->dev_private;
  2878. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2879. struct intel_encoder *encoder;
  2880. int pipe = intel_crtc->pipe;
  2881. int plane = intel_crtc->plane;
  2882. WARN_ON(!crtc->enabled);
  2883. if (intel_crtc->active)
  2884. return;
  2885. intel_crtc->active = true;
  2886. intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
  2887. if (intel_crtc->config.has_pch_encoder)
  2888. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  2889. intel_update_watermarks(dev);
  2890. if (intel_crtc->config.has_pch_encoder)
  2891. dev_priv->display.fdi_link_train(crtc);
  2892. for_each_encoder_on_crtc(dev, crtc, encoder)
  2893. if (encoder->pre_enable)
  2894. encoder->pre_enable(encoder);
  2895. intel_ddi_enable_pipe_clock(intel_crtc);
  2896. ironlake_pfit_enable(intel_crtc);
  2897. /*
  2898. * On ILK+ LUT must be loaded before the pipe is running but with
  2899. * clocks enabled
  2900. */
  2901. intel_crtc_load_lut(crtc);
  2902. intel_ddi_set_pipe_settings(crtc);
  2903. intel_ddi_enable_transcoder_func(crtc);
  2904. intel_enable_pipe(dev_priv, pipe,
  2905. intel_crtc->config.has_pch_encoder);
  2906. intel_enable_plane(dev_priv, plane, pipe);
  2907. intel_enable_planes(crtc);
  2908. intel_crtc_update_cursor(crtc, true);
  2909. hsw_enable_ips(intel_crtc);
  2910. if (intel_crtc->config.has_pch_encoder)
  2911. lpt_pch_enable(crtc);
  2912. mutex_lock(&dev->struct_mutex);
  2913. intel_update_fbc(dev);
  2914. mutex_unlock(&dev->struct_mutex);
  2915. for_each_encoder_on_crtc(dev, crtc, encoder)
  2916. encoder->enable(encoder);
  2917. /*
  2918. * There seems to be a race in PCH platform hw (at least on some
  2919. * outputs) where an enabled pipe still completes any pageflip right
  2920. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2921. * as the first vblank happend, everything works as expected. Hence just
  2922. * wait for one vblank before returning to avoid strange things
  2923. * happening.
  2924. */
  2925. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2926. }
  2927. static void ironlake_pfit_disable(struct intel_crtc *crtc)
  2928. {
  2929. struct drm_device *dev = crtc->base.dev;
  2930. struct drm_i915_private *dev_priv = dev->dev_private;
  2931. int pipe = crtc->pipe;
  2932. /* To avoid upsetting the power well on haswell only disable the pfit if
  2933. * it's in use. The hw state code will make sure we get this right. */
  2934. if (crtc->config.pch_pfit.size) {
  2935. I915_WRITE(PF_CTL(pipe), 0);
  2936. I915_WRITE(PF_WIN_POS(pipe), 0);
  2937. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2938. }
  2939. }
  2940. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2941. {
  2942. struct drm_device *dev = crtc->dev;
  2943. struct drm_i915_private *dev_priv = dev->dev_private;
  2944. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2945. struct intel_encoder *encoder;
  2946. int pipe = intel_crtc->pipe;
  2947. int plane = intel_crtc->plane;
  2948. u32 reg, temp;
  2949. if (!intel_crtc->active)
  2950. return;
  2951. for_each_encoder_on_crtc(dev, crtc, encoder)
  2952. encoder->disable(encoder);
  2953. intel_crtc_wait_for_pending_flips(crtc);
  2954. drm_vblank_off(dev, pipe);
  2955. if (dev_priv->fbc.plane == plane)
  2956. intel_disable_fbc(dev);
  2957. intel_crtc_update_cursor(crtc, false);
  2958. intel_disable_planes(crtc);
  2959. intel_disable_plane(dev_priv, plane, pipe);
  2960. if (intel_crtc->config.has_pch_encoder)
  2961. intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
  2962. intel_disable_pipe(dev_priv, pipe);
  2963. ironlake_pfit_disable(intel_crtc);
  2964. for_each_encoder_on_crtc(dev, crtc, encoder)
  2965. if (encoder->post_disable)
  2966. encoder->post_disable(encoder);
  2967. if (intel_crtc->config.has_pch_encoder) {
  2968. ironlake_fdi_disable(crtc);
  2969. ironlake_disable_pch_transcoder(dev_priv, pipe);
  2970. intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
  2971. if (HAS_PCH_CPT(dev)) {
  2972. /* disable TRANS_DP_CTL */
  2973. reg = TRANS_DP_CTL(pipe);
  2974. temp = I915_READ(reg);
  2975. temp &= ~(TRANS_DP_OUTPUT_ENABLE |
  2976. TRANS_DP_PORT_SEL_MASK);
  2977. temp |= TRANS_DP_PORT_SEL_NONE;
  2978. I915_WRITE(reg, temp);
  2979. /* disable DPLL_SEL */
  2980. temp = I915_READ(PCH_DPLL_SEL);
  2981. temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
  2982. I915_WRITE(PCH_DPLL_SEL, temp);
  2983. }
  2984. /* disable PCH DPLL */
  2985. intel_disable_shared_dpll(intel_crtc);
  2986. ironlake_fdi_pll_disable(intel_crtc);
  2987. }
  2988. intel_crtc->active = false;
  2989. intel_update_watermarks(dev);
  2990. mutex_lock(&dev->struct_mutex);
  2991. intel_update_fbc(dev);
  2992. mutex_unlock(&dev->struct_mutex);
  2993. }
  2994. static void haswell_crtc_disable(struct drm_crtc *crtc)
  2995. {
  2996. struct drm_device *dev = crtc->dev;
  2997. struct drm_i915_private *dev_priv = dev->dev_private;
  2998. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2999. struct intel_encoder *encoder;
  3000. int pipe = intel_crtc->pipe;
  3001. int plane = intel_crtc->plane;
  3002. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3003. if (!intel_crtc->active)
  3004. return;
  3005. for_each_encoder_on_crtc(dev, crtc, encoder)
  3006. encoder->disable(encoder);
  3007. intel_crtc_wait_for_pending_flips(crtc);
  3008. drm_vblank_off(dev, pipe);
  3009. /* FBC must be disabled before disabling the plane on HSW. */
  3010. if (dev_priv->fbc.plane == plane)
  3011. intel_disable_fbc(dev);
  3012. hsw_disable_ips(intel_crtc);
  3013. intel_crtc_update_cursor(crtc, false);
  3014. intel_disable_planes(crtc);
  3015. intel_disable_plane(dev_priv, plane, pipe);
  3016. if (intel_crtc->config.has_pch_encoder)
  3017. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
  3018. intel_disable_pipe(dev_priv, pipe);
  3019. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3020. ironlake_pfit_disable(intel_crtc);
  3021. intel_ddi_disable_pipe_clock(intel_crtc);
  3022. for_each_encoder_on_crtc(dev, crtc, encoder)
  3023. if (encoder->post_disable)
  3024. encoder->post_disable(encoder);
  3025. if (intel_crtc->config.has_pch_encoder) {
  3026. lpt_disable_pch_transcoder(dev_priv);
  3027. intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
  3028. intel_ddi_fdi_disable(crtc);
  3029. }
  3030. intel_crtc->active = false;
  3031. intel_update_watermarks(dev);
  3032. mutex_lock(&dev->struct_mutex);
  3033. intel_update_fbc(dev);
  3034. mutex_unlock(&dev->struct_mutex);
  3035. }
  3036. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3037. {
  3038. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3039. intel_put_shared_dpll(intel_crtc);
  3040. }
  3041. static void haswell_crtc_off(struct drm_crtc *crtc)
  3042. {
  3043. intel_ddi_put_crtc_pll(crtc);
  3044. }
  3045. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3046. {
  3047. if (!enable && intel_crtc->overlay) {
  3048. struct drm_device *dev = intel_crtc->base.dev;
  3049. struct drm_i915_private *dev_priv = dev->dev_private;
  3050. mutex_lock(&dev->struct_mutex);
  3051. dev_priv->mm.interruptible = false;
  3052. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3053. dev_priv->mm.interruptible = true;
  3054. mutex_unlock(&dev->struct_mutex);
  3055. }
  3056. /* Let userspace switch the overlay on again. In most cases userspace
  3057. * has to recompute where to put it anyway.
  3058. */
  3059. }
  3060. /**
  3061. * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
  3062. * cursor plane briefly if not already running after enabling the display
  3063. * plane.
  3064. * This workaround avoids occasional blank screens when self refresh is
  3065. * enabled.
  3066. */
  3067. static void
  3068. g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
  3069. {
  3070. u32 cntl = I915_READ(CURCNTR(pipe));
  3071. if ((cntl & CURSOR_MODE) == 0) {
  3072. u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
  3073. I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
  3074. I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
  3075. intel_wait_for_vblank(dev_priv->dev, pipe);
  3076. I915_WRITE(CURCNTR(pipe), cntl);
  3077. I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
  3078. I915_WRITE(FW_BLC_SELF, fw_bcl_self);
  3079. }
  3080. }
  3081. static void i9xx_pfit_enable(struct intel_crtc *crtc)
  3082. {
  3083. struct drm_device *dev = crtc->base.dev;
  3084. struct drm_i915_private *dev_priv = dev->dev_private;
  3085. struct intel_crtc_config *pipe_config = &crtc->config;
  3086. if (!crtc->config.gmch_pfit.control)
  3087. return;
  3088. /*
  3089. * The panel fitter should only be adjusted whilst the pipe is disabled,
  3090. * according to register description and PRM.
  3091. */
  3092. WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
  3093. assert_pipe_disabled(dev_priv, crtc->pipe);
  3094. I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
  3095. I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
  3096. /* Border color in case we don't scale up to the full screen. Black by
  3097. * default, change to something else for debugging. */
  3098. I915_WRITE(BCLRPAT(crtc->pipe), 0);
  3099. }
  3100. static void valleyview_crtc_enable(struct drm_crtc *crtc)
  3101. {
  3102. struct drm_device *dev = crtc->dev;
  3103. struct drm_i915_private *dev_priv = dev->dev_private;
  3104. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3105. struct intel_encoder *encoder;
  3106. int pipe = intel_crtc->pipe;
  3107. int plane = intel_crtc->plane;
  3108. WARN_ON(!crtc->enabled);
  3109. if (intel_crtc->active)
  3110. return;
  3111. intel_crtc->active = true;
  3112. intel_update_watermarks(dev);
  3113. mutex_lock(&dev_priv->dpio_lock);
  3114. for_each_encoder_on_crtc(dev, crtc, encoder)
  3115. if (encoder->pre_pll_enable)
  3116. encoder->pre_pll_enable(encoder);
  3117. vlv_enable_pll(intel_crtc);
  3118. for_each_encoder_on_crtc(dev, crtc, encoder)
  3119. if (encoder->pre_enable)
  3120. encoder->pre_enable(encoder);
  3121. /* VLV wants encoder enabling _before_ the pipe is up. */
  3122. for_each_encoder_on_crtc(dev, crtc, encoder)
  3123. encoder->enable(encoder);
  3124. i9xx_pfit_enable(intel_crtc);
  3125. intel_crtc_load_lut(crtc);
  3126. intel_enable_pipe(dev_priv, pipe, false);
  3127. intel_enable_plane(dev_priv, plane, pipe);
  3128. intel_enable_planes(crtc);
  3129. intel_crtc_update_cursor(crtc, true);
  3130. intel_update_fbc(dev);
  3131. mutex_unlock(&dev_priv->dpio_lock);
  3132. }
  3133. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3134. {
  3135. struct drm_device *dev = crtc->dev;
  3136. struct drm_i915_private *dev_priv = dev->dev_private;
  3137. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3138. struct intel_encoder *encoder;
  3139. int pipe = intel_crtc->pipe;
  3140. int plane = intel_crtc->plane;
  3141. WARN_ON(!crtc->enabled);
  3142. if (intel_crtc->active)
  3143. return;
  3144. intel_crtc->active = true;
  3145. intel_update_watermarks(dev);
  3146. for_each_encoder_on_crtc(dev, crtc, encoder)
  3147. if (encoder->pre_enable)
  3148. encoder->pre_enable(encoder);
  3149. i9xx_enable_pll(intel_crtc);
  3150. i9xx_pfit_enable(intel_crtc);
  3151. intel_crtc_load_lut(crtc);
  3152. intel_enable_pipe(dev_priv, pipe, false);
  3153. intel_enable_plane(dev_priv, plane, pipe);
  3154. intel_enable_planes(crtc);
  3155. /* The fixup needs to happen before cursor is enabled */
  3156. if (IS_G4X(dev))
  3157. g4x_fixup_plane(dev_priv, pipe);
  3158. intel_crtc_update_cursor(crtc, true);
  3159. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3160. intel_crtc_dpms_overlay(intel_crtc, true);
  3161. intel_update_fbc(dev);
  3162. for_each_encoder_on_crtc(dev, crtc, encoder)
  3163. encoder->enable(encoder);
  3164. }
  3165. static void i9xx_pfit_disable(struct intel_crtc *crtc)
  3166. {
  3167. struct drm_device *dev = crtc->base.dev;
  3168. struct drm_i915_private *dev_priv = dev->dev_private;
  3169. if (!crtc->config.gmch_pfit.control)
  3170. return;
  3171. assert_pipe_disabled(dev_priv, crtc->pipe);
  3172. DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
  3173. I915_READ(PFIT_CONTROL));
  3174. I915_WRITE(PFIT_CONTROL, 0);
  3175. }
  3176. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3177. {
  3178. struct drm_device *dev = crtc->dev;
  3179. struct drm_i915_private *dev_priv = dev->dev_private;
  3180. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3181. struct intel_encoder *encoder;
  3182. int pipe = intel_crtc->pipe;
  3183. int plane = intel_crtc->plane;
  3184. if (!intel_crtc->active)
  3185. return;
  3186. for_each_encoder_on_crtc(dev, crtc, encoder)
  3187. encoder->disable(encoder);
  3188. /* Give the overlay scaler a chance to disable if it's on this pipe */
  3189. intel_crtc_wait_for_pending_flips(crtc);
  3190. drm_vblank_off(dev, pipe);
  3191. if (dev_priv->fbc.plane == plane)
  3192. intel_disable_fbc(dev);
  3193. intel_crtc_dpms_overlay(intel_crtc, false);
  3194. intel_crtc_update_cursor(crtc, false);
  3195. intel_disable_planes(crtc);
  3196. intel_disable_plane(dev_priv, plane, pipe);
  3197. intel_disable_pipe(dev_priv, pipe);
  3198. i9xx_pfit_disable(intel_crtc);
  3199. for_each_encoder_on_crtc(dev, crtc, encoder)
  3200. if (encoder->post_disable)
  3201. encoder->post_disable(encoder);
  3202. i9xx_disable_pll(dev_priv, pipe);
  3203. intel_crtc->active = false;
  3204. intel_update_fbc(dev);
  3205. intel_update_watermarks(dev);
  3206. }
  3207. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3208. {
  3209. }
  3210. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3211. bool enabled)
  3212. {
  3213. struct drm_device *dev = crtc->dev;
  3214. struct drm_i915_master_private *master_priv;
  3215. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3216. int pipe = intel_crtc->pipe;
  3217. if (!dev->primary->master)
  3218. return;
  3219. master_priv = dev->primary->master->driver_priv;
  3220. if (!master_priv->sarea_priv)
  3221. return;
  3222. switch (pipe) {
  3223. case 0:
  3224. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3225. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3226. break;
  3227. case 1:
  3228. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3229. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3230. break;
  3231. default:
  3232. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3233. break;
  3234. }
  3235. }
  3236. /**
  3237. * Sets the power management mode of the pipe and plane.
  3238. */
  3239. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3240. {
  3241. struct drm_device *dev = crtc->dev;
  3242. struct drm_i915_private *dev_priv = dev->dev_private;
  3243. struct intel_encoder *intel_encoder;
  3244. bool enable = false;
  3245. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3246. enable |= intel_encoder->connectors_active;
  3247. if (enable)
  3248. dev_priv->display.crtc_enable(crtc);
  3249. else
  3250. dev_priv->display.crtc_disable(crtc);
  3251. intel_crtc_update_sarea(crtc, enable);
  3252. }
  3253. static void intel_crtc_disable(struct drm_crtc *crtc)
  3254. {
  3255. struct drm_device *dev = crtc->dev;
  3256. struct drm_connector *connector;
  3257. struct drm_i915_private *dev_priv = dev->dev_private;
  3258. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3259. /* crtc should still be enabled when we disable it. */
  3260. WARN_ON(!crtc->enabled);
  3261. dev_priv->display.crtc_disable(crtc);
  3262. intel_crtc->eld_vld = false;
  3263. intel_crtc_update_sarea(crtc, false);
  3264. dev_priv->display.off(crtc);
  3265. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3266. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3267. if (crtc->fb) {
  3268. mutex_lock(&dev->struct_mutex);
  3269. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3270. mutex_unlock(&dev->struct_mutex);
  3271. crtc->fb = NULL;
  3272. }
  3273. /* Update computed state. */
  3274. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3275. if (!connector->encoder || !connector->encoder->crtc)
  3276. continue;
  3277. if (connector->encoder->crtc != crtc)
  3278. continue;
  3279. connector->dpms = DRM_MODE_DPMS_OFF;
  3280. to_intel_encoder(connector->encoder)->connectors_active = false;
  3281. }
  3282. }
  3283. void intel_modeset_disable(struct drm_device *dev)
  3284. {
  3285. struct drm_crtc *crtc;
  3286. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3287. if (crtc->enabled)
  3288. intel_crtc_disable(crtc);
  3289. }
  3290. }
  3291. void intel_encoder_destroy(struct drm_encoder *encoder)
  3292. {
  3293. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3294. drm_encoder_cleanup(encoder);
  3295. kfree(intel_encoder);
  3296. }
  3297. /* Simple dpms helper for encodres with just one connector, no cloning and only
  3298. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3299. * state of the entire output pipe. */
  3300. void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3301. {
  3302. if (mode == DRM_MODE_DPMS_ON) {
  3303. encoder->connectors_active = true;
  3304. intel_crtc_update_dpms(encoder->base.crtc);
  3305. } else {
  3306. encoder->connectors_active = false;
  3307. intel_crtc_update_dpms(encoder->base.crtc);
  3308. }
  3309. }
  3310. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3311. * internal consistency). */
  3312. static void intel_connector_check_state(struct intel_connector *connector)
  3313. {
  3314. if (connector->get_hw_state(connector)) {
  3315. struct intel_encoder *encoder = connector->encoder;
  3316. struct drm_crtc *crtc;
  3317. bool encoder_enabled;
  3318. enum pipe pipe;
  3319. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3320. connector->base.base.id,
  3321. drm_get_connector_name(&connector->base));
  3322. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3323. "wrong connector dpms state\n");
  3324. WARN(connector->base.encoder != &encoder->base,
  3325. "active connector not linked to encoder\n");
  3326. WARN(!encoder->connectors_active,
  3327. "encoder->connectors_active not set\n");
  3328. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3329. WARN(!encoder_enabled, "encoder not enabled\n");
  3330. if (WARN_ON(!encoder->base.crtc))
  3331. return;
  3332. crtc = encoder->base.crtc;
  3333. WARN(!crtc->enabled, "crtc not enabled\n");
  3334. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3335. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3336. "encoder active on the wrong pipe\n");
  3337. }
  3338. }
  3339. /* Even simpler default implementation, if there's really no special case to
  3340. * consider. */
  3341. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3342. {
  3343. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3344. /* All the simple cases only support two dpms states. */
  3345. if (mode != DRM_MODE_DPMS_ON)
  3346. mode = DRM_MODE_DPMS_OFF;
  3347. if (mode == connector->dpms)
  3348. return;
  3349. connector->dpms = mode;
  3350. /* Only need to change hw state when actually enabled */
  3351. if (encoder->base.crtc)
  3352. intel_encoder_dpms(encoder, mode);
  3353. else
  3354. WARN_ON(encoder->connectors_active != false);
  3355. intel_modeset_check_state(connector->dev);
  3356. }
  3357. /* Simple connector->get_hw_state implementation for encoders that support only
  3358. * one connector and no cloning and hence the encoder state determines the state
  3359. * of the connector. */
  3360. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3361. {
  3362. enum pipe pipe = 0;
  3363. struct intel_encoder *encoder = connector->encoder;
  3364. return encoder->get_hw_state(encoder, &pipe);
  3365. }
  3366. static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
  3367. struct intel_crtc_config *pipe_config)
  3368. {
  3369. struct drm_i915_private *dev_priv = dev->dev_private;
  3370. struct intel_crtc *pipe_B_crtc =
  3371. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  3372. DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
  3373. pipe_name(pipe), pipe_config->fdi_lanes);
  3374. if (pipe_config->fdi_lanes > 4) {
  3375. DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
  3376. pipe_name(pipe), pipe_config->fdi_lanes);
  3377. return false;
  3378. }
  3379. if (IS_HASWELL(dev)) {
  3380. if (pipe_config->fdi_lanes > 2) {
  3381. DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
  3382. pipe_config->fdi_lanes);
  3383. return false;
  3384. } else {
  3385. return true;
  3386. }
  3387. }
  3388. if (INTEL_INFO(dev)->num_pipes == 2)
  3389. return true;
  3390. /* Ivybridge 3 pipe is really complicated */
  3391. switch (pipe) {
  3392. case PIPE_A:
  3393. return true;
  3394. case PIPE_B:
  3395. if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  3396. pipe_config->fdi_lanes > 2) {
  3397. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3398. pipe_name(pipe), pipe_config->fdi_lanes);
  3399. return false;
  3400. }
  3401. return true;
  3402. case PIPE_C:
  3403. if (!pipe_has_enabled_pch(pipe_B_crtc) ||
  3404. pipe_B_crtc->config.fdi_lanes <= 2) {
  3405. if (pipe_config->fdi_lanes > 2) {
  3406. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
  3407. pipe_name(pipe), pipe_config->fdi_lanes);
  3408. return false;
  3409. }
  3410. } else {
  3411. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  3412. return false;
  3413. }
  3414. return true;
  3415. default:
  3416. BUG();
  3417. }
  3418. }
  3419. #define RETRY 1
  3420. static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
  3421. struct intel_crtc_config *pipe_config)
  3422. {
  3423. struct drm_device *dev = intel_crtc->base.dev;
  3424. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3425. int lane, link_bw, fdi_dotclock;
  3426. bool setup_ok, needs_recompute = false;
  3427. retry:
  3428. /* FDI is a binary signal running at ~2.7GHz, encoding
  3429. * each output octet as 10 bits. The actual frequency
  3430. * is stored as a divider into a 100MHz clock, and the
  3431. * mode pixel clock is stored in units of 1KHz.
  3432. * Hence the bw of each lane in terms of the mode signal
  3433. * is:
  3434. */
  3435. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  3436. fdi_dotclock = adjusted_mode->clock;
  3437. fdi_dotclock /= pipe_config->pixel_multiplier;
  3438. lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
  3439. pipe_config->pipe_bpp);
  3440. pipe_config->fdi_lanes = lane;
  3441. intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
  3442. link_bw, &pipe_config->fdi_m_n);
  3443. setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
  3444. intel_crtc->pipe, pipe_config);
  3445. if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
  3446. pipe_config->pipe_bpp -= 2*3;
  3447. DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
  3448. pipe_config->pipe_bpp);
  3449. needs_recompute = true;
  3450. pipe_config->bw_constrained = true;
  3451. goto retry;
  3452. }
  3453. if (needs_recompute)
  3454. return RETRY;
  3455. return setup_ok ? 0 : -EINVAL;
  3456. }
  3457. static void hsw_compute_ips_config(struct intel_crtc *crtc,
  3458. struct intel_crtc_config *pipe_config)
  3459. {
  3460. pipe_config->ips_enabled = i915_enable_ips &&
  3461. hsw_crtc_supports_ips(crtc) &&
  3462. pipe_config->pipe_bpp == 24;
  3463. }
  3464. static int intel_crtc_compute_config(struct intel_crtc *crtc,
  3465. struct intel_crtc_config *pipe_config)
  3466. {
  3467. struct drm_device *dev = crtc->base.dev;
  3468. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  3469. if (HAS_PCH_SPLIT(dev)) {
  3470. /* FDI link clock is fixed at 2.7G */
  3471. if (pipe_config->requested_mode.clock * 3
  3472. > IRONLAKE_FDI_FREQ * 4)
  3473. return -EINVAL;
  3474. }
  3475. /* All interlaced capable intel hw wants timings in frames. Note though
  3476. * that intel_lvds_mode_fixup does some funny tricks with the crtc
  3477. * timings, so we need to be careful not to clobber these.*/
  3478. if (!pipe_config->timings_set)
  3479. drm_mode_set_crtcinfo(adjusted_mode, 0);
  3480. /* Cantiga+ cannot handle modes with a hsync front porch of 0.
  3481. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
  3482. */
  3483. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3484. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3485. return -EINVAL;
  3486. if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
  3487. pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
  3488. } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
  3489. /* only a 8bpc pipe, with 6bpc dither through the panel fitter
  3490. * for lvds. */
  3491. pipe_config->pipe_bpp = 8*3;
  3492. }
  3493. if (HAS_IPS(dev))
  3494. hsw_compute_ips_config(crtc, pipe_config);
  3495. /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
  3496. * clock survives for now. */
  3497. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  3498. pipe_config->shared_dpll = crtc->config.shared_dpll;
  3499. if (pipe_config->has_pch_encoder)
  3500. return ironlake_fdi_compute_config(crtc, pipe_config);
  3501. return 0;
  3502. }
  3503. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3504. {
  3505. return 400000; /* FIXME */
  3506. }
  3507. static int i945_get_display_clock_speed(struct drm_device *dev)
  3508. {
  3509. return 400000;
  3510. }
  3511. static int i915_get_display_clock_speed(struct drm_device *dev)
  3512. {
  3513. return 333000;
  3514. }
  3515. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3516. {
  3517. return 200000;
  3518. }
  3519. static int pnv_get_display_clock_speed(struct drm_device *dev)
  3520. {
  3521. u16 gcfgc = 0;
  3522. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3523. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3524. case GC_DISPLAY_CLOCK_267_MHZ_PNV:
  3525. return 267000;
  3526. case GC_DISPLAY_CLOCK_333_MHZ_PNV:
  3527. return 333000;
  3528. case GC_DISPLAY_CLOCK_444_MHZ_PNV:
  3529. return 444000;
  3530. case GC_DISPLAY_CLOCK_200_MHZ_PNV:
  3531. return 200000;
  3532. default:
  3533. DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
  3534. case GC_DISPLAY_CLOCK_133_MHZ_PNV:
  3535. return 133000;
  3536. case GC_DISPLAY_CLOCK_167_MHZ_PNV:
  3537. return 167000;
  3538. }
  3539. }
  3540. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3541. {
  3542. u16 gcfgc = 0;
  3543. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3544. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3545. return 133000;
  3546. else {
  3547. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3548. case GC_DISPLAY_CLOCK_333_MHZ:
  3549. return 333000;
  3550. default:
  3551. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3552. return 190000;
  3553. }
  3554. }
  3555. }
  3556. static int i865_get_display_clock_speed(struct drm_device *dev)
  3557. {
  3558. return 266000;
  3559. }
  3560. static int i855_get_display_clock_speed(struct drm_device *dev)
  3561. {
  3562. u16 hpllcc = 0;
  3563. /* Assume that the hardware is in the high speed state. This
  3564. * should be the default.
  3565. */
  3566. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3567. case GC_CLOCK_133_200:
  3568. case GC_CLOCK_100_200:
  3569. return 200000;
  3570. case GC_CLOCK_166_250:
  3571. return 250000;
  3572. case GC_CLOCK_100_133:
  3573. return 133000;
  3574. }
  3575. /* Shouldn't happen */
  3576. return 0;
  3577. }
  3578. static int i830_get_display_clock_speed(struct drm_device *dev)
  3579. {
  3580. return 133000;
  3581. }
  3582. static void
  3583. intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
  3584. {
  3585. while (*num > DATA_LINK_M_N_MASK ||
  3586. *den > DATA_LINK_M_N_MASK) {
  3587. *num >>= 1;
  3588. *den >>= 1;
  3589. }
  3590. }
  3591. static void compute_m_n(unsigned int m, unsigned int n,
  3592. uint32_t *ret_m, uint32_t *ret_n)
  3593. {
  3594. *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
  3595. *ret_m = div_u64((uint64_t) m * *ret_n, n);
  3596. intel_reduce_m_n_ratio(ret_m, ret_n);
  3597. }
  3598. void
  3599. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  3600. int pixel_clock, int link_clock,
  3601. struct intel_link_m_n *m_n)
  3602. {
  3603. m_n->tu = 64;
  3604. compute_m_n(bits_per_pixel * pixel_clock,
  3605. link_clock * nlanes * 8,
  3606. &m_n->gmch_m, &m_n->gmch_n);
  3607. compute_m_n(pixel_clock, link_clock,
  3608. &m_n->link_m, &m_n->link_n);
  3609. }
  3610. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3611. {
  3612. if (i915_panel_use_ssc >= 0)
  3613. return i915_panel_use_ssc != 0;
  3614. return dev_priv->vbt.lvds_use_ssc
  3615. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3616. }
  3617. static int vlv_get_refclk(struct drm_crtc *crtc)
  3618. {
  3619. struct drm_device *dev = crtc->dev;
  3620. struct drm_i915_private *dev_priv = dev->dev_private;
  3621. int refclk = 27000; /* for DP & HDMI */
  3622. return 100000; /* only one validated so far */
  3623. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  3624. refclk = 96000;
  3625. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3626. if (intel_panel_use_ssc(dev_priv))
  3627. refclk = 100000;
  3628. else
  3629. refclk = 96000;
  3630. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  3631. refclk = 100000;
  3632. }
  3633. return refclk;
  3634. }
  3635. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3636. {
  3637. struct drm_device *dev = crtc->dev;
  3638. struct drm_i915_private *dev_priv = dev->dev_private;
  3639. int refclk;
  3640. if (IS_VALLEYVIEW(dev)) {
  3641. refclk = vlv_get_refclk(crtc);
  3642. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3643. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3644. refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
  3645. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3646. refclk / 1000);
  3647. } else if (!IS_GEN2(dev)) {
  3648. refclk = 96000;
  3649. } else {
  3650. refclk = 48000;
  3651. }
  3652. return refclk;
  3653. }
  3654. static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
  3655. {
  3656. return (1 << dpll->n) << 16 | dpll->m2;
  3657. }
  3658. static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
  3659. {
  3660. return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
  3661. }
  3662. static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
  3663. intel_clock_t *reduced_clock)
  3664. {
  3665. struct drm_device *dev = crtc->base.dev;
  3666. struct drm_i915_private *dev_priv = dev->dev_private;
  3667. int pipe = crtc->pipe;
  3668. u32 fp, fp2 = 0;
  3669. if (IS_PINEVIEW(dev)) {
  3670. fp = pnv_dpll_compute_fp(&crtc->config.dpll);
  3671. if (reduced_clock)
  3672. fp2 = pnv_dpll_compute_fp(reduced_clock);
  3673. } else {
  3674. fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
  3675. if (reduced_clock)
  3676. fp2 = i9xx_dpll_compute_fp(reduced_clock);
  3677. }
  3678. I915_WRITE(FP0(pipe), fp);
  3679. crtc->config.dpll_hw_state.fp0 = fp;
  3680. crtc->lowfreq_avail = false;
  3681. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3682. reduced_clock && i915_powersave) {
  3683. I915_WRITE(FP1(pipe), fp2);
  3684. crtc->config.dpll_hw_state.fp1 = fp2;
  3685. crtc->lowfreq_avail = true;
  3686. } else {
  3687. I915_WRITE(FP1(pipe), fp);
  3688. crtc->config.dpll_hw_state.fp1 = fp;
  3689. }
  3690. }
  3691. static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
  3692. {
  3693. u32 reg_val;
  3694. /*
  3695. * PLLB opamp always calibrates to max value of 0x3f, force enable it
  3696. * and set it to a reasonable value instead.
  3697. */
  3698. reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
  3699. reg_val &= 0xffffff00;
  3700. reg_val |= 0x00000030;
  3701. vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
  3702. reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
  3703. reg_val &= 0x8cffffff;
  3704. reg_val = 0x8c000000;
  3705. vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
  3706. reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
  3707. reg_val &= 0xffffff00;
  3708. vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
  3709. reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
  3710. reg_val &= 0x00ffffff;
  3711. reg_val |= 0xb0000000;
  3712. vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
  3713. }
  3714. static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
  3715. struct intel_link_m_n *m_n)
  3716. {
  3717. struct drm_device *dev = crtc->base.dev;
  3718. struct drm_i915_private *dev_priv = dev->dev_private;
  3719. int pipe = crtc->pipe;
  3720. I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3721. I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
  3722. I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
  3723. I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
  3724. }
  3725. static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
  3726. struct intel_link_m_n *m_n)
  3727. {
  3728. struct drm_device *dev = crtc->base.dev;
  3729. struct drm_i915_private *dev_priv = dev->dev_private;
  3730. int pipe = crtc->pipe;
  3731. enum transcoder transcoder = crtc->config.cpu_transcoder;
  3732. if (INTEL_INFO(dev)->gen >= 5) {
  3733. I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3734. I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
  3735. I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
  3736. I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
  3737. } else {
  3738. I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
  3739. I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
  3740. I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
  3741. I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
  3742. }
  3743. }
  3744. static void intel_dp_set_m_n(struct intel_crtc *crtc)
  3745. {
  3746. if (crtc->config.has_pch_encoder)
  3747. intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3748. else
  3749. intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
  3750. }
  3751. static void vlv_update_pll(struct intel_crtc *crtc)
  3752. {
  3753. struct drm_device *dev = crtc->base.dev;
  3754. struct drm_i915_private *dev_priv = dev->dev_private;
  3755. int pipe = crtc->pipe;
  3756. u32 dpll, mdiv;
  3757. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3758. bool is_hdmi;
  3759. u32 coreclk, reg_val, dpll_md;
  3760. mutex_lock(&dev_priv->dpio_lock);
  3761. is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  3762. bestn = crtc->config.dpll.n;
  3763. bestm1 = crtc->config.dpll.m1;
  3764. bestm2 = crtc->config.dpll.m2;
  3765. bestp1 = crtc->config.dpll.p1;
  3766. bestp2 = crtc->config.dpll.p2;
  3767. /* See eDP HDMI DPIO driver vbios notes doc */
  3768. /* PLL B needs special handling */
  3769. if (pipe)
  3770. vlv_pllb_recal_opamp(dev_priv);
  3771. /* Set up Tx target for periodic Rcomp update */
  3772. vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
  3773. /* Disable target IRef on PLL */
  3774. reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
  3775. reg_val &= 0x00ffffff;
  3776. vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
  3777. /* Disable fast lock */
  3778. vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
  3779. /* Set idtafcrecal before PLL is enabled */
  3780. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3781. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3782. mdiv |= ((bestn << DPIO_N_SHIFT));
  3783. mdiv |= (1 << DPIO_K_SHIFT);
  3784. /*
  3785. * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
  3786. * but we don't support that).
  3787. * Note: don't use the DAC post divider as it seems unstable.
  3788. */
  3789. mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
  3790. vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3791. mdiv |= DPIO_ENABLE_CALIBRATION;
  3792. vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3793. /* Set HBR and RBR LPF coefficients */
  3794. if (crtc->config.port_clock == 162000 ||
  3795. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
  3796. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
  3797. vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
  3798. 0x009f0003);
  3799. else
  3800. vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
  3801. 0x00d0000f);
  3802. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
  3803. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
  3804. /* Use SSC source */
  3805. if (!pipe)
  3806. vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3807. 0x0df40000);
  3808. else
  3809. vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3810. 0x0df70000);
  3811. } else { /* HDMI or VGA */
  3812. /* Use bend source */
  3813. if (!pipe)
  3814. vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3815. 0x0df70000);
  3816. else
  3817. vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
  3818. 0x0df40000);
  3819. }
  3820. coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
  3821. coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
  3822. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
  3823. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
  3824. coreclk |= 0x01000000;
  3825. vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
  3826. vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
  3827. /* Enable DPIO clock input */
  3828. dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
  3829. DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
  3830. if (pipe)
  3831. dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
  3832. dpll |= DPLL_VCO_ENABLE;
  3833. crtc->config.dpll_hw_state.dpll = dpll;
  3834. dpll_md = (crtc->config.pixel_multiplier - 1)
  3835. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3836. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  3837. if (crtc->config.has_dp_encoder)
  3838. intel_dp_set_m_n(crtc);
  3839. mutex_unlock(&dev_priv->dpio_lock);
  3840. }
  3841. static void i9xx_update_pll(struct intel_crtc *crtc,
  3842. intel_clock_t *reduced_clock,
  3843. int num_connectors)
  3844. {
  3845. struct drm_device *dev = crtc->base.dev;
  3846. struct drm_i915_private *dev_priv = dev->dev_private;
  3847. u32 dpll;
  3848. bool is_sdvo;
  3849. struct dpll *clock = &crtc->config.dpll;
  3850. i9xx_update_pll_dividers(crtc, reduced_clock);
  3851. is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
  3852. intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
  3853. dpll = DPLL_VGA_MODE_DIS;
  3854. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
  3855. dpll |= DPLLB_MODE_LVDS;
  3856. else
  3857. dpll |= DPLLB_MODE_DAC_SERIAL;
  3858. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  3859. dpll |= (crtc->config.pixel_multiplier - 1)
  3860. << SDVO_MULTIPLIER_SHIFT_HIRES;
  3861. }
  3862. if (is_sdvo)
  3863. dpll |= DPLL_SDVO_HIGH_SPEED;
  3864. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
  3865. dpll |= DPLL_SDVO_HIGH_SPEED;
  3866. /* compute bitmask from p1 value */
  3867. if (IS_PINEVIEW(dev))
  3868. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3869. else {
  3870. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3871. if (IS_G4X(dev) && reduced_clock)
  3872. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3873. }
  3874. switch (clock->p2) {
  3875. case 5:
  3876. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3877. break;
  3878. case 7:
  3879. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3880. break;
  3881. case 10:
  3882. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3883. break;
  3884. case 14:
  3885. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3886. break;
  3887. }
  3888. if (INTEL_INFO(dev)->gen >= 4)
  3889. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3890. if (crtc->config.sdvo_tv_clock)
  3891. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3892. else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3893. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3894. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3895. else
  3896. dpll |= PLL_REF_INPUT_DREFCLK;
  3897. dpll |= DPLL_VCO_ENABLE;
  3898. crtc->config.dpll_hw_state.dpll = dpll;
  3899. if (INTEL_INFO(dev)->gen >= 4) {
  3900. u32 dpll_md = (crtc->config.pixel_multiplier - 1)
  3901. << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3902. crtc->config.dpll_hw_state.dpll_md = dpll_md;
  3903. }
  3904. if (crtc->config.has_dp_encoder)
  3905. intel_dp_set_m_n(crtc);
  3906. }
  3907. static void i8xx_update_pll(struct intel_crtc *crtc,
  3908. intel_clock_t *reduced_clock,
  3909. int num_connectors)
  3910. {
  3911. struct drm_device *dev = crtc->base.dev;
  3912. struct drm_i915_private *dev_priv = dev->dev_private;
  3913. u32 dpll;
  3914. struct dpll *clock = &crtc->config.dpll;
  3915. i9xx_update_pll_dividers(crtc, reduced_clock);
  3916. dpll = DPLL_VGA_MODE_DIS;
  3917. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
  3918. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3919. } else {
  3920. if (clock->p1 == 2)
  3921. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3922. else
  3923. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3924. if (clock->p2 == 4)
  3925. dpll |= PLL_P2_DIVIDE_BY_4;
  3926. }
  3927. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
  3928. dpll |= DPLL_DVO_2X_MODE;
  3929. if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
  3930. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3931. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3932. else
  3933. dpll |= PLL_REF_INPUT_DREFCLK;
  3934. dpll |= DPLL_VCO_ENABLE;
  3935. crtc->config.dpll_hw_state.dpll = dpll;
  3936. }
  3937. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
  3938. {
  3939. struct drm_device *dev = intel_crtc->base.dev;
  3940. struct drm_i915_private *dev_priv = dev->dev_private;
  3941. enum pipe pipe = intel_crtc->pipe;
  3942. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  3943. struct drm_display_mode *adjusted_mode =
  3944. &intel_crtc->config.adjusted_mode;
  3945. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  3946. uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
  3947. /* We need to be careful not to changed the adjusted mode, for otherwise
  3948. * the hw state checker will get angry at the mismatch. */
  3949. crtc_vtotal = adjusted_mode->crtc_vtotal;
  3950. crtc_vblank_end = adjusted_mode->crtc_vblank_end;
  3951. if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3952. /* the chip adds 2 halflines automatically */
  3953. crtc_vtotal -= 1;
  3954. crtc_vblank_end -= 1;
  3955. vsyncshift = adjusted_mode->crtc_hsync_start
  3956. - adjusted_mode->crtc_htotal / 2;
  3957. } else {
  3958. vsyncshift = 0;
  3959. }
  3960. if (INTEL_INFO(dev)->gen > 3)
  3961. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  3962. I915_WRITE(HTOTAL(cpu_transcoder),
  3963. (adjusted_mode->crtc_hdisplay - 1) |
  3964. ((adjusted_mode->crtc_htotal - 1) << 16));
  3965. I915_WRITE(HBLANK(cpu_transcoder),
  3966. (adjusted_mode->crtc_hblank_start - 1) |
  3967. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3968. I915_WRITE(HSYNC(cpu_transcoder),
  3969. (adjusted_mode->crtc_hsync_start - 1) |
  3970. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3971. I915_WRITE(VTOTAL(cpu_transcoder),
  3972. (adjusted_mode->crtc_vdisplay - 1) |
  3973. ((crtc_vtotal - 1) << 16));
  3974. I915_WRITE(VBLANK(cpu_transcoder),
  3975. (adjusted_mode->crtc_vblank_start - 1) |
  3976. ((crtc_vblank_end - 1) << 16));
  3977. I915_WRITE(VSYNC(cpu_transcoder),
  3978. (adjusted_mode->crtc_vsync_start - 1) |
  3979. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3980. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  3981. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  3982. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  3983. * bits. */
  3984. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  3985. (pipe == PIPE_B || pipe == PIPE_C))
  3986. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  3987. /* pipesrc controls the size that is scaled from, which should
  3988. * always be the user's requested size.
  3989. */
  3990. I915_WRITE(PIPESRC(pipe),
  3991. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3992. }
  3993. static void intel_get_pipe_timings(struct intel_crtc *crtc,
  3994. struct intel_crtc_config *pipe_config)
  3995. {
  3996. struct drm_device *dev = crtc->base.dev;
  3997. struct drm_i915_private *dev_priv = dev->dev_private;
  3998. enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  3999. uint32_t tmp;
  4000. tmp = I915_READ(HTOTAL(cpu_transcoder));
  4001. pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
  4002. pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
  4003. tmp = I915_READ(HBLANK(cpu_transcoder));
  4004. pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
  4005. pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
  4006. tmp = I915_READ(HSYNC(cpu_transcoder));
  4007. pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
  4008. pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
  4009. tmp = I915_READ(VTOTAL(cpu_transcoder));
  4010. pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
  4011. pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
  4012. tmp = I915_READ(VBLANK(cpu_transcoder));
  4013. pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
  4014. pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
  4015. tmp = I915_READ(VSYNC(cpu_transcoder));
  4016. pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
  4017. pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
  4018. if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
  4019. pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
  4020. pipe_config->adjusted_mode.crtc_vtotal += 1;
  4021. pipe_config->adjusted_mode.crtc_vblank_end += 1;
  4022. }
  4023. tmp = I915_READ(PIPESRC(crtc->pipe));
  4024. pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
  4025. pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
  4026. }
  4027. static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
  4028. struct intel_crtc_config *pipe_config)
  4029. {
  4030. struct drm_crtc *crtc = &intel_crtc->base;
  4031. crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
  4032. crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
  4033. crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
  4034. crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
  4035. crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
  4036. crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
  4037. crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
  4038. crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
  4039. crtc->mode.flags = pipe_config->adjusted_mode.flags;
  4040. crtc->mode.clock = pipe_config->adjusted_mode.clock;
  4041. crtc->mode.flags |= pipe_config->adjusted_mode.flags;
  4042. }
  4043. static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
  4044. {
  4045. struct drm_device *dev = intel_crtc->base.dev;
  4046. struct drm_i915_private *dev_priv = dev->dev_private;
  4047. uint32_t pipeconf;
  4048. pipeconf = 0;
  4049. if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  4050. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  4051. * core speed.
  4052. *
  4053. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  4054. * pipe == 0 check?
  4055. */
  4056. if (intel_crtc->config.requested_mode.clock >
  4057. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  4058. pipeconf |= PIPECONF_DOUBLE_WIDE;
  4059. }
  4060. /* only g4x and later have fancy bpc/dither controls */
  4061. if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
  4062. /* Bspec claims that we can't use dithering for 30bpp pipes. */
  4063. if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
  4064. pipeconf |= PIPECONF_DITHER_EN |
  4065. PIPECONF_DITHER_TYPE_SP;
  4066. switch (intel_crtc->config.pipe_bpp) {
  4067. case 18:
  4068. pipeconf |= PIPECONF_6BPC;
  4069. break;
  4070. case 24:
  4071. pipeconf |= PIPECONF_8BPC;
  4072. break;
  4073. case 30:
  4074. pipeconf |= PIPECONF_10BPC;
  4075. break;
  4076. default:
  4077. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4078. BUG();
  4079. }
  4080. }
  4081. if (HAS_PIPE_CXSR(dev)) {
  4082. if (intel_crtc->lowfreq_avail) {
  4083. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4084. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4085. } else {
  4086. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4087. }
  4088. }
  4089. if (!IS_GEN2(dev) &&
  4090. intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4091. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4092. else
  4093. pipeconf |= PIPECONF_PROGRESSIVE;
  4094. if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
  4095. pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
  4096. I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
  4097. POSTING_READ(PIPECONF(intel_crtc->pipe));
  4098. }
  4099. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4100. int x, int y,
  4101. struct drm_framebuffer *fb)
  4102. {
  4103. struct drm_device *dev = crtc->dev;
  4104. struct drm_i915_private *dev_priv = dev->dev_private;
  4105. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4106. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  4107. int pipe = intel_crtc->pipe;
  4108. int plane = intel_crtc->plane;
  4109. int refclk, num_connectors = 0;
  4110. intel_clock_t clock, reduced_clock;
  4111. u32 dspcntr;
  4112. bool ok, has_reduced_clock = false;
  4113. bool is_lvds = false;
  4114. struct intel_encoder *encoder;
  4115. const intel_limit_t *limit;
  4116. int ret;
  4117. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4118. switch (encoder->type) {
  4119. case INTEL_OUTPUT_LVDS:
  4120. is_lvds = true;
  4121. break;
  4122. }
  4123. num_connectors++;
  4124. }
  4125. refclk = i9xx_get_refclk(crtc, num_connectors);
  4126. /*
  4127. * Returns a set of divisors for the desired target clock with the given
  4128. * refclk, or FALSE. The returned values represent the clock equation:
  4129. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4130. */
  4131. limit = intel_limit(crtc, refclk);
  4132. ok = dev_priv->display.find_dpll(limit, crtc,
  4133. intel_crtc->config.port_clock,
  4134. refclk, NULL, &clock);
  4135. if (!ok && !intel_crtc->config.clock_set) {
  4136. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4137. return -EINVAL;
  4138. }
  4139. /* Ensure that the cursor is valid for the new mode before changing... */
  4140. intel_crtc_update_cursor(crtc, true);
  4141. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4142. /*
  4143. * Ensure we match the reduced clock's P to the target clock.
  4144. * If the clocks don't match, we can't switch the display clock
  4145. * by using the FP0/FP1. In such case we will disable the LVDS
  4146. * downclock feature.
  4147. */
  4148. has_reduced_clock =
  4149. dev_priv->display.find_dpll(limit, crtc,
  4150. dev_priv->lvds_downclock,
  4151. refclk, &clock,
  4152. &reduced_clock);
  4153. }
  4154. /* Compat-code for transition, will disappear. */
  4155. if (!intel_crtc->config.clock_set) {
  4156. intel_crtc->config.dpll.n = clock.n;
  4157. intel_crtc->config.dpll.m1 = clock.m1;
  4158. intel_crtc->config.dpll.m2 = clock.m2;
  4159. intel_crtc->config.dpll.p1 = clock.p1;
  4160. intel_crtc->config.dpll.p2 = clock.p2;
  4161. }
  4162. if (IS_GEN2(dev))
  4163. i8xx_update_pll(intel_crtc,
  4164. has_reduced_clock ? &reduced_clock : NULL,
  4165. num_connectors);
  4166. else if (IS_VALLEYVIEW(dev))
  4167. vlv_update_pll(intel_crtc);
  4168. else
  4169. i9xx_update_pll(intel_crtc,
  4170. has_reduced_clock ? &reduced_clock : NULL,
  4171. num_connectors);
  4172. /* Set up the display plane register */
  4173. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4174. if (!IS_VALLEYVIEW(dev)) {
  4175. if (pipe == 0)
  4176. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4177. else
  4178. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4179. }
  4180. intel_set_pipe_timings(intel_crtc);
  4181. /* pipesrc and dspsize control the size that is scaled from,
  4182. * which should always be the user's requested size.
  4183. */
  4184. I915_WRITE(DSPSIZE(plane),
  4185. ((mode->vdisplay - 1) << 16) |
  4186. (mode->hdisplay - 1));
  4187. I915_WRITE(DSPPOS(plane), 0);
  4188. i9xx_set_pipeconf(intel_crtc);
  4189. I915_WRITE(DSPCNTR(plane), dspcntr);
  4190. POSTING_READ(DSPCNTR(plane));
  4191. ret = intel_pipe_set_base(crtc, x, y, fb);
  4192. intel_update_watermarks(dev);
  4193. return ret;
  4194. }
  4195. static void i9xx_get_pfit_config(struct intel_crtc *crtc,
  4196. struct intel_crtc_config *pipe_config)
  4197. {
  4198. struct drm_device *dev = crtc->base.dev;
  4199. struct drm_i915_private *dev_priv = dev->dev_private;
  4200. uint32_t tmp;
  4201. tmp = I915_READ(PFIT_CONTROL);
  4202. if (!(tmp & PFIT_ENABLE))
  4203. return;
  4204. /* Check whether the pfit is attached to our pipe. */
  4205. if (INTEL_INFO(dev)->gen < 4) {
  4206. if (crtc->pipe != PIPE_B)
  4207. return;
  4208. } else {
  4209. if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
  4210. return;
  4211. }
  4212. pipe_config->gmch_pfit.control = tmp;
  4213. pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
  4214. if (INTEL_INFO(dev)->gen < 5)
  4215. pipe_config->gmch_pfit.lvds_border_bits =
  4216. I915_READ(LVDS) & LVDS_BORDER_ENABLE;
  4217. }
  4218. static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
  4219. struct intel_crtc_config *pipe_config)
  4220. {
  4221. struct drm_device *dev = crtc->base.dev;
  4222. struct drm_i915_private *dev_priv = dev->dev_private;
  4223. uint32_t tmp;
  4224. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  4225. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  4226. tmp = I915_READ(PIPECONF(crtc->pipe));
  4227. if (!(tmp & PIPECONF_ENABLE))
  4228. return false;
  4229. intel_get_pipe_timings(crtc, pipe_config);
  4230. i9xx_get_pfit_config(crtc, pipe_config);
  4231. if (INTEL_INFO(dev)->gen >= 4) {
  4232. tmp = I915_READ(DPLL_MD(crtc->pipe));
  4233. pipe_config->pixel_multiplier =
  4234. ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
  4235. >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
  4236. pipe_config->dpll_hw_state.dpll_md = tmp;
  4237. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  4238. tmp = I915_READ(DPLL(crtc->pipe));
  4239. pipe_config->pixel_multiplier =
  4240. ((tmp & SDVO_MULTIPLIER_MASK)
  4241. >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
  4242. } else {
  4243. /* Note that on i915G/GM the pixel multiplier is in the sdvo
  4244. * port and will be fixed up in the encoder->get_config
  4245. * function. */
  4246. pipe_config->pixel_multiplier = 1;
  4247. }
  4248. pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
  4249. if (!IS_VALLEYVIEW(dev)) {
  4250. pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
  4251. pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
  4252. } else {
  4253. /* Mask out read-only status bits. */
  4254. pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
  4255. DPLL_PORTC_READY_MASK |
  4256. DPLL_PORTB_READY_MASK);
  4257. }
  4258. return true;
  4259. }
  4260. static void ironlake_init_pch_refclk(struct drm_device *dev)
  4261. {
  4262. struct drm_i915_private *dev_priv = dev->dev_private;
  4263. struct drm_mode_config *mode_config = &dev->mode_config;
  4264. struct intel_encoder *encoder;
  4265. u32 val, final;
  4266. bool has_lvds = false;
  4267. bool has_cpu_edp = false;
  4268. bool has_panel = false;
  4269. bool has_ck505 = false;
  4270. bool can_ssc = false;
  4271. /* We need to take the global config into account */
  4272. list_for_each_entry(encoder, &mode_config->encoder_list,
  4273. base.head) {
  4274. switch (encoder->type) {
  4275. case INTEL_OUTPUT_LVDS:
  4276. has_panel = true;
  4277. has_lvds = true;
  4278. break;
  4279. case INTEL_OUTPUT_EDP:
  4280. has_panel = true;
  4281. if (enc_to_dig_port(&encoder->base)->port == PORT_A)
  4282. has_cpu_edp = true;
  4283. break;
  4284. }
  4285. }
  4286. if (HAS_PCH_IBX(dev)) {
  4287. has_ck505 = dev_priv->vbt.display_clock_mode;
  4288. can_ssc = has_ck505;
  4289. } else {
  4290. has_ck505 = false;
  4291. can_ssc = true;
  4292. }
  4293. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
  4294. has_panel, has_lvds, has_ck505);
  4295. /* Ironlake: try to setup display ref clock before DPLL
  4296. * enabling. This is only under driver's control after
  4297. * PCH B stepping, previous chipset stepping should be
  4298. * ignoring this setting.
  4299. */
  4300. val = I915_READ(PCH_DREF_CONTROL);
  4301. /* As we must carefully and slowly disable/enable each source in turn,
  4302. * compute the final state we want first and check if we need to
  4303. * make any changes at all.
  4304. */
  4305. final = val;
  4306. final &= ~DREF_NONSPREAD_SOURCE_MASK;
  4307. if (has_ck505)
  4308. final |= DREF_NONSPREAD_CK505_ENABLE;
  4309. else
  4310. final |= DREF_NONSPREAD_SOURCE_ENABLE;
  4311. final &= ~DREF_SSC_SOURCE_MASK;
  4312. final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4313. final &= ~DREF_SSC1_ENABLE;
  4314. if (has_panel) {
  4315. final |= DREF_SSC_SOURCE_ENABLE;
  4316. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4317. final |= DREF_SSC1_ENABLE;
  4318. if (has_cpu_edp) {
  4319. if (intel_panel_use_ssc(dev_priv) && can_ssc)
  4320. final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4321. else
  4322. final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4323. } else
  4324. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4325. } else {
  4326. final |= DREF_SSC_SOURCE_DISABLE;
  4327. final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4328. }
  4329. if (final == val)
  4330. return;
  4331. /* Always enable nonspread source */
  4332. val &= ~DREF_NONSPREAD_SOURCE_MASK;
  4333. if (has_ck505)
  4334. val |= DREF_NONSPREAD_CK505_ENABLE;
  4335. else
  4336. val |= DREF_NONSPREAD_SOURCE_ENABLE;
  4337. if (has_panel) {
  4338. val &= ~DREF_SSC_SOURCE_MASK;
  4339. val |= DREF_SSC_SOURCE_ENABLE;
  4340. /* SSC must be turned on before enabling the CPU output */
  4341. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4342. DRM_DEBUG_KMS("Using SSC on panel\n");
  4343. val |= DREF_SSC1_ENABLE;
  4344. } else
  4345. val &= ~DREF_SSC1_ENABLE;
  4346. /* Get SSC going before enabling the outputs */
  4347. I915_WRITE(PCH_DREF_CONTROL, val);
  4348. POSTING_READ(PCH_DREF_CONTROL);
  4349. udelay(200);
  4350. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4351. /* Enable CPU source on CPU attached eDP */
  4352. if (has_cpu_edp) {
  4353. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4354. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4355. val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4356. }
  4357. else
  4358. val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4359. } else
  4360. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4361. I915_WRITE(PCH_DREF_CONTROL, val);
  4362. POSTING_READ(PCH_DREF_CONTROL);
  4363. udelay(200);
  4364. } else {
  4365. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4366. val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4367. /* Turn off CPU output */
  4368. val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4369. I915_WRITE(PCH_DREF_CONTROL, val);
  4370. POSTING_READ(PCH_DREF_CONTROL);
  4371. udelay(200);
  4372. /* Turn off the SSC source */
  4373. val &= ~DREF_SSC_SOURCE_MASK;
  4374. val |= DREF_SSC_SOURCE_DISABLE;
  4375. /* Turn off SSC1 */
  4376. val &= ~DREF_SSC1_ENABLE;
  4377. I915_WRITE(PCH_DREF_CONTROL, val);
  4378. POSTING_READ(PCH_DREF_CONTROL);
  4379. udelay(200);
  4380. }
  4381. BUG_ON(val != final);
  4382. }
  4383. static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
  4384. {
  4385. uint32_t tmp;
  4386. tmp = I915_READ(SOUTH_CHICKEN2);
  4387. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  4388. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4389. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  4390. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  4391. DRM_ERROR("FDI mPHY reset assert timeout\n");
  4392. tmp = I915_READ(SOUTH_CHICKEN2);
  4393. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  4394. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4395. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  4396. FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
  4397. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  4398. }
  4399. /* WaMPhyProgramming:hsw */
  4400. static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
  4401. {
  4402. uint32_t tmp;
  4403. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  4404. tmp &= ~(0xFF << 24);
  4405. tmp |= (0x12 << 24);
  4406. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  4407. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  4408. tmp |= (1 << 11);
  4409. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  4410. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  4411. tmp |= (1 << 11);
  4412. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  4413. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  4414. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4415. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  4416. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  4417. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4418. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  4419. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  4420. tmp &= ~(7 << 13);
  4421. tmp |= (5 << 13);
  4422. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  4423. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  4424. tmp &= ~(7 << 13);
  4425. tmp |= (5 << 13);
  4426. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  4427. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  4428. tmp &= ~0xFF;
  4429. tmp |= 0x1C;
  4430. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  4431. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  4432. tmp &= ~0xFF;
  4433. tmp |= 0x1C;
  4434. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  4435. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  4436. tmp &= ~(0xFF << 16);
  4437. tmp |= (0x1C << 16);
  4438. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  4439. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  4440. tmp &= ~(0xFF << 16);
  4441. tmp |= (0x1C << 16);
  4442. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  4443. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  4444. tmp |= (1 << 27);
  4445. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  4446. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  4447. tmp |= (1 << 27);
  4448. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  4449. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  4450. tmp &= ~(0xF << 28);
  4451. tmp |= (4 << 28);
  4452. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  4453. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  4454. tmp &= ~(0xF << 28);
  4455. tmp |= (4 << 28);
  4456. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  4457. }
  4458. /* Implements 3 different sequences from BSpec chapter "Display iCLK
  4459. * Programming" based on the parameters passed:
  4460. * - Sequence to enable CLKOUT_DP
  4461. * - Sequence to enable CLKOUT_DP without spread
  4462. * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
  4463. */
  4464. static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
  4465. bool with_fdi)
  4466. {
  4467. struct drm_i915_private *dev_priv = dev->dev_private;
  4468. uint32_t reg, tmp;
  4469. if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
  4470. with_spread = true;
  4471. if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
  4472. with_fdi, "LP PCH doesn't have FDI\n"))
  4473. with_fdi = false;
  4474. mutex_lock(&dev_priv->dpio_lock);
  4475. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4476. tmp &= ~SBI_SSCCTL_DISABLE;
  4477. tmp |= SBI_SSCCTL_PATHALT;
  4478. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4479. udelay(24);
  4480. if (with_spread) {
  4481. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4482. tmp &= ~SBI_SSCCTL_PATHALT;
  4483. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4484. if (with_fdi) {
  4485. lpt_reset_fdi_mphy(dev_priv);
  4486. lpt_program_fdi_mphy(dev_priv);
  4487. }
  4488. }
  4489. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4490. SBI_GEN0 : SBI_DBUFF0;
  4491. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4492. tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4493. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4494. mutex_unlock(&dev_priv->dpio_lock);
  4495. }
  4496. /* Sequence to disable CLKOUT_DP */
  4497. static void lpt_disable_clkout_dp(struct drm_device *dev)
  4498. {
  4499. struct drm_i915_private *dev_priv = dev->dev_private;
  4500. uint32_t reg, tmp;
  4501. mutex_lock(&dev_priv->dpio_lock);
  4502. reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
  4503. SBI_GEN0 : SBI_DBUFF0;
  4504. tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
  4505. tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
  4506. intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
  4507. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4508. if (!(tmp & SBI_SSCCTL_DISABLE)) {
  4509. if (!(tmp & SBI_SSCCTL_PATHALT)) {
  4510. tmp |= SBI_SSCCTL_PATHALT;
  4511. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4512. udelay(32);
  4513. }
  4514. tmp |= SBI_SSCCTL_DISABLE;
  4515. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4516. }
  4517. mutex_unlock(&dev_priv->dpio_lock);
  4518. }
  4519. static void lpt_init_pch_refclk(struct drm_device *dev)
  4520. {
  4521. struct drm_mode_config *mode_config = &dev->mode_config;
  4522. struct intel_encoder *encoder;
  4523. bool has_vga = false;
  4524. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4525. switch (encoder->type) {
  4526. case INTEL_OUTPUT_ANALOG:
  4527. has_vga = true;
  4528. break;
  4529. }
  4530. }
  4531. if (has_vga)
  4532. lpt_enable_clkout_dp(dev, true, true);
  4533. else
  4534. lpt_disable_clkout_dp(dev);
  4535. }
  4536. /*
  4537. * Initialize reference clocks when the driver loads
  4538. */
  4539. void intel_init_pch_refclk(struct drm_device *dev)
  4540. {
  4541. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4542. ironlake_init_pch_refclk(dev);
  4543. else if (HAS_PCH_LPT(dev))
  4544. lpt_init_pch_refclk(dev);
  4545. }
  4546. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4547. {
  4548. struct drm_device *dev = crtc->dev;
  4549. struct drm_i915_private *dev_priv = dev->dev_private;
  4550. struct intel_encoder *encoder;
  4551. int num_connectors = 0;
  4552. bool is_lvds = false;
  4553. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4554. switch (encoder->type) {
  4555. case INTEL_OUTPUT_LVDS:
  4556. is_lvds = true;
  4557. break;
  4558. }
  4559. num_connectors++;
  4560. }
  4561. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4562. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4563. dev_priv->vbt.lvds_ssc_freq);
  4564. return dev_priv->vbt.lvds_ssc_freq * 1000;
  4565. }
  4566. return 120000;
  4567. }
  4568. static void ironlake_set_pipeconf(struct drm_crtc *crtc)
  4569. {
  4570. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4571. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4572. int pipe = intel_crtc->pipe;
  4573. uint32_t val;
  4574. val = 0;
  4575. switch (intel_crtc->config.pipe_bpp) {
  4576. case 18:
  4577. val |= PIPECONF_6BPC;
  4578. break;
  4579. case 24:
  4580. val |= PIPECONF_8BPC;
  4581. break;
  4582. case 30:
  4583. val |= PIPECONF_10BPC;
  4584. break;
  4585. case 36:
  4586. val |= PIPECONF_12BPC;
  4587. break;
  4588. default:
  4589. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4590. BUG();
  4591. }
  4592. if (intel_crtc->config.dither)
  4593. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4594. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4595. val |= PIPECONF_INTERLACED_ILK;
  4596. else
  4597. val |= PIPECONF_PROGRESSIVE;
  4598. if (intel_crtc->config.limited_color_range)
  4599. val |= PIPECONF_COLOR_RANGE_SELECT;
  4600. I915_WRITE(PIPECONF(pipe), val);
  4601. POSTING_READ(PIPECONF(pipe));
  4602. }
  4603. /*
  4604. * Set up the pipe CSC unit.
  4605. *
  4606. * Currently only full range RGB to limited range RGB conversion
  4607. * is supported, but eventually this should handle various
  4608. * RGB<->YCbCr scenarios as well.
  4609. */
  4610. static void intel_set_pipe_csc(struct drm_crtc *crtc)
  4611. {
  4612. struct drm_device *dev = crtc->dev;
  4613. struct drm_i915_private *dev_priv = dev->dev_private;
  4614. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4615. int pipe = intel_crtc->pipe;
  4616. uint16_t coeff = 0x7800; /* 1.0 */
  4617. /*
  4618. * TODO: Check what kind of values actually come out of the pipe
  4619. * with these coeff/postoff values and adjust to get the best
  4620. * accuracy. Perhaps we even need to take the bpc value into
  4621. * consideration.
  4622. */
  4623. if (intel_crtc->config.limited_color_range)
  4624. coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
  4625. /*
  4626. * GY/GU and RY/RU should be the other way around according
  4627. * to BSpec, but reality doesn't agree. Just set them up in
  4628. * a way that results in the correct picture.
  4629. */
  4630. I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
  4631. I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
  4632. I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
  4633. I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
  4634. I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
  4635. I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
  4636. I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
  4637. I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
  4638. I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
  4639. if (INTEL_INFO(dev)->gen > 6) {
  4640. uint16_t postoff = 0;
  4641. if (intel_crtc->config.limited_color_range)
  4642. postoff = (16 * (1 << 13) / 255) & 0x1fff;
  4643. I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
  4644. I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
  4645. I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
  4646. I915_WRITE(PIPE_CSC_MODE(pipe), 0);
  4647. } else {
  4648. uint32_t mode = CSC_MODE_YUV_TO_RGB;
  4649. if (intel_crtc->config.limited_color_range)
  4650. mode |= CSC_BLACK_SCREEN_OFFSET;
  4651. I915_WRITE(PIPE_CSC_MODE(pipe), mode);
  4652. }
  4653. }
  4654. static void haswell_set_pipeconf(struct drm_crtc *crtc)
  4655. {
  4656. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4657. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4658. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  4659. uint32_t val;
  4660. val = 0;
  4661. if (intel_crtc->config.dither)
  4662. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4663. if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
  4664. val |= PIPECONF_INTERLACED_ILK;
  4665. else
  4666. val |= PIPECONF_PROGRESSIVE;
  4667. I915_WRITE(PIPECONF(cpu_transcoder), val);
  4668. POSTING_READ(PIPECONF(cpu_transcoder));
  4669. I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
  4670. POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
  4671. }
  4672. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  4673. intel_clock_t *clock,
  4674. bool *has_reduced_clock,
  4675. intel_clock_t *reduced_clock)
  4676. {
  4677. struct drm_device *dev = crtc->dev;
  4678. struct drm_i915_private *dev_priv = dev->dev_private;
  4679. struct intel_encoder *intel_encoder;
  4680. int refclk;
  4681. const intel_limit_t *limit;
  4682. bool ret, is_lvds = false;
  4683. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4684. switch (intel_encoder->type) {
  4685. case INTEL_OUTPUT_LVDS:
  4686. is_lvds = true;
  4687. break;
  4688. }
  4689. }
  4690. refclk = ironlake_get_refclk(crtc);
  4691. /*
  4692. * Returns a set of divisors for the desired target clock with the given
  4693. * refclk, or FALSE. The returned values represent the clock equation:
  4694. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4695. */
  4696. limit = intel_limit(crtc, refclk);
  4697. ret = dev_priv->display.find_dpll(limit, crtc,
  4698. to_intel_crtc(crtc)->config.port_clock,
  4699. refclk, NULL, clock);
  4700. if (!ret)
  4701. return false;
  4702. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4703. /*
  4704. * Ensure we match the reduced clock's P to the target clock.
  4705. * If the clocks don't match, we can't switch the display clock
  4706. * by using the FP0/FP1. In such case we will disable the LVDS
  4707. * downclock feature.
  4708. */
  4709. *has_reduced_clock =
  4710. dev_priv->display.find_dpll(limit, crtc,
  4711. dev_priv->lvds_downclock,
  4712. refclk, clock,
  4713. reduced_clock);
  4714. }
  4715. return true;
  4716. }
  4717. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  4718. {
  4719. struct drm_i915_private *dev_priv = dev->dev_private;
  4720. uint32_t temp;
  4721. temp = I915_READ(SOUTH_CHICKEN1);
  4722. if (temp & FDI_BC_BIFURCATION_SELECT)
  4723. return;
  4724. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4725. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4726. temp |= FDI_BC_BIFURCATION_SELECT;
  4727. DRM_DEBUG_KMS("enabling fdi C rx\n");
  4728. I915_WRITE(SOUTH_CHICKEN1, temp);
  4729. POSTING_READ(SOUTH_CHICKEN1);
  4730. }
  4731. static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
  4732. {
  4733. struct drm_device *dev = intel_crtc->base.dev;
  4734. struct drm_i915_private *dev_priv = dev->dev_private;
  4735. switch (intel_crtc->pipe) {
  4736. case PIPE_A:
  4737. break;
  4738. case PIPE_B:
  4739. if (intel_crtc->config.fdi_lanes > 2)
  4740. WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  4741. else
  4742. cpt_enable_fdi_bc_bifurcation(dev);
  4743. break;
  4744. case PIPE_C:
  4745. cpt_enable_fdi_bc_bifurcation(dev);
  4746. break;
  4747. default:
  4748. BUG();
  4749. }
  4750. }
  4751. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  4752. {
  4753. /*
  4754. * Account for spread spectrum to avoid
  4755. * oversubscribing the link. Max center spread
  4756. * is 2.5%; use 5% for safety's sake.
  4757. */
  4758. u32 bps = target_clock * bpp * 21 / 20;
  4759. return bps / (link_bw * 8) + 1;
  4760. }
  4761. static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
  4762. {
  4763. return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
  4764. }
  4765. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  4766. u32 *fp,
  4767. intel_clock_t *reduced_clock, u32 *fp2)
  4768. {
  4769. struct drm_crtc *crtc = &intel_crtc->base;
  4770. struct drm_device *dev = crtc->dev;
  4771. struct drm_i915_private *dev_priv = dev->dev_private;
  4772. struct intel_encoder *intel_encoder;
  4773. uint32_t dpll;
  4774. int factor, num_connectors = 0;
  4775. bool is_lvds = false, is_sdvo = false;
  4776. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4777. switch (intel_encoder->type) {
  4778. case INTEL_OUTPUT_LVDS:
  4779. is_lvds = true;
  4780. break;
  4781. case INTEL_OUTPUT_SDVO:
  4782. case INTEL_OUTPUT_HDMI:
  4783. is_sdvo = true;
  4784. break;
  4785. }
  4786. num_connectors++;
  4787. }
  4788. /* Enable autotuning of the PLL clock (if permissible) */
  4789. factor = 21;
  4790. if (is_lvds) {
  4791. if ((intel_panel_use_ssc(dev_priv) &&
  4792. dev_priv->vbt.lvds_ssc_freq == 100) ||
  4793. (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
  4794. factor = 25;
  4795. } else if (intel_crtc->config.sdvo_tv_clock)
  4796. factor = 20;
  4797. if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
  4798. *fp |= FP_CB_TUNE;
  4799. if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
  4800. *fp2 |= FP_CB_TUNE;
  4801. dpll = 0;
  4802. if (is_lvds)
  4803. dpll |= DPLLB_MODE_LVDS;
  4804. else
  4805. dpll |= DPLLB_MODE_DAC_SERIAL;
  4806. dpll |= (intel_crtc->config.pixel_multiplier - 1)
  4807. << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4808. if (is_sdvo)
  4809. dpll |= DPLL_SDVO_HIGH_SPEED;
  4810. if (intel_crtc->config.has_dp_encoder)
  4811. dpll |= DPLL_SDVO_HIGH_SPEED;
  4812. /* compute bitmask from p1 value */
  4813. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4814. /* also FPA1 */
  4815. dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4816. switch (intel_crtc->config.dpll.p2) {
  4817. case 5:
  4818. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4819. break;
  4820. case 7:
  4821. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4822. break;
  4823. case 10:
  4824. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4825. break;
  4826. case 14:
  4827. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4828. break;
  4829. }
  4830. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4831. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4832. else
  4833. dpll |= PLL_REF_INPUT_DREFCLK;
  4834. return dpll | DPLL_VCO_ENABLE;
  4835. }
  4836. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4837. int x, int y,
  4838. struct drm_framebuffer *fb)
  4839. {
  4840. struct drm_device *dev = crtc->dev;
  4841. struct drm_i915_private *dev_priv = dev->dev_private;
  4842. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4843. int pipe = intel_crtc->pipe;
  4844. int plane = intel_crtc->plane;
  4845. int num_connectors = 0;
  4846. intel_clock_t clock, reduced_clock;
  4847. u32 dpll = 0, fp = 0, fp2 = 0;
  4848. bool ok, has_reduced_clock = false;
  4849. bool is_lvds = false;
  4850. struct intel_encoder *encoder;
  4851. struct intel_shared_dpll *pll;
  4852. int ret;
  4853. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4854. switch (encoder->type) {
  4855. case INTEL_OUTPUT_LVDS:
  4856. is_lvds = true;
  4857. break;
  4858. }
  4859. num_connectors++;
  4860. }
  4861. WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  4862. "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  4863. ok = ironlake_compute_clocks(crtc, &clock,
  4864. &has_reduced_clock, &reduced_clock);
  4865. if (!ok && !intel_crtc->config.clock_set) {
  4866. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4867. return -EINVAL;
  4868. }
  4869. /* Compat-code for transition, will disappear. */
  4870. if (!intel_crtc->config.clock_set) {
  4871. intel_crtc->config.dpll.n = clock.n;
  4872. intel_crtc->config.dpll.m1 = clock.m1;
  4873. intel_crtc->config.dpll.m2 = clock.m2;
  4874. intel_crtc->config.dpll.p1 = clock.p1;
  4875. intel_crtc->config.dpll.p2 = clock.p2;
  4876. }
  4877. /* Ensure that the cursor is valid for the new mode before changing... */
  4878. intel_crtc_update_cursor(crtc, true);
  4879. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  4880. if (intel_crtc->config.has_pch_encoder) {
  4881. fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
  4882. if (has_reduced_clock)
  4883. fp2 = i9xx_dpll_compute_fp(&reduced_clock);
  4884. dpll = ironlake_compute_dpll(intel_crtc,
  4885. &fp, &reduced_clock,
  4886. has_reduced_clock ? &fp2 : NULL);
  4887. intel_crtc->config.dpll_hw_state.dpll = dpll;
  4888. intel_crtc->config.dpll_hw_state.fp0 = fp;
  4889. if (has_reduced_clock)
  4890. intel_crtc->config.dpll_hw_state.fp1 = fp2;
  4891. else
  4892. intel_crtc->config.dpll_hw_state.fp1 = fp;
  4893. pll = intel_get_shared_dpll(intel_crtc);
  4894. if (pll == NULL) {
  4895. DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
  4896. pipe_name(pipe));
  4897. return -EINVAL;
  4898. }
  4899. } else
  4900. intel_put_shared_dpll(intel_crtc);
  4901. if (intel_crtc->config.has_dp_encoder)
  4902. intel_dp_set_m_n(intel_crtc);
  4903. if (is_lvds && has_reduced_clock && i915_powersave)
  4904. intel_crtc->lowfreq_avail = true;
  4905. else
  4906. intel_crtc->lowfreq_avail = false;
  4907. if (intel_crtc->config.has_pch_encoder) {
  4908. pll = intel_crtc_to_shared_dpll(intel_crtc);
  4909. }
  4910. intel_set_pipe_timings(intel_crtc);
  4911. if (intel_crtc->config.has_pch_encoder) {
  4912. intel_cpu_transcoder_set_m_n(intel_crtc,
  4913. &intel_crtc->config.fdi_m_n);
  4914. }
  4915. if (IS_IVYBRIDGE(dev))
  4916. ivybridge_update_fdi_bc_bifurcation(intel_crtc);
  4917. ironlake_set_pipeconf(crtc);
  4918. /* Set up the display plane register */
  4919. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  4920. POSTING_READ(DSPCNTR(plane));
  4921. ret = intel_pipe_set_base(crtc, x, y, fb);
  4922. intel_update_watermarks(dev);
  4923. return ret;
  4924. }
  4925. static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
  4926. struct intel_crtc_config *pipe_config)
  4927. {
  4928. struct drm_device *dev = crtc->base.dev;
  4929. struct drm_i915_private *dev_priv = dev->dev_private;
  4930. enum transcoder transcoder = pipe_config->cpu_transcoder;
  4931. pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
  4932. pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
  4933. pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
  4934. & ~TU_SIZE_MASK;
  4935. pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
  4936. pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
  4937. & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
  4938. }
  4939. static void ironlake_get_pfit_config(struct intel_crtc *crtc,
  4940. struct intel_crtc_config *pipe_config)
  4941. {
  4942. struct drm_device *dev = crtc->base.dev;
  4943. struct drm_i915_private *dev_priv = dev->dev_private;
  4944. uint32_t tmp;
  4945. tmp = I915_READ(PF_CTL(crtc->pipe));
  4946. if (tmp & PF_ENABLE) {
  4947. pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
  4948. pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
  4949. /* We currently do not free assignements of panel fitters on
  4950. * ivb/hsw (since we don't use the higher upscaling modes which
  4951. * differentiates them) so just WARN about this case for now. */
  4952. if (IS_GEN7(dev)) {
  4953. WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
  4954. PF_PIPE_SEL_IVB(crtc->pipe));
  4955. }
  4956. }
  4957. }
  4958. static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
  4959. struct intel_crtc_config *pipe_config)
  4960. {
  4961. struct drm_device *dev = crtc->base.dev;
  4962. struct drm_i915_private *dev_priv = dev->dev_private;
  4963. uint32_t tmp;
  4964. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  4965. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  4966. tmp = I915_READ(PIPECONF(crtc->pipe));
  4967. if (!(tmp & PIPECONF_ENABLE))
  4968. return false;
  4969. if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
  4970. struct intel_shared_dpll *pll;
  4971. pipe_config->has_pch_encoder = true;
  4972. tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
  4973. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  4974. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  4975. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  4976. if (HAS_PCH_IBX(dev_priv->dev)) {
  4977. pipe_config->shared_dpll =
  4978. (enum intel_dpll_id) crtc->pipe;
  4979. } else {
  4980. tmp = I915_READ(PCH_DPLL_SEL);
  4981. if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
  4982. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
  4983. else
  4984. pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
  4985. }
  4986. pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
  4987. WARN_ON(!pll->get_hw_state(dev_priv, pll,
  4988. &pipe_config->dpll_hw_state));
  4989. tmp = pipe_config->dpll_hw_state.dpll;
  4990. pipe_config->pixel_multiplier =
  4991. ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
  4992. >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
  4993. } else {
  4994. pipe_config->pixel_multiplier = 1;
  4995. }
  4996. intel_get_pipe_timings(crtc, pipe_config);
  4997. ironlake_get_pfit_config(crtc, pipe_config);
  4998. return true;
  4999. }
  5000. static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
  5001. {
  5002. struct drm_device *dev = dev_priv->dev;
  5003. struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
  5004. struct intel_crtc *crtc;
  5005. unsigned long irqflags;
  5006. uint32_t val, pch_hpd_mask;
  5007. pch_hpd_mask = SDE_PORTB_HOTPLUG_CPT | SDE_PORTC_HOTPLUG_CPT;
  5008. if (!(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE))
  5009. pch_hpd_mask |= SDE_PORTD_HOTPLUG_CPT | SDE_CRT_HOTPLUG_CPT;
  5010. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
  5011. WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
  5012. pipe_name(crtc->pipe));
  5013. WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
  5014. WARN(plls->spll_refcount, "SPLL enabled\n");
  5015. WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
  5016. WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
  5017. WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
  5018. WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
  5019. "CPU PWM1 enabled\n");
  5020. WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
  5021. "CPU PWM2 enabled\n");
  5022. WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
  5023. "PCH PWM1 enabled\n");
  5024. WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
  5025. "Utility pin enabled\n");
  5026. WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
  5027. spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  5028. val = I915_READ(DEIMR);
  5029. WARN((val & ~DE_PCH_EVENT_IVB) != val,
  5030. "Unexpected DEIMR bits enabled: 0x%x\n", val);
  5031. val = I915_READ(SDEIMR);
  5032. WARN((val & ~pch_hpd_mask) != val,
  5033. "Unexpected SDEIMR bits enabled: 0x%x\n", val);
  5034. spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
  5035. }
  5036. /*
  5037. * This function implements pieces of two sequences from BSpec:
  5038. * - Sequence for display software to disable LCPLL
  5039. * - Sequence for display software to allow package C8+
  5040. * The steps implemented here are just the steps that actually touch the LCPLL
  5041. * register. Callers should take care of disabling all the display engine
  5042. * functions, doing the mode unset, fixing interrupts, etc.
  5043. */
  5044. void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
  5045. bool switch_to_fclk, bool allow_power_down)
  5046. {
  5047. uint32_t val;
  5048. assert_can_disable_lcpll(dev_priv);
  5049. val = I915_READ(LCPLL_CTL);
  5050. if (switch_to_fclk) {
  5051. val |= LCPLL_CD_SOURCE_FCLK;
  5052. I915_WRITE(LCPLL_CTL, val);
  5053. if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
  5054. LCPLL_CD_SOURCE_FCLK_DONE, 1))
  5055. DRM_ERROR("Switching to FCLK failed\n");
  5056. val = I915_READ(LCPLL_CTL);
  5057. }
  5058. val |= LCPLL_PLL_DISABLE;
  5059. I915_WRITE(LCPLL_CTL, val);
  5060. POSTING_READ(LCPLL_CTL);
  5061. if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
  5062. DRM_ERROR("LCPLL still locked\n");
  5063. val = I915_READ(D_COMP);
  5064. val |= D_COMP_COMP_DISABLE;
  5065. I915_WRITE(D_COMP, val);
  5066. POSTING_READ(D_COMP);
  5067. ndelay(100);
  5068. if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
  5069. DRM_ERROR("D_COMP RCOMP still in progress\n");
  5070. if (allow_power_down) {
  5071. val = I915_READ(LCPLL_CTL);
  5072. val |= LCPLL_POWER_DOWN_ALLOW;
  5073. I915_WRITE(LCPLL_CTL, val);
  5074. POSTING_READ(LCPLL_CTL);
  5075. }
  5076. }
  5077. /*
  5078. * Fully restores LCPLL, disallowing power down and switching back to LCPLL
  5079. * source.
  5080. */
  5081. void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
  5082. {
  5083. uint32_t val;
  5084. val = I915_READ(LCPLL_CTL);
  5085. if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
  5086. LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
  5087. return;
  5088. if (val & LCPLL_POWER_DOWN_ALLOW) {
  5089. val &= ~LCPLL_POWER_DOWN_ALLOW;
  5090. I915_WRITE(LCPLL_CTL, val);
  5091. }
  5092. val = I915_READ(D_COMP);
  5093. val |= D_COMP_COMP_FORCE;
  5094. val &= ~D_COMP_COMP_DISABLE;
  5095. I915_WRITE(D_COMP, val);
  5096. I915_READ(D_COMP);
  5097. val = I915_READ(LCPLL_CTL);
  5098. val &= ~LCPLL_PLL_DISABLE;
  5099. I915_WRITE(LCPLL_CTL, val);
  5100. if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
  5101. DRM_ERROR("LCPLL not locked yet\n");
  5102. if (val & LCPLL_CD_SOURCE_FCLK) {
  5103. val = I915_READ(LCPLL_CTL);
  5104. val &= ~LCPLL_CD_SOURCE_FCLK;
  5105. I915_WRITE(LCPLL_CTL, val);
  5106. if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
  5107. LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
  5108. DRM_ERROR("Switching back to LCPLL failed\n");
  5109. }
  5110. }
  5111. static void haswell_modeset_global_resources(struct drm_device *dev)
  5112. {
  5113. bool enable = false;
  5114. struct intel_crtc *crtc;
  5115. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  5116. if (!crtc->base.enabled)
  5117. continue;
  5118. if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
  5119. crtc->config.cpu_transcoder != TRANSCODER_EDP)
  5120. enable = true;
  5121. }
  5122. intel_set_power_well(dev, enable);
  5123. }
  5124. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  5125. int x, int y,
  5126. struct drm_framebuffer *fb)
  5127. {
  5128. struct drm_device *dev = crtc->dev;
  5129. struct drm_i915_private *dev_priv = dev->dev_private;
  5130. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5131. int plane = intel_crtc->plane;
  5132. int ret;
  5133. if (!intel_ddi_pll_mode_set(crtc))
  5134. return -EINVAL;
  5135. /* Ensure that the cursor is valid for the new mode before changing... */
  5136. intel_crtc_update_cursor(crtc, true);
  5137. if (intel_crtc->config.has_dp_encoder)
  5138. intel_dp_set_m_n(intel_crtc);
  5139. intel_crtc->lowfreq_avail = false;
  5140. intel_set_pipe_timings(intel_crtc);
  5141. if (intel_crtc->config.has_pch_encoder) {
  5142. intel_cpu_transcoder_set_m_n(intel_crtc,
  5143. &intel_crtc->config.fdi_m_n);
  5144. }
  5145. haswell_set_pipeconf(crtc);
  5146. intel_set_pipe_csc(crtc);
  5147. /* Set up the display plane register */
  5148. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
  5149. POSTING_READ(DSPCNTR(plane));
  5150. ret = intel_pipe_set_base(crtc, x, y, fb);
  5151. intel_update_watermarks(dev);
  5152. return ret;
  5153. }
  5154. static bool haswell_get_pipe_config(struct intel_crtc *crtc,
  5155. struct intel_crtc_config *pipe_config)
  5156. {
  5157. struct drm_device *dev = crtc->base.dev;
  5158. struct drm_i915_private *dev_priv = dev->dev_private;
  5159. enum intel_display_power_domain pfit_domain;
  5160. uint32_t tmp;
  5161. pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
  5162. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  5163. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  5164. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  5165. enum pipe trans_edp_pipe;
  5166. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  5167. default:
  5168. WARN(1, "unknown pipe linked to edp transcoder\n");
  5169. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  5170. case TRANS_DDI_EDP_INPUT_A_ON:
  5171. trans_edp_pipe = PIPE_A;
  5172. break;
  5173. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  5174. trans_edp_pipe = PIPE_B;
  5175. break;
  5176. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  5177. trans_edp_pipe = PIPE_C;
  5178. break;
  5179. }
  5180. if (trans_edp_pipe == crtc->pipe)
  5181. pipe_config->cpu_transcoder = TRANSCODER_EDP;
  5182. }
  5183. if (!intel_display_power_enabled(dev,
  5184. POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
  5185. return false;
  5186. tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
  5187. if (!(tmp & PIPECONF_ENABLE))
  5188. return false;
  5189. /*
  5190. * Haswell has only FDI/PCH transcoder A. It is which is connected to
  5191. * DDI E. So just check whether this pipe is wired to DDI E and whether
  5192. * the PCH transcoder is on.
  5193. */
  5194. tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
  5195. if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
  5196. I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
  5197. pipe_config->has_pch_encoder = true;
  5198. tmp = I915_READ(FDI_RX_CTL(PIPE_A));
  5199. pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
  5200. FDI_DP_PORT_WIDTH_SHIFT) + 1;
  5201. ironlake_get_fdi_m_n_config(crtc, pipe_config);
  5202. }
  5203. intel_get_pipe_timings(crtc, pipe_config);
  5204. pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
  5205. if (intel_display_power_enabled(dev, pfit_domain))
  5206. ironlake_get_pfit_config(crtc, pipe_config);
  5207. pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
  5208. (I915_READ(IPS_CTL) & IPS_ENABLE);
  5209. pipe_config->pixel_multiplier = 1;
  5210. return true;
  5211. }
  5212. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  5213. int x, int y,
  5214. struct drm_framebuffer *fb)
  5215. {
  5216. struct drm_device *dev = crtc->dev;
  5217. struct drm_i915_private *dev_priv = dev->dev_private;
  5218. struct drm_encoder_helper_funcs *encoder_funcs;
  5219. struct intel_encoder *encoder;
  5220. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5221. struct drm_display_mode *adjusted_mode =
  5222. &intel_crtc->config.adjusted_mode;
  5223. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  5224. int pipe = intel_crtc->pipe;
  5225. int ret;
  5226. drm_vblank_pre_modeset(dev, pipe);
  5227. ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
  5228. drm_vblank_post_modeset(dev, pipe);
  5229. if (ret != 0)
  5230. return ret;
  5231. for_each_encoder_on_crtc(dev, crtc, encoder) {
  5232. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  5233. encoder->base.base.id,
  5234. drm_get_encoder_name(&encoder->base),
  5235. mode->base.id, mode->name);
  5236. if (encoder->mode_set) {
  5237. encoder->mode_set(encoder);
  5238. } else {
  5239. encoder_funcs = encoder->base.helper_private;
  5240. encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
  5241. }
  5242. }
  5243. return 0;
  5244. }
  5245. static bool intel_eld_uptodate(struct drm_connector *connector,
  5246. int reg_eldv, uint32_t bits_eldv,
  5247. int reg_elda, uint32_t bits_elda,
  5248. int reg_edid)
  5249. {
  5250. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5251. uint8_t *eld = connector->eld;
  5252. uint32_t i;
  5253. i = I915_READ(reg_eldv);
  5254. i &= bits_eldv;
  5255. if (!eld[0])
  5256. return !i;
  5257. if (!i)
  5258. return false;
  5259. i = I915_READ(reg_elda);
  5260. i &= ~bits_elda;
  5261. I915_WRITE(reg_elda, i);
  5262. for (i = 0; i < eld[2]; i++)
  5263. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  5264. return false;
  5265. return true;
  5266. }
  5267. static void g4x_write_eld(struct drm_connector *connector,
  5268. struct drm_crtc *crtc)
  5269. {
  5270. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5271. uint8_t *eld = connector->eld;
  5272. uint32_t eldv;
  5273. uint32_t len;
  5274. uint32_t i;
  5275. i = I915_READ(G4X_AUD_VID_DID);
  5276. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  5277. eldv = G4X_ELDV_DEVCL_DEVBLC;
  5278. else
  5279. eldv = G4X_ELDV_DEVCTG;
  5280. if (intel_eld_uptodate(connector,
  5281. G4X_AUD_CNTL_ST, eldv,
  5282. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  5283. G4X_HDMIW_HDMIEDID))
  5284. return;
  5285. i = I915_READ(G4X_AUD_CNTL_ST);
  5286. i &= ~(eldv | G4X_ELD_ADDR);
  5287. len = (i >> 9) & 0x1f; /* ELD buffer size */
  5288. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5289. if (!eld[0])
  5290. return;
  5291. len = min_t(uint8_t, eld[2], len);
  5292. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5293. for (i = 0; i < len; i++)
  5294. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  5295. i = I915_READ(G4X_AUD_CNTL_ST);
  5296. i |= eldv;
  5297. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5298. }
  5299. static void haswell_write_eld(struct drm_connector *connector,
  5300. struct drm_crtc *crtc)
  5301. {
  5302. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5303. uint8_t *eld = connector->eld;
  5304. struct drm_device *dev = crtc->dev;
  5305. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5306. uint32_t eldv;
  5307. uint32_t i;
  5308. int len;
  5309. int pipe = to_intel_crtc(crtc)->pipe;
  5310. int tmp;
  5311. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  5312. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  5313. int aud_config = HSW_AUD_CFG(pipe);
  5314. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  5315. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  5316. /* Audio output enable */
  5317. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  5318. tmp = I915_READ(aud_cntrl_st2);
  5319. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  5320. I915_WRITE(aud_cntrl_st2, tmp);
  5321. /* Wait for 1 vertical blank */
  5322. intel_wait_for_vblank(dev, pipe);
  5323. /* Set ELD valid state */
  5324. tmp = I915_READ(aud_cntrl_st2);
  5325. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
  5326. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  5327. I915_WRITE(aud_cntrl_st2, tmp);
  5328. tmp = I915_READ(aud_cntrl_st2);
  5329. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
  5330. /* Enable HDMI mode */
  5331. tmp = I915_READ(aud_config);
  5332. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
  5333. /* clear N_programing_enable and N_value_index */
  5334. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  5335. I915_WRITE(aud_config, tmp);
  5336. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5337. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  5338. intel_crtc->eld_vld = true;
  5339. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5340. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5341. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5342. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5343. } else
  5344. I915_WRITE(aud_config, 0);
  5345. if (intel_eld_uptodate(connector,
  5346. aud_cntrl_st2, eldv,
  5347. aud_cntl_st, IBX_ELD_ADDRESS,
  5348. hdmiw_hdmiedid))
  5349. return;
  5350. i = I915_READ(aud_cntrl_st2);
  5351. i &= ~eldv;
  5352. I915_WRITE(aud_cntrl_st2, i);
  5353. if (!eld[0])
  5354. return;
  5355. i = I915_READ(aud_cntl_st);
  5356. i &= ~IBX_ELD_ADDRESS;
  5357. I915_WRITE(aud_cntl_st, i);
  5358. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5359. DRM_DEBUG_DRIVER("port num:%d\n", i);
  5360. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5361. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5362. for (i = 0; i < len; i++)
  5363. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5364. i = I915_READ(aud_cntrl_st2);
  5365. i |= eldv;
  5366. I915_WRITE(aud_cntrl_st2, i);
  5367. }
  5368. static void ironlake_write_eld(struct drm_connector *connector,
  5369. struct drm_crtc *crtc)
  5370. {
  5371. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5372. uint8_t *eld = connector->eld;
  5373. uint32_t eldv;
  5374. uint32_t i;
  5375. int len;
  5376. int hdmiw_hdmiedid;
  5377. int aud_config;
  5378. int aud_cntl_st;
  5379. int aud_cntrl_st2;
  5380. int pipe = to_intel_crtc(crtc)->pipe;
  5381. if (HAS_PCH_IBX(connector->dev)) {
  5382. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  5383. aud_config = IBX_AUD_CFG(pipe);
  5384. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  5385. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5386. } else {
  5387. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  5388. aud_config = CPT_AUD_CFG(pipe);
  5389. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  5390. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5391. }
  5392. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5393. i = I915_READ(aud_cntl_st);
  5394. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5395. if (!i) {
  5396. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5397. /* operate blindly on all ports */
  5398. eldv = IBX_ELD_VALIDB;
  5399. eldv |= IBX_ELD_VALIDB << 4;
  5400. eldv |= IBX_ELD_VALIDB << 8;
  5401. } else {
  5402. DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
  5403. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5404. }
  5405. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5406. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5407. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5408. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5409. } else
  5410. I915_WRITE(aud_config, 0);
  5411. if (intel_eld_uptodate(connector,
  5412. aud_cntrl_st2, eldv,
  5413. aud_cntl_st, IBX_ELD_ADDRESS,
  5414. hdmiw_hdmiedid))
  5415. return;
  5416. i = I915_READ(aud_cntrl_st2);
  5417. i &= ~eldv;
  5418. I915_WRITE(aud_cntrl_st2, i);
  5419. if (!eld[0])
  5420. return;
  5421. i = I915_READ(aud_cntl_st);
  5422. i &= ~IBX_ELD_ADDRESS;
  5423. I915_WRITE(aud_cntl_st, i);
  5424. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5425. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5426. for (i = 0; i < len; i++)
  5427. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5428. i = I915_READ(aud_cntrl_st2);
  5429. i |= eldv;
  5430. I915_WRITE(aud_cntrl_st2, i);
  5431. }
  5432. void intel_write_eld(struct drm_encoder *encoder,
  5433. struct drm_display_mode *mode)
  5434. {
  5435. struct drm_crtc *crtc = encoder->crtc;
  5436. struct drm_connector *connector;
  5437. struct drm_device *dev = encoder->dev;
  5438. struct drm_i915_private *dev_priv = dev->dev_private;
  5439. connector = drm_select_eld(encoder, mode);
  5440. if (!connector)
  5441. return;
  5442. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5443. connector->base.id,
  5444. drm_get_connector_name(connector),
  5445. connector->encoder->base.id,
  5446. drm_get_encoder_name(connector->encoder));
  5447. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5448. if (dev_priv->display.write_eld)
  5449. dev_priv->display.write_eld(connector, crtc);
  5450. }
  5451. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  5452. void intel_crtc_load_lut(struct drm_crtc *crtc)
  5453. {
  5454. struct drm_device *dev = crtc->dev;
  5455. struct drm_i915_private *dev_priv = dev->dev_private;
  5456. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5457. enum pipe pipe = intel_crtc->pipe;
  5458. int palreg = PALETTE(pipe);
  5459. int i;
  5460. bool reenable_ips = false;
  5461. /* The clocks have to be on to load the palette. */
  5462. if (!crtc->enabled || !intel_crtc->active)
  5463. return;
  5464. if (!HAS_PCH_SPLIT(dev_priv->dev))
  5465. assert_pll_enabled(dev_priv, pipe);
  5466. /* use legacy palette for Ironlake */
  5467. if (HAS_PCH_SPLIT(dev))
  5468. palreg = LGC_PALETTE(pipe);
  5469. /* Workaround : Do not read or write the pipe palette/gamma data while
  5470. * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
  5471. */
  5472. if (intel_crtc->config.ips_enabled &&
  5473. ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
  5474. GAMMA_MODE_MODE_SPLIT)) {
  5475. hsw_disable_ips(intel_crtc);
  5476. reenable_ips = true;
  5477. }
  5478. for (i = 0; i < 256; i++) {
  5479. I915_WRITE(palreg + 4 * i,
  5480. (intel_crtc->lut_r[i] << 16) |
  5481. (intel_crtc->lut_g[i] << 8) |
  5482. intel_crtc->lut_b[i]);
  5483. }
  5484. if (reenable_ips)
  5485. hsw_enable_ips(intel_crtc);
  5486. }
  5487. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5488. {
  5489. struct drm_device *dev = crtc->dev;
  5490. struct drm_i915_private *dev_priv = dev->dev_private;
  5491. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5492. bool visible = base != 0;
  5493. u32 cntl;
  5494. if (intel_crtc->cursor_visible == visible)
  5495. return;
  5496. cntl = I915_READ(_CURACNTR);
  5497. if (visible) {
  5498. /* On these chipsets we can only modify the base whilst
  5499. * the cursor is disabled.
  5500. */
  5501. I915_WRITE(_CURABASE, base);
  5502. cntl &= ~(CURSOR_FORMAT_MASK);
  5503. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5504. cntl |= CURSOR_ENABLE |
  5505. CURSOR_GAMMA_ENABLE |
  5506. CURSOR_FORMAT_ARGB;
  5507. } else
  5508. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5509. I915_WRITE(_CURACNTR, cntl);
  5510. intel_crtc->cursor_visible = visible;
  5511. }
  5512. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5513. {
  5514. struct drm_device *dev = crtc->dev;
  5515. struct drm_i915_private *dev_priv = dev->dev_private;
  5516. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5517. int pipe = intel_crtc->pipe;
  5518. bool visible = base != 0;
  5519. if (intel_crtc->cursor_visible != visible) {
  5520. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5521. if (base) {
  5522. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5523. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5524. cntl |= pipe << 28; /* Connect to correct pipe */
  5525. } else {
  5526. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5527. cntl |= CURSOR_MODE_DISABLE;
  5528. }
  5529. I915_WRITE(CURCNTR(pipe), cntl);
  5530. intel_crtc->cursor_visible = visible;
  5531. }
  5532. /* and commit changes on next vblank */
  5533. I915_WRITE(CURBASE(pipe), base);
  5534. }
  5535. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5536. {
  5537. struct drm_device *dev = crtc->dev;
  5538. struct drm_i915_private *dev_priv = dev->dev_private;
  5539. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5540. int pipe = intel_crtc->pipe;
  5541. bool visible = base != 0;
  5542. if (intel_crtc->cursor_visible != visible) {
  5543. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5544. if (base) {
  5545. cntl &= ~CURSOR_MODE;
  5546. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5547. } else {
  5548. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5549. cntl |= CURSOR_MODE_DISABLE;
  5550. }
  5551. if (IS_HASWELL(dev))
  5552. cntl |= CURSOR_PIPE_CSC_ENABLE;
  5553. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5554. intel_crtc->cursor_visible = visible;
  5555. }
  5556. /* and commit changes on next vblank */
  5557. I915_WRITE(CURBASE_IVB(pipe), base);
  5558. }
  5559. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5560. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5561. bool on)
  5562. {
  5563. struct drm_device *dev = crtc->dev;
  5564. struct drm_i915_private *dev_priv = dev->dev_private;
  5565. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5566. int pipe = intel_crtc->pipe;
  5567. int x = intel_crtc->cursor_x;
  5568. int y = intel_crtc->cursor_y;
  5569. u32 base, pos;
  5570. bool visible;
  5571. pos = 0;
  5572. if (on && crtc->enabled && crtc->fb) {
  5573. base = intel_crtc->cursor_addr;
  5574. if (x > (int) crtc->fb->width)
  5575. base = 0;
  5576. if (y > (int) crtc->fb->height)
  5577. base = 0;
  5578. } else
  5579. base = 0;
  5580. if (x < 0) {
  5581. if (x + intel_crtc->cursor_width < 0)
  5582. base = 0;
  5583. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5584. x = -x;
  5585. }
  5586. pos |= x << CURSOR_X_SHIFT;
  5587. if (y < 0) {
  5588. if (y + intel_crtc->cursor_height < 0)
  5589. base = 0;
  5590. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5591. y = -y;
  5592. }
  5593. pos |= y << CURSOR_Y_SHIFT;
  5594. visible = base != 0;
  5595. if (!visible && !intel_crtc->cursor_visible)
  5596. return;
  5597. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  5598. I915_WRITE(CURPOS_IVB(pipe), pos);
  5599. ivb_update_cursor(crtc, base);
  5600. } else {
  5601. I915_WRITE(CURPOS(pipe), pos);
  5602. if (IS_845G(dev) || IS_I865G(dev))
  5603. i845_update_cursor(crtc, base);
  5604. else
  5605. i9xx_update_cursor(crtc, base);
  5606. }
  5607. }
  5608. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5609. struct drm_file *file,
  5610. uint32_t handle,
  5611. uint32_t width, uint32_t height)
  5612. {
  5613. struct drm_device *dev = crtc->dev;
  5614. struct drm_i915_private *dev_priv = dev->dev_private;
  5615. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5616. struct drm_i915_gem_object *obj;
  5617. uint32_t addr;
  5618. int ret;
  5619. /* if we want to turn off the cursor ignore width and height */
  5620. if (!handle) {
  5621. DRM_DEBUG_KMS("cursor off\n");
  5622. addr = 0;
  5623. obj = NULL;
  5624. mutex_lock(&dev->struct_mutex);
  5625. goto finish;
  5626. }
  5627. /* Currently we only support 64x64 cursors */
  5628. if (width != 64 || height != 64) {
  5629. DRM_ERROR("we currently only support 64x64 cursors\n");
  5630. return -EINVAL;
  5631. }
  5632. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5633. if (&obj->base == NULL)
  5634. return -ENOENT;
  5635. if (obj->base.size < width * height * 4) {
  5636. DRM_ERROR("buffer is to small\n");
  5637. ret = -ENOMEM;
  5638. goto fail;
  5639. }
  5640. /* we only need to pin inside GTT if cursor is non-phy */
  5641. mutex_lock(&dev->struct_mutex);
  5642. if (!dev_priv->info->cursor_needs_physical) {
  5643. unsigned alignment;
  5644. if (obj->tiling_mode) {
  5645. DRM_ERROR("cursor cannot be tiled\n");
  5646. ret = -EINVAL;
  5647. goto fail_locked;
  5648. }
  5649. /* Note that the w/a also requires 2 PTE of padding following
  5650. * the bo. We currently fill all unused PTE with the shadow
  5651. * page and so we should always have valid PTE following the
  5652. * cursor preventing the VT-d warning.
  5653. */
  5654. alignment = 0;
  5655. if (need_vtd_wa(dev))
  5656. alignment = 64*1024;
  5657. ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
  5658. if (ret) {
  5659. DRM_ERROR("failed to move cursor bo into the GTT\n");
  5660. goto fail_locked;
  5661. }
  5662. ret = i915_gem_object_put_fence(obj);
  5663. if (ret) {
  5664. DRM_ERROR("failed to release fence for cursor");
  5665. goto fail_unpin;
  5666. }
  5667. addr = i915_gem_obj_ggtt_offset(obj);
  5668. } else {
  5669. int align = IS_I830(dev) ? 16 * 1024 : 256;
  5670. ret = i915_gem_attach_phys_object(dev, obj,
  5671. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  5672. align);
  5673. if (ret) {
  5674. DRM_ERROR("failed to attach phys object\n");
  5675. goto fail_locked;
  5676. }
  5677. addr = obj->phys_obj->handle->busaddr;
  5678. }
  5679. if (IS_GEN2(dev))
  5680. I915_WRITE(CURSIZE, (height << 12) | width);
  5681. finish:
  5682. if (intel_crtc->cursor_bo) {
  5683. if (dev_priv->info->cursor_needs_physical) {
  5684. if (intel_crtc->cursor_bo != obj)
  5685. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  5686. } else
  5687. i915_gem_object_unpin(intel_crtc->cursor_bo);
  5688. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  5689. }
  5690. mutex_unlock(&dev->struct_mutex);
  5691. intel_crtc->cursor_addr = addr;
  5692. intel_crtc->cursor_bo = obj;
  5693. intel_crtc->cursor_width = width;
  5694. intel_crtc->cursor_height = height;
  5695. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  5696. return 0;
  5697. fail_unpin:
  5698. i915_gem_object_unpin(obj);
  5699. fail_locked:
  5700. mutex_unlock(&dev->struct_mutex);
  5701. fail:
  5702. drm_gem_object_unreference_unlocked(&obj->base);
  5703. return ret;
  5704. }
  5705. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  5706. {
  5707. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5708. intel_crtc->cursor_x = x;
  5709. intel_crtc->cursor_y = y;
  5710. intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
  5711. return 0;
  5712. }
  5713. /** Sets the color ramps on behalf of RandR */
  5714. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  5715. u16 blue, int regno)
  5716. {
  5717. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5718. intel_crtc->lut_r[regno] = red >> 8;
  5719. intel_crtc->lut_g[regno] = green >> 8;
  5720. intel_crtc->lut_b[regno] = blue >> 8;
  5721. }
  5722. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  5723. u16 *blue, int regno)
  5724. {
  5725. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5726. *red = intel_crtc->lut_r[regno] << 8;
  5727. *green = intel_crtc->lut_g[regno] << 8;
  5728. *blue = intel_crtc->lut_b[regno] << 8;
  5729. }
  5730. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5731. u16 *blue, uint32_t start, uint32_t size)
  5732. {
  5733. int end = (start + size > 256) ? 256 : start + size, i;
  5734. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5735. for (i = start; i < end; i++) {
  5736. intel_crtc->lut_r[i] = red[i] >> 8;
  5737. intel_crtc->lut_g[i] = green[i] >> 8;
  5738. intel_crtc->lut_b[i] = blue[i] >> 8;
  5739. }
  5740. intel_crtc_load_lut(crtc);
  5741. }
  5742. /* VESA 640x480x72Hz mode to set on the pipe */
  5743. static struct drm_display_mode load_detect_mode = {
  5744. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5745. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5746. };
  5747. static struct drm_framebuffer *
  5748. intel_framebuffer_create(struct drm_device *dev,
  5749. struct drm_mode_fb_cmd2 *mode_cmd,
  5750. struct drm_i915_gem_object *obj)
  5751. {
  5752. struct intel_framebuffer *intel_fb;
  5753. int ret;
  5754. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  5755. if (!intel_fb) {
  5756. drm_gem_object_unreference_unlocked(&obj->base);
  5757. return ERR_PTR(-ENOMEM);
  5758. }
  5759. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  5760. if (ret) {
  5761. drm_gem_object_unreference_unlocked(&obj->base);
  5762. kfree(intel_fb);
  5763. return ERR_PTR(ret);
  5764. }
  5765. return &intel_fb->base;
  5766. }
  5767. static u32
  5768. intel_framebuffer_pitch_for_width(int width, int bpp)
  5769. {
  5770. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  5771. return ALIGN(pitch, 64);
  5772. }
  5773. static u32
  5774. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  5775. {
  5776. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  5777. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  5778. }
  5779. static struct drm_framebuffer *
  5780. intel_framebuffer_create_for_mode(struct drm_device *dev,
  5781. struct drm_display_mode *mode,
  5782. int depth, int bpp)
  5783. {
  5784. struct drm_i915_gem_object *obj;
  5785. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  5786. obj = i915_gem_alloc_object(dev,
  5787. intel_framebuffer_size_for_mode(mode, bpp));
  5788. if (obj == NULL)
  5789. return ERR_PTR(-ENOMEM);
  5790. mode_cmd.width = mode->hdisplay;
  5791. mode_cmd.height = mode->vdisplay;
  5792. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  5793. bpp);
  5794. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  5795. return intel_framebuffer_create(dev, &mode_cmd, obj);
  5796. }
  5797. static struct drm_framebuffer *
  5798. mode_fits_in_fbdev(struct drm_device *dev,
  5799. struct drm_display_mode *mode)
  5800. {
  5801. struct drm_i915_private *dev_priv = dev->dev_private;
  5802. struct drm_i915_gem_object *obj;
  5803. struct drm_framebuffer *fb;
  5804. if (dev_priv->fbdev == NULL)
  5805. return NULL;
  5806. obj = dev_priv->fbdev->ifb.obj;
  5807. if (obj == NULL)
  5808. return NULL;
  5809. fb = &dev_priv->fbdev->ifb.base;
  5810. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  5811. fb->bits_per_pixel))
  5812. return NULL;
  5813. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  5814. return NULL;
  5815. return fb;
  5816. }
  5817. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  5818. struct drm_display_mode *mode,
  5819. struct intel_load_detect_pipe *old)
  5820. {
  5821. struct intel_crtc *intel_crtc;
  5822. struct intel_encoder *intel_encoder =
  5823. intel_attached_encoder(connector);
  5824. struct drm_crtc *possible_crtc;
  5825. struct drm_encoder *encoder = &intel_encoder->base;
  5826. struct drm_crtc *crtc = NULL;
  5827. struct drm_device *dev = encoder->dev;
  5828. struct drm_framebuffer *fb;
  5829. int i = -1;
  5830. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5831. connector->base.id, drm_get_connector_name(connector),
  5832. encoder->base.id, drm_get_encoder_name(encoder));
  5833. /*
  5834. * Algorithm gets a little messy:
  5835. *
  5836. * - if the connector already has an assigned crtc, use it (but make
  5837. * sure it's on first)
  5838. *
  5839. * - try to find the first unused crtc that can drive this connector,
  5840. * and use that if we find one
  5841. */
  5842. /* See if we already have a CRTC for this connector */
  5843. if (encoder->crtc) {
  5844. crtc = encoder->crtc;
  5845. mutex_lock(&crtc->mutex);
  5846. old->dpms_mode = connector->dpms;
  5847. old->load_detect_temp = false;
  5848. /* Make sure the crtc and connector are running */
  5849. if (connector->dpms != DRM_MODE_DPMS_ON)
  5850. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  5851. return true;
  5852. }
  5853. /* Find an unused one (if possible) */
  5854. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  5855. i++;
  5856. if (!(encoder->possible_crtcs & (1 << i)))
  5857. continue;
  5858. if (!possible_crtc->enabled) {
  5859. crtc = possible_crtc;
  5860. break;
  5861. }
  5862. }
  5863. /*
  5864. * If we didn't find an unused CRTC, don't use any.
  5865. */
  5866. if (!crtc) {
  5867. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  5868. return false;
  5869. }
  5870. mutex_lock(&crtc->mutex);
  5871. intel_encoder->new_crtc = to_intel_crtc(crtc);
  5872. to_intel_connector(connector)->new_encoder = intel_encoder;
  5873. intel_crtc = to_intel_crtc(crtc);
  5874. old->dpms_mode = connector->dpms;
  5875. old->load_detect_temp = true;
  5876. old->release_fb = NULL;
  5877. if (!mode)
  5878. mode = &load_detect_mode;
  5879. /* We need a framebuffer large enough to accommodate all accesses
  5880. * that the plane may generate whilst we perform load detection.
  5881. * We can not rely on the fbcon either being present (we get called
  5882. * during its initialisation to detect all boot displays, or it may
  5883. * not even exist) or that it is large enough to satisfy the
  5884. * requested mode.
  5885. */
  5886. fb = mode_fits_in_fbdev(dev, mode);
  5887. if (fb == NULL) {
  5888. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5889. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5890. old->release_fb = fb;
  5891. } else
  5892. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5893. if (IS_ERR(fb)) {
  5894. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5895. mutex_unlock(&crtc->mutex);
  5896. return false;
  5897. }
  5898. if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  5899. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5900. if (old->release_fb)
  5901. old->release_fb->funcs->destroy(old->release_fb);
  5902. mutex_unlock(&crtc->mutex);
  5903. return false;
  5904. }
  5905. /* let the connector get through one full cycle before testing */
  5906. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5907. return true;
  5908. }
  5909. void intel_release_load_detect_pipe(struct drm_connector *connector,
  5910. struct intel_load_detect_pipe *old)
  5911. {
  5912. struct intel_encoder *intel_encoder =
  5913. intel_attached_encoder(connector);
  5914. struct drm_encoder *encoder = &intel_encoder->base;
  5915. struct drm_crtc *crtc = encoder->crtc;
  5916. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5917. connector->base.id, drm_get_connector_name(connector),
  5918. encoder->base.id, drm_get_encoder_name(encoder));
  5919. if (old->load_detect_temp) {
  5920. to_intel_connector(connector)->new_encoder = NULL;
  5921. intel_encoder->new_crtc = NULL;
  5922. intel_set_mode(crtc, NULL, 0, 0, NULL);
  5923. if (old->release_fb) {
  5924. drm_framebuffer_unregister_private(old->release_fb);
  5925. drm_framebuffer_unreference(old->release_fb);
  5926. }
  5927. mutex_unlock(&crtc->mutex);
  5928. return;
  5929. }
  5930. /* Switch crtc and encoder back off if necessary */
  5931. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  5932. connector->funcs->dpms(connector, old->dpms_mode);
  5933. mutex_unlock(&crtc->mutex);
  5934. }
  5935. /* Returns the clock of the currently programmed mode of the given pipe. */
  5936. static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  5937. struct intel_crtc_config *pipe_config)
  5938. {
  5939. struct drm_device *dev = crtc->base.dev;
  5940. struct drm_i915_private *dev_priv = dev->dev_private;
  5941. int pipe = pipe_config->cpu_transcoder;
  5942. u32 dpll = I915_READ(DPLL(pipe));
  5943. u32 fp;
  5944. intel_clock_t clock;
  5945. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5946. fp = I915_READ(FP0(pipe));
  5947. else
  5948. fp = I915_READ(FP1(pipe));
  5949. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5950. if (IS_PINEVIEW(dev)) {
  5951. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5952. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5953. } else {
  5954. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5955. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5956. }
  5957. if (!IS_GEN2(dev)) {
  5958. if (IS_PINEVIEW(dev))
  5959. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5960. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5961. else
  5962. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5963. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5964. switch (dpll & DPLL_MODE_MASK) {
  5965. case DPLLB_MODE_DAC_SERIAL:
  5966. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5967. 5 : 10;
  5968. break;
  5969. case DPLLB_MODE_LVDS:
  5970. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5971. 7 : 14;
  5972. break;
  5973. default:
  5974. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5975. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5976. pipe_config->adjusted_mode.clock = 0;
  5977. return;
  5978. }
  5979. if (IS_PINEVIEW(dev))
  5980. pineview_clock(96000, &clock);
  5981. else
  5982. i9xx_clock(96000, &clock);
  5983. } else {
  5984. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5985. if (is_lvds) {
  5986. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5987. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5988. clock.p2 = 14;
  5989. if ((dpll & PLL_REF_INPUT_MASK) ==
  5990. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5991. /* XXX: might not be 66MHz */
  5992. i9xx_clock(66000, &clock);
  5993. } else
  5994. i9xx_clock(48000, &clock);
  5995. } else {
  5996. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5997. clock.p1 = 2;
  5998. else {
  5999. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  6000. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  6001. }
  6002. if (dpll & PLL_P2_DIVIDE_BY_4)
  6003. clock.p2 = 4;
  6004. else
  6005. clock.p2 = 2;
  6006. i9xx_clock(48000, &clock);
  6007. }
  6008. }
  6009. pipe_config->adjusted_mode.clock = clock.dot *
  6010. pipe_config->pixel_multiplier;
  6011. }
  6012. static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
  6013. struct intel_crtc_config *pipe_config)
  6014. {
  6015. struct drm_device *dev = crtc->base.dev;
  6016. struct drm_i915_private *dev_priv = dev->dev_private;
  6017. enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
  6018. int link_freq, repeat;
  6019. u64 clock;
  6020. u32 link_m, link_n;
  6021. repeat = pipe_config->pixel_multiplier;
  6022. /*
  6023. * The calculation for the data clock is:
  6024. * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
  6025. * But we want to avoid losing precison if possible, so:
  6026. * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
  6027. *
  6028. * and the link clock is simpler:
  6029. * link_clock = (m * link_clock * repeat) / n
  6030. */
  6031. /*
  6032. * We need to get the FDI or DP link clock here to derive
  6033. * the M/N dividers.
  6034. *
  6035. * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
  6036. * For DP, it's either 1.62GHz or 2.7GHz.
  6037. * We do our calculations in 10*MHz since we don't need much precison.
  6038. */
  6039. if (pipe_config->has_pch_encoder)
  6040. link_freq = intel_fdi_link_freq(dev) * 10000;
  6041. else
  6042. link_freq = pipe_config->port_clock;
  6043. link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
  6044. link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
  6045. if (!link_m || !link_n)
  6046. return;
  6047. clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
  6048. do_div(clock, link_n);
  6049. pipe_config->adjusted_mode.clock = clock;
  6050. }
  6051. /** Returns the currently programmed mode of the given pipe. */
  6052. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  6053. struct drm_crtc *crtc)
  6054. {
  6055. struct drm_i915_private *dev_priv = dev->dev_private;
  6056. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6057. enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
  6058. struct drm_display_mode *mode;
  6059. struct intel_crtc_config pipe_config;
  6060. int htot = I915_READ(HTOTAL(cpu_transcoder));
  6061. int hsync = I915_READ(HSYNC(cpu_transcoder));
  6062. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  6063. int vsync = I915_READ(VSYNC(cpu_transcoder));
  6064. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  6065. if (!mode)
  6066. return NULL;
  6067. /*
  6068. * Construct a pipe_config sufficient for getting the clock info
  6069. * back out of crtc_clock_get.
  6070. *
  6071. * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
  6072. * to use a real value here instead.
  6073. */
  6074. pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
  6075. pipe_config.pixel_multiplier = 1;
  6076. i9xx_crtc_clock_get(intel_crtc, &pipe_config);
  6077. mode->clock = pipe_config.adjusted_mode.clock;
  6078. mode->hdisplay = (htot & 0xffff) + 1;
  6079. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  6080. mode->hsync_start = (hsync & 0xffff) + 1;
  6081. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  6082. mode->vdisplay = (vtot & 0xffff) + 1;
  6083. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  6084. mode->vsync_start = (vsync & 0xffff) + 1;
  6085. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  6086. drm_mode_set_name(mode);
  6087. return mode;
  6088. }
  6089. static void intel_increase_pllclock(struct drm_crtc *crtc)
  6090. {
  6091. struct drm_device *dev = crtc->dev;
  6092. drm_i915_private_t *dev_priv = dev->dev_private;
  6093. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6094. int pipe = intel_crtc->pipe;
  6095. int dpll_reg = DPLL(pipe);
  6096. int dpll;
  6097. if (HAS_PCH_SPLIT(dev))
  6098. return;
  6099. if (!dev_priv->lvds_downclock_avail)
  6100. return;
  6101. dpll = I915_READ(dpll_reg);
  6102. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  6103. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  6104. assert_panel_unlocked(dev_priv, pipe);
  6105. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  6106. I915_WRITE(dpll_reg, dpll);
  6107. intel_wait_for_vblank(dev, pipe);
  6108. dpll = I915_READ(dpll_reg);
  6109. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  6110. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  6111. }
  6112. }
  6113. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  6114. {
  6115. struct drm_device *dev = crtc->dev;
  6116. drm_i915_private_t *dev_priv = dev->dev_private;
  6117. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6118. if (HAS_PCH_SPLIT(dev))
  6119. return;
  6120. if (!dev_priv->lvds_downclock_avail)
  6121. return;
  6122. /*
  6123. * Since this is called by a timer, we should never get here in
  6124. * the manual case.
  6125. */
  6126. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  6127. int pipe = intel_crtc->pipe;
  6128. int dpll_reg = DPLL(pipe);
  6129. int dpll;
  6130. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  6131. assert_panel_unlocked(dev_priv, pipe);
  6132. dpll = I915_READ(dpll_reg);
  6133. dpll |= DISPLAY_RATE_SELECT_FPA1;
  6134. I915_WRITE(dpll_reg, dpll);
  6135. intel_wait_for_vblank(dev, pipe);
  6136. dpll = I915_READ(dpll_reg);
  6137. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  6138. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  6139. }
  6140. }
  6141. void intel_mark_busy(struct drm_device *dev)
  6142. {
  6143. i915_update_gfx_val(dev->dev_private);
  6144. }
  6145. void intel_mark_idle(struct drm_device *dev)
  6146. {
  6147. struct drm_crtc *crtc;
  6148. if (!i915_powersave)
  6149. return;
  6150. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6151. if (!crtc->fb)
  6152. continue;
  6153. intel_decrease_pllclock(crtc);
  6154. }
  6155. }
  6156. void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
  6157. struct intel_ring_buffer *ring)
  6158. {
  6159. struct drm_device *dev = obj->base.dev;
  6160. struct drm_crtc *crtc;
  6161. if (!i915_powersave)
  6162. return;
  6163. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6164. if (!crtc->fb)
  6165. continue;
  6166. if (to_intel_framebuffer(crtc->fb)->obj != obj)
  6167. continue;
  6168. intel_increase_pllclock(crtc);
  6169. if (ring && intel_fbc_enabled(dev))
  6170. ring->fbc_dirty = true;
  6171. }
  6172. }
  6173. static void intel_crtc_destroy(struct drm_crtc *crtc)
  6174. {
  6175. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6176. struct drm_device *dev = crtc->dev;
  6177. struct intel_unpin_work *work;
  6178. unsigned long flags;
  6179. spin_lock_irqsave(&dev->event_lock, flags);
  6180. work = intel_crtc->unpin_work;
  6181. intel_crtc->unpin_work = NULL;
  6182. spin_unlock_irqrestore(&dev->event_lock, flags);
  6183. if (work) {
  6184. cancel_work_sync(&work->work);
  6185. kfree(work);
  6186. }
  6187. intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
  6188. drm_crtc_cleanup(crtc);
  6189. kfree(intel_crtc);
  6190. }
  6191. static void intel_unpin_work_fn(struct work_struct *__work)
  6192. {
  6193. struct intel_unpin_work *work =
  6194. container_of(__work, struct intel_unpin_work, work);
  6195. struct drm_device *dev = work->crtc->dev;
  6196. mutex_lock(&dev->struct_mutex);
  6197. intel_unpin_fb_obj(work->old_fb_obj);
  6198. drm_gem_object_unreference(&work->pending_flip_obj->base);
  6199. drm_gem_object_unreference(&work->old_fb_obj->base);
  6200. intel_update_fbc(dev);
  6201. mutex_unlock(&dev->struct_mutex);
  6202. BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  6203. atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  6204. kfree(work);
  6205. }
  6206. static void do_intel_finish_page_flip(struct drm_device *dev,
  6207. struct drm_crtc *crtc)
  6208. {
  6209. drm_i915_private_t *dev_priv = dev->dev_private;
  6210. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6211. struct intel_unpin_work *work;
  6212. unsigned long flags;
  6213. /* Ignore early vblank irqs */
  6214. if (intel_crtc == NULL)
  6215. return;
  6216. spin_lock_irqsave(&dev->event_lock, flags);
  6217. work = intel_crtc->unpin_work;
  6218. /* Ensure we don't miss a work->pending update ... */
  6219. smp_rmb();
  6220. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  6221. spin_unlock_irqrestore(&dev->event_lock, flags);
  6222. return;
  6223. }
  6224. /* and that the unpin work is consistent wrt ->pending. */
  6225. smp_rmb();
  6226. intel_crtc->unpin_work = NULL;
  6227. if (work->event)
  6228. drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  6229. drm_vblank_put(dev, intel_crtc->pipe);
  6230. spin_unlock_irqrestore(&dev->event_lock, flags);
  6231. wake_up_all(&dev_priv->pending_flip_queue);
  6232. queue_work(dev_priv->wq, &work->work);
  6233. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  6234. }
  6235. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  6236. {
  6237. drm_i915_private_t *dev_priv = dev->dev_private;
  6238. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  6239. do_intel_finish_page_flip(dev, crtc);
  6240. }
  6241. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  6242. {
  6243. drm_i915_private_t *dev_priv = dev->dev_private;
  6244. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  6245. do_intel_finish_page_flip(dev, crtc);
  6246. }
  6247. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  6248. {
  6249. drm_i915_private_t *dev_priv = dev->dev_private;
  6250. struct intel_crtc *intel_crtc =
  6251. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  6252. unsigned long flags;
  6253. /* NB: An MMIO update of the plane base pointer will also
  6254. * generate a page-flip completion irq, i.e. every modeset
  6255. * is also accompanied by a spurious intel_prepare_page_flip().
  6256. */
  6257. spin_lock_irqsave(&dev->event_lock, flags);
  6258. if (intel_crtc->unpin_work)
  6259. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  6260. spin_unlock_irqrestore(&dev->event_lock, flags);
  6261. }
  6262. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  6263. {
  6264. /* Ensure that the work item is consistent when activating it ... */
  6265. smp_wmb();
  6266. atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  6267. /* and that it is marked active as soon as the irq could fire. */
  6268. smp_wmb();
  6269. }
  6270. static int intel_gen2_queue_flip(struct drm_device *dev,
  6271. struct drm_crtc *crtc,
  6272. struct drm_framebuffer *fb,
  6273. struct drm_i915_gem_object *obj)
  6274. {
  6275. struct drm_i915_private *dev_priv = dev->dev_private;
  6276. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6277. u32 flip_mask;
  6278. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6279. int ret;
  6280. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6281. if (ret)
  6282. goto err;
  6283. ret = intel_ring_begin(ring, 6);
  6284. if (ret)
  6285. goto err_unpin;
  6286. /* Can't queue multiple flips, so wait for the previous
  6287. * one to finish before executing the next.
  6288. */
  6289. if (intel_crtc->plane)
  6290. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6291. else
  6292. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6293. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6294. intel_ring_emit(ring, MI_NOOP);
  6295. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6296. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6297. intel_ring_emit(ring, fb->pitches[0]);
  6298. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6299. intel_ring_emit(ring, 0); /* aux display base address, unused */
  6300. intel_mark_page_flip_active(intel_crtc);
  6301. intel_ring_advance(ring);
  6302. return 0;
  6303. err_unpin:
  6304. intel_unpin_fb_obj(obj);
  6305. err:
  6306. return ret;
  6307. }
  6308. static int intel_gen3_queue_flip(struct drm_device *dev,
  6309. struct drm_crtc *crtc,
  6310. struct drm_framebuffer *fb,
  6311. struct drm_i915_gem_object *obj)
  6312. {
  6313. struct drm_i915_private *dev_priv = dev->dev_private;
  6314. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6315. u32 flip_mask;
  6316. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6317. int ret;
  6318. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6319. if (ret)
  6320. goto err;
  6321. ret = intel_ring_begin(ring, 6);
  6322. if (ret)
  6323. goto err_unpin;
  6324. if (intel_crtc->plane)
  6325. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6326. else
  6327. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6328. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  6329. intel_ring_emit(ring, MI_NOOP);
  6330. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  6331. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6332. intel_ring_emit(ring, fb->pitches[0]);
  6333. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6334. intel_ring_emit(ring, MI_NOOP);
  6335. intel_mark_page_flip_active(intel_crtc);
  6336. intel_ring_advance(ring);
  6337. return 0;
  6338. err_unpin:
  6339. intel_unpin_fb_obj(obj);
  6340. err:
  6341. return ret;
  6342. }
  6343. static int intel_gen4_queue_flip(struct drm_device *dev,
  6344. struct drm_crtc *crtc,
  6345. struct drm_framebuffer *fb,
  6346. struct drm_i915_gem_object *obj)
  6347. {
  6348. struct drm_i915_private *dev_priv = dev->dev_private;
  6349. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6350. uint32_t pf, pipesrc;
  6351. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6352. int ret;
  6353. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6354. if (ret)
  6355. goto err;
  6356. ret = intel_ring_begin(ring, 4);
  6357. if (ret)
  6358. goto err_unpin;
  6359. /* i965+ uses the linear or tiled offsets from the
  6360. * Display Registers (which do not change across a page-flip)
  6361. * so we need only reprogram the base address.
  6362. */
  6363. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6364. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6365. intel_ring_emit(ring, fb->pitches[0]);
  6366. intel_ring_emit(ring,
  6367. (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
  6368. obj->tiling_mode);
  6369. /* XXX Enabling the panel-fitter across page-flip is so far
  6370. * untested on non-native modes, so ignore it for now.
  6371. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  6372. */
  6373. pf = 0;
  6374. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6375. intel_ring_emit(ring, pf | pipesrc);
  6376. intel_mark_page_flip_active(intel_crtc);
  6377. intel_ring_advance(ring);
  6378. return 0;
  6379. err_unpin:
  6380. intel_unpin_fb_obj(obj);
  6381. err:
  6382. return ret;
  6383. }
  6384. static int intel_gen6_queue_flip(struct drm_device *dev,
  6385. struct drm_crtc *crtc,
  6386. struct drm_framebuffer *fb,
  6387. struct drm_i915_gem_object *obj)
  6388. {
  6389. struct drm_i915_private *dev_priv = dev->dev_private;
  6390. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6391. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  6392. uint32_t pf, pipesrc;
  6393. int ret;
  6394. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6395. if (ret)
  6396. goto err;
  6397. ret = intel_ring_begin(ring, 4);
  6398. if (ret)
  6399. goto err_unpin;
  6400. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  6401. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6402. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  6403. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6404. /* Contrary to the suggestions in the documentation,
  6405. * "Enable Panel Fitter" does not seem to be required when page
  6406. * flipping with a non-native mode, and worse causes a normal
  6407. * modeset to fail.
  6408. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  6409. */
  6410. pf = 0;
  6411. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6412. intel_ring_emit(ring, pf | pipesrc);
  6413. intel_mark_page_flip_active(intel_crtc);
  6414. intel_ring_advance(ring);
  6415. return 0;
  6416. err_unpin:
  6417. intel_unpin_fb_obj(obj);
  6418. err:
  6419. return ret;
  6420. }
  6421. /*
  6422. * On gen7 we currently use the blit ring because (in early silicon at least)
  6423. * the render ring doesn't give us interrpts for page flip completion, which
  6424. * means clients will hang after the first flip is queued. Fortunately the
  6425. * blit ring generates interrupts properly, so use it instead.
  6426. */
  6427. static int intel_gen7_queue_flip(struct drm_device *dev,
  6428. struct drm_crtc *crtc,
  6429. struct drm_framebuffer *fb,
  6430. struct drm_i915_gem_object *obj)
  6431. {
  6432. struct drm_i915_private *dev_priv = dev->dev_private;
  6433. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6434. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  6435. uint32_t plane_bit = 0;
  6436. int ret;
  6437. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6438. if (ret)
  6439. goto err;
  6440. switch(intel_crtc->plane) {
  6441. case PLANE_A:
  6442. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  6443. break;
  6444. case PLANE_B:
  6445. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  6446. break;
  6447. case PLANE_C:
  6448. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  6449. break;
  6450. default:
  6451. WARN_ONCE(1, "unknown plane in flip command\n");
  6452. ret = -ENODEV;
  6453. goto err_unpin;
  6454. }
  6455. ret = intel_ring_begin(ring, 4);
  6456. if (ret)
  6457. goto err_unpin;
  6458. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  6459. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6460. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
  6461. intel_ring_emit(ring, (MI_NOOP));
  6462. intel_mark_page_flip_active(intel_crtc);
  6463. intel_ring_advance(ring);
  6464. return 0;
  6465. err_unpin:
  6466. intel_unpin_fb_obj(obj);
  6467. err:
  6468. return ret;
  6469. }
  6470. static int intel_default_queue_flip(struct drm_device *dev,
  6471. struct drm_crtc *crtc,
  6472. struct drm_framebuffer *fb,
  6473. struct drm_i915_gem_object *obj)
  6474. {
  6475. return -ENODEV;
  6476. }
  6477. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6478. struct drm_framebuffer *fb,
  6479. struct drm_pending_vblank_event *event)
  6480. {
  6481. struct drm_device *dev = crtc->dev;
  6482. struct drm_i915_private *dev_priv = dev->dev_private;
  6483. struct drm_framebuffer *old_fb = crtc->fb;
  6484. struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
  6485. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6486. struct intel_unpin_work *work;
  6487. unsigned long flags;
  6488. int ret;
  6489. /* Can't change pixel format via MI display flips. */
  6490. if (fb->pixel_format != crtc->fb->pixel_format)
  6491. return -EINVAL;
  6492. /*
  6493. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  6494. * Note that pitch changes could also affect these register.
  6495. */
  6496. if (INTEL_INFO(dev)->gen > 3 &&
  6497. (fb->offsets[0] != crtc->fb->offsets[0] ||
  6498. fb->pitches[0] != crtc->fb->pitches[0]))
  6499. return -EINVAL;
  6500. work = kzalloc(sizeof *work, GFP_KERNEL);
  6501. if (work == NULL)
  6502. return -ENOMEM;
  6503. work->event = event;
  6504. work->crtc = crtc;
  6505. work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
  6506. INIT_WORK(&work->work, intel_unpin_work_fn);
  6507. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6508. if (ret)
  6509. goto free_work;
  6510. /* We borrow the event spin lock for protecting unpin_work */
  6511. spin_lock_irqsave(&dev->event_lock, flags);
  6512. if (intel_crtc->unpin_work) {
  6513. spin_unlock_irqrestore(&dev->event_lock, flags);
  6514. kfree(work);
  6515. drm_vblank_put(dev, intel_crtc->pipe);
  6516. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6517. return -EBUSY;
  6518. }
  6519. intel_crtc->unpin_work = work;
  6520. spin_unlock_irqrestore(&dev->event_lock, flags);
  6521. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  6522. flush_workqueue(dev_priv->wq);
  6523. ret = i915_mutex_lock_interruptible(dev);
  6524. if (ret)
  6525. goto cleanup;
  6526. /* Reference the objects for the scheduled work. */
  6527. drm_gem_object_reference(&work->old_fb_obj->base);
  6528. drm_gem_object_reference(&obj->base);
  6529. crtc->fb = fb;
  6530. work->pending_flip_obj = obj;
  6531. work->enable_stall_check = true;
  6532. atomic_inc(&intel_crtc->unpin_work_count);
  6533. intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
  6534. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  6535. if (ret)
  6536. goto cleanup_pending;
  6537. intel_disable_fbc(dev);
  6538. intel_mark_fb_busy(obj, NULL);
  6539. mutex_unlock(&dev->struct_mutex);
  6540. trace_i915_flip_request(intel_crtc->plane, obj);
  6541. return 0;
  6542. cleanup_pending:
  6543. atomic_dec(&intel_crtc->unpin_work_count);
  6544. crtc->fb = old_fb;
  6545. drm_gem_object_unreference(&work->old_fb_obj->base);
  6546. drm_gem_object_unreference(&obj->base);
  6547. mutex_unlock(&dev->struct_mutex);
  6548. cleanup:
  6549. spin_lock_irqsave(&dev->event_lock, flags);
  6550. intel_crtc->unpin_work = NULL;
  6551. spin_unlock_irqrestore(&dev->event_lock, flags);
  6552. drm_vblank_put(dev, intel_crtc->pipe);
  6553. free_work:
  6554. kfree(work);
  6555. return ret;
  6556. }
  6557. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6558. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6559. .load_lut = intel_crtc_load_lut,
  6560. };
  6561. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  6562. struct drm_crtc *crtc)
  6563. {
  6564. struct drm_device *dev;
  6565. struct drm_crtc *tmp;
  6566. int crtc_mask = 1;
  6567. WARN(!crtc, "checking null crtc?\n");
  6568. dev = crtc->dev;
  6569. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  6570. if (tmp == crtc)
  6571. break;
  6572. crtc_mask <<= 1;
  6573. }
  6574. if (encoder->possible_crtcs & crtc_mask)
  6575. return true;
  6576. return false;
  6577. }
  6578. /**
  6579. * intel_modeset_update_staged_output_state
  6580. *
  6581. * Updates the staged output configuration state, e.g. after we've read out the
  6582. * current hw state.
  6583. */
  6584. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  6585. {
  6586. struct intel_encoder *encoder;
  6587. struct intel_connector *connector;
  6588. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6589. base.head) {
  6590. connector->new_encoder =
  6591. to_intel_encoder(connector->base.encoder);
  6592. }
  6593. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6594. base.head) {
  6595. encoder->new_crtc =
  6596. to_intel_crtc(encoder->base.crtc);
  6597. }
  6598. }
  6599. /**
  6600. * intel_modeset_commit_output_state
  6601. *
  6602. * This function copies the stage display pipe configuration to the real one.
  6603. */
  6604. static void intel_modeset_commit_output_state(struct drm_device *dev)
  6605. {
  6606. struct intel_encoder *encoder;
  6607. struct intel_connector *connector;
  6608. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6609. base.head) {
  6610. connector->base.encoder = &connector->new_encoder->base;
  6611. }
  6612. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6613. base.head) {
  6614. encoder->base.crtc = &encoder->new_crtc->base;
  6615. }
  6616. }
  6617. static void
  6618. connected_sink_compute_bpp(struct intel_connector * connector,
  6619. struct intel_crtc_config *pipe_config)
  6620. {
  6621. int bpp = pipe_config->pipe_bpp;
  6622. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
  6623. connector->base.base.id,
  6624. drm_get_connector_name(&connector->base));
  6625. /* Don't use an invalid EDID bpc value */
  6626. if (connector->base.display_info.bpc &&
  6627. connector->base.display_info.bpc * 3 < bpp) {
  6628. DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
  6629. bpp, connector->base.display_info.bpc*3);
  6630. pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
  6631. }
  6632. /* Clamp bpp to 8 on screens without EDID 1.4 */
  6633. if (connector->base.display_info.bpc == 0 && bpp > 24) {
  6634. DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
  6635. bpp);
  6636. pipe_config->pipe_bpp = 24;
  6637. }
  6638. }
  6639. static int
  6640. compute_baseline_pipe_bpp(struct intel_crtc *crtc,
  6641. struct drm_framebuffer *fb,
  6642. struct intel_crtc_config *pipe_config)
  6643. {
  6644. struct drm_device *dev = crtc->base.dev;
  6645. struct intel_connector *connector;
  6646. int bpp;
  6647. switch (fb->pixel_format) {
  6648. case DRM_FORMAT_C8:
  6649. bpp = 8*3; /* since we go through a colormap */
  6650. break;
  6651. case DRM_FORMAT_XRGB1555:
  6652. case DRM_FORMAT_ARGB1555:
  6653. /* checked in intel_framebuffer_init already */
  6654. if (WARN_ON(INTEL_INFO(dev)->gen > 3))
  6655. return -EINVAL;
  6656. case DRM_FORMAT_RGB565:
  6657. bpp = 6*3; /* min is 18bpp */
  6658. break;
  6659. case DRM_FORMAT_XBGR8888:
  6660. case DRM_FORMAT_ABGR8888:
  6661. /* checked in intel_framebuffer_init already */
  6662. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6663. return -EINVAL;
  6664. case DRM_FORMAT_XRGB8888:
  6665. case DRM_FORMAT_ARGB8888:
  6666. bpp = 8*3;
  6667. break;
  6668. case DRM_FORMAT_XRGB2101010:
  6669. case DRM_FORMAT_ARGB2101010:
  6670. case DRM_FORMAT_XBGR2101010:
  6671. case DRM_FORMAT_ABGR2101010:
  6672. /* checked in intel_framebuffer_init already */
  6673. if (WARN_ON(INTEL_INFO(dev)->gen < 4))
  6674. return -EINVAL;
  6675. bpp = 10*3;
  6676. break;
  6677. /* TODO: gen4+ supports 16 bpc floating point, too. */
  6678. default:
  6679. DRM_DEBUG_KMS("unsupported depth\n");
  6680. return -EINVAL;
  6681. }
  6682. pipe_config->pipe_bpp = bpp;
  6683. /* Clamp display bpp to EDID value */
  6684. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6685. base.head) {
  6686. if (!connector->new_encoder ||
  6687. connector->new_encoder->new_crtc != crtc)
  6688. continue;
  6689. connected_sink_compute_bpp(connector, pipe_config);
  6690. }
  6691. return bpp;
  6692. }
  6693. static void intel_dump_pipe_config(struct intel_crtc *crtc,
  6694. struct intel_crtc_config *pipe_config,
  6695. const char *context)
  6696. {
  6697. DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
  6698. context, pipe_name(crtc->pipe));
  6699. DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
  6700. DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
  6701. pipe_config->pipe_bpp, pipe_config->dither);
  6702. DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
  6703. pipe_config->has_pch_encoder,
  6704. pipe_config->fdi_lanes,
  6705. pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
  6706. pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
  6707. pipe_config->fdi_m_n.tu);
  6708. DRM_DEBUG_KMS("requested mode:\n");
  6709. drm_mode_debug_printmodeline(&pipe_config->requested_mode);
  6710. DRM_DEBUG_KMS("adjusted mode:\n");
  6711. drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
  6712. DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
  6713. pipe_config->gmch_pfit.control,
  6714. pipe_config->gmch_pfit.pgm_ratios,
  6715. pipe_config->gmch_pfit.lvds_border_bits);
  6716. DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
  6717. pipe_config->pch_pfit.pos,
  6718. pipe_config->pch_pfit.size);
  6719. DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
  6720. }
  6721. static bool check_encoder_cloning(struct drm_crtc *crtc)
  6722. {
  6723. int num_encoders = 0;
  6724. bool uncloneable_encoders = false;
  6725. struct intel_encoder *encoder;
  6726. list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
  6727. base.head) {
  6728. if (&encoder->new_crtc->base != crtc)
  6729. continue;
  6730. num_encoders++;
  6731. if (!encoder->cloneable)
  6732. uncloneable_encoders = true;
  6733. }
  6734. return !(num_encoders > 1 && uncloneable_encoders);
  6735. }
  6736. static struct intel_crtc_config *
  6737. intel_modeset_pipe_config(struct drm_crtc *crtc,
  6738. struct drm_framebuffer *fb,
  6739. struct drm_display_mode *mode)
  6740. {
  6741. struct drm_device *dev = crtc->dev;
  6742. struct drm_encoder_helper_funcs *encoder_funcs;
  6743. struct intel_encoder *encoder;
  6744. struct intel_crtc_config *pipe_config;
  6745. int plane_bpp, ret = -EINVAL;
  6746. bool retry = true;
  6747. if (!check_encoder_cloning(crtc)) {
  6748. DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
  6749. return ERR_PTR(-EINVAL);
  6750. }
  6751. pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
  6752. if (!pipe_config)
  6753. return ERR_PTR(-ENOMEM);
  6754. drm_mode_copy(&pipe_config->adjusted_mode, mode);
  6755. drm_mode_copy(&pipe_config->requested_mode, mode);
  6756. pipe_config->cpu_transcoder =
  6757. (enum transcoder) to_intel_crtc(crtc)->pipe;
  6758. pipe_config->shared_dpll = DPLL_ID_PRIVATE;
  6759. /* Compute a starting value for pipe_config->pipe_bpp taking the source
  6760. * plane pixel format and any sink constraints into account. Returns the
  6761. * source plane bpp so that dithering can be selected on mismatches
  6762. * after encoders and crtc also have had their say. */
  6763. plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
  6764. fb, pipe_config);
  6765. if (plane_bpp < 0)
  6766. goto fail;
  6767. encoder_retry:
  6768. /* Ensure the port clock defaults are reset when retrying. */
  6769. pipe_config->port_clock = 0;
  6770. pipe_config->pixel_multiplier = 1;
  6771. /* Pass our mode to the connectors and the CRTC to give them a chance to
  6772. * adjust it according to limitations or connector properties, and also
  6773. * a chance to reject the mode entirely.
  6774. */
  6775. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6776. base.head) {
  6777. if (&encoder->new_crtc->base != crtc)
  6778. continue;
  6779. if (encoder->compute_config) {
  6780. if (!(encoder->compute_config(encoder, pipe_config))) {
  6781. DRM_DEBUG_KMS("Encoder config failure\n");
  6782. goto fail;
  6783. }
  6784. continue;
  6785. }
  6786. encoder_funcs = encoder->base.helper_private;
  6787. if (!(encoder_funcs->mode_fixup(&encoder->base,
  6788. &pipe_config->requested_mode,
  6789. &pipe_config->adjusted_mode))) {
  6790. DRM_DEBUG_KMS("Encoder fixup failed\n");
  6791. goto fail;
  6792. }
  6793. }
  6794. /* Set default port clock if not overwritten by the encoder. Needs to be
  6795. * done afterwards in case the encoder adjusts the mode. */
  6796. if (!pipe_config->port_clock)
  6797. pipe_config->port_clock = pipe_config->adjusted_mode.clock;
  6798. ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
  6799. if (ret < 0) {
  6800. DRM_DEBUG_KMS("CRTC fixup failed\n");
  6801. goto fail;
  6802. }
  6803. if (ret == RETRY) {
  6804. if (WARN(!retry, "loop in pipe configuration computation\n")) {
  6805. ret = -EINVAL;
  6806. goto fail;
  6807. }
  6808. DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
  6809. retry = false;
  6810. goto encoder_retry;
  6811. }
  6812. pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
  6813. DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
  6814. plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
  6815. return pipe_config;
  6816. fail:
  6817. kfree(pipe_config);
  6818. return ERR_PTR(ret);
  6819. }
  6820. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  6821. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  6822. static void
  6823. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  6824. unsigned *prepare_pipes, unsigned *disable_pipes)
  6825. {
  6826. struct intel_crtc *intel_crtc;
  6827. struct drm_device *dev = crtc->dev;
  6828. struct intel_encoder *encoder;
  6829. struct intel_connector *connector;
  6830. struct drm_crtc *tmp_crtc;
  6831. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  6832. /* Check which crtcs have changed outputs connected to them, these need
  6833. * to be part of the prepare_pipes mask. We don't (yet) support global
  6834. * modeset across multiple crtcs, so modeset_pipes will only have one
  6835. * bit set at most. */
  6836. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6837. base.head) {
  6838. if (connector->base.encoder == &connector->new_encoder->base)
  6839. continue;
  6840. if (connector->base.encoder) {
  6841. tmp_crtc = connector->base.encoder->crtc;
  6842. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  6843. }
  6844. if (connector->new_encoder)
  6845. *prepare_pipes |=
  6846. 1 << connector->new_encoder->new_crtc->pipe;
  6847. }
  6848. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6849. base.head) {
  6850. if (encoder->base.crtc == &encoder->new_crtc->base)
  6851. continue;
  6852. if (encoder->base.crtc) {
  6853. tmp_crtc = encoder->base.crtc;
  6854. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  6855. }
  6856. if (encoder->new_crtc)
  6857. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  6858. }
  6859. /* Check for any pipes that will be fully disabled ... */
  6860. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  6861. base.head) {
  6862. bool used = false;
  6863. /* Don't try to disable disabled crtcs. */
  6864. if (!intel_crtc->base.enabled)
  6865. continue;
  6866. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6867. base.head) {
  6868. if (encoder->new_crtc == intel_crtc)
  6869. used = true;
  6870. }
  6871. if (!used)
  6872. *disable_pipes |= 1 << intel_crtc->pipe;
  6873. }
  6874. /* set_mode is also used to update properties on life display pipes. */
  6875. intel_crtc = to_intel_crtc(crtc);
  6876. if (crtc->enabled)
  6877. *prepare_pipes |= 1 << intel_crtc->pipe;
  6878. /*
  6879. * For simplicity do a full modeset on any pipe where the output routing
  6880. * changed. We could be more clever, but that would require us to be
  6881. * more careful with calling the relevant encoder->mode_set functions.
  6882. */
  6883. if (*prepare_pipes)
  6884. *modeset_pipes = *prepare_pipes;
  6885. /* ... and mask these out. */
  6886. *modeset_pipes &= ~(*disable_pipes);
  6887. *prepare_pipes &= ~(*disable_pipes);
  6888. /*
  6889. * HACK: We don't (yet) fully support global modesets. intel_set_config
  6890. * obies this rule, but the modeset restore mode of
  6891. * intel_modeset_setup_hw_state does not.
  6892. */
  6893. *modeset_pipes &= 1 << intel_crtc->pipe;
  6894. *prepare_pipes &= 1 << intel_crtc->pipe;
  6895. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  6896. *modeset_pipes, *prepare_pipes, *disable_pipes);
  6897. }
  6898. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  6899. {
  6900. struct drm_encoder *encoder;
  6901. struct drm_device *dev = crtc->dev;
  6902. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  6903. if (encoder->crtc == crtc)
  6904. return true;
  6905. return false;
  6906. }
  6907. static void
  6908. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  6909. {
  6910. struct intel_encoder *intel_encoder;
  6911. struct intel_crtc *intel_crtc;
  6912. struct drm_connector *connector;
  6913. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  6914. base.head) {
  6915. if (!intel_encoder->base.crtc)
  6916. continue;
  6917. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  6918. if (prepare_pipes & (1 << intel_crtc->pipe))
  6919. intel_encoder->connectors_active = false;
  6920. }
  6921. intel_modeset_commit_output_state(dev);
  6922. /* Update computed state. */
  6923. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  6924. base.head) {
  6925. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  6926. }
  6927. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  6928. if (!connector->encoder || !connector->encoder->crtc)
  6929. continue;
  6930. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  6931. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  6932. struct drm_property *dpms_property =
  6933. dev->mode_config.dpms_property;
  6934. connector->dpms = DRM_MODE_DPMS_ON;
  6935. drm_object_property_set_value(&connector->base,
  6936. dpms_property,
  6937. DRM_MODE_DPMS_ON);
  6938. intel_encoder = to_intel_encoder(connector->encoder);
  6939. intel_encoder->connectors_active = true;
  6940. }
  6941. }
  6942. }
  6943. static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
  6944. struct intel_crtc_config *new)
  6945. {
  6946. int clock1, clock2, diff;
  6947. clock1 = cur->adjusted_mode.clock;
  6948. clock2 = new->adjusted_mode.clock;
  6949. if (clock1 == clock2)
  6950. return true;
  6951. if (!clock1 || !clock2)
  6952. return false;
  6953. diff = abs(clock1 - clock2);
  6954. if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
  6955. return true;
  6956. return false;
  6957. }
  6958. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  6959. list_for_each_entry((intel_crtc), \
  6960. &(dev)->mode_config.crtc_list, \
  6961. base.head) \
  6962. if (mask & (1 <<(intel_crtc)->pipe))
  6963. static bool
  6964. intel_pipe_config_compare(struct drm_device *dev,
  6965. struct intel_crtc_config *current_config,
  6966. struct intel_crtc_config *pipe_config)
  6967. {
  6968. #define PIPE_CONF_CHECK_X(name) \
  6969. if (current_config->name != pipe_config->name) { \
  6970. DRM_ERROR("mismatch in " #name " " \
  6971. "(expected 0x%08x, found 0x%08x)\n", \
  6972. current_config->name, \
  6973. pipe_config->name); \
  6974. return false; \
  6975. }
  6976. #define PIPE_CONF_CHECK_I(name) \
  6977. if (current_config->name != pipe_config->name) { \
  6978. DRM_ERROR("mismatch in " #name " " \
  6979. "(expected %i, found %i)\n", \
  6980. current_config->name, \
  6981. pipe_config->name); \
  6982. return false; \
  6983. }
  6984. #define PIPE_CONF_CHECK_FLAGS(name, mask) \
  6985. if ((current_config->name ^ pipe_config->name) & (mask)) { \
  6986. DRM_ERROR("mismatch in " #name "(" #mask ") " \
  6987. "(expected %i, found %i)\n", \
  6988. current_config->name & (mask), \
  6989. pipe_config->name & (mask)); \
  6990. return false; \
  6991. }
  6992. #define PIPE_CONF_QUIRK(quirk) \
  6993. ((current_config->quirks | pipe_config->quirks) & (quirk))
  6994. PIPE_CONF_CHECK_I(cpu_transcoder);
  6995. PIPE_CONF_CHECK_I(has_pch_encoder);
  6996. PIPE_CONF_CHECK_I(fdi_lanes);
  6997. PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
  6998. PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
  6999. PIPE_CONF_CHECK_I(fdi_m_n.link_m);
  7000. PIPE_CONF_CHECK_I(fdi_m_n.link_n);
  7001. PIPE_CONF_CHECK_I(fdi_m_n.tu);
  7002. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
  7003. PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
  7004. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
  7005. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
  7006. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
  7007. PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
  7008. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
  7009. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
  7010. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
  7011. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
  7012. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
  7013. PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
  7014. PIPE_CONF_CHECK_I(pixel_multiplier);
  7015. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7016. DRM_MODE_FLAG_INTERLACE);
  7017. if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
  7018. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7019. DRM_MODE_FLAG_PHSYNC);
  7020. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7021. DRM_MODE_FLAG_NHSYNC);
  7022. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7023. DRM_MODE_FLAG_PVSYNC);
  7024. PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
  7025. DRM_MODE_FLAG_NVSYNC);
  7026. }
  7027. PIPE_CONF_CHECK_I(requested_mode.hdisplay);
  7028. PIPE_CONF_CHECK_I(requested_mode.vdisplay);
  7029. PIPE_CONF_CHECK_I(gmch_pfit.control);
  7030. /* pfit ratios are autocomputed by the hw on gen4+ */
  7031. if (INTEL_INFO(dev)->gen < 4)
  7032. PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
  7033. PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
  7034. PIPE_CONF_CHECK_I(pch_pfit.pos);
  7035. PIPE_CONF_CHECK_I(pch_pfit.size);
  7036. PIPE_CONF_CHECK_I(ips_enabled);
  7037. PIPE_CONF_CHECK_I(shared_dpll);
  7038. PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
  7039. PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
  7040. PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
  7041. PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
  7042. #undef PIPE_CONF_CHECK_X
  7043. #undef PIPE_CONF_CHECK_I
  7044. #undef PIPE_CONF_CHECK_FLAGS
  7045. #undef PIPE_CONF_QUIRK
  7046. if (!IS_HASWELL(dev)) {
  7047. if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
  7048. DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
  7049. current_config->adjusted_mode.clock,
  7050. pipe_config->adjusted_mode.clock);
  7051. return false;
  7052. }
  7053. }
  7054. return true;
  7055. }
  7056. static void
  7057. check_connector_state(struct drm_device *dev)
  7058. {
  7059. struct intel_connector *connector;
  7060. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7061. base.head) {
  7062. /* This also checks the encoder/connector hw state with the
  7063. * ->get_hw_state callbacks. */
  7064. intel_connector_check_state(connector);
  7065. WARN(&connector->new_encoder->base != connector->base.encoder,
  7066. "connector's staged encoder doesn't match current encoder\n");
  7067. }
  7068. }
  7069. static void
  7070. check_encoder_state(struct drm_device *dev)
  7071. {
  7072. struct intel_encoder *encoder;
  7073. struct intel_connector *connector;
  7074. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7075. base.head) {
  7076. bool enabled = false;
  7077. bool active = false;
  7078. enum pipe pipe, tracked_pipe;
  7079. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  7080. encoder->base.base.id,
  7081. drm_get_encoder_name(&encoder->base));
  7082. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  7083. "encoder's stage crtc doesn't match current crtc\n");
  7084. WARN(encoder->connectors_active && !encoder->base.crtc,
  7085. "encoder's active_connectors set, but no crtc\n");
  7086. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7087. base.head) {
  7088. if (connector->base.encoder != &encoder->base)
  7089. continue;
  7090. enabled = true;
  7091. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  7092. active = true;
  7093. }
  7094. WARN(!!encoder->base.crtc != enabled,
  7095. "encoder's enabled state mismatch "
  7096. "(expected %i, found %i)\n",
  7097. !!encoder->base.crtc, enabled);
  7098. WARN(active && !encoder->base.crtc,
  7099. "active encoder with no crtc\n");
  7100. WARN(encoder->connectors_active != active,
  7101. "encoder's computed active state doesn't match tracked active state "
  7102. "(expected %i, found %i)\n", active, encoder->connectors_active);
  7103. active = encoder->get_hw_state(encoder, &pipe);
  7104. WARN(active != encoder->connectors_active,
  7105. "encoder's hw state doesn't match sw tracking "
  7106. "(expected %i, found %i)\n",
  7107. encoder->connectors_active, active);
  7108. if (!encoder->base.crtc)
  7109. continue;
  7110. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  7111. WARN(active && pipe != tracked_pipe,
  7112. "active encoder's pipe doesn't match"
  7113. "(expected %i, found %i)\n",
  7114. tracked_pipe, pipe);
  7115. }
  7116. }
  7117. static void
  7118. check_crtc_state(struct drm_device *dev)
  7119. {
  7120. drm_i915_private_t *dev_priv = dev->dev_private;
  7121. struct intel_crtc *crtc;
  7122. struct intel_encoder *encoder;
  7123. struct intel_crtc_config pipe_config;
  7124. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7125. base.head) {
  7126. bool enabled = false;
  7127. bool active = false;
  7128. memset(&pipe_config, 0, sizeof(pipe_config));
  7129. DRM_DEBUG_KMS("[CRTC:%d]\n",
  7130. crtc->base.base.id);
  7131. WARN(crtc->active && !crtc->base.enabled,
  7132. "active crtc, but not enabled in sw tracking\n");
  7133. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7134. base.head) {
  7135. if (encoder->base.crtc != &crtc->base)
  7136. continue;
  7137. enabled = true;
  7138. if (encoder->connectors_active)
  7139. active = true;
  7140. }
  7141. WARN(active != crtc->active,
  7142. "crtc's computed active state doesn't match tracked active state "
  7143. "(expected %i, found %i)\n", active, crtc->active);
  7144. WARN(enabled != crtc->base.enabled,
  7145. "crtc's computed enabled state doesn't match tracked enabled state "
  7146. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  7147. active = dev_priv->display.get_pipe_config(crtc,
  7148. &pipe_config);
  7149. /* hw state is inconsistent with the pipe A quirk */
  7150. if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  7151. active = crtc->active;
  7152. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7153. base.head) {
  7154. if (encoder->base.crtc != &crtc->base)
  7155. continue;
  7156. if (encoder->get_config)
  7157. encoder->get_config(encoder, &pipe_config);
  7158. }
  7159. if (dev_priv->display.get_clock)
  7160. dev_priv->display.get_clock(crtc, &pipe_config);
  7161. WARN(crtc->active != active,
  7162. "crtc active state doesn't match with hw state "
  7163. "(expected %i, found %i)\n", crtc->active, active);
  7164. if (active &&
  7165. !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
  7166. WARN(1, "pipe state doesn't match!\n");
  7167. intel_dump_pipe_config(crtc, &pipe_config,
  7168. "[hw state]");
  7169. intel_dump_pipe_config(crtc, &crtc->config,
  7170. "[sw state]");
  7171. }
  7172. }
  7173. }
  7174. static void
  7175. check_shared_dpll_state(struct drm_device *dev)
  7176. {
  7177. drm_i915_private_t *dev_priv = dev->dev_private;
  7178. struct intel_crtc *crtc;
  7179. struct intel_dpll_hw_state dpll_hw_state;
  7180. int i;
  7181. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7182. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  7183. int enabled_crtcs = 0, active_crtcs = 0;
  7184. bool active;
  7185. memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
  7186. DRM_DEBUG_KMS("%s\n", pll->name);
  7187. active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
  7188. WARN(pll->active > pll->refcount,
  7189. "more active pll users than references: %i vs %i\n",
  7190. pll->active, pll->refcount);
  7191. WARN(pll->active && !pll->on,
  7192. "pll in active use but not on in sw tracking\n");
  7193. WARN(pll->on && !pll->active,
  7194. "pll in on but not on in use in sw tracking\n");
  7195. WARN(pll->on != active,
  7196. "pll on state mismatch (expected %i, found %i)\n",
  7197. pll->on, active);
  7198. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  7199. base.head) {
  7200. if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
  7201. enabled_crtcs++;
  7202. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  7203. active_crtcs++;
  7204. }
  7205. WARN(pll->active != active_crtcs,
  7206. "pll active crtcs mismatch (expected %i, found %i)\n",
  7207. pll->active, active_crtcs);
  7208. WARN(pll->refcount != enabled_crtcs,
  7209. "pll enabled crtcs mismatch (expected %i, found %i)\n",
  7210. pll->refcount, enabled_crtcs);
  7211. WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
  7212. sizeof(dpll_hw_state)),
  7213. "pll hw state mismatch\n");
  7214. }
  7215. }
  7216. void
  7217. intel_modeset_check_state(struct drm_device *dev)
  7218. {
  7219. check_connector_state(dev);
  7220. check_encoder_state(dev);
  7221. check_crtc_state(dev);
  7222. check_shared_dpll_state(dev);
  7223. }
  7224. static int __intel_set_mode(struct drm_crtc *crtc,
  7225. struct drm_display_mode *mode,
  7226. int x, int y, struct drm_framebuffer *fb)
  7227. {
  7228. struct drm_device *dev = crtc->dev;
  7229. drm_i915_private_t *dev_priv = dev->dev_private;
  7230. struct drm_display_mode *saved_mode, *saved_hwmode;
  7231. struct intel_crtc_config *pipe_config = NULL;
  7232. struct intel_crtc *intel_crtc;
  7233. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  7234. int ret = 0;
  7235. saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
  7236. if (!saved_mode)
  7237. return -ENOMEM;
  7238. saved_hwmode = saved_mode + 1;
  7239. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  7240. &prepare_pipes, &disable_pipes);
  7241. *saved_hwmode = crtc->hwmode;
  7242. *saved_mode = crtc->mode;
  7243. /* Hack: Because we don't (yet) support global modeset on multiple
  7244. * crtcs, we don't keep track of the new mode for more than one crtc.
  7245. * Hence simply check whether any bit is set in modeset_pipes in all the
  7246. * pieces of code that are not yet converted to deal with mutliple crtcs
  7247. * changing their mode at the same time. */
  7248. if (modeset_pipes) {
  7249. pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
  7250. if (IS_ERR(pipe_config)) {
  7251. ret = PTR_ERR(pipe_config);
  7252. pipe_config = NULL;
  7253. goto out;
  7254. }
  7255. intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
  7256. "[modeset]");
  7257. }
  7258. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  7259. intel_crtc_disable(&intel_crtc->base);
  7260. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  7261. if (intel_crtc->base.enabled)
  7262. dev_priv->display.crtc_disable(&intel_crtc->base);
  7263. }
  7264. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  7265. * to set it here already despite that we pass it down the callchain.
  7266. */
  7267. if (modeset_pipes) {
  7268. crtc->mode = *mode;
  7269. /* mode_set/enable/disable functions rely on a correct pipe
  7270. * config. */
  7271. to_intel_crtc(crtc)->config = *pipe_config;
  7272. }
  7273. /* Only after disabling all output pipelines that will be changed can we
  7274. * update the the output configuration. */
  7275. intel_modeset_update_state(dev, prepare_pipes);
  7276. if (dev_priv->display.modeset_global_resources)
  7277. dev_priv->display.modeset_global_resources(dev);
  7278. /* Set up the DPLL and any encoders state that needs to adjust or depend
  7279. * on the DPLL.
  7280. */
  7281. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  7282. ret = intel_crtc_mode_set(&intel_crtc->base,
  7283. x, y, fb);
  7284. if (ret)
  7285. goto done;
  7286. }
  7287. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  7288. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  7289. dev_priv->display.crtc_enable(&intel_crtc->base);
  7290. if (modeset_pipes) {
  7291. /* Store real post-adjustment hardware mode. */
  7292. crtc->hwmode = pipe_config->adjusted_mode;
  7293. /* Calculate and store various constants which
  7294. * are later needed by vblank and swap-completion
  7295. * timestamping. They are derived from true hwmode.
  7296. */
  7297. drm_calc_timestamping_constants(crtc);
  7298. }
  7299. /* FIXME: add subpixel order */
  7300. done:
  7301. if (ret && crtc->enabled) {
  7302. crtc->hwmode = *saved_hwmode;
  7303. crtc->mode = *saved_mode;
  7304. }
  7305. out:
  7306. kfree(pipe_config);
  7307. kfree(saved_mode);
  7308. return ret;
  7309. }
  7310. int intel_set_mode(struct drm_crtc *crtc,
  7311. struct drm_display_mode *mode,
  7312. int x, int y, struct drm_framebuffer *fb)
  7313. {
  7314. int ret;
  7315. ret = __intel_set_mode(crtc, mode, x, y, fb);
  7316. if (ret == 0)
  7317. intel_modeset_check_state(crtc->dev);
  7318. return ret;
  7319. }
  7320. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  7321. {
  7322. intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  7323. }
  7324. #undef for_each_intel_crtc_masked
  7325. static void intel_set_config_free(struct intel_set_config *config)
  7326. {
  7327. if (!config)
  7328. return;
  7329. kfree(config->save_connector_encoders);
  7330. kfree(config->save_encoder_crtcs);
  7331. kfree(config);
  7332. }
  7333. static int intel_set_config_save_state(struct drm_device *dev,
  7334. struct intel_set_config *config)
  7335. {
  7336. struct drm_encoder *encoder;
  7337. struct drm_connector *connector;
  7338. int count;
  7339. config->save_encoder_crtcs =
  7340. kcalloc(dev->mode_config.num_encoder,
  7341. sizeof(struct drm_crtc *), GFP_KERNEL);
  7342. if (!config->save_encoder_crtcs)
  7343. return -ENOMEM;
  7344. config->save_connector_encoders =
  7345. kcalloc(dev->mode_config.num_connector,
  7346. sizeof(struct drm_encoder *), GFP_KERNEL);
  7347. if (!config->save_connector_encoders)
  7348. return -ENOMEM;
  7349. /* Copy data. Note that driver private data is not affected.
  7350. * Should anything bad happen only the expected state is
  7351. * restored, not the drivers personal bookkeeping.
  7352. */
  7353. count = 0;
  7354. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  7355. config->save_encoder_crtcs[count++] = encoder->crtc;
  7356. }
  7357. count = 0;
  7358. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  7359. config->save_connector_encoders[count++] = connector->encoder;
  7360. }
  7361. return 0;
  7362. }
  7363. static void intel_set_config_restore_state(struct drm_device *dev,
  7364. struct intel_set_config *config)
  7365. {
  7366. struct intel_encoder *encoder;
  7367. struct intel_connector *connector;
  7368. int count;
  7369. count = 0;
  7370. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  7371. encoder->new_crtc =
  7372. to_intel_crtc(config->save_encoder_crtcs[count++]);
  7373. }
  7374. count = 0;
  7375. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  7376. connector->new_encoder =
  7377. to_intel_encoder(config->save_connector_encoders[count++]);
  7378. }
  7379. }
  7380. static bool
  7381. is_crtc_connector_off(struct drm_mode_set *set)
  7382. {
  7383. int i;
  7384. if (set->num_connectors == 0)
  7385. return false;
  7386. if (WARN_ON(set->connectors == NULL))
  7387. return false;
  7388. for (i = 0; i < set->num_connectors; i++)
  7389. if (set->connectors[i]->encoder &&
  7390. set->connectors[i]->encoder->crtc == set->crtc &&
  7391. set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
  7392. return true;
  7393. return false;
  7394. }
  7395. static void
  7396. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  7397. struct intel_set_config *config)
  7398. {
  7399. /* We should be able to check here if the fb has the same properties
  7400. * and then just flip_or_move it */
  7401. if (is_crtc_connector_off(set)) {
  7402. config->mode_changed = true;
  7403. } else if (set->crtc->fb != set->fb) {
  7404. /* If we have no fb then treat it as a full mode set */
  7405. if (set->crtc->fb == NULL) {
  7406. struct intel_crtc *intel_crtc =
  7407. to_intel_crtc(set->crtc);
  7408. if (intel_crtc->active && i915_fastboot) {
  7409. DRM_DEBUG_KMS("crtc has no fb, will flip\n");
  7410. config->fb_changed = true;
  7411. } else {
  7412. DRM_DEBUG_KMS("inactive crtc, full mode set\n");
  7413. config->mode_changed = true;
  7414. }
  7415. } else if (set->fb == NULL) {
  7416. config->mode_changed = true;
  7417. } else if (set->fb->pixel_format !=
  7418. set->crtc->fb->pixel_format) {
  7419. config->mode_changed = true;
  7420. } else {
  7421. config->fb_changed = true;
  7422. }
  7423. }
  7424. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  7425. config->fb_changed = true;
  7426. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  7427. DRM_DEBUG_KMS("modes are different, full mode set\n");
  7428. drm_mode_debug_printmodeline(&set->crtc->mode);
  7429. drm_mode_debug_printmodeline(set->mode);
  7430. config->mode_changed = true;
  7431. }
  7432. }
  7433. static int
  7434. intel_modeset_stage_output_state(struct drm_device *dev,
  7435. struct drm_mode_set *set,
  7436. struct intel_set_config *config)
  7437. {
  7438. struct drm_crtc *new_crtc;
  7439. struct intel_connector *connector;
  7440. struct intel_encoder *encoder;
  7441. int count, ro;
  7442. /* The upper layers ensure that we either disable a crtc or have a list
  7443. * of connectors. For paranoia, double-check this. */
  7444. WARN_ON(!set->fb && (set->num_connectors != 0));
  7445. WARN_ON(set->fb && (set->num_connectors == 0));
  7446. count = 0;
  7447. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7448. base.head) {
  7449. /* Otherwise traverse passed in connector list and get encoders
  7450. * for them. */
  7451. for (ro = 0; ro < set->num_connectors; ro++) {
  7452. if (set->connectors[ro] == &connector->base) {
  7453. connector->new_encoder = connector->encoder;
  7454. break;
  7455. }
  7456. }
  7457. /* If we disable the crtc, disable all its connectors. Also, if
  7458. * the connector is on the changing crtc but not on the new
  7459. * connector list, disable it. */
  7460. if ((!set->fb || ro == set->num_connectors) &&
  7461. connector->base.encoder &&
  7462. connector->base.encoder->crtc == set->crtc) {
  7463. connector->new_encoder = NULL;
  7464. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  7465. connector->base.base.id,
  7466. drm_get_connector_name(&connector->base));
  7467. }
  7468. if (&connector->new_encoder->base != connector->base.encoder) {
  7469. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  7470. config->mode_changed = true;
  7471. }
  7472. }
  7473. /* connector->new_encoder is now updated for all connectors. */
  7474. /* Update crtc of enabled connectors. */
  7475. count = 0;
  7476. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7477. base.head) {
  7478. if (!connector->new_encoder)
  7479. continue;
  7480. new_crtc = connector->new_encoder->base.crtc;
  7481. for (ro = 0; ro < set->num_connectors; ro++) {
  7482. if (set->connectors[ro] == &connector->base)
  7483. new_crtc = set->crtc;
  7484. }
  7485. /* Make sure the new CRTC will work with the encoder */
  7486. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  7487. new_crtc)) {
  7488. return -EINVAL;
  7489. }
  7490. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  7491. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  7492. connector->base.base.id,
  7493. drm_get_connector_name(&connector->base),
  7494. new_crtc->base.id);
  7495. }
  7496. /* Check for any encoders that needs to be disabled. */
  7497. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7498. base.head) {
  7499. list_for_each_entry(connector,
  7500. &dev->mode_config.connector_list,
  7501. base.head) {
  7502. if (connector->new_encoder == encoder) {
  7503. WARN_ON(!connector->new_encoder->new_crtc);
  7504. goto next_encoder;
  7505. }
  7506. }
  7507. encoder->new_crtc = NULL;
  7508. next_encoder:
  7509. /* Only now check for crtc changes so we don't miss encoders
  7510. * that will be disabled. */
  7511. if (&encoder->new_crtc->base != encoder->base.crtc) {
  7512. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  7513. config->mode_changed = true;
  7514. }
  7515. }
  7516. /* Now we've also updated encoder->new_crtc for all encoders. */
  7517. return 0;
  7518. }
  7519. static int intel_crtc_set_config(struct drm_mode_set *set)
  7520. {
  7521. struct drm_device *dev;
  7522. struct drm_mode_set save_set;
  7523. struct intel_set_config *config;
  7524. int ret;
  7525. BUG_ON(!set);
  7526. BUG_ON(!set->crtc);
  7527. BUG_ON(!set->crtc->helper_private);
  7528. /* Enforce sane interface api - has been abused by the fb helper. */
  7529. BUG_ON(!set->mode && set->fb);
  7530. BUG_ON(set->fb && set->num_connectors == 0);
  7531. if (set->fb) {
  7532. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  7533. set->crtc->base.id, set->fb->base.id,
  7534. (int)set->num_connectors, set->x, set->y);
  7535. } else {
  7536. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  7537. }
  7538. dev = set->crtc->dev;
  7539. ret = -ENOMEM;
  7540. config = kzalloc(sizeof(*config), GFP_KERNEL);
  7541. if (!config)
  7542. goto out_config;
  7543. ret = intel_set_config_save_state(dev, config);
  7544. if (ret)
  7545. goto out_config;
  7546. save_set.crtc = set->crtc;
  7547. save_set.mode = &set->crtc->mode;
  7548. save_set.x = set->crtc->x;
  7549. save_set.y = set->crtc->y;
  7550. save_set.fb = set->crtc->fb;
  7551. /* Compute whether we need a full modeset, only an fb base update or no
  7552. * change at all. In the future we might also check whether only the
  7553. * mode changed, e.g. for LVDS where we only change the panel fitter in
  7554. * such cases. */
  7555. intel_set_config_compute_mode_changes(set, config);
  7556. ret = intel_modeset_stage_output_state(dev, set, config);
  7557. if (ret)
  7558. goto fail;
  7559. if (config->mode_changed) {
  7560. ret = intel_set_mode(set->crtc, set->mode,
  7561. set->x, set->y, set->fb);
  7562. } else if (config->fb_changed) {
  7563. intel_crtc_wait_for_pending_flips(set->crtc);
  7564. ret = intel_pipe_set_base(set->crtc,
  7565. set->x, set->y, set->fb);
  7566. }
  7567. if (ret) {
  7568. DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
  7569. set->crtc->base.id, ret);
  7570. fail:
  7571. intel_set_config_restore_state(dev, config);
  7572. /* Try to restore the config */
  7573. if (config->mode_changed &&
  7574. intel_set_mode(save_set.crtc, save_set.mode,
  7575. save_set.x, save_set.y, save_set.fb))
  7576. DRM_ERROR("failed to restore config after modeset failure\n");
  7577. }
  7578. out_config:
  7579. intel_set_config_free(config);
  7580. return ret;
  7581. }
  7582. static const struct drm_crtc_funcs intel_crtc_funcs = {
  7583. .cursor_set = intel_crtc_cursor_set,
  7584. .cursor_move = intel_crtc_cursor_move,
  7585. .gamma_set = intel_crtc_gamma_set,
  7586. .set_config = intel_crtc_set_config,
  7587. .destroy = intel_crtc_destroy,
  7588. .page_flip = intel_crtc_page_flip,
  7589. };
  7590. static void intel_cpu_pll_init(struct drm_device *dev)
  7591. {
  7592. if (HAS_DDI(dev))
  7593. intel_ddi_pll_init(dev);
  7594. }
  7595. static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
  7596. struct intel_shared_dpll *pll,
  7597. struct intel_dpll_hw_state *hw_state)
  7598. {
  7599. uint32_t val;
  7600. val = I915_READ(PCH_DPLL(pll->id));
  7601. hw_state->dpll = val;
  7602. hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
  7603. hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
  7604. return val & DPLL_VCO_ENABLE;
  7605. }
  7606. static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
  7607. struct intel_shared_dpll *pll)
  7608. {
  7609. I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
  7610. I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
  7611. }
  7612. static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
  7613. struct intel_shared_dpll *pll)
  7614. {
  7615. /* PCH refclock must be enabled first */
  7616. assert_pch_refclk_enabled(dev_priv);
  7617. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  7618. /* Wait for the clocks to stabilize. */
  7619. POSTING_READ(PCH_DPLL(pll->id));
  7620. udelay(150);
  7621. /* The pixel multiplier can only be updated once the
  7622. * DPLL is enabled and the clocks are stable.
  7623. *
  7624. * So write it again.
  7625. */
  7626. I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
  7627. POSTING_READ(PCH_DPLL(pll->id));
  7628. udelay(200);
  7629. }
  7630. static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
  7631. struct intel_shared_dpll *pll)
  7632. {
  7633. struct drm_device *dev = dev_priv->dev;
  7634. struct intel_crtc *crtc;
  7635. /* Make sure no transcoder isn't still depending on us. */
  7636. list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
  7637. if (intel_crtc_to_shared_dpll(crtc) == pll)
  7638. assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
  7639. }
  7640. I915_WRITE(PCH_DPLL(pll->id), 0);
  7641. POSTING_READ(PCH_DPLL(pll->id));
  7642. udelay(200);
  7643. }
  7644. static char *ibx_pch_dpll_names[] = {
  7645. "PCH DPLL A",
  7646. "PCH DPLL B",
  7647. };
  7648. static void ibx_pch_dpll_init(struct drm_device *dev)
  7649. {
  7650. struct drm_i915_private *dev_priv = dev->dev_private;
  7651. int i;
  7652. dev_priv->num_shared_dpll = 2;
  7653. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  7654. dev_priv->shared_dplls[i].id = i;
  7655. dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
  7656. dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
  7657. dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
  7658. dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
  7659. dev_priv->shared_dplls[i].get_hw_state =
  7660. ibx_pch_dpll_get_hw_state;
  7661. }
  7662. }
  7663. static void intel_shared_dpll_init(struct drm_device *dev)
  7664. {
  7665. struct drm_i915_private *dev_priv = dev->dev_private;
  7666. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  7667. ibx_pch_dpll_init(dev);
  7668. else
  7669. dev_priv->num_shared_dpll = 0;
  7670. BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
  7671. DRM_DEBUG_KMS("%i shared PLLs initialized\n",
  7672. dev_priv->num_shared_dpll);
  7673. }
  7674. static void intel_crtc_init(struct drm_device *dev, int pipe)
  7675. {
  7676. drm_i915_private_t *dev_priv = dev->dev_private;
  7677. struct intel_crtc *intel_crtc;
  7678. int i;
  7679. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  7680. if (intel_crtc == NULL)
  7681. return;
  7682. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  7683. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  7684. for (i = 0; i < 256; i++) {
  7685. intel_crtc->lut_r[i] = i;
  7686. intel_crtc->lut_g[i] = i;
  7687. intel_crtc->lut_b[i] = i;
  7688. }
  7689. /* Swap pipes & planes for FBC on pre-965 */
  7690. intel_crtc->pipe = pipe;
  7691. intel_crtc->plane = pipe;
  7692. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  7693. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  7694. intel_crtc->plane = !pipe;
  7695. }
  7696. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  7697. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  7698. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  7699. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  7700. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  7701. }
  7702. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  7703. struct drm_file *file)
  7704. {
  7705. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  7706. struct drm_mode_object *drmmode_obj;
  7707. struct intel_crtc *crtc;
  7708. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  7709. return -ENODEV;
  7710. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  7711. DRM_MODE_OBJECT_CRTC);
  7712. if (!drmmode_obj) {
  7713. DRM_ERROR("no such CRTC id\n");
  7714. return -EINVAL;
  7715. }
  7716. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  7717. pipe_from_crtc_id->pipe = crtc->pipe;
  7718. return 0;
  7719. }
  7720. static int intel_encoder_clones(struct intel_encoder *encoder)
  7721. {
  7722. struct drm_device *dev = encoder->base.dev;
  7723. struct intel_encoder *source_encoder;
  7724. int index_mask = 0;
  7725. int entry = 0;
  7726. list_for_each_entry(source_encoder,
  7727. &dev->mode_config.encoder_list, base.head) {
  7728. if (encoder == source_encoder)
  7729. index_mask |= (1 << entry);
  7730. /* Intel hw has only one MUX where enocoders could be cloned. */
  7731. if (encoder->cloneable && source_encoder->cloneable)
  7732. index_mask |= (1 << entry);
  7733. entry++;
  7734. }
  7735. return index_mask;
  7736. }
  7737. static bool has_edp_a(struct drm_device *dev)
  7738. {
  7739. struct drm_i915_private *dev_priv = dev->dev_private;
  7740. if (!IS_MOBILE(dev))
  7741. return false;
  7742. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  7743. return false;
  7744. if (IS_GEN5(dev) &&
  7745. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  7746. return false;
  7747. return true;
  7748. }
  7749. static void intel_setup_outputs(struct drm_device *dev)
  7750. {
  7751. struct drm_i915_private *dev_priv = dev->dev_private;
  7752. struct intel_encoder *encoder;
  7753. bool dpd_is_edp = false;
  7754. intel_lvds_init(dev);
  7755. if (!IS_ULT(dev))
  7756. intel_crt_init(dev);
  7757. if (HAS_DDI(dev)) {
  7758. int found;
  7759. /* Haswell uses DDI functions to detect digital outputs */
  7760. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  7761. /* DDI A only supports eDP */
  7762. if (found)
  7763. intel_ddi_init(dev, PORT_A);
  7764. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  7765. * register */
  7766. found = I915_READ(SFUSE_STRAP);
  7767. if (found & SFUSE_STRAP_DDIB_DETECTED)
  7768. intel_ddi_init(dev, PORT_B);
  7769. if (found & SFUSE_STRAP_DDIC_DETECTED)
  7770. intel_ddi_init(dev, PORT_C);
  7771. if (found & SFUSE_STRAP_DDID_DETECTED)
  7772. intel_ddi_init(dev, PORT_D);
  7773. } else if (HAS_PCH_SPLIT(dev)) {
  7774. int found;
  7775. dpd_is_edp = intel_dpd_is_edp(dev);
  7776. if (has_edp_a(dev))
  7777. intel_dp_init(dev, DP_A, PORT_A);
  7778. if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
  7779. /* PCH SDVOB multiplex with HDMIB */
  7780. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  7781. if (!found)
  7782. intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
  7783. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  7784. intel_dp_init(dev, PCH_DP_B, PORT_B);
  7785. }
  7786. if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
  7787. intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
  7788. if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
  7789. intel_hdmi_init(dev, PCH_HDMID, PORT_D);
  7790. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  7791. intel_dp_init(dev, PCH_DP_C, PORT_C);
  7792. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  7793. intel_dp_init(dev, PCH_DP_D, PORT_D);
  7794. } else if (IS_VALLEYVIEW(dev)) {
  7795. /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
  7796. if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
  7797. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
  7798. if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
  7799. intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
  7800. PORT_B);
  7801. if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
  7802. intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
  7803. }
  7804. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  7805. bool found = false;
  7806. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  7807. DRM_DEBUG_KMS("probing SDVOB\n");
  7808. found = intel_sdvo_init(dev, GEN3_SDVOB, true);
  7809. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  7810. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  7811. intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
  7812. }
  7813. if (!found && SUPPORTS_INTEGRATED_DP(dev))
  7814. intel_dp_init(dev, DP_B, PORT_B);
  7815. }
  7816. /* Before G4X SDVOC doesn't have its own detect register */
  7817. if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
  7818. DRM_DEBUG_KMS("probing SDVOC\n");
  7819. found = intel_sdvo_init(dev, GEN3_SDVOC, false);
  7820. }
  7821. if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
  7822. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  7823. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  7824. intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
  7825. }
  7826. if (SUPPORTS_INTEGRATED_DP(dev))
  7827. intel_dp_init(dev, DP_C, PORT_C);
  7828. }
  7829. if (SUPPORTS_INTEGRATED_DP(dev) &&
  7830. (I915_READ(DP_D) & DP_DETECTED))
  7831. intel_dp_init(dev, DP_D, PORT_D);
  7832. } else if (IS_GEN2(dev))
  7833. intel_dvo_init(dev);
  7834. if (SUPPORTS_TV(dev))
  7835. intel_tv_init(dev);
  7836. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  7837. encoder->base.possible_crtcs = encoder->crtc_mask;
  7838. encoder->base.possible_clones =
  7839. intel_encoder_clones(encoder);
  7840. }
  7841. intel_init_pch_refclk(dev);
  7842. drm_helper_move_panel_connectors_to_head(dev);
  7843. }
  7844. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  7845. {
  7846. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  7847. drm_framebuffer_cleanup(fb);
  7848. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  7849. kfree(intel_fb);
  7850. }
  7851. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  7852. struct drm_file *file,
  7853. unsigned int *handle)
  7854. {
  7855. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  7856. struct drm_i915_gem_object *obj = intel_fb->obj;
  7857. return drm_gem_handle_create(file, &obj->base, handle);
  7858. }
  7859. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  7860. .destroy = intel_user_framebuffer_destroy,
  7861. .create_handle = intel_user_framebuffer_create_handle,
  7862. };
  7863. int intel_framebuffer_init(struct drm_device *dev,
  7864. struct intel_framebuffer *intel_fb,
  7865. struct drm_mode_fb_cmd2 *mode_cmd,
  7866. struct drm_i915_gem_object *obj)
  7867. {
  7868. int pitch_limit;
  7869. int ret;
  7870. if (obj->tiling_mode == I915_TILING_Y) {
  7871. DRM_DEBUG("hardware does not support tiling Y\n");
  7872. return -EINVAL;
  7873. }
  7874. if (mode_cmd->pitches[0] & 63) {
  7875. DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
  7876. mode_cmd->pitches[0]);
  7877. return -EINVAL;
  7878. }
  7879. if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
  7880. pitch_limit = 32*1024;
  7881. } else if (INTEL_INFO(dev)->gen >= 4) {
  7882. if (obj->tiling_mode)
  7883. pitch_limit = 16*1024;
  7884. else
  7885. pitch_limit = 32*1024;
  7886. } else if (INTEL_INFO(dev)->gen >= 3) {
  7887. if (obj->tiling_mode)
  7888. pitch_limit = 8*1024;
  7889. else
  7890. pitch_limit = 16*1024;
  7891. } else
  7892. /* XXX DSPC is limited to 4k tiled */
  7893. pitch_limit = 8*1024;
  7894. if (mode_cmd->pitches[0] > pitch_limit) {
  7895. DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
  7896. obj->tiling_mode ? "tiled" : "linear",
  7897. mode_cmd->pitches[0], pitch_limit);
  7898. return -EINVAL;
  7899. }
  7900. if (obj->tiling_mode != I915_TILING_NONE &&
  7901. mode_cmd->pitches[0] != obj->stride) {
  7902. DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
  7903. mode_cmd->pitches[0], obj->stride);
  7904. return -EINVAL;
  7905. }
  7906. /* Reject formats not supported by any plane early. */
  7907. switch (mode_cmd->pixel_format) {
  7908. case DRM_FORMAT_C8:
  7909. case DRM_FORMAT_RGB565:
  7910. case DRM_FORMAT_XRGB8888:
  7911. case DRM_FORMAT_ARGB8888:
  7912. break;
  7913. case DRM_FORMAT_XRGB1555:
  7914. case DRM_FORMAT_ARGB1555:
  7915. if (INTEL_INFO(dev)->gen > 3) {
  7916. DRM_DEBUG("unsupported pixel format: %s\n",
  7917. drm_get_format_name(mode_cmd->pixel_format));
  7918. return -EINVAL;
  7919. }
  7920. break;
  7921. case DRM_FORMAT_XBGR8888:
  7922. case DRM_FORMAT_ABGR8888:
  7923. case DRM_FORMAT_XRGB2101010:
  7924. case DRM_FORMAT_ARGB2101010:
  7925. case DRM_FORMAT_XBGR2101010:
  7926. case DRM_FORMAT_ABGR2101010:
  7927. if (INTEL_INFO(dev)->gen < 4) {
  7928. DRM_DEBUG("unsupported pixel format: %s\n",
  7929. drm_get_format_name(mode_cmd->pixel_format));
  7930. return -EINVAL;
  7931. }
  7932. break;
  7933. case DRM_FORMAT_YUYV:
  7934. case DRM_FORMAT_UYVY:
  7935. case DRM_FORMAT_YVYU:
  7936. case DRM_FORMAT_VYUY:
  7937. if (INTEL_INFO(dev)->gen < 5) {
  7938. DRM_DEBUG("unsupported pixel format: %s\n",
  7939. drm_get_format_name(mode_cmd->pixel_format));
  7940. return -EINVAL;
  7941. }
  7942. break;
  7943. default:
  7944. DRM_DEBUG("unsupported pixel format: %s\n",
  7945. drm_get_format_name(mode_cmd->pixel_format));
  7946. return -EINVAL;
  7947. }
  7948. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  7949. if (mode_cmd->offsets[0] != 0)
  7950. return -EINVAL;
  7951. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  7952. intel_fb->obj = obj;
  7953. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  7954. if (ret) {
  7955. DRM_ERROR("framebuffer init failed %d\n", ret);
  7956. return ret;
  7957. }
  7958. return 0;
  7959. }
  7960. static struct drm_framebuffer *
  7961. intel_user_framebuffer_create(struct drm_device *dev,
  7962. struct drm_file *filp,
  7963. struct drm_mode_fb_cmd2 *mode_cmd)
  7964. {
  7965. struct drm_i915_gem_object *obj;
  7966. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  7967. mode_cmd->handles[0]));
  7968. if (&obj->base == NULL)
  7969. return ERR_PTR(-ENOENT);
  7970. return intel_framebuffer_create(dev, mode_cmd, obj);
  7971. }
  7972. static const struct drm_mode_config_funcs intel_mode_funcs = {
  7973. .fb_create = intel_user_framebuffer_create,
  7974. .output_poll_changed = intel_fb_output_poll_changed,
  7975. };
  7976. /* Set up chip specific display functions */
  7977. static void intel_init_display(struct drm_device *dev)
  7978. {
  7979. struct drm_i915_private *dev_priv = dev->dev_private;
  7980. if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
  7981. dev_priv->display.find_dpll = g4x_find_best_dpll;
  7982. else if (IS_VALLEYVIEW(dev))
  7983. dev_priv->display.find_dpll = vlv_find_best_dpll;
  7984. else if (IS_PINEVIEW(dev))
  7985. dev_priv->display.find_dpll = pnv_find_best_dpll;
  7986. else
  7987. dev_priv->display.find_dpll = i9xx_find_best_dpll;
  7988. if (HAS_DDI(dev)) {
  7989. dev_priv->display.get_pipe_config = haswell_get_pipe_config;
  7990. dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  7991. dev_priv->display.crtc_enable = haswell_crtc_enable;
  7992. dev_priv->display.crtc_disable = haswell_crtc_disable;
  7993. dev_priv->display.off = haswell_crtc_off;
  7994. dev_priv->display.update_plane = ironlake_update_plane;
  7995. } else if (HAS_PCH_SPLIT(dev)) {
  7996. dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
  7997. dev_priv->display.get_clock = ironlake_crtc_clock_get;
  7998. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  7999. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  8000. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  8001. dev_priv->display.off = ironlake_crtc_off;
  8002. dev_priv->display.update_plane = ironlake_update_plane;
  8003. } else if (IS_VALLEYVIEW(dev)) {
  8004. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8005. dev_priv->display.get_clock = i9xx_crtc_clock_get;
  8006. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8007. dev_priv->display.crtc_enable = valleyview_crtc_enable;
  8008. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8009. dev_priv->display.off = i9xx_crtc_off;
  8010. dev_priv->display.update_plane = i9xx_update_plane;
  8011. } else {
  8012. dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
  8013. dev_priv->display.get_clock = i9xx_crtc_clock_get;
  8014. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  8015. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  8016. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  8017. dev_priv->display.off = i9xx_crtc_off;
  8018. dev_priv->display.update_plane = i9xx_update_plane;
  8019. }
  8020. /* Returns the core display clock speed */
  8021. if (IS_VALLEYVIEW(dev))
  8022. dev_priv->display.get_display_clock_speed =
  8023. valleyview_get_display_clock_speed;
  8024. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  8025. dev_priv->display.get_display_clock_speed =
  8026. i945_get_display_clock_speed;
  8027. else if (IS_I915G(dev))
  8028. dev_priv->display.get_display_clock_speed =
  8029. i915_get_display_clock_speed;
  8030. else if (IS_I945GM(dev) || IS_845G(dev))
  8031. dev_priv->display.get_display_clock_speed =
  8032. i9xx_misc_get_display_clock_speed;
  8033. else if (IS_PINEVIEW(dev))
  8034. dev_priv->display.get_display_clock_speed =
  8035. pnv_get_display_clock_speed;
  8036. else if (IS_I915GM(dev))
  8037. dev_priv->display.get_display_clock_speed =
  8038. i915gm_get_display_clock_speed;
  8039. else if (IS_I865G(dev))
  8040. dev_priv->display.get_display_clock_speed =
  8041. i865_get_display_clock_speed;
  8042. else if (IS_I85X(dev))
  8043. dev_priv->display.get_display_clock_speed =
  8044. i855_get_display_clock_speed;
  8045. else /* 852, 830 */
  8046. dev_priv->display.get_display_clock_speed =
  8047. i830_get_display_clock_speed;
  8048. if (HAS_PCH_SPLIT(dev)) {
  8049. if (IS_GEN5(dev)) {
  8050. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  8051. dev_priv->display.write_eld = ironlake_write_eld;
  8052. } else if (IS_GEN6(dev)) {
  8053. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  8054. dev_priv->display.write_eld = ironlake_write_eld;
  8055. } else if (IS_IVYBRIDGE(dev)) {
  8056. /* FIXME: detect B0+ stepping and use auto training */
  8057. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  8058. dev_priv->display.write_eld = ironlake_write_eld;
  8059. dev_priv->display.modeset_global_resources =
  8060. ivb_modeset_global_resources;
  8061. } else if (IS_HASWELL(dev)) {
  8062. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  8063. dev_priv->display.write_eld = haswell_write_eld;
  8064. dev_priv->display.modeset_global_resources =
  8065. haswell_modeset_global_resources;
  8066. }
  8067. } else if (IS_G4X(dev)) {
  8068. dev_priv->display.write_eld = g4x_write_eld;
  8069. }
  8070. /* Default just returns -ENODEV to indicate unsupported */
  8071. dev_priv->display.queue_flip = intel_default_queue_flip;
  8072. switch (INTEL_INFO(dev)->gen) {
  8073. case 2:
  8074. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  8075. break;
  8076. case 3:
  8077. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  8078. break;
  8079. case 4:
  8080. case 5:
  8081. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  8082. break;
  8083. case 6:
  8084. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  8085. break;
  8086. case 7:
  8087. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  8088. break;
  8089. }
  8090. }
  8091. /*
  8092. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  8093. * resume, or other times. This quirk makes sure that's the case for
  8094. * affected systems.
  8095. */
  8096. static void quirk_pipea_force(struct drm_device *dev)
  8097. {
  8098. struct drm_i915_private *dev_priv = dev->dev_private;
  8099. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  8100. DRM_INFO("applying pipe a force quirk\n");
  8101. }
  8102. /*
  8103. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  8104. */
  8105. static void quirk_ssc_force_disable(struct drm_device *dev)
  8106. {
  8107. struct drm_i915_private *dev_priv = dev->dev_private;
  8108. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  8109. DRM_INFO("applying lvds SSC disable quirk\n");
  8110. }
  8111. /*
  8112. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  8113. * brightness value
  8114. */
  8115. static void quirk_invert_brightness(struct drm_device *dev)
  8116. {
  8117. struct drm_i915_private *dev_priv = dev->dev_private;
  8118. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  8119. DRM_INFO("applying inverted panel brightness quirk\n");
  8120. }
  8121. /*
  8122. * Some machines (Dell XPS13) suffer broken backlight controls if
  8123. * BLM_PCH_PWM_ENABLE is set.
  8124. */
  8125. static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
  8126. {
  8127. struct drm_i915_private *dev_priv = dev->dev_private;
  8128. dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
  8129. DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
  8130. }
  8131. struct intel_quirk {
  8132. int device;
  8133. int subsystem_vendor;
  8134. int subsystem_device;
  8135. void (*hook)(struct drm_device *dev);
  8136. };
  8137. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  8138. struct intel_dmi_quirk {
  8139. void (*hook)(struct drm_device *dev);
  8140. const struct dmi_system_id (*dmi_id_list)[];
  8141. };
  8142. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  8143. {
  8144. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  8145. return 1;
  8146. }
  8147. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  8148. {
  8149. .dmi_id_list = &(const struct dmi_system_id[]) {
  8150. {
  8151. .callback = intel_dmi_reverse_brightness,
  8152. .ident = "NCR Corporation",
  8153. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  8154. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  8155. },
  8156. },
  8157. { } /* terminating entry */
  8158. },
  8159. .hook = quirk_invert_brightness,
  8160. },
  8161. };
  8162. static struct intel_quirk intel_quirks[] = {
  8163. /* HP Mini needs pipe A force quirk (LP: #322104) */
  8164. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  8165. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  8166. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  8167. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  8168. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  8169. /* 830/845 need to leave pipe A & dpll A up */
  8170. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8171. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  8172. /* Lenovo U160 cannot use SSC on LVDS */
  8173. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  8174. /* Sony Vaio Y cannot use SSC on LVDS */
  8175. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  8176. /* Acer Aspire 5734Z must invert backlight brightness */
  8177. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  8178. /* Acer/eMachines G725 */
  8179. { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  8180. /* Acer/eMachines e725 */
  8181. { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  8182. /* Acer/Packard Bell NCL20 */
  8183. { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  8184. /* Acer Aspire 4736Z */
  8185. { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
  8186. /* Dell XPS13 HD Sandy Bridge */
  8187. { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
  8188. /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
  8189. { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
  8190. };
  8191. static void intel_init_quirks(struct drm_device *dev)
  8192. {
  8193. struct pci_dev *d = dev->pdev;
  8194. int i;
  8195. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  8196. struct intel_quirk *q = &intel_quirks[i];
  8197. if (d->device == q->device &&
  8198. (d->subsystem_vendor == q->subsystem_vendor ||
  8199. q->subsystem_vendor == PCI_ANY_ID) &&
  8200. (d->subsystem_device == q->subsystem_device ||
  8201. q->subsystem_device == PCI_ANY_ID))
  8202. q->hook(dev);
  8203. }
  8204. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  8205. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  8206. intel_dmi_quirks[i].hook(dev);
  8207. }
  8208. }
  8209. /* Disable the VGA plane that we never use */
  8210. static void i915_disable_vga(struct drm_device *dev)
  8211. {
  8212. struct drm_i915_private *dev_priv = dev->dev_private;
  8213. u8 sr1;
  8214. u32 vga_reg = i915_vgacntrl_reg(dev);
  8215. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  8216. outb(SR01, VGA_SR_INDEX);
  8217. sr1 = inb(VGA_SR_DATA);
  8218. outb(sr1 | 1<<5, VGA_SR_DATA);
  8219. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  8220. udelay(300);
  8221. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  8222. POSTING_READ(vga_reg);
  8223. }
  8224. void intel_modeset_init_hw(struct drm_device *dev)
  8225. {
  8226. intel_init_power_well(dev);
  8227. intel_prepare_ddi(dev);
  8228. intel_init_clock_gating(dev);
  8229. mutex_lock(&dev->struct_mutex);
  8230. intel_enable_gt_powersave(dev);
  8231. mutex_unlock(&dev->struct_mutex);
  8232. }
  8233. void intel_modeset_suspend_hw(struct drm_device *dev)
  8234. {
  8235. intel_suspend_hw(dev);
  8236. }
  8237. void intel_modeset_init(struct drm_device *dev)
  8238. {
  8239. struct drm_i915_private *dev_priv = dev->dev_private;
  8240. int i, j, ret;
  8241. drm_mode_config_init(dev);
  8242. dev->mode_config.min_width = 0;
  8243. dev->mode_config.min_height = 0;
  8244. dev->mode_config.preferred_depth = 24;
  8245. dev->mode_config.prefer_shadow = 1;
  8246. dev->mode_config.funcs = &intel_mode_funcs;
  8247. intel_init_quirks(dev);
  8248. intel_init_pm(dev);
  8249. if (INTEL_INFO(dev)->num_pipes == 0)
  8250. return;
  8251. intel_init_display(dev);
  8252. if (IS_GEN2(dev)) {
  8253. dev->mode_config.max_width = 2048;
  8254. dev->mode_config.max_height = 2048;
  8255. } else if (IS_GEN3(dev)) {
  8256. dev->mode_config.max_width = 4096;
  8257. dev->mode_config.max_height = 4096;
  8258. } else {
  8259. dev->mode_config.max_width = 8192;
  8260. dev->mode_config.max_height = 8192;
  8261. }
  8262. dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  8263. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  8264. INTEL_INFO(dev)->num_pipes,
  8265. INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
  8266. for_each_pipe(i) {
  8267. intel_crtc_init(dev, i);
  8268. for (j = 0; j < dev_priv->num_plane; j++) {
  8269. ret = intel_plane_init(dev, i, j);
  8270. if (ret)
  8271. DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
  8272. pipe_name(i), sprite_name(i, j), ret);
  8273. }
  8274. }
  8275. intel_cpu_pll_init(dev);
  8276. intel_shared_dpll_init(dev);
  8277. /* Just disable it once at startup */
  8278. i915_disable_vga(dev);
  8279. intel_setup_outputs(dev);
  8280. /* Just in case the BIOS is doing something questionable. */
  8281. intel_disable_fbc(dev);
  8282. }
  8283. static void
  8284. intel_connector_break_all_links(struct intel_connector *connector)
  8285. {
  8286. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8287. connector->base.encoder = NULL;
  8288. connector->encoder->connectors_active = false;
  8289. connector->encoder->base.crtc = NULL;
  8290. }
  8291. static void intel_enable_pipe_a(struct drm_device *dev)
  8292. {
  8293. struct intel_connector *connector;
  8294. struct drm_connector *crt = NULL;
  8295. struct intel_load_detect_pipe load_detect_temp;
  8296. /* We can't just switch on the pipe A, we need to set things up with a
  8297. * proper mode and output configuration. As a gross hack, enable pipe A
  8298. * by enabling the load detect pipe once. */
  8299. list_for_each_entry(connector,
  8300. &dev->mode_config.connector_list,
  8301. base.head) {
  8302. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  8303. crt = &connector->base;
  8304. break;
  8305. }
  8306. }
  8307. if (!crt)
  8308. return;
  8309. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  8310. intel_release_load_detect_pipe(crt, &load_detect_temp);
  8311. }
  8312. static bool
  8313. intel_check_plane_mapping(struct intel_crtc *crtc)
  8314. {
  8315. struct drm_device *dev = crtc->base.dev;
  8316. struct drm_i915_private *dev_priv = dev->dev_private;
  8317. u32 reg, val;
  8318. if (INTEL_INFO(dev)->num_pipes == 1)
  8319. return true;
  8320. reg = DSPCNTR(!crtc->plane);
  8321. val = I915_READ(reg);
  8322. if ((val & DISPLAY_PLANE_ENABLE) &&
  8323. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  8324. return false;
  8325. return true;
  8326. }
  8327. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  8328. {
  8329. struct drm_device *dev = crtc->base.dev;
  8330. struct drm_i915_private *dev_priv = dev->dev_private;
  8331. u32 reg;
  8332. /* Clear any frame start delays used for debugging left by the BIOS */
  8333. reg = PIPECONF(crtc->config.cpu_transcoder);
  8334. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  8335. /* We need to sanitize the plane -> pipe mapping first because this will
  8336. * disable the crtc (and hence change the state) if it is wrong. Note
  8337. * that gen4+ has a fixed plane -> pipe mapping. */
  8338. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  8339. struct intel_connector *connector;
  8340. bool plane;
  8341. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  8342. crtc->base.base.id);
  8343. /* Pipe has the wrong plane attached and the plane is active.
  8344. * Temporarily change the plane mapping and disable everything
  8345. * ... */
  8346. plane = crtc->plane;
  8347. crtc->plane = !plane;
  8348. dev_priv->display.crtc_disable(&crtc->base);
  8349. crtc->plane = plane;
  8350. /* ... and break all links. */
  8351. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8352. base.head) {
  8353. if (connector->encoder->base.crtc != &crtc->base)
  8354. continue;
  8355. intel_connector_break_all_links(connector);
  8356. }
  8357. WARN_ON(crtc->active);
  8358. crtc->base.enabled = false;
  8359. }
  8360. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  8361. crtc->pipe == PIPE_A && !crtc->active) {
  8362. /* BIOS forgot to enable pipe A, this mostly happens after
  8363. * resume. Force-enable the pipe to fix this, the update_dpms
  8364. * call below we restore the pipe to the right state, but leave
  8365. * the required bits on. */
  8366. intel_enable_pipe_a(dev);
  8367. }
  8368. /* Adjust the state of the output pipe according to whether we
  8369. * have active connectors/encoders. */
  8370. intel_crtc_update_dpms(&crtc->base);
  8371. if (crtc->active != crtc->base.enabled) {
  8372. struct intel_encoder *encoder;
  8373. /* This can happen either due to bugs in the get_hw_state
  8374. * functions or because the pipe is force-enabled due to the
  8375. * pipe A quirk. */
  8376. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  8377. crtc->base.base.id,
  8378. crtc->base.enabled ? "enabled" : "disabled",
  8379. crtc->active ? "enabled" : "disabled");
  8380. crtc->base.enabled = crtc->active;
  8381. /* Because we only establish the connector -> encoder ->
  8382. * crtc links if something is active, this means the
  8383. * crtc is now deactivated. Break the links. connector
  8384. * -> encoder links are only establish when things are
  8385. * actually up, hence no need to break them. */
  8386. WARN_ON(crtc->active);
  8387. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  8388. WARN_ON(encoder->connectors_active);
  8389. encoder->base.crtc = NULL;
  8390. }
  8391. }
  8392. }
  8393. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  8394. {
  8395. struct intel_connector *connector;
  8396. struct drm_device *dev = encoder->base.dev;
  8397. /* We need to check both for a crtc link (meaning that the
  8398. * encoder is active and trying to read from a pipe) and the
  8399. * pipe itself being active. */
  8400. bool has_active_crtc = encoder->base.crtc &&
  8401. to_intel_crtc(encoder->base.crtc)->active;
  8402. if (encoder->connectors_active && !has_active_crtc) {
  8403. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  8404. encoder->base.base.id,
  8405. drm_get_encoder_name(&encoder->base));
  8406. /* Connector is active, but has no active pipe. This is
  8407. * fallout from our resume register restoring. Disable
  8408. * the encoder manually again. */
  8409. if (encoder->base.crtc) {
  8410. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  8411. encoder->base.base.id,
  8412. drm_get_encoder_name(&encoder->base));
  8413. encoder->disable(encoder);
  8414. }
  8415. /* Inconsistent output/port/pipe state happens presumably due to
  8416. * a bug in one of the get_hw_state functions. Or someplace else
  8417. * in our code, like the register restore mess on resume. Clamp
  8418. * things to off as a safer default. */
  8419. list_for_each_entry(connector,
  8420. &dev->mode_config.connector_list,
  8421. base.head) {
  8422. if (connector->encoder != encoder)
  8423. continue;
  8424. intel_connector_break_all_links(connector);
  8425. }
  8426. }
  8427. /* Enabled encoders without active connectors will be fixed in
  8428. * the crtc fixup. */
  8429. }
  8430. void i915_redisable_vga(struct drm_device *dev)
  8431. {
  8432. struct drm_i915_private *dev_priv = dev->dev_private;
  8433. u32 vga_reg = i915_vgacntrl_reg(dev);
  8434. if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
  8435. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  8436. i915_disable_vga(dev);
  8437. }
  8438. }
  8439. static void intel_modeset_readout_hw_state(struct drm_device *dev)
  8440. {
  8441. struct drm_i915_private *dev_priv = dev->dev_private;
  8442. enum pipe pipe;
  8443. struct intel_crtc *crtc;
  8444. struct intel_encoder *encoder;
  8445. struct intel_connector *connector;
  8446. int i;
  8447. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8448. base.head) {
  8449. memset(&crtc->config, 0, sizeof(crtc->config));
  8450. crtc->active = dev_priv->display.get_pipe_config(crtc,
  8451. &crtc->config);
  8452. crtc->base.enabled = crtc->active;
  8453. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  8454. crtc->base.base.id,
  8455. crtc->active ? "enabled" : "disabled");
  8456. }
  8457. /* FIXME: Smash this into the new shared dpll infrastructure. */
  8458. if (HAS_DDI(dev))
  8459. intel_ddi_setup_hw_pll_state(dev);
  8460. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8461. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8462. pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
  8463. pll->active = 0;
  8464. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8465. base.head) {
  8466. if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
  8467. pll->active++;
  8468. }
  8469. pll->refcount = pll->active;
  8470. DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
  8471. pll->name, pll->refcount, pll->on);
  8472. }
  8473. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8474. base.head) {
  8475. pipe = 0;
  8476. if (encoder->get_hw_state(encoder, &pipe)) {
  8477. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8478. encoder->base.crtc = &crtc->base;
  8479. if (encoder->get_config)
  8480. encoder->get_config(encoder, &crtc->config);
  8481. } else {
  8482. encoder->base.crtc = NULL;
  8483. }
  8484. encoder->connectors_active = false;
  8485. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  8486. encoder->base.base.id,
  8487. drm_get_encoder_name(&encoder->base),
  8488. encoder->base.crtc ? "enabled" : "disabled",
  8489. pipe);
  8490. }
  8491. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8492. base.head) {
  8493. if (!crtc->active)
  8494. continue;
  8495. if (dev_priv->display.get_clock)
  8496. dev_priv->display.get_clock(crtc,
  8497. &crtc->config);
  8498. }
  8499. list_for_each_entry(connector, &dev->mode_config.connector_list,
  8500. base.head) {
  8501. if (connector->get_hw_state(connector)) {
  8502. connector->base.dpms = DRM_MODE_DPMS_ON;
  8503. connector->encoder->connectors_active = true;
  8504. connector->base.encoder = &connector->encoder->base;
  8505. } else {
  8506. connector->base.dpms = DRM_MODE_DPMS_OFF;
  8507. connector->base.encoder = NULL;
  8508. }
  8509. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  8510. connector->base.base.id,
  8511. drm_get_connector_name(&connector->base),
  8512. connector->base.encoder ? "enabled" : "disabled");
  8513. }
  8514. }
  8515. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  8516. * and i915 state tracking structures. */
  8517. void intel_modeset_setup_hw_state(struct drm_device *dev,
  8518. bool force_restore)
  8519. {
  8520. struct drm_i915_private *dev_priv = dev->dev_private;
  8521. enum pipe pipe;
  8522. struct drm_plane *plane;
  8523. struct intel_crtc *crtc;
  8524. struct intel_encoder *encoder;
  8525. int i;
  8526. intel_modeset_readout_hw_state(dev);
  8527. /*
  8528. * Now that we have the config, copy it to each CRTC struct
  8529. * Note that this could go away if we move to using crtc_config
  8530. * checking everywhere.
  8531. */
  8532. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  8533. base.head) {
  8534. if (crtc->active && i915_fastboot) {
  8535. intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
  8536. DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
  8537. crtc->base.base.id);
  8538. drm_mode_debug_printmodeline(&crtc->base.mode);
  8539. }
  8540. }
  8541. /* HW state is read out, now we need to sanitize this mess. */
  8542. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  8543. base.head) {
  8544. intel_sanitize_encoder(encoder);
  8545. }
  8546. for_each_pipe(pipe) {
  8547. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  8548. intel_sanitize_crtc(crtc);
  8549. intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
  8550. }
  8551. for (i = 0; i < dev_priv->num_shared_dpll; i++) {
  8552. struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
  8553. if (!pll->on || pll->active)
  8554. continue;
  8555. DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
  8556. pll->disable(dev_priv, pll);
  8557. pll->on = false;
  8558. }
  8559. if (force_restore) {
  8560. /*
  8561. * We need to use raw interfaces for restoring state to avoid
  8562. * checking (bogus) intermediate states.
  8563. */
  8564. for_each_pipe(pipe) {
  8565. struct drm_crtc *crtc =
  8566. dev_priv->pipe_to_crtc_mapping[pipe];
  8567. __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
  8568. crtc->fb);
  8569. }
  8570. list_for_each_entry(plane, &dev->mode_config.plane_list, head)
  8571. intel_plane_restore(plane);
  8572. i915_redisable_vga(dev);
  8573. } else {
  8574. intel_modeset_update_staged_output_state(dev);
  8575. }
  8576. intel_modeset_check_state(dev);
  8577. drm_mode_config_reset(dev);
  8578. }
  8579. void intel_modeset_gem_init(struct drm_device *dev)
  8580. {
  8581. intel_modeset_init_hw(dev);
  8582. intel_setup_overlay(dev);
  8583. intel_modeset_setup_hw_state(dev, false);
  8584. }
  8585. void intel_modeset_cleanup(struct drm_device *dev)
  8586. {
  8587. struct drm_i915_private *dev_priv = dev->dev_private;
  8588. struct drm_crtc *crtc;
  8589. struct intel_crtc *intel_crtc;
  8590. /*
  8591. * Interrupts and polling as the first thing to avoid creating havoc.
  8592. * Too much stuff here (turning of rps, connectors, ...) would
  8593. * experience fancy races otherwise.
  8594. */
  8595. drm_irq_uninstall(dev);
  8596. cancel_work_sync(&dev_priv->hotplug_work);
  8597. /*
  8598. * Due to the hpd irq storm handling the hotplug work can re-arm the
  8599. * poll handlers. Hence disable polling after hpd handling is shut down.
  8600. */
  8601. drm_kms_helper_poll_fini(dev);
  8602. mutex_lock(&dev->struct_mutex);
  8603. intel_unregister_dsm_handler();
  8604. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  8605. /* Skip inactive CRTCs */
  8606. if (!crtc->fb)
  8607. continue;
  8608. intel_crtc = to_intel_crtc(crtc);
  8609. intel_increase_pllclock(crtc);
  8610. }
  8611. intel_disable_fbc(dev);
  8612. intel_disable_gt_powersave(dev);
  8613. ironlake_teardown_rc6(dev);
  8614. mutex_unlock(&dev->struct_mutex);
  8615. /* flush any delayed tasks or pending work */
  8616. flush_scheduled_work();
  8617. /* destroy backlight, if any, before the connectors */
  8618. intel_panel_destroy_backlight(dev);
  8619. drm_mode_config_cleanup(dev);
  8620. intel_cleanup_overlay(dev);
  8621. }
  8622. /*
  8623. * Return which encoder is currently attached for connector.
  8624. */
  8625. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  8626. {
  8627. return &intel_attached_encoder(connector)->base;
  8628. }
  8629. void intel_connector_attach_encoder(struct intel_connector *connector,
  8630. struct intel_encoder *encoder)
  8631. {
  8632. connector->encoder = encoder;
  8633. drm_mode_connector_attach_encoder(&connector->base,
  8634. &encoder->base);
  8635. }
  8636. /*
  8637. * set vga decode state - true == enable VGA decode
  8638. */
  8639. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  8640. {
  8641. struct drm_i915_private *dev_priv = dev->dev_private;
  8642. u16 gmch_ctrl;
  8643. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  8644. if (state)
  8645. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  8646. else
  8647. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  8648. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  8649. return 0;
  8650. }
  8651. struct intel_display_error_state {
  8652. u32 power_well_driver;
  8653. struct intel_cursor_error_state {
  8654. u32 control;
  8655. u32 position;
  8656. u32 base;
  8657. u32 size;
  8658. } cursor[I915_MAX_PIPES];
  8659. struct intel_pipe_error_state {
  8660. enum transcoder cpu_transcoder;
  8661. u32 conf;
  8662. u32 source;
  8663. u32 htotal;
  8664. u32 hblank;
  8665. u32 hsync;
  8666. u32 vtotal;
  8667. u32 vblank;
  8668. u32 vsync;
  8669. } pipe[I915_MAX_PIPES];
  8670. struct intel_plane_error_state {
  8671. u32 control;
  8672. u32 stride;
  8673. u32 size;
  8674. u32 pos;
  8675. u32 addr;
  8676. u32 surface;
  8677. u32 tile_offset;
  8678. } plane[I915_MAX_PIPES];
  8679. };
  8680. struct intel_display_error_state *
  8681. intel_display_capture_error_state(struct drm_device *dev)
  8682. {
  8683. drm_i915_private_t *dev_priv = dev->dev_private;
  8684. struct intel_display_error_state *error;
  8685. enum transcoder cpu_transcoder;
  8686. int i;
  8687. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  8688. if (error == NULL)
  8689. return NULL;
  8690. if (HAS_POWER_WELL(dev))
  8691. error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
  8692. for_each_pipe(i) {
  8693. cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
  8694. error->pipe[i].cpu_transcoder = cpu_transcoder;
  8695. if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
  8696. error->cursor[i].control = I915_READ(CURCNTR(i));
  8697. error->cursor[i].position = I915_READ(CURPOS(i));
  8698. error->cursor[i].base = I915_READ(CURBASE(i));
  8699. } else {
  8700. error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
  8701. error->cursor[i].position = I915_READ(CURPOS_IVB(i));
  8702. error->cursor[i].base = I915_READ(CURBASE_IVB(i));
  8703. }
  8704. error->plane[i].control = I915_READ(DSPCNTR(i));
  8705. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  8706. if (INTEL_INFO(dev)->gen <= 3) {
  8707. error->plane[i].size = I915_READ(DSPSIZE(i));
  8708. error->plane[i].pos = I915_READ(DSPPOS(i));
  8709. }
  8710. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  8711. error->plane[i].addr = I915_READ(DSPADDR(i));
  8712. if (INTEL_INFO(dev)->gen >= 4) {
  8713. error->plane[i].surface = I915_READ(DSPSURF(i));
  8714. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  8715. }
  8716. error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  8717. error->pipe[i].source = I915_READ(PIPESRC(i));
  8718. error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  8719. error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  8720. error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  8721. error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  8722. error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  8723. error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  8724. }
  8725. /* In the code above we read the registers without checking if the power
  8726. * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
  8727. * prevent the next I915_WRITE from detecting it and printing an error
  8728. * message. */
  8729. intel_uncore_clear_errors(dev);
  8730. return error;
  8731. }
  8732. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  8733. void
  8734. intel_display_print_error_state(struct drm_i915_error_state_buf *m,
  8735. struct drm_device *dev,
  8736. struct intel_display_error_state *error)
  8737. {
  8738. int i;
  8739. err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
  8740. if (HAS_POWER_WELL(dev))
  8741. err_printf(m, "PWR_WELL_CTL2: %08x\n",
  8742. error->power_well_driver);
  8743. for_each_pipe(i) {
  8744. err_printf(m, "Pipe [%d]:\n", i);
  8745. err_printf(m, " CPU transcoder: %c\n",
  8746. transcoder_name(error->pipe[i].cpu_transcoder));
  8747. err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  8748. err_printf(m, " SRC: %08x\n", error->pipe[i].source);
  8749. err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  8750. err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  8751. err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  8752. err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  8753. err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  8754. err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  8755. err_printf(m, "Plane [%d]:\n", i);
  8756. err_printf(m, " CNTR: %08x\n", error->plane[i].control);
  8757. err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  8758. if (INTEL_INFO(dev)->gen <= 3) {
  8759. err_printf(m, " SIZE: %08x\n", error->plane[i].size);
  8760. err_printf(m, " POS: %08x\n", error->plane[i].pos);
  8761. }
  8762. if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
  8763. err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  8764. if (INTEL_INFO(dev)->gen >= 4) {
  8765. err_printf(m, " SURF: %08x\n", error->plane[i].surface);
  8766. err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  8767. }
  8768. err_printf(m, "Cursor [%d]:\n", i);
  8769. err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  8770. err_printf(m, " POS: %08x\n", error->cursor[i].position);
  8771. err_printf(m, " BASE: %08x\n", error->cursor[i].base);
  8772. }
  8773. }