uda134x.c 17 KB

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  1. /*
  2. * uda134x.c -- UDA134X ALSA SoC Codec driver
  3. *
  4. * Modifications by Christian Pellegrin <chripell@evolware.org>
  5. *
  6. * Copyright 2007 Dension Audio Systems Ltd.
  7. * Author: Zoltan Devai
  8. *
  9. * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/delay.h>
  17. #include <linux/slab.h>
  18. #include <sound/pcm.h>
  19. #include <sound/pcm_params.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/uda134x.h>
  23. #include <sound/l3.h>
  24. #include "uda134x.h"
  25. #define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
  26. #define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
  27. SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)
  28. struct uda134x_priv {
  29. int sysclk;
  30. int dai_fmt;
  31. struct snd_pcm_substream *master_substream;
  32. struct snd_pcm_substream *slave_substream;
  33. };
  34. /* In-data addresses are hard-coded into the reg-cache values */
  35. static const char uda134x_reg[UDA134X_REGS_NUM] = {
  36. /* Extended address registers */
  37. 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  38. /* Status, data regs */
  39. 0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
  40. };
  41. /*
  42. * The codec has no support for reading its registers except for peak level...
  43. */
  44. static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
  45. unsigned int reg)
  46. {
  47. u8 *cache = codec->reg_cache;
  48. if (reg >= UDA134X_REGS_NUM)
  49. return -1;
  50. return cache[reg];
  51. }
  52. /*
  53. * Write the register cache
  54. */
  55. static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
  56. u8 reg, unsigned int value)
  57. {
  58. u8 *cache = codec->reg_cache;
  59. if (reg >= UDA134X_REGS_NUM)
  60. return;
  61. cache[reg] = value;
  62. }
  63. /*
  64. * Write to the uda134x registers
  65. *
  66. */
  67. static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
  68. unsigned int value)
  69. {
  70. int ret;
  71. u8 addr;
  72. u8 data = value;
  73. struct uda134x_platform_data *pd = codec->control_data;
  74. pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
  75. if (reg >= UDA134X_REGS_NUM) {
  76. printk(KERN_ERR "%s unknown register: reg: %u",
  77. __func__, reg);
  78. return -EINVAL;
  79. }
  80. uda134x_write_reg_cache(codec, reg, value);
  81. switch (reg) {
  82. case UDA134X_STATUS0:
  83. case UDA134X_STATUS1:
  84. addr = UDA134X_STATUS_ADDR;
  85. break;
  86. case UDA134X_DATA000:
  87. case UDA134X_DATA001:
  88. case UDA134X_DATA010:
  89. case UDA134X_DATA011:
  90. addr = UDA134X_DATA0_ADDR;
  91. break;
  92. case UDA134X_DATA1:
  93. addr = UDA134X_DATA1_ADDR;
  94. break;
  95. default:
  96. /* It's an extended address register */
  97. addr = (reg | UDA134X_EXTADDR_PREFIX);
  98. ret = l3_write(&pd->l3,
  99. UDA134X_DATA0_ADDR, &addr, 1);
  100. if (ret != 1)
  101. return -EIO;
  102. addr = UDA134X_DATA0_ADDR;
  103. data = (value | UDA134X_EXTDATA_PREFIX);
  104. break;
  105. }
  106. ret = l3_write(&pd->l3,
  107. addr, &data, 1);
  108. if (ret != 1)
  109. return -EIO;
  110. return 0;
  111. }
  112. static inline void uda134x_reset(struct snd_soc_codec *codec)
  113. {
  114. u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
  115. uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
  116. msleep(1);
  117. uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
  118. }
  119. static int uda134x_mute(struct snd_soc_dai *dai, int mute)
  120. {
  121. struct snd_soc_codec *codec = dai->codec;
  122. u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
  123. pr_debug("%s mute: %d\n", __func__, mute);
  124. if (mute)
  125. mute_reg |= (1<<2);
  126. else
  127. mute_reg &= ~(1<<2);
  128. uda134x_write(codec, UDA134X_DATA010, mute_reg);
  129. return 0;
  130. }
  131. static int uda134x_startup(struct snd_pcm_substream *substream,
  132. struct snd_soc_dai *dai)
  133. {
  134. struct snd_soc_codec *codec = dai->codec;
  135. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  136. struct snd_pcm_runtime *master_runtime;
  137. if (uda134x->master_substream) {
  138. master_runtime = uda134x->master_substream->runtime;
  139. pr_debug("%s constraining to %d bits at %d\n", __func__,
  140. master_runtime->sample_bits,
  141. master_runtime->rate);
  142. snd_pcm_hw_constraint_minmax(substream->runtime,
  143. SNDRV_PCM_HW_PARAM_RATE,
  144. master_runtime->rate,
  145. master_runtime->rate);
  146. snd_pcm_hw_constraint_minmax(substream->runtime,
  147. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  148. master_runtime->sample_bits,
  149. master_runtime->sample_bits);
  150. uda134x->slave_substream = substream;
  151. } else
  152. uda134x->master_substream = substream;
  153. return 0;
  154. }
  155. static void uda134x_shutdown(struct snd_pcm_substream *substream,
  156. struct snd_soc_dai *dai)
  157. {
  158. struct snd_soc_codec *codec = dai->codec;
  159. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  160. if (uda134x->master_substream == substream)
  161. uda134x->master_substream = uda134x->slave_substream;
  162. uda134x->slave_substream = NULL;
  163. }
  164. static int uda134x_hw_params(struct snd_pcm_substream *substream,
  165. struct snd_pcm_hw_params *params,
  166. struct snd_soc_dai *dai)
  167. {
  168. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  169. struct snd_soc_codec *codec = rtd->codec;
  170. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  171. u8 hw_params;
  172. if (substream == uda134x->slave_substream) {
  173. pr_debug("%s ignoring hw_params for slave substream\n",
  174. __func__);
  175. return 0;
  176. }
  177. hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
  178. hw_params &= STATUS0_SYSCLK_MASK;
  179. hw_params &= STATUS0_DAIFMT_MASK;
  180. pr_debug("%s sysclk: %d, rate:%d\n", __func__,
  181. uda134x->sysclk, params_rate(params));
  182. /* set SYSCLK / fs ratio */
  183. switch (uda134x->sysclk / params_rate(params)) {
  184. case 512:
  185. break;
  186. case 384:
  187. hw_params |= (1<<4);
  188. break;
  189. case 256:
  190. hw_params |= (1<<5);
  191. break;
  192. default:
  193. printk(KERN_ERR "%s unsupported fs\n", __func__);
  194. return -EINVAL;
  195. }
  196. pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
  197. uda134x->dai_fmt, params_format(params));
  198. /* set DAI format and word length */
  199. switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  200. case SND_SOC_DAIFMT_I2S:
  201. break;
  202. case SND_SOC_DAIFMT_RIGHT_J:
  203. switch (params_format(params)) {
  204. case SNDRV_PCM_FORMAT_S16_LE:
  205. hw_params |= (1<<1);
  206. break;
  207. case SNDRV_PCM_FORMAT_S18_3LE:
  208. hw_params |= (1<<2);
  209. break;
  210. case SNDRV_PCM_FORMAT_S20_3LE:
  211. hw_params |= ((1<<2) | (1<<1));
  212. break;
  213. default:
  214. printk(KERN_ERR "%s unsupported format (right)\n",
  215. __func__);
  216. return -EINVAL;
  217. }
  218. break;
  219. case SND_SOC_DAIFMT_LEFT_J:
  220. hw_params |= (1<<3);
  221. break;
  222. default:
  223. printk(KERN_ERR "%s unsupported format\n", __func__);
  224. return -EINVAL;
  225. }
  226. uda134x_write(codec, UDA134X_STATUS0, hw_params);
  227. return 0;
  228. }
  229. static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  230. int clk_id, unsigned int freq, int dir)
  231. {
  232. struct snd_soc_codec *codec = codec_dai->codec;
  233. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  234. pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
  235. clk_id, freq, dir);
  236. /* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
  237. because the codec is slave. Of course limitations of the clock
  238. master (the IIS controller) apply.
  239. We'll error out on set_hw_params if it's not OK */
  240. if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
  241. uda134x->sysclk = freq;
  242. return 0;
  243. }
  244. printk(KERN_ERR "%s unsupported sysclk\n", __func__);
  245. return -EINVAL;
  246. }
  247. static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
  248. unsigned int fmt)
  249. {
  250. struct snd_soc_codec *codec = codec_dai->codec;
  251. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  252. pr_debug("%s fmt: %08X\n", __func__, fmt);
  253. /* codec supports only full slave mode */
  254. if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
  255. printk(KERN_ERR "%s unsupported slave mode\n", __func__);
  256. return -EINVAL;
  257. }
  258. /* no support for clock inversion */
  259. if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
  260. printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
  261. return -EINVAL;
  262. }
  263. /* We can't setup DAI format here as it depends on the word bit num */
  264. /* so let's just store the value for later */
  265. uda134x->dai_fmt = fmt;
  266. return 0;
  267. }
  268. static int uda134x_set_bias_level(struct snd_soc_codec *codec,
  269. enum snd_soc_bias_level level)
  270. {
  271. struct uda134x_platform_data *pd = codec->control_data;
  272. int i;
  273. u8 *cache = codec->reg_cache;
  274. pr_debug("%s bias level %d\n", __func__, level);
  275. switch (level) {
  276. case SND_SOC_BIAS_ON:
  277. break;
  278. case SND_SOC_BIAS_PREPARE:
  279. /* power on */
  280. if (pd->power) {
  281. pd->power(1);
  282. /* Sync reg_cache with the hardware */
  283. for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
  284. codec->driver->write(codec, i, *cache++);
  285. }
  286. break;
  287. case SND_SOC_BIAS_STANDBY:
  288. break;
  289. case SND_SOC_BIAS_OFF:
  290. /* power off */
  291. if (pd->power)
  292. pd->power(0);
  293. break;
  294. }
  295. codec->dapm.bias_level = level;
  296. return 0;
  297. }
  298. static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
  299. "Minimum2", "Maximum"};
  300. static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
  301. static const char *uda134x_mixmode[] = {"Differential", "Analog1",
  302. "Analog2", "Both"};
  303. static const struct soc_enum uda134x_mixer_enum[] = {
  304. SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
  305. SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
  306. SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
  307. };
  308. static const struct snd_kcontrol_new uda1341_snd_controls[] = {
  309. SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
  310. SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
  311. SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
  312. SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
  313. SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
  314. SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
  315. SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
  316. SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
  317. SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
  318. SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
  319. SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
  320. SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
  321. SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
  322. SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
  323. SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
  324. SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
  325. SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
  326. SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
  327. SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
  328. SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
  329. };
  330. static const struct snd_kcontrol_new uda1340_snd_controls[] = {
  331. SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
  332. SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
  333. SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
  334. SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
  335. SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
  336. SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
  337. };
  338. static const struct snd_kcontrol_new uda1345_snd_controls[] = {
  339. SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
  340. SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
  341. SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
  342. };
  343. /* UDA1341 has the DAC/ADC power down in STATUS1 */
  344. static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
  345. SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
  346. SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
  347. };
  348. /* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
  349. static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
  350. SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
  351. SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
  352. };
  353. /* Common DAPM widgets */
  354. static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
  355. SND_SOC_DAPM_INPUT("VINL1"),
  356. SND_SOC_DAPM_INPUT("VINR1"),
  357. SND_SOC_DAPM_INPUT("VINL2"),
  358. SND_SOC_DAPM_INPUT("VINR2"),
  359. SND_SOC_DAPM_OUTPUT("VOUTL"),
  360. SND_SOC_DAPM_OUTPUT("VOUTR"),
  361. };
  362. static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
  363. { "ADC", NULL, "VINL1" },
  364. { "ADC", NULL, "VINR1" },
  365. { "ADC", NULL, "VINL2" },
  366. { "ADC", NULL, "VINR2" },
  367. { "VOUTL", NULL, "DAC" },
  368. { "VOUTR", NULL, "DAC" },
  369. };
  370. static const struct snd_soc_dai_ops uda134x_dai_ops = {
  371. .startup = uda134x_startup,
  372. .shutdown = uda134x_shutdown,
  373. .hw_params = uda134x_hw_params,
  374. .digital_mute = uda134x_mute,
  375. .set_sysclk = uda134x_set_dai_sysclk,
  376. .set_fmt = uda134x_set_dai_fmt,
  377. };
  378. static struct snd_soc_dai_driver uda134x_dai = {
  379. .name = "uda134x-hifi",
  380. /* playback capabilities */
  381. .playback = {
  382. .stream_name = "Playback",
  383. .channels_min = 1,
  384. .channels_max = 2,
  385. .rates = UDA134X_RATES,
  386. .formats = UDA134X_FORMATS,
  387. },
  388. /* capture capabilities */
  389. .capture = {
  390. .stream_name = "Capture",
  391. .channels_min = 1,
  392. .channels_max = 2,
  393. .rates = UDA134X_RATES,
  394. .formats = UDA134X_FORMATS,
  395. },
  396. /* pcm operations */
  397. .ops = &uda134x_dai_ops,
  398. };
  399. static int uda134x_soc_probe(struct snd_soc_codec *codec)
  400. {
  401. struct uda134x_priv *uda134x;
  402. struct uda134x_platform_data *pd = codec->card->dev->platform_data;
  403. const struct snd_soc_dapm_widget *widgets;
  404. unsigned num_widgets;
  405. int ret;
  406. printk(KERN_INFO "UDA134X SoC Audio Codec\n");
  407. if (!pd) {
  408. printk(KERN_ERR "UDA134X SoC codec: "
  409. "missing L3 bitbang function\n");
  410. return -ENODEV;
  411. }
  412. switch (pd->model) {
  413. case UDA134X_UDA1340:
  414. case UDA134X_UDA1341:
  415. case UDA134X_UDA1344:
  416. case UDA134X_UDA1345:
  417. break;
  418. default:
  419. printk(KERN_ERR "UDA134X SoC codec: "
  420. "unsupported model %d\n",
  421. pd->model);
  422. return -EINVAL;
  423. }
  424. uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
  425. if (uda134x == NULL)
  426. return -ENOMEM;
  427. snd_soc_codec_set_drvdata(codec, uda134x);
  428. codec->control_data = pd;
  429. if (pd->power)
  430. pd->power(1);
  431. uda134x_reset(codec);
  432. if (pd->is_powered_on_standby)
  433. uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
  434. else
  435. uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  436. if (pd->model == UDA134X_UDA1341) {
  437. widgets = uda1341_dapm_widgets;
  438. num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
  439. } else {
  440. widgets = uda1340_dapm_widgets;
  441. num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
  442. }
  443. ret = snd_soc_dapm_new_controls(&codec->dapm, widgets, num_widgets);
  444. if (ret) {
  445. printk(KERN_ERR "%s failed to register dapm controls: %d",
  446. __func__, ret);
  447. kfree(uda134x);
  448. return ret;
  449. }
  450. switch (pd->model) {
  451. case UDA134X_UDA1340:
  452. case UDA134X_UDA1344:
  453. ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
  454. ARRAY_SIZE(uda1340_snd_controls));
  455. break;
  456. case UDA134X_UDA1341:
  457. ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
  458. ARRAY_SIZE(uda1341_snd_controls));
  459. break;
  460. case UDA134X_UDA1345:
  461. ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
  462. ARRAY_SIZE(uda1345_snd_controls));
  463. break;
  464. default:
  465. printk(KERN_ERR "%s unknown codec type: %d",
  466. __func__, pd->model);
  467. kfree(uda134x);
  468. return -EINVAL;
  469. }
  470. if (ret < 0) {
  471. printk(KERN_ERR "UDA134X: failed to register controls\n");
  472. kfree(uda134x);
  473. return ret;
  474. }
  475. return 0;
  476. }
  477. /* power down chip */
  478. static int uda134x_soc_remove(struct snd_soc_codec *codec)
  479. {
  480. struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
  481. uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  482. uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  483. kfree(uda134x);
  484. return 0;
  485. }
  486. #if defined(CONFIG_PM)
  487. static int uda134x_soc_suspend(struct snd_soc_codec *codec)
  488. {
  489. uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  490. uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  491. return 0;
  492. }
  493. static int uda134x_soc_resume(struct snd_soc_codec *codec)
  494. {
  495. uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
  496. uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
  497. return 0;
  498. }
  499. #else
  500. #define uda134x_soc_suspend NULL
  501. #define uda134x_soc_resume NULL
  502. #endif /* CONFIG_PM */
  503. static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
  504. .probe = uda134x_soc_probe,
  505. .remove = uda134x_soc_remove,
  506. .suspend = uda134x_soc_suspend,
  507. .resume = uda134x_soc_resume,
  508. .reg_cache_size = sizeof(uda134x_reg),
  509. .reg_word_size = sizeof(u8),
  510. .reg_cache_default = uda134x_reg,
  511. .reg_cache_step = 1,
  512. .read = uda134x_read_reg_cache,
  513. .write = uda134x_write,
  514. .set_bias_level = uda134x_set_bias_level,
  515. .dapm_widgets = uda134x_dapm_widgets,
  516. .num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets),
  517. .dapm_routes = uda134x_dapm_routes,
  518. .num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes),
  519. };
  520. static int uda134x_codec_probe(struct platform_device *pdev)
  521. {
  522. return snd_soc_register_codec(&pdev->dev,
  523. &soc_codec_dev_uda134x, &uda134x_dai, 1);
  524. }
  525. static int uda134x_codec_remove(struct platform_device *pdev)
  526. {
  527. snd_soc_unregister_codec(&pdev->dev);
  528. return 0;
  529. }
  530. static struct platform_driver uda134x_codec_driver = {
  531. .driver = {
  532. .name = "uda134x-codec",
  533. .owner = THIS_MODULE,
  534. },
  535. .probe = uda134x_codec_probe,
  536. .remove = uda134x_codec_remove,
  537. };
  538. module_platform_driver(uda134x_codec_driver);
  539. MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
  540. MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
  541. MODULE_LICENSE("GPL");