tlv320aic3x.c 52 KB

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  1. /*
  2. * ALSA SoC TLV320AIC3X codec driver
  3. *
  4. * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
  5. * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
  6. *
  7. * Based on sound/soc/codecs/wm8753.c by Liam Girdwood
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * Notes:
  14. * The AIC3X is a driver for a low power stereo audio
  15. * codecs aic31, aic32, aic33, aic3007.
  16. *
  17. * It supports full aic33 codec functionality.
  18. * The compatibility with aic32, aic31 and aic3007 is as follows:
  19. * aic32/aic3007 | aic31
  20. * ---------------------------------------
  21. * MONO_LOUT -> N/A | MONO_LOUT -> N/A
  22. * | IN1L -> LINE1L
  23. * | IN1R -> LINE1R
  24. * | IN2L -> LINE2L
  25. * | IN2R -> LINE2R
  26. * | MIC3L/R -> N/A
  27. * truncated internal functionality in
  28. * accordance with documentation
  29. * ---------------------------------------
  30. *
  31. * Hence the machine layer should disable unsupported inputs/outputs by
  32. * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc.
  33. */
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/init.h>
  37. #include <linux/delay.h>
  38. #include <linux/pm.h>
  39. #include <linux/i2c.h>
  40. #include <linux/gpio.h>
  41. #include <linux/regulator/consumer.h>
  42. #include <linux/of_gpio.h>
  43. #include <linux/slab.h>
  44. #include <sound/core.h>
  45. #include <sound/pcm.h>
  46. #include <sound/pcm_params.h>
  47. #include <sound/soc.h>
  48. #include <sound/initval.h>
  49. #include <sound/tlv.h>
  50. #include <sound/tlv320aic3x.h>
  51. #include "tlv320aic3x.h"
  52. #define AIC3X_NUM_SUPPLIES 4
  53. static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
  54. "IOVDD", /* I/O Voltage */
  55. "DVDD", /* Digital Core Voltage */
  56. "AVDD", /* Analog DAC Voltage */
  57. "DRVDD", /* ADC Analog and Output Driver Voltage */
  58. };
  59. static LIST_HEAD(reset_list);
  60. struct aic3x_priv;
  61. struct aic3x_disable_nb {
  62. struct notifier_block nb;
  63. struct aic3x_priv *aic3x;
  64. };
  65. /* codec private data */
  66. struct aic3x_priv {
  67. struct snd_soc_codec *codec;
  68. struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
  69. struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
  70. enum snd_soc_control_type control_type;
  71. struct aic3x_setup_data *setup;
  72. unsigned int sysclk;
  73. struct list_head list;
  74. int master;
  75. int gpio_reset;
  76. int power;
  77. #define AIC3X_MODEL_3X 0
  78. #define AIC3X_MODEL_33 1
  79. #define AIC3X_MODEL_3007 2
  80. u16 model;
  81. /* Selects the micbias voltage */
  82. enum aic3x_micbias_voltage micbias_vg;
  83. };
  84. /*
  85. * AIC3X register cache
  86. * We can't read the AIC3X register space when we are
  87. * using 2 wire for device control, so we cache them instead.
  88. * There is no point in caching the reset register
  89. */
  90. static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
  91. 0x00, 0x00, 0x00, 0x10, /* 0 */
  92. 0x04, 0x00, 0x00, 0x00, /* 4 */
  93. 0x00, 0x00, 0x00, 0x01, /* 8 */
  94. 0x00, 0x00, 0x00, 0x80, /* 12 */
  95. 0x80, 0xff, 0xff, 0x78, /* 16 */
  96. 0x78, 0x78, 0x78, 0x78, /* 20 */
  97. 0x78, 0x00, 0x00, 0xfe, /* 24 */
  98. 0x00, 0x00, 0xfe, 0x00, /* 28 */
  99. 0x18, 0x18, 0x00, 0x00, /* 32 */
  100. 0x00, 0x00, 0x00, 0x00, /* 36 */
  101. 0x00, 0x00, 0x00, 0x80, /* 40 */
  102. 0x80, 0x00, 0x00, 0x00, /* 44 */
  103. 0x00, 0x00, 0x00, 0x04, /* 48 */
  104. 0x00, 0x00, 0x00, 0x00, /* 52 */
  105. 0x00, 0x00, 0x04, 0x00, /* 56 */
  106. 0x00, 0x00, 0x00, 0x00, /* 60 */
  107. 0x00, 0x04, 0x00, 0x00, /* 64 */
  108. 0x00, 0x00, 0x00, 0x00, /* 68 */
  109. 0x04, 0x00, 0x00, 0x00, /* 72 */
  110. 0x00, 0x00, 0x00, 0x00, /* 76 */
  111. 0x00, 0x00, 0x00, 0x00, /* 80 */
  112. 0x00, 0x00, 0x00, 0x00, /* 84 */
  113. 0x00, 0x00, 0x00, 0x00, /* 88 */
  114. 0x00, 0x00, 0x00, 0x00, /* 92 */
  115. 0x00, 0x00, 0x00, 0x00, /* 96 */
  116. 0x00, 0x00, 0x02, 0x00, /* 100 */
  117. 0x00, 0x00, 0x00, 0x00, /* 104 */
  118. 0x00, 0x00, /* 108 */
  119. };
  120. #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
  121. SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
  122. snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
  123. /*
  124. * All input lines are connected when !0xf and disconnected with 0xf bit field,
  125. * so we have to use specific dapm_put call for input mixer
  126. */
  127. static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
  128. struct snd_ctl_elem_value *ucontrol)
  129. {
  130. struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
  131. struct soc_mixer_control *mc =
  132. (struct soc_mixer_control *)kcontrol->private_value;
  133. unsigned int reg = mc->reg;
  134. unsigned int shift = mc->shift;
  135. int max = mc->max;
  136. unsigned int mask = (1 << fls(max)) - 1;
  137. unsigned int invert = mc->invert;
  138. unsigned short val;
  139. struct snd_soc_dapm_update update;
  140. int connect, change;
  141. val = (ucontrol->value.integer.value[0] & mask);
  142. mask = 0xf;
  143. if (val)
  144. val = mask;
  145. connect = !!val;
  146. if (invert)
  147. val = mask - val;
  148. mask <<= shift;
  149. val <<= shift;
  150. change = snd_soc_test_bits(codec, val, mask, reg);
  151. if (change) {
  152. update.kcontrol = kcontrol;
  153. update.reg = reg;
  154. update.mask = mask;
  155. update.val = val;
  156. snd_soc_dapm_mixer_update_power(&codec->dapm, kcontrol, connect,
  157. &update);
  158. }
  159. return change;
  160. }
  161. /*
  162. * mic bias power on/off share the same register bits with
  163. * output voltage of mic bias. when power on mic bias, we
  164. * need reclaim it to voltage value.
  165. * 0x0 = Powered off
  166. * 0x1 = MICBIAS output is powered to 2.0V,
  167. * 0x2 = MICBIAS output is powered to 2.5V
  168. * 0x3 = MICBIAS output is connected to AVDD
  169. */
  170. static int mic_bias_event(struct snd_soc_dapm_widget *w,
  171. struct snd_kcontrol *kcontrol, int event)
  172. {
  173. struct snd_soc_codec *codec = w->codec;
  174. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  175. switch (event) {
  176. case SND_SOC_DAPM_POST_PMU:
  177. /* change mic bias voltage to user defined */
  178. snd_soc_update_bits(codec, MICBIAS_CTRL,
  179. MICBIAS_LEVEL_MASK,
  180. aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
  181. break;
  182. case SND_SOC_DAPM_PRE_PMD:
  183. snd_soc_update_bits(codec, MICBIAS_CTRL,
  184. MICBIAS_LEVEL_MASK, 0);
  185. break;
  186. }
  187. return 0;
  188. }
  189. static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
  190. static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
  191. static const char *aic3x_left_hpcom_mux[] =
  192. { "differential of HPLOUT", "constant VCM", "single-ended" };
  193. static const char *aic3x_right_hpcom_mux[] =
  194. { "differential of HPROUT", "constant VCM", "single-ended",
  195. "differential of HPLCOM", "external feedback" };
  196. static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
  197. static const char *aic3x_adc_hpf[] =
  198. { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
  199. #define LDAC_ENUM 0
  200. #define RDAC_ENUM 1
  201. #define LHPCOM_ENUM 2
  202. #define RHPCOM_ENUM 3
  203. #define LINE1L_2_L_ENUM 4
  204. #define LINE1L_2_R_ENUM 5
  205. #define LINE1R_2_L_ENUM 6
  206. #define LINE1R_2_R_ENUM 7
  207. #define LINE2L_ENUM 8
  208. #define LINE2R_ENUM 9
  209. #define ADC_HPF_ENUM 10
  210. static const struct soc_enum aic3x_enum[] = {
  211. SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
  212. SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
  213. SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
  214. SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
  215. SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  216. SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  217. SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  218. SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  219. SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  220. SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
  221. SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
  222. };
  223. static const char *aic3x_agc_level[] =
  224. { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
  225. static const struct soc_enum aic3x_agc_level_enum[] = {
  226. SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
  227. SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
  228. };
  229. static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
  230. static const struct soc_enum aic3x_agc_attack_enum[] = {
  231. SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
  232. SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
  233. };
  234. static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
  235. static const struct soc_enum aic3x_agc_decay_enum[] = {
  236. SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
  237. SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
  238. };
  239. /*
  240. * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps
  241. */
  242. static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
  243. /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */
  244. static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
  245. /*
  246. * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB.
  247. * Step size is approximately 0.5 dB over most of the scale but increasing
  248. * near the very low levels.
  249. * Define dB scale so that it is mostly correct for range about -55 to 0 dB
  250. * but having increasing dB difference below that (and where it doesn't count
  251. * so much). This setting shows -50 dB (actual is -50.3 dB) for register
  252. * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117.
  253. */
  254. static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
  255. static const struct snd_kcontrol_new aic3x_snd_controls[] = {
  256. /* Output */
  257. SOC_DOUBLE_R_TLV("PCM Playback Volume",
  258. LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
  259. /*
  260. * Output controls that map to output mixer switches. Note these are
  261. * only for swapped L-to-R and R-to-L routes. See below stereo controls
  262. * for direct L-to-L and R-to-R routes.
  263. */
  264. SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
  265. LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  266. SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
  267. PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  268. SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
  269. DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
  270. SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
  271. LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  272. SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
  273. PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  274. SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
  275. DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
  276. SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
  277. LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  278. SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
  279. PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  280. SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
  281. DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
  282. SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
  283. LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  284. SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
  285. PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  286. SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
  287. DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
  288. SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
  289. LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  290. SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
  291. PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  292. SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
  293. DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
  294. SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
  295. LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  296. SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
  297. PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  298. SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
  299. DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
  300. /* Stereo output controls for direct L-to-L and R-to-R routes */
  301. SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
  302. LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
  303. 0, 118, 1, output_stage_tlv),
  304. SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
  305. PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
  306. 0, 118, 1, output_stage_tlv),
  307. SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
  308. DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
  309. 0, 118, 1, output_stage_tlv),
  310. SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
  311. LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
  312. 0, 118, 1, output_stage_tlv),
  313. SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
  314. PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
  315. 0, 118, 1, output_stage_tlv),
  316. SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
  317. DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
  318. 0, 118, 1, output_stage_tlv),
  319. SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
  320. LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
  321. 0, 118, 1, output_stage_tlv),
  322. SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
  323. PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
  324. 0, 118, 1, output_stage_tlv),
  325. SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
  326. DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
  327. 0, 118, 1, output_stage_tlv),
  328. SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
  329. LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
  330. 0, 118, 1, output_stage_tlv),
  331. SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
  332. PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
  333. 0, 118, 1, output_stage_tlv),
  334. SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
  335. DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
  336. 0, 118, 1, output_stage_tlv),
  337. /* Output pin mute controls */
  338. SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
  339. 0x01, 0),
  340. SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
  341. SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
  342. 0x01, 0),
  343. SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
  344. 0x01, 0),
  345. /*
  346. * Note: enable Automatic input Gain Controller with care. It can
  347. * adjust PGA to max value when ADC is on and will never go back.
  348. */
  349. SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
  350. SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
  351. SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
  352. SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
  353. SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
  354. SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
  355. SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
  356. /* De-emphasis */
  357. SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
  358. /* Input */
  359. SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
  360. 0, 119, 0, adc_tlv),
  361. SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
  362. SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
  363. };
  364. /*
  365. * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps
  366. */
  367. static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
  368. static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
  369. SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
  370. /* Left DAC Mux */
  371. static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
  372. SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
  373. /* Right DAC Mux */
  374. static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
  375. SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
  376. /* Left HPCOM Mux */
  377. static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
  378. SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
  379. /* Right HPCOM Mux */
  380. static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
  381. SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
  382. /* Left Line Mixer */
  383. static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
  384. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
  385. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
  386. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
  387. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
  388. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
  389. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
  390. };
  391. /* Right Line Mixer */
  392. static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
  393. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
  394. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
  395. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
  396. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
  397. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
  398. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
  399. };
  400. /* Mono Mixer */
  401. static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
  402. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
  403. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
  404. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
  405. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
  406. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
  407. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
  408. };
  409. /* Left HP Mixer */
  410. static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
  411. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
  412. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
  413. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
  414. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
  415. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
  416. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
  417. };
  418. /* Right HP Mixer */
  419. static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
  420. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
  421. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
  422. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
  423. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
  424. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
  425. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
  426. };
  427. /* Left HPCOM Mixer */
  428. static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
  429. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
  430. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
  431. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
  432. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
  433. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
  434. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
  435. };
  436. /* Right HPCOM Mixer */
  437. static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
  438. SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
  439. SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
  440. SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
  441. SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
  442. SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
  443. SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
  444. };
  445. /* Left PGA Mixer */
  446. static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
  447. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
  448. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
  449. SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
  450. SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
  451. SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
  452. };
  453. /* Right PGA Mixer */
  454. static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
  455. SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
  456. SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
  457. SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
  458. SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
  459. SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
  460. };
  461. /* Left Line1 Mux */
  462. static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
  463. SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
  464. static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
  465. SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
  466. /* Right Line1 Mux */
  467. static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
  468. SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
  469. static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
  470. SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
  471. /* Left Line2 Mux */
  472. static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
  473. SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
  474. /* Right Line2 Mux */
  475. static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
  476. SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
  477. static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
  478. /* Left DAC to Left Outputs */
  479. SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
  480. SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
  481. &aic3x_left_dac_mux_controls),
  482. SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
  483. &aic3x_left_hpcom_mux_controls),
  484. SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
  485. SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
  486. SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
  487. /* Right DAC to Right Outputs */
  488. SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
  489. SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
  490. &aic3x_right_dac_mux_controls),
  491. SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
  492. &aic3x_right_hpcom_mux_controls),
  493. SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
  494. SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
  495. SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
  496. /* Mono Output */
  497. SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
  498. /* Inputs to Left ADC */
  499. SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
  500. SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
  501. &aic3x_left_pga_mixer_controls[0],
  502. ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
  503. SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
  504. &aic3x_left_line1l_mux_controls),
  505. SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
  506. &aic3x_left_line1r_mux_controls),
  507. SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
  508. &aic3x_left_line2_mux_controls),
  509. /* Inputs to Right ADC */
  510. SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
  511. LINE1R_2_RADC_CTRL, 2, 0),
  512. SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
  513. &aic3x_right_pga_mixer_controls[0],
  514. ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
  515. SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
  516. &aic3x_right_line1l_mux_controls),
  517. SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
  518. &aic3x_right_line1r_mux_controls),
  519. SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
  520. &aic3x_right_line2_mux_controls),
  521. /*
  522. * Not a real mic bias widget but similar function. This is for dynamic
  523. * control of GPIO1 digital mic modulator clock output function when
  524. * using digital mic.
  525. */
  526. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
  527. AIC3X_GPIO1_REG, 4, 0xf,
  528. AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
  529. AIC3X_GPIO1_FUNC_DISABLED),
  530. /*
  531. * Also similar function like mic bias. Selects digital mic with
  532. * configurable oversampling rate instead of ADC converter.
  533. */
  534. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
  535. AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
  536. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
  537. AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
  538. SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
  539. AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
  540. /* Mic Bias */
  541. SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
  542. mic_bias_event,
  543. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
  544. /* Output mixers */
  545. SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
  546. &aic3x_left_line_mixer_controls[0],
  547. ARRAY_SIZE(aic3x_left_line_mixer_controls)),
  548. SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
  549. &aic3x_right_line_mixer_controls[0],
  550. ARRAY_SIZE(aic3x_right_line_mixer_controls)),
  551. SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
  552. &aic3x_mono_mixer_controls[0],
  553. ARRAY_SIZE(aic3x_mono_mixer_controls)),
  554. SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
  555. &aic3x_left_hp_mixer_controls[0],
  556. ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
  557. SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
  558. &aic3x_right_hp_mixer_controls[0],
  559. ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
  560. SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
  561. &aic3x_left_hpcom_mixer_controls[0],
  562. ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
  563. SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
  564. &aic3x_right_hpcom_mixer_controls[0],
  565. ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
  566. SND_SOC_DAPM_OUTPUT("LLOUT"),
  567. SND_SOC_DAPM_OUTPUT("RLOUT"),
  568. SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
  569. SND_SOC_DAPM_OUTPUT("HPLOUT"),
  570. SND_SOC_DAPM_OUTPUT("HPROUT"),
  571. SND_SOC_DAPM_OUTPUT("HPLCOM"),
  572. SND_SOC_DAPM_OUTPUT("HPRCOM"),
  573. SND_SOC_DAPM_INPUT("MIC3L"),
  574. SND_SOC_DAPM_INPUT("MIC3R"),
  575. SND_SOC_DAPM_INPUT("LINE1L"),
  576. SND_SOC_DAPM_INPUT("LINE1R"),
  577. SND_SOC_DAPM_INPUT("LINE2L"),
  578. SND_SOC_DAPM_INPUT("LINE2R"),
  579. /*
  580. * Virtual output pin to detection block inside codec. This can be
  581. * used to keep codec bias on if gpio or detection features are needed.
  582. * Force pin on or construct a path with an input jack and mic bias
  583. * widgets.
  584. */
  585. SND_SOC_DAPM_OUTPUT("Detection"),
  586. };
  587. static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
  588. /* Class-D outputs */
  589. SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
  590. SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
  591. SND_SOC_DAPM_OUTPUT("SPOP"),
  592. SND_SOC_DAPM_OUTPUT("SPOM"),
  593. };
  594. static const struct snd_soc_dapm_route intercon[] = {
  595. /* Left Input */
  596. {"Left Line1L Mux", "single-ended", "LINE1L"},
  597. {"Left Line1L Mux", "differential", "LINE1L"},
  598. {"Left Line2L Mux", "single-ended", "LINE2L"},
  599. {"Left Line2L Mux", "differential", "LINE2L"},
  600. {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
  601. {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
  602. {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
  603. {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
  604. {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
  605. {"Left ADC", NULL, "Left PGA Mixer"},
  606. {"Left ADC", NULL, "GPIO1 dmic modclk"},
  607. /* Right Input */
  608. {"Right Line1R Mux", "single-ended", "LINE1R"},
  609. {"Right Line1R Mux", "differential", "LINE1R"},
  610. {"Right Line2R Mux", "single-ended", "LINE2R"},
  611. {"Right Line2R Mux", "differential", "LINE2R"},
  612. {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
  613. {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
  614. {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
  615. {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
  616. {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
  617. {"Right ADC", NULL, "Right PGA Mixer"},
  618. {"Right ADC", NULL, "GPIO1 dmic modclk"},
  619. /*
  620. * Logical path between digital mic enable and GPIO1 modulator clock
  621. * output function
  622. */
  623. {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
  624. {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
  625. {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
  626. /* Left DAC Output */
  627. {"Left DAC Mux", "DAC_L1", "Left DAC"},
  628. {"Left DAC Mux", "DAC_L2", "Left DAC"},
  629. {"Left DAC Mux", "DAC_L3", "Left DAC"},
  630. /* Right DAC Output */
  631. {"Right DAC Mux", "DAC_R1", "Right DAC"},
  632. {"Right DAC Mux", "DAC_R2", "Right DAC"},
  633. {"Right DAC Mux", "DAC_R3", "Right DAC"},
  634. /* Left Line Output */
  635. {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  636. {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  637. {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
  638. {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  639. {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  640. {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
  641. {"Left Line Out", NULL, "Left Line Mixer"},
  642. {"Left Line Out", NULL, "Left DAC Mux"},
  643. {"LLOUT", NULL, "Left Line Out"},
  644. /* Right Line Output */
  645. {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  646. {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  647. {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
  648. {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  649. {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  650. {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
  651. {"Right Line Out", NULL, "Right Line Mixer"},
  652. {"Right Line Out", NULL, "Right DAC Mux"},
  653. {"RLOUT", NULL, "Right Line Out"},
  654. /* Mono Output */
  655. {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  656. {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  657. {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
  658. {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  659. {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  660. {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
  661. {"Mono Out", NULL, "Mono Mixer"},
  662. {"MONO_LOUT", NULL, "Mono Out"},
  663. /* Left HP Output */
  664. {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  665. {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  666. {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
  667. {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  668. {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  669. {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
  670. {"Left HP Out", NULL, "Left HP Mixer"},
  671. {"Left HP Out", NULL, "Left DAC Mux"},
  672. {"HPLOUT", NULL, "Left HP Out"},
  673. /* Right HP Output */
  674. {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  675. {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  676. {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
  677. {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  678. {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  679. {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
  680. {"Right HP Out", NULL, "Right HP Mixer"},
  681. {"Right HP Out", NULL, "Right DAC Mux"},
  682. {"HPROUT", NULL, "Right HP Out"},
  683. /* Left HPCOM Output */
  684. {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  685. {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  686. {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
  687. {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  688. {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  689. {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
  690. {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
  691. {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
  692. {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
  693. {"Left HP Com", NULL, "Left HPCOM Mux"},
  694. {"HPLCOM", NULL, "Left HP Com"},
  695. /* Right HPCOM Output */
  696. {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
  697. {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
  698. {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
  699. {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
  700. {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
  701. {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
  702. {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
  703. {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
  704. {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
  705. {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
  706. {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
  707. {"Right HP Com", NULL, "Right HPCOM Mux"},
  708. {"HPRCOM", NULL, "Right HP Com"},
  709. };
  710. static const struct snd_soc_dapm_route intercon_3007[] = {
  711. /* Class-D outputs */
  712. {"Left Class-D Out", NULL, "Left Line Out"},
  713. {"Right Class-D Out", NULL, "Left Line Out"},
  714. {"SPOP", NULL, "Left Class-D Out"},
  715. {"SPOM", NULL, "Right Class-D Out"},
  716. };
  717. static int aic3x_add_widgets(struct snd_soc_codec *codec)
  718. {
  719. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  720. struct snd_soc_dapm_context *dapm = &codec->dapm;
  721. snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
  722. ARRAY_SIZE(aic3x_dapm_widgets));
  723. /* set up audio path interconnects */
  724. snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
  725. if (aic3x->model == AIC3X_MODEL_3007) {
  726. snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
  727. ARRAY_SIZE(aic3007_dapm_widgets));
  728. snd_soc_dapm_add_routes(dapm, intercon_3007,
  729. ARRAY_SIZE(intercon_3007));
  730. }
  731. return 0;
  732. }
  733. static int aic3x_hw_params(struct snd_pcm_substream *substream,
  734. struct snd_pcm_hw_params *params,
  735. struct snd_soc_dai *dai)
  736. {
  737. struct snd_soc_codec *codec = dai->codec;
  738. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  739. int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
  740. u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
  741. u16 d, pll_d = 1;
  742. int clk;
  743. /* select data word length */
  744. data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
  745. switch (params_format(params)) {
  746. case SNDRV_PCM_FORMAT_S16_LE:
  747. break;
  748. case SNDRV_PCM_FORMAT_S20_3LE:
  749. data |= (0x01 << 4);
  750. break;
  751. case SNDRV_PCM_FORMAT_S24_LE:
  752. data |= (0x02 << 4);
  753. break;
  754. case SNDRV_PCM_FORMAT_S32_LE:
  755. data |= (0x03 << 4);
  756. break;
  757. }
  758. snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
  759. /* Fsref can be 44100 or 48000 */
  760. fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
  761. /* Try to find a value for Q which allows us to bypass the PLL and
  762. * generate CODEC_CLK directly. */
  763. for (pll_q = 2; pll_q < 18; pll_q++)
  764. if (aic3x->sysclk / (128 * pll_q) == fsref) {
  765. bypass_pll = 1;
  766. break;
  767. }
  768. if (bypass_pll) {
  769. pll_q &= 0xf;
  770. snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
  771. snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
  772. /* disable PLL if it is bypassed */
  773. snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
  774. } else {
  775. snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
  776. /* enable PLL when it is used */
  777. snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
  778. PLL_ENABLE, PLL_ENABLE);
  779. }
  780. /* Route Left DAC to left channel input and
  781. * right DAC to right channel input */
  782. data = (LDAC2LCH | RDAC2RCH);
  783. data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
  784. if (params_rate(params) >= 64000)
  785. data |= DUAL_RATE_MODE;
  786. snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
  787. /* codec sample rate select */
  788. data = (fsref * 20) / params_rate(params);
  789. if (params_rate(params) < 64000)
  790. data /= 2;
  791. data /= 5;
  792. data -= 2;
  793. data |= (data << 4);
  794. snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
  795. if (bypass_pll)
  796. return 0;
  797. /* Use PLL, compute appropriate setup for j, d, r and p, the closest
  798. * one wins the game. Try with d==0 first, next with d!=0.
  799. * Constraints for j are according to the datasheet.
  800. * The sysclk is divided by 1000 to prevent integer overflows.
  801. */
  802. codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
  803. for (r = 1; r <= 16; r++)
  804. for (p = 1; p <= 8; p++) {
  805. for (j = 4; j <= 55; j++) {
  806. /* This is actually 1000*((j+(d/10000))*r)/p
  807. * The term had to be converted to get
  808. * rid of the division by 10000; d = 0 here
  809. */
  810. int tmp_clk = (1000 * j * r) / p;
  811. /* Check whether this values get closer than
  812. * the best ones we had before
  813. */
  814. if (abs(codec_clk - tmp_clk) <
  815. abs(codec_clk - last_clk)) {
  816. pll_j = j; pll_d = 0;
  817. pll_r = r; pll_p = p;
  818. last_clk = tmp_clk;
  819. }
  820. /* Early exit for exact matches */
  821. if (tmp_clk == codec_clk)
  822. goto found;
  823. }
  824. }
  825. /* try with d != 0 */
  826. for (p = 1; p <= 8; p++) {
  827. j = codec_clk * p / 1000;
  828. if (j < 4 || j > 11)
  829. continue;
  830. /* do not use codec_clk here since we'd loose precision */
  831. d = ((2048 * p * fsref) - j * aic3x->sysclk)
  832. * 100 / (aic3x->sysclk/100);
  833. clk = (10000 * j + d) / (10 * p);
  834. /* check whether this values get closer than the best
  835. * ones we had before */
  836. if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
  837. pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
  838. last_clk = clk;
  839. }
  840. /* Early exit for exact matches */
  841. if (clk == codec_clk)
  842. goto found;
  843. }
  844. if (last_clk == 0) {
  845. printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
  846. return -EINVAL;
  847. }
  848. found:
  849. snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
  850. snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
  851. pll_r << PLLR_SHIFT);
  852. snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
  853. snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
  854. (pll_d >> 6) << PLLD_MSB_SHIFT);
  855. snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
  856. (pll_d & 0x3F) << PLLD_LSB_SHIFT);
  857. return 0;
  858. }
  859. static int aic3x_mute(struct snd_soc_dai *dai, int mute)
  860. {
  861. struct snd_soc_codec *codec = dai->codec;
  862. u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
  863. u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
  864. if (mute) {
  865. snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
  866. snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
  867. } else {
  868. snd_soc_write(codec, LDAC_VOL, ldac_reg);
  869. snd_soc_write(codec, RDAC_VOL, rdac_reg);
  870. }
  871. return 0;
  872. }
  873. static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  874. int clk_id, unsigned int freq, int dir)
  875. {
  876. struct snd_soc_codec *codec = codec_dai->codec;
  877. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  878. /* set clock on MCLK or GPIO2 or BCLK */
  879. snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
  880. clk_id << PLLCLK_IN_SHIFT);
  881. snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
  882. clk_id << CLKDIV_IN_SHIFT);
  883. aic3x->sysclk = freq;
  884. return 0;
  885. }
  886. static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
  887. unsigned int fmt)
  888. {
  889. struct snd_soc_codec *codec = codec_dai->codec;
  890. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  891. u8 iface_areg, iface_breg;
  892. int delay = 0;
  893. iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
  894. iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
  895. /* set master/slave audio interface */
  896. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  897. case SND_SOC_DAIFMT_CBM_CFM:
  898. aic3x->master = 1;
  899. iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
  900. break;
  901. case SND_SOC_DAIFMT_CBS_CFS:
  902. aic3x->master = 0;
  903. iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
  904. break;
  905. default:
  906. return -EINVAL;
  907. }
  908. /*
  909. * match both interface format and signal polarities since they
  910. * are fixed
  911. */
  912. switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
  913. SND_SOC_DAIFMT_INV_MASK)) {
  914. case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
  915. break;
  916. case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
  917. delay = 1;
  918. case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
  919. iface_breg |= (0x01 << 6);
  920. break;
  921. case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
  922. iface_breg |= (0x02 << 6);
  923. break;
  924. case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
  925. iface_breg |= (0x03 << 6);
  926. break;
  927. default:
  928. return -EINVAL;
  929. }
  930. /* set iface */
  931. snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
  932. snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
  933. snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
  934. return 0;
  935. }
  936. static int aic3x_init_3007(struct snd_soc_codec *codec)
  937. {
  938. u8 tmp1, tmp2, *cache = codec->reg_cache;
  939. /*
  940. * There is no need to cache writes to undocumented page 0xD but
  941. * respective page 0 register cache entries must be preserved
  942. */
  943. tmp1 = cache[0xD];
  944. tmp2 = cache[0x8];
  945. /* Class-D speaker driver init; datasheet p. 46 */
  946. snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
  947. snd_soc_write(codec, 0xD, 0x0D);
  948. snd_soc_write(codec, 0x8, 0x5C);
  949. snd_soc_write(codec, 0x8, 0x5D);
  950. snd_soc_write(codec, 0x8, 0x5C);
  951. snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
  952. cache[0xD] = tmp1;
  953. cache[0x8] = tmp2;
  954. return 0;
  955. }
  956. static int aic3x_regulator_event(struct notifier_block *nb,
  957. unsigned long event, void *data)
  958. {
  959. struct aic3x_disable_nb *disable_nb =
  960. container_of(nb, struct aic3x_disable_nb, nb);
  961. struct aic3x_priv *aic3x = disable_nb->aic3x;
  962. if (event & REGULATOR_EVENT_DISABLE) {
  963. /*
  964. * Put codec to reset and require cache sync as at least one
  965. * of the supplies was disabled
  966. */
  967. if (gpio_is_valid(aic3x->gpio_reset))
  968. gpio_set_value(aic3x->gpio_reset, 0);
  969. aic3x->codec->cache_sync = 1;
  970. }
  971. return 0;
  972. }
  973. static int aic3x_set_power(struct snd_soc_codec *codec, int power)
  974. {
  975. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  976. int i, ret;
  977. u8 *cache = codec->reg_cache;
  978. if (power) {
  979. ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
  980. aic3x->supplies);
  981. if (ret)
  982. goto out;
  983. aic3x->power = 1;
  984. /*
  985. * Reset release and cache sync is necessary only if some
  986. * supply was off or if there were cached writes
  987. */
  988. if (!codec->cache_sync)
  989. goto out;
  990. if (gpio_is_valid(aic3x->gpio_reset)) {
  991. udelay(1);
  992. gpio_set_value(aic3x->gpio_reset, 1);
  993. }
  994. /* Sync reg_cache with the hardware */
  995. codec->cache_only = 0;
  996. for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
  997. snd_soc_write(codec, i, cache[i]);
  998. if (aic3x->model == AIC3X_MODEL_3007)
  999. aic3x_init_3007(codec);
  1000. codec->cache_sync = 0;
  1001. } else {
  1002. /*
  1003. * Do soft reset to this codec instance in order to clear
  1004. * possible VDD leakage currents in case the supply regulators
  1005. * remain on
  1006. */
  1007. snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
  1008. codec->cache_sync = 1;
  1009. aic3x->power = 0;
  1010. /* HW writes are needless when bias is off */
  1011. codec->cache_only = 1;
  1012. ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
  1013. aic3x->supplies);
  1014. }
  1015. out:
  1016. return ret;
  1017. }
  1018. static int aic3x_set_bias_level(struct snd_soc_codec *codec,
  1019. enum snd_soc_bias_level level)
  1020. {
  1021. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  1022. switch (level) {
  1023. case SND_SOC_BIAS_ON:
  1024. break;
  1025. case SND_SOC_BIAS_PREPARE:
  1026. if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
  1027. aic3x->master) {
  1028. /* enable pll */
  1029. snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
  1030. PLL_ENABLE, PLL_ENABLE);
  1031. }
  1032. break;
  1033. case SND_SOC_BIAS_STANDBY:
  1034. if (!aic3x->power)
  1035. aic3x_set_power(codec, 1);
  1036. if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
  1037. aic3x->master) {
  1038. /* disable pll */
  1039. snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
  1040. PLL_ENABLE, 0);
  1041. }
  1042. break;
  1043. case SND_SOC_BIAS_OFF:
  1044. if (aic3x->power)
  1045. aic3x_set_power(codec, 0);
  1046. break;
  1047. }
  1048. codec->dapm.bias_level = level;
  1049. return 0;
  1050. }
  1051. #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
  1052. #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  1053. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  1054. static const struct snd_soc_dai_ops aic3x_dai_ops = {
  1055. .hw_params = aic3x_hw_params,
  1056. .digital_mute = aic3x_mute,
  1057. .set_sysclk = aic3x_set_dai_sysclk,
  1058. .set_fmt = aic3x_set_dai_fmt,
  1059. };
  1060. static struct snd_soc_dai_driver aic3x_dai = {
  1061. .name = "tlv320aic3x-hifi",
  1062. .playback = {
  1063. .stream_name = "Playback",
  1064. .channels_min = 2,
  1065. .channels_max = 2,
  1066. .rates = AIC3X_RATES,
  1067. .formats = AIC3X_FORMATS,},
  1068. .capture = {
  1069. .stream_name = "Capture",
  1070. .channels_min = 2,
  1071. .channels_max = 2,
  1072. .rates = AIC3X_RATES,
  1073. .formats = AIC3X_FORMATS,},
  1074. .ops = &aic3x_dai_ops,
  1075. .symmetric_rates = 1,
  1076. };
  1077. static int aic3x_suspend(struct snd_soc_codec *codec)
  1078. {
  1079. aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1080. return 0;
  1081. }
  1082. static int aic3x_resume(struct snd_soc_codec *codec)
  1083. {
  1084. aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1085. return 0;
  1086. }
  1087. /*
  1088. * initialise the AIC3X driver
  1089. * register the mixer and dsp interfaces with the kernel
  1090. */
  1091. static int aic3x_init(struct snd_soc_codec *codec)
  1092. {
  1093. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  1094. snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
  1095. snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
  1096. /* DAC default volume and mute */
  1097. snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
  1098. snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
  1099. /* DAC to HP default volume and route to Output mixer */
  1100. snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
  1101. snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
  1102. snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
  1103. snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
  1104. /* DAC to Line Out default volume and route to Output mixer */
  1105. snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1106. snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1107. /* DAC to Mono Line Out default volume and route to Output mixer */
  1108. snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1109. snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
  1110. /* unmute all outputs */
  1111. snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
  1112. snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
  1113. snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
  1114. snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
  1115. snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
  1116. snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
  1117. snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
  1118. /* ADC default volume and unmute */
  1119. snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
  1120. snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
  1121. /* By default route Line1 to ADC PGA mixer */
  1122. snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
  1123. snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
  1124. /* PGA to HP Bypass default volume, disconnect from Output Mixer */
  1125. snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
  1126. snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
  1127. snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
  1128. snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
  1129. /* PGA to Line Out default volume, disconnect from Output Mixer */
  1130. snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
  1131. snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
  1132. /* PGA to Mono Line Out default volume, disconnect from Output Mixer */
  1133. snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
  1134. snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
  1135. /* Line2 to HP Bypass default volume, disconnect from Output Mixer */
  1136. snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
  1137. snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
  1138. snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
  1139. snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
  1140. /* Line2 Line Out default volume, disconnect from Output Mixer */
  1141. snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
  1142. snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
  1143. /* Line2 to Mono Out default volume, disconnect from Output Mixer */
  1144. snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
  1145. snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
  1146. if (aic3x->model == AIC3X_MODEL_3007) {
  1147. aic3x_init_3007(codec);
  1148. snd_soc_write(codec, CLASSD_CTRL, 0);
  1149. }
  1150. return 0;
  1151. }
  1152. static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
  1153. {
  1154. struct aic3x_priv *a;
  1155. list_for_each_entry(a, &reset_list, list) {
  1156. if (gpio_is_valid(aic3x->gpio_reset) &&
  1157. aic3x->gpio_reset == a->gpio_reset)
  1158. return true;
  1159. }
  1160. return false;
  1161. }
  1162. static int aic3x_probe(struct snd_soc_codec *codec)
  1163. {
  1164. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  1165. int ret, i;
  1166. INIT_LIST_HEAD(&aic3x->list);
  1167. aic3x->codec = codec;
  1168. ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
  1169. if (ret != 0) {
  1170. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  1171. return ret;
  1172. }
  1173. if (gpio_is_valid(aic3x->gpio_reset) &&
  1174. !aic3x_is_shared_reset(aic3x)) {
  1175. ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
  1176. if (ret != 0)
  1177. goto err_gpio;
  1178. gpio_direction_output(aic3x->gpio_reset, 0);
  1179. }
  1180. for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
  1181. aic3x->supplies[i].supply = aic3x_supply_names[i];
  1182. ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
  1183. aic3x->supplies);
  1184. if (ret != 0) {
  1185. dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
  1186. goto err_get;
  1187. }
  1188. for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
  1189. aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
  1190. aic3x->disable_nb[i].aic3x = aic3x;
  1191. ret = regulator_register_notifier(aic3x->supplies[i].consumer,
  1192. &aic3x->disable_nb[i].nb);
  1193. if (ret) {
  1194. dev_err(codec->dev,
  1195. "Failed to request regulator notifier: %d\n",
  1196. ret);
  1197. goto err_notif;
  1198. }
  1199. }
  1200. codec->cache_only = 1;
  1201. aic3x_init(codec);
  1202. if (aic3x->setup) {
  1203. /* setup GPIO functions */
  1204. snd_soc_write(codec, AIC3X_GPIO1_REG,
  1205. (aic3x->setup->gpio_func[0] & 0xf) << 4);
  1206. snd_soc_write(codec, AIC3X_GPIO2_REG,
  1207. (aic3x->setup->gpio_func[1] & 0xf) << 4);
  1208. }
  1209. snd_soc_add_codec_controls(codec, aic3x_snd_controls,
  1210. ARRAY_SIZE(aic3x_snd_controls));
  1211. if (aic3x->model == AIC3X_MODEL_3007)
  1212. snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
  1213. /* set mic bias voltage */
  1214. switch (aic3x->micbias_vg) {
  1215. case AIC3X_MICBIAS_2_0V:
  1216. case AIC3X_MICBIAS_2_5V:
  1217. case AIC3X_MICBIAS_AVDDV:
  1218. snd_soc_update_bits(codec, MICBIAS_CTRL,
  1219. MICBIAS_LEVEL_MASK,
  1220. (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
  1221. break;
  1222. case AIC3X_MICBIAS_OFF:
  1223. /*
  1224. * noting to do. target won't enter here. This is just to avoid
  1225. * compile time warning "warning: enumeration value
  1226. * 'AIC3X_MICBIAS_OFF' not handled in switch"
  1227. */
  1228. break;
  1229. }
  1230. aic3x_add_widgets(codec);
  1231. list_add(&aic3x->list, &reset_list);
  1232. return 0;
  1233. err_notif:
  1234. while (i--)
  1235. regulator_unregister_notifier(aic3x->supplies[i].consumer,
  1236. &aic3x->disable_nb[i].nb);
  1237. regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
  1238. err_get:
  1239. if (gpio_is_valid(aic3x->gpio_reset) &&
  1240. !aic3x_is_shared_reset(aic3x))
  1241. gpio_free(aic3x->gpio_reset);
  1242. err_gpio:
  1243. return ret;
  1244. }
  1245. static int aic3x_remove(struct snd_soc_codec *codec)
  1246. {
  1247. struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
  1248. int i;
  1249. aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1250. list_del(&aic3x->list);
  1251. if (gpio_is_valid(aic3x->gpio_reset) &&
  1252. !aic3x_is_shared_reset(aic3x)) {
  1253. gpio_set_value(aic3x->gpio_reset, 0);
  1254. gpio_free(aic3x->gpio_reset);
  1255. }
  1256. for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
  1257. regulator_unregister_notifier(aic3x->supplies[i].consumer,
  1258. &aic3x->disable_nb[i].nb);
  1259. regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
  1260. return 0;
  1261. }
  1262. static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
  1263. .set_bias_level = aic3x_set_bias_level,
  1264. .idle_bias_off = true,
  1265. .reg_cache_size = ARRAY_SIZE(aic3x_reg),
  1266. .reg_word_size = sizeof(u8),
  1267. .reg_cache_default = aic3x_reg,
  1268. .probe = aic3x_probe,
  1269. .remove = aic3x_remove,
  1270. .suspend = aic3x_suspend,
  1271. .resume = aic3x_resume,
  1272. };
  1273. /*
  1274. * AIC3X 2 wire address can be up to 4 devices with device addresses
  1275. * 0x18, 0x19, 0x1A, 0x1B
  1276. */
  1277. static const struct i2c_device_id aic3x_i2c_id[] = {
  1278. { "tlv320aic3x", AIC3X_MODEL_3X },
  1279. { "tlv320aic33", AIC3X_MODEL_33 },
  1280. { "tlv320aic3007", AIC3X_MODEL_3007 },
  1281. { "tlv320aic3106", AIC3X_MODEL_3X },
  1282. { }
  1283. };
  1284. MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
  1285. /*
  1286. * If the i2c layer weren't so broken, we could pass this kind of data
  1287. * around
  1288. */
  1289. static int aic3x_i2c_probe(struct i2c_client *i2c,
  1290. const struct i2c_device_id *id)
  1291. {
  1292. struct aic3x_pdata *pdata = i2c->dev.platform_data;
  1293. struct aic3x_priv *aic3x;
  1294. struct aic3x_setup_data *ai3x_setup;
  1295. struct device_node *np = i2c->dev.of_node;
  1296. int ret;
  1297. u32 value;
  1298. aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
  1299. if (aic3x == NULL) {
  1300. dev_err(&i2c->dev, "failed to create private data\n");
  1301. return -ENOMEM;
  1302. }
  1303. aic3x->control_type = SND_SOC_I2C;
  1304. i2c_set_clientdata(i2c, aic3x);
  1305. if (pdata) {
  1306. aic3x->gpio_reset = pdata->gpio_reset;
  1307. aic3x->setup = pdata->setup;
  1308. aic3x->micbias_vg = pdata->micbias_vg;
  1309. } else if (np) {
  1310. ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
  1311. GFP_KERNEL);
  1312. if (ai3x_setup == NULL) {
  1313. dev_err(&i2c->dev, "failed to create private data\n");
  1314. return -ENOMEM;
  1315. }
  1316. ret = of_get_named_gpio(np, "gpio-reset", 0);
  1317. if (ret >= 0)
  1318. aic3x->gpio_reset = ret;
  1319. else
  1320. aic3x->gpio_reset = -1;
  1321. if (of_property_read_u32_array(np, "ai3x-gpio-func",
  1322. ai3x_setup->gpio_func, 2) >= 0) {
  1323. aic3x->setup = ai3x_setup;
  1324. }
  1325. if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
  1326. switch (value) {
  1327. case 1 :
  1328. aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
  1329. break;
  1330. case 2 :
  1331. aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
  1332. break;
  1333. case 3 :
  1334. aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
  1335. break;
  1336. default :
  1337. aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
  1338. dev_err(&i2c->dev, "Unsuitable MicBias voltage "
  1339. "found in DT\n");
  1340. }
  1341. } else {
  1342. aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
  1343. }
  1344. } else {
  1345. aic3x->gpio_reset = -1;
  1346. }
  1347. aic3x->model = id->driver_data;
  1348. ret = snd_soc_register_codec(&i2c->dev,
  1349. &soc_codec_dev_aic3x, &aic3x_dai, 1);
  1350. return ret;
  1351. }
  1352. static int aic3x_i2c_remove(struct i2c_client *client)
  1353. {
  1354. snd_soc_unregister_codec(&client->dev);
  1355. return 0;
  1356. }
  1357. #if defined(CONFIG_OF)
  1358. static const struct of_device_id tlv320aic3x_of_match[] = {
  1359. { .compatible = "ti,tlv320aic3x", },
  1360. { .compatible = "ti,tlv320aic33" },
  1361. { .compatible = "ti,tlv320aic3007" },
  1362. { .compatible = "ti,tlv320aic3106" },
  1363. {},
  1364. };
  1365. MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
  1366. #endif
  1367. /* machine i2c codec control layer */
  1368. static struct i2c_driver aic3x_i2c_driver = {
  1369. .driver = {
  1370. .name = "tlv320aic3x-codec",
  1371. .owner = THIS_MODULE,
  1372. .of_match_table = of_match_ptr(tlv320aic3x_of_match),
  1373. },
  1374. .probe = aic3x_i2c_probe,
  1375. .remove = aic3x_i2c_remove,
  1376. .id_table = aic3x_i2c_id,
  1377. };
  1378. module_i2c_driver(aic3x_i2c_driver);
  1379. MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
  1380. MODULE_AUTHOR("Vladimir Barinov");
  1381. MODULE_LICENSE("GPL");