adau1701.c 19 KB

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  1. /*
  2. * Driver for ADAU1701 SigmaDSP processor
  3. *
  4. * Copyright 2011 Analog Devices Inc.
  5. * Author: Lars-Peter Clausen <lars@metafoo.de>
  6. * based on an inital version by Cliff Cai <cliff.cai@analog.com>
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/i2c.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/of.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/of_device.h>
  18. #include <linux/regmap.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include "sigmadsp.h"
  24. #include "adau1701.h"
  25. #define ADAU1701_DSPCTRL 0x081c
  26. #define ADAU1701_SEROCTL 0x081e
  27. #define ADAU1701_SERICTL 0x081f
  28. #define ADAU1701_AUXNPOW 0x0822
  29. #define ADAU1701_PINCONF_0 0x0820
  30. #define ADAU1701_PINCONF_1 0x0821
  31. #define ADAU1701_AUXNPOW 0x0822
  32. #define ADAU1701_OSCIPOW 0x0826
  33. #define ADAU1701_DACSET 0x0827
  34. #define ADAU1701_MAX_REGISTER 0x0828
  35. #define ADAU1701_DSPCTRL_CR (1 << 2)
  36. #define ADAU1701_DSPCTRL_DAM (1 << 3)
  37. #define ADAU1701_DSPCTRL_ADM (1 << 4)
  38. #define ADAU1701_DSPCTRL_SR_48 0x00
  39. #define ADAU1701_DSPCTRL_SR_96 0x01
  40. #define ADAU1701_DSPCTRL_SR_192 0x02
  41. #define ADAU1701_DSPCTRL_SR_MASK 0x03
  42. #define ADAU1701_SEROCTL_INV_LRCLK 0x2000
  43. #define ADAU1701_SEROCTL_INV_BCLK 0x1000
  44. #define ADAU1701_SEROCTL_MASTER 0x0800
  45. #define ADAU1701_SEROCTL_OBF16 0x0000
  46. #define ADAU1701_SEROCTL_OBF8 0x0200
  47. #define ADAU1701_SEROCTL_OBF4 0x0400
  48. #define ADAU1701_SEROCTL_OBF2 0x0600
  49. #define ADAU1701_SEROCTL_OBF_MASK 0x0600
  50. #define ADAU1701_SEROCTL_OLF1024 0x0000
  51. #define ADAU1701_SEROCTL_OLF512 0x0080
  52. #define ADAU1701_SEROCTL_OLF256 0x0100
  53. #define ADAU1701_SEROCTL_OLF_MASK 0x0180
  54. #define ADAU1701_SEROCTL_MSB_DEALY1 0x0000
  55. #define ADAU1701_SEROCTL_MSB_DEALY0 0x0004
  56. #define ADAU1701_SEROCTL_MSB_DEALY8 0x0008
  57. #define ADAU1701_SEROCTL_MSB_DEALY12 0x000c
  58. #define ADAU1701_SEROCTL_MSB_DEALY16 0x0010
  59. #define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c
  60. #define ADAU1701_SEROCTL_WORD_LEN_24 0x0000
  61. #define ADAU1701_SEROCTL_WORD_LEN_20 0x0001
  62. #define ADAU1701_SEROCTL_WORD_LEN_16 0x0010
  63. #define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003
  64. #define ADAU1701_AUXNPOW_VBPD 0x40
  65. #define ADAU1701_AUXNPOW_VRPD 0x20
  66. #define ADAU1701_SERICTL_I2S 0
  67. #define ADAU1701_SERICTL_LEFTJ 1
  68. #define ADAU1701_SERICTL_TDM 2
  69. #define ADAU1701_SERICTL_RIGHTJ_24 3
  70. #define ADAU1701_SERICTL_RIGHTJ_20 4
  71. #define ADAU1701_SERICTL_RIGHTJ_18 5
  72. #define ADAU1701_SERICTL_RIGHTJ_16 6
  73. #define ADAU1701_SERICTL_MODE_MASK 7
  74. #define ADAU1701_SERICTL_INV_BCLK BIT(3)
  75. #define ADAU1701_SERICTL_INV_LRCLK BIT(4)
  76. #define ADAU1701_OSCIPOW_OPD 0x04
  77. #define ADAU1701_DACSET_DACINIT 1
  78. #define ADAU1707_CLKDIV_UNSET (-1U)
  79. #define ADAU1701_FIRMWARE "adau1701.bin"
  80. struct adau1701 {
  81. int gpio_nreset;
  82. int gpio_pll_mode[2];
  83. unsigned int dai_fmt;
  84. unsigned int pll_clkdiv;
  85. unsigned int sysclk;
  86. struct regmap *regmap;
  87. u8 pin_config[12];
  88. };
  89. static const struct snd_kcontrol_new adau1701_controls[] = {
  90. SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0),
  91. };
  92. static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = {
  93. SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1),
  94. SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1),
  95. SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1),
  96. SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1),
  97. SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1),
  98. SND_SOC_DAPM_OUTPUT("OUT0"),
  99. SND_SOC_DAPM_OUTPUT("OUT1"),
  100. SND_SOC_DAPM_OUTPUT("OUT2"),
  101. SND_SOC_DAPM_OUTPUT("OUT3"),
  102. SND_SOC_DAPM_INPUT("IN0"),
  103. SND_SOC_DAPM_INPUT("IN1"),
  104. };
  105. static const struct snd_soc_dapm_route adau1701_dapm_routes[] = {
  106. { "OUT0", NULL, "DAC0" },
  107. { "OUT1", NULL, "DAC1" },
  108. { "OUT2", NULL, "DAC2" },
  109. { "OUT3", NULL, "DAC3" },
  110. { "ADC", NULL, "IN0" },
  111. { "ADC", NULL, "IN1" },
  112. };
  113. static unsigned int adau1701_register_size(struct device *dev,
  114. unsigned int reg)
  115. {
  116. switch (reg) {
  117. case ADAU1701_PINCONF_0:
  118. case ADAU1701_PINCONF_1:
  119. return 3;
  120. case ADAU1701_DSPCTRL:
  121. case ADAU1701_SEROCTL:
  122. case ADAU1701_AUXNPOW:
  123. case ADAU1701_OSCIPOW:
  124. case ADAU1701_DACSET:
  125. return 2;
  126. case ADAU1701_SERICTL:
  127. return 1;
  128. }
  129. dev_err(dev, "Unsupported register address: %d\n", reg);
  130. return 0;
  131. }
  132. static bool adau1701_volatile_reg(struct device *dev, unsigned int reg)
  133. {
  134. switch (reg) {
  135. case ADAU1701_DACSET:
  136. return true;
  137. default:
  138. return false;
  139. }
  140. }
  141. static int adau1701_reg_write(void *context, unsigned int reg,
  142. unsigned int value)
  143. {
  144. struct i2c_client *client = context;
  145. unsigned int i;
  146. unsigned int size;
  147. uint8_t buf[5];
  148. int ret;
  149. size = adau1701_register_size(&client->dev, reg);
  150. if (size == 0)
  151. return -EINVAL;
  152. buf[0] = reg >> 8;
  153. buf[1] = reg & 0xff;
  154. for (i = size + 1; i >= 2; --i) {
  155. buf[i] = value;
  156. value >>= 8;
  157. }
  158. ret = i2c_master_send(client, buf, size + 2);
  159. if (ret == size + 2)
  160. return 0;
  161. else if (ret < 0)
  162. return ret;
  163. else
  164. return -EIO;
  165. }
  166. static int adau1701_reg_read(void *context, unsigned int reg,
  167. unsigned int *value)
  168. {
  169. int ret;
  170. unsigned int i;
  171. unsigned int size;
  172. uint8_t send_buf[2], recv_buf[3];
  173. struct i2c_client *client = context;
  174. struct i2c_msg msgs[2];
  175. size = adau1701_register_size(&client->dev, reg);
  176. if (size == 0)
  177. return -EINVAL;
  178. send_buf[0] = reg >> 8;
  179. send_buf[1] = reg & 0xff;
  180. msgs[0].addr = client->addr;
  181. msgs[0].len = sizeof(send_buf);
  182. msgs[0].buf = send_buf;
  183. msgs[0].flags = 0;
  184. msgs[1].addr = client->addr;
  185. msgs[1].len = size;
  186. msgs[1].buf = recv_buf;
  187. msgs[1].flags = I2C_M_RD;
  188. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  189. if (ret < 0)
  190. return ret;
  191. else if (ret != ARRAY_SIZE(msgs))
  192. return -EIO;
  193. *value = 0;
  194. for (i = 0; i < size; i++)
  195. *value |= recv_buf[i] << (i * 8);
  196. return 0;
  197. }
  198. static int adau1701_reset(struct snd_soc_codec *codec, unsigned int clkdiv)
  199. {
  200. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  201. struct i2c_client *client = to_i2c_client(codec->dev);
  202. int ret;
  203. if (clkdiv != ADAU1707_CLKDIV_UNSET &&
  204. gpio_is_valid(adau1701->gpio_pll_mode[0]) &&
  205. gpio_is_valid(adau1701->gpio_pll_mode[1])) {
  206. switch (clkdiv) {
  207. case 64:
  208. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
  209. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
  210. break;
  211. case 256:
  212. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
  213. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
  214. break;
  215. case 384:
  216. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
  217. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
  218. break;
  219. case 0: /* fallback */
  220. case 512:
  221. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
  222. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
  223. break;
  224. }
  225. }
  226. adau1701->pll_clkdiv = clkdiv;
  227. if (gpio_is_valid(adau1701->gpio_nreset)) {
  228. gpio_set_value_cansleep(adau1701->gpio_nreset, 0);
  229. /* minimum reset time is 20ns */
  230. udelay(1);
  231. gpio_set_value_cansleep(adau1701->gpio_nreset, 1);
  232. /* power-up time may be as long as 85ms */
  233. mdelay(85);
  234. }
  235. /*
  236. * Postpone the firmware download to a point in time when we
  237. * know the correct PLL setup
  238. */
  239. if (clkdiv != ADAU1707_CLKDIV_UNSET) {
  240. ret = process_sigma_firmware(client, ADAU1701_FIRMWARE);
  241. if (ret) {
  242. dev_warn(codec->dev, "Failed to load firmware\n");
  243. return ret;
  244. }
  245. }
  246. regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT);
  247. regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR);
  248. regcache_mark_dirty(adau1701->regmap);
  249. regcache_sync(adau1701->regmap);
  250. return 0;
  251. }
  252. static int adau1701_set_capture_pcm_format(struct snd_soc_codec *codec,
  253. snd_pcm_format_t format)
  254. {
  255. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  256. unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK;
  257. unsigned int val;
  258. switch (format) {
  259. case SNDRV_PCM_FORMAT_S16_LE:
  260. val = ADAU1701_SEROCTL_WORD_LEN_16;
  261. break;
  262. case SNDRV_PCM_FORMAT_S20_3LE:
  263. val = ADAU1701_SEROCTL_WORD_LEN_20;
  264. break;
  265. case SNDRV_PCM_FORMAT_S24_LE:
  266. val = ADAU1701_SEROCTL_WORD_LEN_24;
  267. break;
  268. default:
  269. return -EINVAL;
  270. }
  271. if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) {
  272. switch (format) {
  273. case SNDRV_PCM_FORMAT_S16_LE:
  274. val |= ADAU1701_SEROCTL_MSB_DEALY16;
  275. break;
  276. case SNDRV_PCM_FORMAT_S20_3LE:
  277. val |= ADAU1701_SEROCTL_MSB_DEALY12;
  278. break;
  279. case SNDRV_PCM_FORMAT_S24_LE:
  280. val |= ADAU1701_SEROCTL_MSB_DEALY8;
  281. break;
  282. }
  283. mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK;
  284. }
  285. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val);
  286. return 0;
  287. }
  288. static int adau1701_set_playback_pcm_format(struct snd_soc_codec *codec,
  289. snd_pcm_format_t format)
  290. {
  291. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  292. unsigned int val;
  293. if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
  294. return 0;
  295. switch (format) {
  296. case SNDRV_PCM_FORMAT_S16_LE:
  297. val = ADAU1701_SERICTL_RIGHTJ_16;
  298. break;
  299. case SNDRV_PCM_FORMAT_S20_3LE:
  300. val = ADAU1701_SERICTL_RIGHTJ_20;
  301. break;
  302. case SNDRV_PCM_FORMAT_S24_LE:
  303. val = ADAU1701_SERICTL_RIGHTJ_24;
  304. break;
  305. default:
  306. return -EINVAL;
  307. }
  308. regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL,
  309. ADAU1701_SERICTL_MODE_MASK, val);
  310. return 0;
  311. }
  312. static int adau1701_hw_params(struct snd_pcm_substream *substream,
  313. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  314. {
  315. struct snd_soc_codec *codec = dai->codec;
  316. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  317. unsigned int clkdiv = adau1701->sysclk / params_rate(params);
  318. snd_pcm_format_t format;
  319. unsigned int val;
  320. int ret;
  321. /*
  322. * If the mclk/lrclk ratio changes, the chip needs updated PLL
  323. * mode GPIO settings, and a full reset cycle, including a new
  324. * firmware upload.
  325. */
  326. if (clkdiv != adau1701->pll_clkdiv) {
  327. ret = adau1701_reset(codec, clkdiv);
  328. if (ret < 0)
  329. return ret;
  330. }
  331. switch (params_rate(params)) {
  332. case 192000:
  333. val = ADAU1701_DSPCTRL_SR_192;
  334. break;
  335. case 96000:
  336. val = ADAU1701_DSPCTRL_SR_96;
  337. break;
  338. case 48000:
  339. val = ADAU1701_DSPCTRL_SR_48;
  340. break;
  341. default:
  342. return -EINVAL;
  343. }
  344. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  345. ADAU1701_DSPCTRL_SR_MASK, val);
  346. format = params_format(params);
  347. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  348. return adau1701_set_playback_pcm_format(codec, format);
  349. else
  350. return adau1701_set_capture_pcm_format(codec, format);
  351. }
  352. static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
  353. unsigned int fmt)
  354. {
  355. struct snd_soc_codec *codec = codec_dai->codec;
  356. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  357. unsigned int serictl = 0x00, seroctl = 0x00;
  358. bool invert_lrclk;
  359. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  360. case SND_SOC_DAIFMT_CBM_CFM:
  361. /* master, 64-bits per sample, 1 frame per sample */
  362. seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
  363. | ADAU1701_SEROCTL_OLF1024;
  364. break;
  365. case SND_SOC_DAIFMT_CBS_CFS:
  366. break;
  367. default:
  368. return -EINVAL;
  369. }
  370. /* clock inversion */
  371. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  372. case SND_SOC_DAIFMT_NB_NF:
  373. invert_lrclk = false;
  374. break;
  375. case SND_SOC_DAIFMT_NB_IF:
  376. invert_lrclk = true;
  377. break;
  378. case SND_SOC_DAIFMT_IB_NF:
  379. invert_lrclk = false;
  380. serictl |= ADAU1701_SERICTL_INV_BCLK;
  381. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  382. break;
  383. case SND_SOC_DAIFMT_IB_IF:
  384. invert_lrclk = true;
  385. serictl |= ADAU1701_SERICTL_INV_BCLK;
  386. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  387. break;
  388. default:
  389. return -EINVAL;
  390. }
  391. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  392. case SND_SOC_DAIFMT_I2S:
  393. break;
  394. case SND_SOC_DAIFMT_LEFT_J:
  395. serictl |= ADAU1701_SERICTL_LEFTJ;
  396. seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
  397. invert_lrclk = !invert_lrclk;
  398. break;
  399. case SND_SOC_DAIFMT_RIGHT_J:
  400. serictl |= ADAU1701_SERICTL_RIGHTJ_24;
  401. seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
  402. invert_lrclk = !invert_lrclk;
  403. break;
  404. default:
  405. return -EINVAL;
  406. }
  407. if (invert_lrclk) {
  408. seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
  409. serictl |= ADAU1701_SERICTL_INV_LRCLK;
  410. }
  411. adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  412. regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
  413. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
  414. ~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
  415. return 0;
  416. }
  417. static int adau1701_set_bias_level(struct snd_soc_codec *codec,
  418. enum snd_soc_bias_level level)
  419. {
  420. unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD;
  421. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  422. switch (level) {
  423. case SND_SOC_BIAS_ON:
  424. break;
  425. case SND_SOC_BIAS_PREPARE:
  426. break;
  427. case SND_SOC_BIAS_STANDBY:
  428. /* Enable VREF and VREF buffer */
  429. regmap_update_bits(adau1701->regmap,
  430. ADAU1701_AUXNPOW, mask, 0x00);
  431. break;
  432. case SND_SOC_BIAS_OFF:
  433. /* Disable VREF and VREF buffer */
  434. regmap_update_bits(adau1701->regmap,
  435. ADAU1701_AUXNPOW, mask, mask);
  436. break;
  437. }
  438. codec->dapm.bias_level = level;
  439. return 0;
  440. }
  441. static int adau1701_digital_mute(struct snd_soc_dai *dai, int mute)
  442. {
  443. struct snd_soc_codec *codec = dai->codec;
  444. unsigned int mask = ADAU1701_DSPCTRL_DAM;
  445. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  446. unsigned int val;
  447. if (mute)
  448. val = 0;
  449. else
  450. val = mask;
  451. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val);
  452. return 0;
  453. }
  454. static int adau1701_set_sysclk(struct snd_soc_codec *codec, int clk_id,
  455. int source, unsigned int freq, int dir)
  456. {
  457. unsigned int val;
  458. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  459. switch (clk_id) {
  460. case ADAU1701_CLK_SRC_OSC:
  461. val = 0x0;
  462. break;
  463. case ADAU1701_CLK_SRC_MCLK:
  464. val = ADAU1701_OSCIPOW_OPD;
  465. break;
  466. default:
  467. return -EINVAL;
  468. }
  469. regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW,
  470. ADAU1701_OSCIPOW_OPD, val);
  471. adau1701->sysclk = freq;
  472. return 0;
  473. }
  474. #define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
  475. SNDRV_PCM_RATE_192000)
  476. #define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  477. SNDRV_PCM_FMTBIT_S24_LE)
  478. static const struct snd_soc_dai_ops adau1701_dai_ops = {
  479. .set_fmt = adau1701_set_dai_fmt,
  480. .hw_params = adau1701_hw_params,
  481. .digital_mute = adau1701_digital_mute,
  482. };
  483. static struct snd_soc_dai_driver adau1701_dai = {
  484. .name = "adau1701",
  485. .playback = {
  486. .stream_name = "Playback",
  487. .channels_min = 2,
  488. .channels_max = 8,
  489. .rates = ADAU1701_RATES,
  490. .formats = ADAU1701_FORMATS,
  491. },
  492. .capture = {
  493. .stream_name = "Capture",
  494. .channels_min = 2,
  495. .channels_max = 8,
  496. .rates = ADAU1701_RATES,
  497. .formats = ADAU1701_FORMATS,
  498. },
  499. .ops = &adau1701_dai_ops,
  500. .symmetric_rates = 1,
  501. };
  502. #ifdef CONFIG_OF
  503. static const struct of_device_id adau1701_dt_ids[] = {
  504. { .compatible = "adi,adau1701", },
  505. { }
  506. };
  507. MODULE_DEVICE_TABLE(of, adau1701_dt_ids);
  508. #endif
  509. static int adau1701_probe(struct snd_soc_codec *codec)
  510. {
  511. int i, ret;
  512. unsigned int val;
  513. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  514. /*
  515. * Let the pll_clkdiv variable default to something that won't happen
  516. * at runtime. That way, we can postpone the firmware download from
  517. * adau1701_reset() to a point in time when we know the correct PLL
  518. * mode parameters.
  519. */
  520. adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET;
  521. /* initalize with pre-configured pll mode settings */
  522. ret = adau1701_reset(codec, adau1701->pll_clkdiv);
  523. if (ret < 0)
  524. return ret;
  525. /* set up pin config */
  526. val = 0;
  527. for (i = 0; i < 6; i++)
  528. val |= adau1701->pin_config[i] << (i * 4);
  529. regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val);
  530. val = 0;
  531. for (i = 0; i < 6; i++)
  532. val |= adau1701->pin_config[i + 6] << (i * 4);
  533. regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val);
  534. return 0;
  535. }
  536. static struct snd_soc_codec_driver adau1701_codec_drv = {
  537. .probe = adau1701_probe,
  538. .set_bias_level = adau1701_set_bias_level,
  539. .idle_bias_off = true,
  540. .controls = adau1701_controls,
  541. .num_controls = ARRAY_SIZE(adau1701_controls),
  542. .dapm_widgets = adau1701_dapm_widgets,
  543. .num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets),
  544. .dapm_routes = adau1701_dapm_routes,
  545. .num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes),
  546. .set_sysclk = adau1701_set_sysclk,
  547. };
  548. static const struct regmap_config adau1701_regmap = {
  549. .reg_bits = 16,
  550. .val_bits = 32,
  551. .max_register = ADAU1701_MAX_REGISTER,
  552. .cache_type = REGCACHE_RBTREE,
  553. .volatile_reg = adau1701_volatile_reg,
  554. .reg_write = adau1701_reg_write,
  555. .reg_read = adau1701_reg_read,
  556. };
  557. static int adau1701_i2c_probe(struct i2c_client *client,
  558. const struct i2c_device_id *id)
  559. {
  560. struct adau1701 *adau1701;
  561. struct device *dev = &client->dev;
  562. int gpio_nreset = -EINVAL;
  563. int gpio_pll_mode[2] = { -EINVAL, -EINVAL };
  564. int ret;
  565. adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL);
  566. if (!adau1701)
  567. return -ENOMEM;
  568. adau1701->regmap = devm_regmap_init(dev, NULL, client,
  569. &adau1701_regmap);
  570. if (IS_ERR(adau1701->regmap))
  571. return PTR_ERR(adau1701->regmap);
  572. if (dev->of_node) {
  573. gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0);
  574. if (gpio_nreset < 0 && gpio_nreset != -ENOENT)
  575. return gpio_nreset;
  576. gpio_pll_mode[0] = of_get_named_gpio(dev->of_node,
  577. "adi,pll-mode-gpios", 0);
  578. if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT)
  579. return gpio_pll_mode[0];
  580. gpio_pll_mode[1] = of_get_named_gpio(dev->of_node,
  581. "adi,pll-mode-gpios", 1);
  582. if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT)
  583. return gpio_pll_mode[1];
  584. of_property_read_u32(dev->of_node, "adi,pll-clkdiv",
  585. &adau1701->pll_clkdiv);
  586. of_property_read_u8_array(dev->of_node, "adi,pin-config",
  587. adau1701->pin_config,
  588. ARRAY_SIZE(adau1701->pin_config));
  589. }
  590. if (gpio_is_valid(gpio_nreset)) {
  591. ret = devm_gpio_request_one(dev, gpio_nreset, GPIOF_OUT_INIT_LOW,
  592. "ADAU1701 Reset");
  593. if (ret < 0)
  594. return ret;
  595. }
  596. if (gpio_is_valid(gpio_pll_mode[0]) &&
  597. gpio_is_valid(gpio_pll_mode[1])) {
  598. ret = devm_gpio_request_one(dev, gpio_pll_mode[0],
  599. GPIOF_OUT_INIT_LOW,
  600. "ADAU1701 PLL mode 0");
  601. if (ret < 0)
  602. return ret;
  603. ret = devm_gpio_request_one(dev, gpio_pll_mode[1],
  604. GPIOF_OUT_INIT_LOW,
  605. "ADAU1701 PLL mode 1");
  606. if (ret < 0)
  607. return ret;
  608. }
  609. adau1701->gpio_nreset = gpio_nreset;
  610. adau1701->gpio_pll_mode[0] = gpio_pll_mode[0];
  611. adau1701->gpio_pll_mode[1] = gpio_pll_mode[1];
  612. i2c_set_clientdata(client, adau1701);
  613. ret = snd_soc_register_codec(&client->dev, &adau1701_codec_drv,
  614. &adau1701_dai, 1);
  615. return ret;
  616. }
  617. static int adau1701_i2c_remove(struct i2c_client *client)
  618. {
  619. snd_soc_unregister_codec(&client->dev);
  620. return 0;
  621. }
  622. static const struct i2c_device_id adau1701_i2c_id[] = {
  623. { "adau1401", 0 },
  624. { "adau1401a", 0 },
  625. { "adau1701", 0 },
  626. { "adau1702", 0 },
  627. { }
  628. };
  629. MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id);
  630. static struct i2c_driver adau1701_i2c_driver = {
  631. .driver = {
  632. .name = "adau1701",
  633. .owner = THIS_MODULE,
  634. .of_match_table = of_match_ptr(adau1701_dt_ids),
  635. },
  636. .probe = adau1701_i2c_probe,
  637. .remove = adau1701_i2c_remove,
  638. .id_table = adau1701_i2c_id,
  639. };
  640. module_i2c_driver(adau1701_i2c_driver);
  641. MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver");
  642. MODULE_AUTHOR("Cliff Cai <cliff.cai@analog.com>");
  643. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  644. MODULE_LICENSE("GPL");