kirkwood.dtsi 6.1 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,kirkwood";
  5. interrupt-parent = <&intc>;
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "marvell,feroceon";
  12. reg = <0>;
  13. clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  14. clock-names = "cpu_clk", "ddrclk", "powersave";
  15. };
  16. };
  17. aliases {
  18. gpio0 = &gpio0;
  19. gpio1 = &gpio1;
  20. };
  21. mbus {
  22. compatible = "marvell,kirkwood-mbus", "simple-bus";
  23. #address-cells = <2>;
  24. #size-cells = <1>;
  25. controller = <&mbusc>;
  26. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
  27. pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
  28. };
  29. ocp@f1000000 {
  30. compatible = "simple-bus";
  31. ranges = <0x00000000 0xf1000000 0x0100000
  32. 0xf4000000 0xf4000000 0x0000400
  33. 0xf5000000 0xf5000000 0x0000400>;
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. mbusc: mbus-controller@20000 {
  37. compatible = "marvell,mbus-controller";
  38. reg = <0x20000 0x80>, <0x1500 0x20>;
  39. };
  40. timer: timer@20300 {
  41. compatible = "marvell,orion-timer";
  42. reg = <0x20300 0x20>;
  43. interrupt-parent = <&bridge_intc>;
  44. interrupts = <1>, <2>;
  45. clocks = <&core_clk 0>;
  46. };
  47. intc: main-interrupt-ctrl@20200 {
  48. compatible = "marvell,orion-intc";
  49. interrupt-controller;
  50. #interrupt-cells = <1>;
  51. reg = <0x20200 0x10>, <0x20210 0x10>;
  52. };
  53. bridge_intc: bridge-interrupt-ctrl@20110 {
  54. compatible = "marvell,orion-bridge-intc";
  55. interrupt-controller;
  56. #interrupt-cells = <1>;
  57. reg = <0x20110 0x8>;
  58. interrupts = <1>;
  59. marvell,#interrupts = <6>;
  60. };
  61. core_clk: core-clocks@10030 {
  62. compatible = "marvell,kirkwood-core-clock";
  63. reg = <0x10030 0x4>;
  64. #clock-cells = <1>;
  65. };
  66. gpio0: gpio@10100 {
  67. compatible = "marvell,orion-gpio";
  68. #gpio-cells = <2>;
  69. gpio-controller;
  70. reg = <0x10100 0x40>;
  71. ngpios = <32>;
  72. interrupt-controller;
  73. #interrupt-cells = <2>;
  74. interrupts = <35>, <36>, <37>, <38>;
  75. clocks = <&gate_clk 7>;
  76. };
  77. gpio1: gpio@10140 {
  78. compatible = "marvell,orion-gpio";
  79. #gpio-cells = <2>;
  80. gpio-controller;
  81. reg = <0x10140 0x40>;
  82. ngpios = <18>;
  83. interrupt-controller;
  84. #interrupt-cells = <2>;
  85. interrupts = <39>, <40>, <41>;
  86. clocks = <&gate_clk 7>;
  87. };
  88. serial@12000 {
  89. compatible = "ns16550a";
  90. reg = <0x12000 0x100>;
  91. reg-shift = <2>;
  92. interrupts = <33>;
  93. clocks = <&gate_clk 7>;
  94. status = "disabled";
  95. };
  96. serial@12100 {
  97. compatible = "ns16550a";
  98. reg = <0x12100 0x100>;
  99. reg-shift = <2>;
  100. interrupts = <34>;
  101. clocks = <&gate_clk 7>;
  102. status = "disabled";
  103. };
  104. spi@10600 {
  105. compatible = "marvell,orion-spi";
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. cell-index = <0>;
  109. interrupts = <23>;
  110. reg = <0x10600 0x28>;
  111. clocks = <&gate_clk 7>;
  112. status = "disabled";
  113. };
  114. gate_clk: clock-gating-control@2011c {
  115. compatible = "marvell,kirkwood-gating-clock";
  116. reg = <0x2011c 0x4>;
  117. clocks = <&core_clk 0>;
  118. #clock-cells = <1>;
  119. };
  120. wdt: watchdog-timer@20300 {
  121. compatible = "marvell,orion-wdt";
  122. reg = <0x20300 0x28>;
  123. interrupt-parent = <&bridge_intc>;
  124. interrupts = <3>;
  125. clocks = <&gate_clk 7>;
  126. status = "okay";
  127. };
  128. xor@60800 {
  129. compatible = "marvell,orion-xor";
  130. reg = <0x60800 0x100
  131. 0x60A00 0x100>;
  132. status = "okay";
  133. clocks = <&gate_clk 8>;
  134. xor00 {
  135. interrupts = <5>;
  136. dmacap,memcpy;
  137. dmacap,xor;
  138. };
  139. xor01 {
  140. interrupts = <6>;
  141. dmacap,memcpy;
  142. dmacap,xor;
  143. dmacap,memset;
  144. };
  145. };
  146. xor@60900 {
  147. compatible = "marvell,orion-xor";
  148. reg = <0x60900 0x100
  149. 0x60B00 0x100>;
  150. status = "okay";
  151. clocks = <&gate_clk 16>;
  152. xor00 {
  153. interrupts = <7>;
  154. dmacap,memcpy;
  155. dmacap,xor;
  156. };
  157. xor01 {
  158. interrupts = <8>;
  159. dmacap,memcpy;
  160. dmacap,xor;
  161. dmacap,memset;
  162. };
  163. };
  164. ehci@50000 {
  165. compatible = "marvell,orion-ehci";
  166. reg = <0x50000 0x1000>;
  167. interrupts = <19>;
  168. clocks = <&gate_clk 3>;
  169. status = "okay";
  170. };
  171. nand@3000000 {
  172. #address-cells = <1>;
  173. #size-cells = <1>;
  174. cle = <0>;
  175. ale = <1>;
  176. bank-width = <1>;
  177. compatible = "marvell,orion-nand";
  178. reg = <0xf4000000 0x400>;
  179. chip-delay = <25>;
  180. /* set partition map and/or chip-delay in board dts */
  181. clocks = <&gate_clk 7>;
  182. status = "disabled";
  183. };
  184. i2c@11000 {
  185. compatible = "marvell,mv64xxx-i2c";
  186. reg = <0x11000 0x20>;
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. interrupts = <29>;
  190. clock-frequency = <100000>;
  191. clocks = <&gate_clk 7>;
  192. status = "disabled";
  193. };
  194. crypto@30000 {
  195. compatible = "marvell,orion-crypto";
  196. reg = <0x30000 0x10000>,
  197. <0xf5000000 0x800>;
  198. reg-names = "regs", "sram";
  199. interrupts = <22>;
  200. clocks = <&gate_clk 17>;
  201. status = "okay";
  202. };
  203. mdio: mdio-bus@72004 {
  204. compatible = "marvell,orion-mdio";
  205. #address-cells = <1>;
  206. #size-cells = <0>;
  207. reg = <0x72004 0x84>;
  208. interrupts = <46>;
  209. clocks = <&gate_clk 0>;
  210. status = "disabled";
  211. /* add phy nodes in board file */
  212. };
  213. eth0: ethernet-controller@72000 {
  214. compatible = "marvell,kirkwood-eth";
  215. #address-cells = <1>;
  216. #size-cells = <0>;
  217. reg = <0x72000 0x4000>;
  218. clocks = <&gate_clk 0>;
  219. marvell,tx-checksum-limit = <1600>;
  220. status = "disabled";
  221. ethernet0-port@0 {
  222. device_type = "network";
  223. compatible = "marvell,kirkwood-eth-port";
  224. reg = <0>;
  225. interrupts = <11>;
  226. /* overwrite MAC address in bootloader */
  227. local-mac-address = [00 00 00 00 00 00];
  228. /* set phy-handle property in board file */
  229. };
  230. };
  231. eth1: ethernet-controller@76000 {
  232. compatible = "marvell,kirkwood-eth";
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. reg = <0x76000 0x4000>;
  236. clocks = <&gate_clk 19>;
  237. marvell,tx-checksum-limit = <1600>;
  238. status = "disabled";
  239. ethernet1-port@0 {
  240. device_type = "network";
  241. compatible = "marvell,kirkwood-eth-port";
  242. reg = <0>;
  243. interrupts = <15>;
  244. /* overwrite MAC address in bootloader */
  245. local-mac-address = [00 00 00 00 00 00];
  246. /* set phy-handle property in board file */
  247. };
  248. };
  249. };
  250. };