at91sam9x5.dtsi 26 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. #include "skeleton.dtsi"
  12. #include <dt-bindings/dma/at91.h>
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/gpio/gpio.h>
  16. / {
  17. model = "Atmel AT91SAM9x5 family SoC";
  18. compatible = "atmel,at91sam9x5";
  19. interrupt-parent = <&aic>;
  20. aliases {
  21. serial0 = &dbgu;
  22. serial1 = &usart0;
  23. serial2 = &usart1;
  24. serial3 = &usart2;
  25. gpio0 = &pioA;
  26. gpio1 = &pioB;
  27. gpio2 = &pioC;
  28. gpio3 = &pioD;
  29. tcb0 = &tcb0;
  30. tcb1 = &tcb1;
  31. i2c0 = &i2c0;
  32. i2c1 = &i2c1;
  33. i2c2 = &i2c2;
  34. ssc0 = &ssc0;
  35. };
  36. cpus {
  37. #address-cells = <0>;
  38. #size-cells = <0>;
  39. cpu {
  40. compatible = "arm,arm926ej-s";
  41. device_type = "cpu";
  42. };
  43. };
  44. memory {
  45. reg = <0x20000000 0x10000000>;
  46. };
  47. ahb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. apb {
  53. compatible = "simple-bus";
  54. #address-cells = <1>;
  55. #size-cells = <1>;
  56. ranges;
  57. aic: interrupt-controller@fffff000 {
  58. #interrupt-cells = <3>;
  59. compatible = "atmel,at91rm9200-aic";
  60. interrupt-controller;
  61. reg = <0xfffff000 0x200>;
  62. atmel,external-irqs = <31>;
  63. };
  64. ramc0: ramc@ffffe800 {
  65. compatible = "atmel,at91sam9g45-ddramc";
  66. reg = <0xffffe800 0x200>;
  67. };
  68. pmc: pmc@fffffc00 {
  69. compatible = "atmel,at91rm9200-pmc";
  70. reg = <0xfffffc00 0x100>;
  71. };
  72. rstc@fffffe00 {
  73. compatible = "atmel,at91sam9g45-rstc";
  74. reg = <0xfffffe00 0x10>;
  75. };
  76. shdwc@fffffe10 {
  77. compatible = "atmel,at91sam9x5-shdwc";
  78. reg = <0xfffffe10 0x10>;
  79. };
  80. pit: timer@fffffe30 {
  81. compatible = "atmel,at91sam9260-pit";
  82. reg = <0xfffffe30 0xf>;
  83. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  84. };
  85. tcb0: timer@f8008000 {
  86. compatible = "atmel,at91sam9x5-tcb";
  87. reg = <0xf8008000 0x100>;
  88. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  89. };
  90. tcb1: timer@f800c000 {
  91. compatible = "atmel,at91sam9x5-tcb";
  92. reg = <0xf800c000 0x100>;
  93. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  94. };
  95. dma0: dma-controller@ffffec00 {
  96. compatible = "atmel,at91sam9g45-dma";
  97. reg = <0xffffec00 0x200>;
  98. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  99. #dma-cells = <2>;
  100. };
  101. dma1: dma-controller@ffffee00 {
  102. compatible = "atmel,at91sam9g45-dma";
  103. reg = <0xffffee00 0x200>;
  104. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
  105. #dma-cells = <2>;
  106. };
  107. pinctrl@fffff400 {
  108. #address-cells = <1>;
  109. #size-cells = <1>;
  110. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  111. ranges = <0xfffff400 0xfffff400 0x800>;
  112. /* shared pinctrl settings */
  113. dbgu {
  114. pinctrl_dbgu: dbgu-0 {
  115. atmel,pins =
  116. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  117. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph A with pullup */
  118. };
  119. };
  120. usart0 {
  121. pinctrl_usart0: usart0-0 {
  122. atmel,pins =
  123. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
  124. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA1 periph A */
  125. };
  126. pinctrl_usart0_rts: usart0_rts-0 {
  127. atmel,pins =
  128. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
  129. };
  130. pinctrl_usart0_cts: usart0_cts-0 {
  131. atmel,pins =
  132. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
  133. };
  134. pinctrl_usart0_sck: usart0_sck-0 {
  135. atmel,pins =
  136. <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
  137. };
  138. };
  139. usart1 {
  140. pinctrl_usart1: usart1-0 {
  141. atmel,pins =
  142. <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
  143. AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
  144. };
  145. pinctrl_usart1_rts: usart1_rts-0 {
  146. atmel,pins =
  147. <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
  148. };
  149. pinctrl_usart1_cts: usart1_cts-0 {
  150. atmel,pins =
  151. <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
  152. };
  153. pinctrl_usart1_sck: usart1_sck-0 {
  154. atmel,pins =
  155. <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
  156. };
  157. };
  158. usart2 {
  159. pinctrl_usart2: usart2-0 {
  160. atmel,pins =
  161. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  162. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
  163. };
  164. pinctrl_usart2_rts: usart2_rts-0 {
  165. atmel,pins =
  166. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  167. };
  168. pinctrl_usart2_cts: usart2_cts-0 {
  169. atmel,pins =
  170. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  171. };
  172. pinctrl_usart2_sck: usart2_sck-0 {
  173. atmel,pins =
  174. <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
  175. };
  176. };
  177. usart3 {
  178. pinctrl_usart3: usart3-0 {
  179. atmel,pins =
  180. <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC22 periph B with pullup */
  181. AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
  182. };
  183. pinctrl_usart3_rts: usart3_rts-0 {
  184. atmel,pins =
  185. <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
  186. };
  187. pinctrl_usart3_cts: usart3_cts-0 {
  188. atmel,pins =
  189. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
  190. };
  191. pinctrl_usart3_sck: usart3_sck-0 {
  192. atmel,pins =
  193. <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
  194. };
  195. };
  196. uart0 {
  197. pinctrl_uart0: uart0-0 {
  198. atmel,pins =
  199. <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC8 periph C */
  200. AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC9 periph C with pullup */
  201. };
  202. };
  203. uart1 {
  204. pinctrl_uart1: uart1-0 {
  205. atmel,pins =
  206. <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC16 periph C */
  207. AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>; /* PC17 periph C with pullup */
  208. };
  209. };
  210. nand {
  211. pinctrl_nand: nand-0 {
  212. atmel,pins =
  213. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A Read Enable */
  214. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A Write Enable */
  215. AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD2 periph A Address Latch Enable */
  216. AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A Command Latch Enable */
  217. AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD4 gpio Chip Enable pin pull_up */
  218. AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY/BUSY pin pull_up */
  219. AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD6 periph A Data bit 0 */
  220. AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD7 periph A Data bit 1 */
  221. AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD8 periph A Data bit 2 */
  222. AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A Data bit 3 */
  223. AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A Data bit 4 */
  224. AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A Data bit 5 */
  225. AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD12 periph A Data bit 6 */
  226. AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
  227. };
  228. pinctrl_nand_16bits: nand_16bits-0 {
  229. atmel,pins =
  230. <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A Data bit 8 */
  231. AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A Data bit 9 */
  232. AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD16 periph A Data bit 10 */
  233. AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A Data bit 11 */
  234. AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD18 periph A Data bit 12 */
  235. AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD19 periph A Data bit 13 */
  236. AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD20 periph A Data bit 14 */
  237. AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
  238. };
  239. };
  240. macb0 {
  241. pinctrl_macb0_rmii: macb0_rmii-0 {
  242. atmel,pins =
  243. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */
  244. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */
  245. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB2 periph A */
  246. AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */
  247. AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
  248. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB5 periph A */
  249. AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
  250. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
  251. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
  252. AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
  253. };
  254. pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
  255. atmel,pins =
  256. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB8 periph A */
  257. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A */
  258. AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  259. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */
  260. AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
  261. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */
  262. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
  263. AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
  264. };
  265. };
  266. mmc0 {
  267. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  268. atmel,pins =
  269. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  270. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  271. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
  272. };
  273. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  274. atmel,pins =
  275. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  276. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  277. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  278. };
  279. };
  280. mmc1 {
  281. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  282. atmel,pins =
  283. <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA13 periph B */
  284. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
  285. AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA11 periph B with pullup */
  286. };
  287. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  288. atmel,pins =
  289. <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
  290. AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
  291. AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA4 periph B with pullup */
  292. };
  293. };
  294. ssc0 {
  295. pinctrl_ssc0_tx: ssc0_tx-0 {
  296. atmel,pins =
  297. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  298. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  299. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
  300. };
  301. pinctrl_ssc0_rx: ssc0_rx-0 {
  302. atmel,pins =
  303. <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  304. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  305. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  306. };
  307. };
  308. spi0 {
  309. pinctrl_spi0: spi0-0 {
  310. atmel,pins =
  311. <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
  312. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
  313. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
  314. };
  315. };
  316. spi1 {
  317. pinctrl_spi1: spi1-0 {
  318. atmel,pins =
  319. <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
  320. AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
  321. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
  322. };
  323. };
  324. i2c0 {
  325. pinctrl_i2c0: i2c0-0 {
  326. atmel,pins =
  327. <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A I2C0 data */
  328. AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
  329. };
  330. };
  331. i2c1 {
  332. pinctrl_i2c1: i2c1-0 {
  333. atmel,pins =
  334. <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC0 periph C I2C1 data */
  335. AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC1 periph C I2C1 clock */
  336. };
  337. };
  338. i2c2 {
  339. pinctrl_i2c2: i2c2-0 {
  340. atmel,pins =
  341. <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B I2C2 data */
  342. AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B I2C2 clock */
  343. };
  344. };
  345. i2c_gpio0 {
  346. pinctrl_i2c_gpio0: i2c_gpio0-0 {
  347. atmel,pins =
  348. <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
  349. AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA31 gpio multidrive I2C0 clock */
  350. };
  351. };
  352. i2c_gpio1 {
  353. pinctrl_i2c_gpio1: i2c_gpio1-0 {
  354. atmel,pins =
  355. <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PC0 gpio multidrive I2C1 data */
  356. AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PC1 gpio multidrive I2C1 clock */
  357. };
  358. };
  359. i2c_gpio2 {
  360. pinctrl_i2c_gpio2: i2c_gpio2-0 {
  361. atmel,pins =
  362. <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PB4 gpio multidrive I2C2 data */
  363. AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB5 gpio multidrive I2C2 clock */
  364. };
  365. };
  366. tcb0 {
  367. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  368. atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  369. };
  370. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  371. atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  372. };
  373. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  374. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  375. };
  376. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  377. atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  378. };
  379. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  380. atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  381. };
  382. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  383. atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  384. };
  385. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  386. atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  387. };
  388. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  389. atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  390. };
  391. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  392. atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  393. };
  394. };
  395. tcb1 {
  396. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  397. atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  398. };
  399. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  400. atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  401. };
  402. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  403. atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  404. };
  405. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  406. atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  407. };
  408. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  409. atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  410. };
  411. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  412. atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  413. };
  414. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  415. atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  416. };
  417. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  418. atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  419. };
  420. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  421. atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  422. };
  423. };
  424. pioA: gpio@fffff400 {
  425. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  426. reg = <0xfffff400 0x200>;
  427. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  428. #gpio-cells = <2>;
  429. gpio-controller;
  430. interrupt-controller;
  431. #interrupt-cells = <2>;
  432. };
  433. pioB: gpio@fffff600 {
  434. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  435. reg = <0xfffff600 0x200>;
  436. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  437. #gpio-cells = <2>;
  438. gpio-controller;
  439. #gpio-lines = <19>;
  440. interrupt-controller;
  441. #interrupt-cells = <2>;
  442. };
  443. pioC: gpio@fffff800 {
  444. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  445. reg = <0xfffff800 0x200>;
  446. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  447. #gpio-cells = <2>;
  448. gpio-controller;
  449. interrupt-controller;
  450. #interrupt-cells = <2>;
  451. };
  452. pioD: gpio@fffffa00 {
  453. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  454. reg = <0xfffffa00 0x200>;
  455. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  456. #gpio-cells = <2>;
  457. gpio-controller;
  458. #gpio-lines = <22>;
  459. interrupt-controller;
  460. #interrupt-cells = <2>;
  461. };
  462. };
  463. ssc0: ssc@f0010000 {
  464. compatible = "atmel,at91sam9g45-ssc";
  465. reg = <0xf0010000 0x4000>;
  466. interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
  467. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
  468. <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
  469. dma-names = "tx", "rx";
  470. pinctrl-names = "default";
  471. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  472. status = "disabled";
  473. };
  474. mmc0: mmc@f0008000 {
  475. compatible = "atmel,hsmci";
  476. reg = <0xf0008000 0x600>;
  477. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
  478. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
  479. dma-names = "rxtx";
  480. pinctrl-names = "default";
  481. #address-cells = <1>;
  482. #size-cells = <0>;
  483. status = "disabled";
  484. };
  485. mmc1: mmc@f000c000 {
  486. compatible = "atmel,hsmci";
  487. reg = <0xf000c000 0x600>;
  488. interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
  489. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
  490. dma-names = "rxtx";
  491. pinctrl-names = "default";
  492. #address-cells = <1>;
  493. #size-cells = <0>;
  494. status = "disabled";
  495. };
  496. dbgu: serial@fffff200 {
  497. compatible = "atmel,at91sam9260-usart";
  498. reg = <0xfffff200 0x200>;
  499. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_dbgu>;
  502. status = "disabled";
  503. };
  504. usart0: serial@f801c000 {
  505. compatible = "atmel,at91sam9260-usart";
  506. reg = <0xf801c000 0x200>;
  507. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
  508. pinctrl-names = "default";
  509. pinctrl-0 = <&pinctrl_usart0>;
  510. status = "disabled";
  511. };
  512. usart1: serial@f8020000 {
  513. compatible = "atmel,at91sam9260-usart";
  514. reg = <0xf8020000 0x200>;
  515. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  516. pinctrl-names = "default";
  517. pinctrl-0 = <&pinctrl_usart1>;
  518. status = "disabled";
  519. };
  520. usart2: serial@f8024000 {
  521. compatible = "atmel,at91sam9260-usart";
  522. reg = <0xf8024000 0x200>;
  523. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  524. pinctrl-names = "default";
  525. pinctrl-0 = <&pinctrl_usart2>;
  526. status = "disabled";
  527. };
  528. macb0: ethernet@f802c000 {
  529. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  530. reg = <0xf802c000 0x100>;
  531. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
  532. pinctrl-names = "default";
  533. pinctrl-0 = <&pinctrl_macb0_rmii>;
  534. status = "disabled";
  535. };
  536. macb1: ethernet@f8030000 {
  537. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  538. reg = <0xf8030000 0x100>;
  539. interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
  540. status = "disabled";
  541. };
  542. i2c0: i2c@f8010000 {
  543. compatible = "atmel,at91sam9x5-i2c";
  544. reg = <0xf8010000 0x100>;
  545. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
  546. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
  547. <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
  548. dma-names = "tx", "rx";
  549. #address-cells = <1>;
  550. #size-cells = <0>;
  551. pinctrl-names = "default";
  552. pinctrl-0 = <&pinctrl_i2c0>;
  553. status = "disabled";
  554. };
  555. i2c1: i2c@f8014000 {
  556. compatible = "atmel,at91sam9x5-i2c";
  557. reg = <0xf8014000 0x100>;
  558. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
  559. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
  560. <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
  561. dma-names = "tx", "rx";
  562. #address-cells = <1>;
  563. #size-cells = <0>;
  564. pinctrl-names = "default";
  565. pinctrl-0 = <&pinctrl_i2c1>;
  566. status = "disabled";
  567. };
  568. i2c2: i2c@f8018000 {
  569. compatible = "atmel,at91sam9x5-i2c";
  570. reg = <0xf8018000 0x100>;
  571. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
  572. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
  573. <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
  574. dma-names = "tx", "rx";
  575. #address-cells = <1>;
  576. #size-cells = <0>;
  577. pinctrl-names = "default";
  578. pinctrl-0 = <&pinctrl_i2c2>;
  579. status = "disabled";
  580. };
  581. uart0: serial@f8040000 {
  582. compatible = "atmel,at91sam9260-usart";
  583. reg = <0xf8040000 0x200>;
  584. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
  585. pinctrl-names = "default";
  586. pinctrl-0 = <&pinctrl_uart0>;
  587. status = "disabled";
  588. };
  589. uart1: serial@f8044000 {
  590. compatible = "atmel,at91sam9260-usart";
  591. reg = <0xf8044000 0x200>;
  592. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  593. pinctrl-names = "default";
  594. pinctrl-0 = <&pinctrl_uart1>;
  595. status = "disabled";
  596. };
  597. adc0: adc@f804c000 {
  598. compatible = "atmel,at91sam9260-adc";
  599. reg = <0xf804c000 0x100>;
  600. interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
  601. atmel,adc-use-external;
  602. atmel,adc-channels-used = <0xffff>;
  603. atmel,adc-vref = <3300>;
  604. atmel,adc-num-channels = <12>;
  605. atmel,adc-startup-time = <40>;
  606. atmel,adc-channel-base = <0x50>;
  607. atmel,adc-drdy-mask = <0x1000000>;
  608. atmel,adc-status-register = <0x30>;
  609. atmel,adc-trigger-register = <0xc0>;
  610. atmel,adc-res = <8 10>;
  611. atmel,adc-res-names = "lowres", "highres";
  612. atmel,adc-use-res = "highres";
  613. trigger@0 {
  614. trigger-name = "external-rising";
  615. trigger-value = <0x1>;
  616. trigger-external;
  617. };
  618. trigger@1 {
  619. trigger-name = "external-falling";
  620. trigger-value = <0x2>;
  621. trigger-external;
  622. };
  623. trigger@2 {
  624. trigger-name = "external-any";
  625. trigger-value = <0x3>;
  626. trigger-external;
  627. };
  628. trigger@3 {
  629. trigger-name = "continuous";
  630. trigger-value = <0x6>;
  631. };
  632. };
  633. spi0: spi@f0000000 {
  634. #address-cells = <1>;
  635. #size-cells = <0>;
  636. compatible = "atmel,at91rm9200-spi";
  637. reg = <0xf0000000 0x100>;
  638. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  639. dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
  640. <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
  641. dma-names = "tx", "rx";
  642. pinctrl-names = "default";
  643. pinctrl-0 = <&pinctrl_spi0>;
  644. status = "disabled";
  645. };
  646. spi1: spi@f0004000 {
  647. #address-cells = <1>;
  648. #size-cells = <0>;
  649. compatible = "atmel,at91rm9200-spi";
  650. reg = <0xf0004000 0x100>;
  651. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
  652. dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
  653. <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
  654. dma-names = "tx", "rx";
  655. pinctrl-names = "default";
  656. pinctrl-0 = <&pinctrl_spi1>;
  657. status = "disabled";
  658. };
  659. usb2: gadget@f803c000 {
  660. #address-cells = <1>;
  661. #size-cells = <0>;
  662. compatible = "atmel,at91sam9rl-udc";
  663. reg = <0x00500000 0x80000
  664. 0xf803c000 0x400>;
  665. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
  666. status = "disabled";
  667. ep0 {
  668. reg = <0>;
  669. atmel,fifo-size = <64>;
  670. atmel,nb-banks = <1>;
  671. };
  672. ep1 {
  673. reg = <1>;
  674. atmel,fifo-size = <1024>;
  675. atmel,nb-banks = <2>;
  676. atmel,can-dma;
  677. atmel,can-isoc;
  678. };
  679. ep2 {
  680. reg = <2>;
  681. atmel,fifo-size = <1024>;
  682. atmel,nb-banks = <2>;
  683. atmel,can-dma;
  684. atmel,can-isoc;
  685. };
  686. ep3 {
  687. reg = <3>;
  688. atmel,fifo-size = <1024>;
  689. atmel,nb-banks = <3>;
  690. atmel,can-dma;
  691. };
  692. ep4 {
  693. reg = <4>;
  694. atmel,fifo-size = <1024>;
  695. atmel,nb-banks = <3>;
  696. atmel,can-dma;
  697. };
  698. ep5 {
  699. reg = <5>;
  700. atmel,fifo-size = <1024>;
  701. atmel,nb-banks = <3>;
  702. atmel,can-dma;
  703. atmel,can-isoc;
  704. };
  705. ep6 {
  706. reg = <6>;
  707. atmel,fifo-size = <1024>;
  708. atmel,nb-banks = <3>;
  709. atmel,can-dma;
  710. atmel,can-isoc;
  711. };
  712. };
  713. watchdog@fffffe40 {
  714. compatible = "atmel,at91sam9260-wdt";
  715. reg = <0xfffffe40 0x10>;
  716. status = "disabled";
  717. };
  718. rtc@fffffeb0 {
  719. compatible = "atmel,at91sam9x5-rtc";
  720. reg = <0xfffffeb0 0x40>;
  721. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  722. status = "disabled";
  723. };
  724. };
  725. nand0: nand@40000000 {
  726. compatible = "atmel,at91rm9200-nand";
  727. #address-cells = <1>;
  728. #size-cells = <1>;
  729. reg = <0x40000000 0x10000000
  730. 0xffffe000 0x600 /* PMECC Registers */
  731. 0xffffe600 0x200 /* PMECC Error Location Registers */
  732. 0x00108000 0x18000 /* PMECC looup table in ROM code */
  733. >;
  734. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  735. atmel,nand-addr-offset = <21>;
  736. atmel,nand-cmd-offset = <22>;
  737. pinctrl-names = "default";
  738. pinctrl-0 = <&pinctrl_nand>;
  739. gpios = <&pioD 5 GPIO_ACTIVE_HIGH
  740. &pioD 4 GPIO_ACTIVE_HIGH
  741. 0
  742. >;
  743. status = "disabled";
  744. };
  745. usb0: ohci@00600000 {
  746. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  747. reg = <0x00600000 0x100000>;
  748. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  749. status = "disabled";
  750. };
  751. usb1: ehci@00700000 {
  752. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  753. reg = <0x00700000 0x100000>;
  754. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  755. status = "disabled";
  756. };
  757. };
  758. i2c@0 {
  759. compatible = "i2c-gpio";
  760. gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
  761. &pioA 31 GPIO_ACTIVE_HIGH /* scl */
  762. >;
  763. i2c-gpio,sda-open-drain;
  764. i2c-gpio,scl-open-drain;
  765. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  766. #address-cells = <1>;
  767. #size-cells = <0>;
  768. pinctrl-names = "default";
  769. pinctrl-0 = <&pinctrl_i2c_gpio0>;
  770. status = "disabled";
  771. };
  772. i2c@1 {
  773. compatible = "i2c-gpio";
  774. gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
  775. &pioC 1 GPIO_ACTIVE_HIGH /* scl */
  776. >;
  777. i2c-gpio,sda-open-drain;
  778. i2c-gpio,scl-open-drain;
  779. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  780. #address-cells = <1>;
  781. #size-cells = <0>;
  782. pinctrl-names = "default";
  783. pinctrl-0 = <&pinctrl_i2c_gpio1>;
  784. status = "disabled";
  785. };
  786. i2c@2 {
  787. compatible = "i2c-gpio";
  788. gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
  789. &pioB 5 GPIO_ACTIVE_HIGH /* scl */
  790. >;
  791. i2c-gpio,sda-open-drain;
  792. i2c-gpio,scl-open-drain;
  793. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  794. #address-cells = <1>;
  795. #size-cells = <0>;
  796. pinctrl-names = "default";
  797. pinctrl-0 = <&pinctrl_i2c_gpio2>;
  798. status = "disabled";
  799. };
  800. };