ath.h 2.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101
  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef ATH_H
  17. #define ATH_H
  18. #include <linux/skbuff.h>
  19. #include <linux/if_ether.h>
  20. #include <net/mac80211.h>
  21. static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  22. struct ath_ani {
  23. bool caldone;
  24. int16_t noise_floor;
  25. unsigned int longcal_timer;
  26. unsigned int shortcal_timer;
  27. unsigned int resetcal_timer;
  28. unsigned int checkani_timer;
  29. struct timer_list timer;
  30. };
  31. enum ath_device_state {
  32. ATH_HW_UNAVAILABLE,
  33. ATH_HW_INITIALIZED,
  34. };
  35. struct reg_dmn_pair_mapping {
  36. u16 regDmnEnum;
  37. u16 reg_5ghz_ctl;
  38. u16 reg_2ghz_ctl;
  39. };
  40. struct ath_regulatory {
  41. char alpha2[2];
  42. u16 country_code;
  43. u16 max_power_level;
  44. u32 tp_scale;
  45. u16 current_rd;
  46. u16 current_rd_ext;
  47. int16_t power_limit;
  48. struct reg_dmn_pair_mapping *regpair;
  49. };
  50. struct ath_ops {
  51. unsigned int (*read)(void *, u32 reg_offset);
  52. void (*write)(void *, u32 val, u32 reg_offset);
  53. };
  54. struct ath_common;
  55. struct ath_bus_ops {
  56. void (*read_cachesize)(struct ath_common *common, int *csz);
  57. void (*cleanup)(struct ath_common *common);
  58. bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
  59. void (*bt_coex_prep)(struct ath_common *common);
  60. };
  61. struct ath_common {
  62. void *ah;
  63. void *priv;
  64. struct ieee80211_hw *hw;
  65. int debug_mask;
  66. enum ath_device_state state;
  67. struct ath_ani ani;
  68. u16 cachelsz;
  69. u16 curaid;
  70. u8 macaddr[ETH_ALEN];
  71. u8 curbssid[ETH_ALEN];
  72. u8 bssidmask[ETH_ALEN];
  73. u8 tx_chainmask;
  74. u8 rx_chainmask;
  75. struct ath_regulatory regulatory;
  76. const struct ath_ops *ops;
  77. const struct ath_bus_ops *bus_ops;
  78. };
  79. struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
  80. u32 len,
  81. gfp_t gfp_mask);
  82. void ath_hw_setbssidmask(struct ath_common *common);
  83. #endif /* ATH_H */