rt2800.h 56 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998
  1. /*
  2. Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
  3. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  4. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  5. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  6. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  7. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  8. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  9. Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10. <http://rt2x00.serialmonkey.com>
  11. This program is free software; you can redistribute it and/or modify
  12. it under the terms of the GNU General Public License as published by
  13. the Free Software Foundation; either version 2 of the License, or
  14. (at your option) any later version.
  15. This program is distributed in the hope that it will be useful,
  16. but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. GNU General Public License for more details.
  19. You should have received a copy of the GNU General Public License
  20. along with this program; if not, write to the
  21. Free Software Foundation, Inc.,
  22. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23. */
  24. /*
  25. Module: rt2800
  26. Abstract: Data structures and registers for the rt2800 modules.
  27. Supported chipsets: RT2800E, RT2800ED & RT2800U.
  28. */
  29. #ifndef RT2800_H
  30. #define RT2800_H
  31. /*
  32. * RF chip defines.
  33. *
  34. * RF2820 2.4G 2T3R
  35. * RF2850 2.4G/5G 2T3R
  36. * RF2720 2.4G 1T2R
  37. * RF2750 2.4G/5G 1T2R
  38. * RF3020 2.4G 1T1R
  39. * RF2020 2.4G B/G
  40. * RF3021 2.4G 1T2R
  41. * RF3022 2.4G 2T2R
  42. * RF3052 2.4G 2T2R
  43. */
  44. #define RF2820 0x0001
  45. #define RF2850 0x0002
  46. #define RF2720 0x0003
  47. #define RF2750 0x0004
  48. #define RF3020 0x0005
  49. #define RF2020 0x0006
  50. #define RF3021 0x0007
  51. #define RF3022 0x0008
  52. #define RF3052 0x0009
  53. #define RF3320 0x000b
  54. /*
  55. * Chipset revisions.
  56. */
  57. #define REV_RT2860C 0x0100
  58. #define REV_RT2860D 0x0101
  59. #define REV_RT2872E 0x0200
  60. #define REV_RT3070E 0x0200
  61. #define REV_RT3070F 0x0201
  62. #define REV_RT3071E 0x0211
  63. #define REV_RT3090E 0x0211
  64. #define REV_RT3390E 0x0211
  65. /*
  66. * Signal information.
  67. * Default offset is required for RSSI <-> dBm conversion.
  68. */
  69. #define DEFAULT_RSSI_OFFSET 120 /* FIXME */
  70. /*
  71. * Register layout information.
  72. */
  73. #define CSR_REG_BASE 0x1000
  74. #define CSR_REG_SIZE 0x0800
  75. #define EEPROM_BASE 0x0000
  76. #define EEPROM_SIZE 0x0110
  77. #define BBP_BASE 0x0000
  78. #define BBP_SIZE 0x0080
  79. #define RF_BASE 0x0004
  80. #define RF_SIZE 0x0010
  81. /*
  82. * Number of TX queues.
  83. */
  84. #define NUM_TX_QUEUES 4
  85. /*
  86. * Registers.
  87. */
  88. /*
  89. * E2PROM_CSR: PCI EEPROM control register.
  90. * RELOAD: Write 1 to reload eeprom content.
  91. * TYPE: 0: 93c46, 1:93c66.
  92. * LOAD_STATUS: 1:loading, 0:done.
  93. */
  94. #define E2PROM_CSR 0x0004
  95. #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
  96. #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
  97. #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
  98. #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
  99. #define E2PROM_CSR_TYPE FIELD32(0x00000030)
  100. #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
  101. #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
  102. /*
  103. * OPT_14: Unknown register used by rt3xxx devices.
  104. */
  105. #define OPT_14_CSR 0x0114
  106. #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
  107. /*
  108. * INT_SOURCE_CSR: Interrupt source register.
  109. * Write one to clear corresponding bit.
  110. * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
  111. */
  112. #define INT_SOURCE_CSR 0x0200
  113. #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
  114. #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
  115. #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
  116. #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
  117. #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
  118. #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
  119. #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
  120. #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
  121. #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
  122. #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
  123. #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
  124. #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
  125. #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
  126. #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
  127. #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
  128. #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
  129. #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
  130. #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
  131. /*
  132. * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
  133. */
  134. #define INT_MASK_CSR 0x0204
  135. #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
  136. #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
  137. #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
  138. #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
  139. #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
  140. #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
  141. #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
  142. #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
  143. #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
  144. #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
  145. #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
  146. #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
  147. #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
  148. #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
  149. #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
  150. #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
  151. #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
  152. #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
  153. /*
  154. * WPDMA_GLO_CFG
  155. */
  156. #define WPDMA_GLO_CFG 0x0208
  157. #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
  158. #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
  159. #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
  160. #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
  161. #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
  162. #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
  163. #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
  164. #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
  165. #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
  166. /*
  167. * WPDMA_RST_IDX
  168. */
  169. #define WPDMA_RST_IDX 0x020c
  170. #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
  171. #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
  172. #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
  173. #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
  174. #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
  175. #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
  176. #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
  177. /*
  178. * DELAY_INT_CFG
  179. */
  180. #define DELAY_INT_CFG 0x0210
  181. #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
  182. #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
  183. #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
  184. #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
  185. #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
  186. #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
  187. /*
  188. * WMM_AIFSN_CFG: Aifsn for each EDCA AC
  189. * AIFSN0: AC_BE
  190. * AIFSN1: AC_BK
  191. * AIFSN2: AC_VI
  192. * AIFSN3: AC_VO
  193. */
  194. #define WMM_AIFSN_CFG 0x0214
  195. #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
  196. #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
  197. #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
  198. #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
  199. /*
  200. * WMM_CWMIN_CSR: CWmin for each EDCA AC
  201. * CWMIN0: AC_BE
  202. * CWMIN1: AC_BK
  203. * CWMIN2: AC_VI
  204. * CWMIN3: AC_VO
  205. */
  206. #define WMM_CWMIN_CFG 0x0218
  207. #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
  208. #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
  209. #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
  210. #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
  211. /*
  212. * WMM_CWMAX_CSR: CWmax for each EDCA AC
  213. * CWMAX0: AC_BE
  214. * CWMAX1: AC_BK
  215. * CWMAX2: AC_VI
  216. * CWMAX3: AC_VO
  217. */
  218. #define WMM_CWMAX_CFG 0x021c
  219. #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
  220. #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
  221. #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
  222. #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
  223. /*
  224. * AC_TXOP0: AC_BK/AC_BE TXOP register
  225. * AC0TXOP: AC_BK in unit of 32us
  226. * AC1TXOP: AC_BE in unit of 32us
  227. */
  228. #define WMM_TXOP0_CFG 0x0220
  229. #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
  230. #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
  231. /*
  232. * AC_TXOP1: AC_VO/AC_VI TXOP register
  233. * AC2TXOP: AC_VI in unit of 32us
  234. * AC3TXOP: AC_VO in unit of 32us
  235. */
  236. #define WMM_TXOP1_CFG 0x0224
  237. #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
  238. #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
  239. /*
  240. * GPIO_CTRL_CFG:
  241. */
  242. #define GPIO_CTRL_CFG 0x0228
  243. #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
  244. #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
  245. #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
  246. #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
  247. #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
  248. #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
  249. #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
  250. #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
  251. #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
  252. /*
  253. * MCU_CMD_CFG
  254. */
  255. #define MCU_CMD_CFG 0x022c
  256. /*
  257. * AC_BK register offsets
  258. */
  259. #define TX_BASE_PTR0 0x0230
  260. #define TX_MAX_CNT0 0x0234
  261. #define TX_CTX_IDX0 0x0238
  262. #define TX_DTX_IDX0 0x023c
  263. /*
  264. * AC_BE register offsets
  265. */
  266. #define TX_BASE_PTR1 0x0240
  267. #define TX_MAX_CNT1 0x0244
  268. #define TX_CTX_IDX1 0x0248
  269. #define TX_DTX_IDX1 0x024c
  270. /*
  271. * AC_VI register offsets
  272. */
  273. #define TX_BASE_PTR2 0x0250
  274. #define TX_MAX_CNT2 0x0254
  275. #define TX_CTX_IDX2 0x0258
  276. #define TX_DTX_IDX2 0x025c
  277. /*
  278. * AC_VO register offsets
  279. */
  280. #define TX_BASE_PTR3 0x0260
  281. #define TX_MAX_CNT3 0x0264
  282. #define TX_CTX_IDX3 0x0268
  283. #define TX_DTX_IDX3 0x026c
  284. /*
  285. * HCCA register offsets
  286. */
  287. #define TX_BASE_PTR4 0x0270
  288. #define TX_MAX_CNT4 0x0274
  289. #define TX_CTX_IDX4 0x0278
  290. #define TX_DTX_IDX4 0x027c
  291. /*
  292. * MGMT register offsets
  293. */
  294. #define TX_BASE_PTR5 0x0280
  295. #define TX_MAX_CNT5 0x0284
  296. #define TX_CTX_IDX5 0x0288
  297. #define TX_DTX_IDX5 0x028c
  298. /*
  299. * RX register offsets
  300. */
  301. #define RX_BASE_PTR 0x0290
  302. #define RX_MAX_CNT 0x0294
  303. #define RX_CRX_IDX 0x0298
  304. #define RX_DRX_IDX 0x029c
  305. /*
  306. * USB_DMA_CFG
  307. * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
  308. * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
  309. * PHY_CLEAR: phy watch dog enable.
  310. * TX_CLEAR: Clear USB DMA TX path.
  311. * TXOP_HALT: Halt TXOP count down when TX buffer is full.
  312. * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
  313. * RX_BULK_EN: Enable USB DMA Rx.
  314. * TX_BULK_EN: Enable USB DMA Tx.
  315. * EP_OUT_VALID: OUT endpoint data valid.
  316. * RX_BUSY: USB DMA RX FSM busy.
  317. * TX_BUSY: USB DMA TX FSM busy.
  318. */
  319. #define USB_DMA_CFG 0x02a0
  320. #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
  321. #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
  322. #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
  323. #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
  324. #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
  325. #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
  326. #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
  327. #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
  328. #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
  329. #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
  330. #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
  331. /*
  332. * US_CYC_CNT
  333. */
  334. #define US_CYC_CNT 0x02a4
  335. #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
  336. /*
  337. * PBF_SYS_CTRL
  338. * HOST_RAM_WRITE: enable Host program ram write selection
  339. */
  340. #define PBF_SYS_CTRL 0x0400
  341. #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
  342. #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
  343. /*
  344. * HOST-MCU shared memory
  345. */
  346. #define HOST_CMD_CSR 0x0404
  347. #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
  348. /*
  349. * PBF registers
  350. * Most are for debug. Driver doesn't touch PBF register.
  351. */
  352. #define PBF_CFG 0x0408
  353. #define PBF_MAX_PCNT 0x040c
  354. #define PBF_CTRL 0x0410
  355. #define PBF_INT_STA 0x0414
  356. #define PBF_INT_ENA 0x0418
  357. /*
  358. * BCN_OFFSET0:
  359. */
  360. #define BCN_OFFSET0 0x042c
  361. #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
  362. #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
  363. #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
  364. #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
  365. /*
  366. * BCN_OFFSET1:
  367. */
  368. #define BCN_OFFSET1 0x0430
  369. #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
  370. #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
  371. #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
  372. #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
  373. /*
  374. * PBF registers
  375. * Most are for debug. Driver doesn't touch PBF register.
  376. */
  377. #define TXRXQ_PCNT 0x0438
  378. #define PBF_DBG 0x043c
  379. /*
  380. * RF registers
  381. */
  382. #define RF_CSR_CFG 0x0500
  383. #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
  384. #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
  385. #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
  386. #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
  387. /*
  388. * EFUSE_CSR: RT30x0 EEPROM
  389. */
  390. #define EFUSE_CTRL 0x0580
  391. #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
  392. #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
  393. #define EFUSE_CTRL_KICK FIELD32(0x40000000)
  394. #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
  395. /*
  396. * EFUSE_DATA0
  397. */
  398. #define EFUSE_DATA0 0x0590
  399. /*
  400. * EFUSE_DATA1
  401. */
  402. #define EFUSE_DATA1 0x0594
  403. /*
  404. * EFUSE_DATA2
  405. */
  406. #define EFUSE_DATA2 0x0598
  407. /*
  408. * EFUSE_DATA3
  409. */
  410. #define EFUSE_DATA3 0x059c
  411. /*
  412. * LDO_CFG0
  413. */
  414. #define LDO_CFG0 0x05d4
  415. #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
  416. #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
  417. #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
  418. #define LDO_CFG0_BGSEL FIELD32(0x03000000)
  419. #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
  420. #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
  421. #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
  422. /*
  423. * GPIO_SWITCH
  424. */
  425. #define GPIO_SWITCH 0x05dc
  426. #define GPIO_SWITCH_0 FIELD32(0x00000001)
  427. #define GPIO_SWITCH_1 FIELD32(0x00000002)
  428. #define GPIO_SWITCH_2 FIELD32(0x00000004)
  429. #define GPIO_SWITCH_3 FIELD32(0x00000008)
  430. #define GPIO_SWITCH_4 FIELD32(0x00000010)
  431. #define GPIO_SWITCH_5 FIELD32(0x00000020)
  432. #define GPIO_SWITCH_6 FIELD32(0x00000040)
  433. #define GPIO_SWITCH_7 FIELD32(0x00000080)
  434. /*
  435. * MAC Control/Status Registers(CSR).
  436. * Some values are set in TU, whereas 1 TU == 1024 us.
  437. */
  438. /*
  439. * MAC_CSR0: ASIC revision number.
  440. * ASIC_REV: 0
  441. * ASIC_VER: 2860 or 2870
  442. */
  443. #define MAC_CSR0 0x1000
  444. #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
  445. #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
  446. /*
  447. * MAC_SYS_CTRL:
  448. */
  449. #define MAC_SYS_CTRL 0x1004
  450. #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
  451. #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
  452. #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
  453. #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
  454. #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
  455. #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
  456. #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
  457. #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
  458. /*
  459. * MAC_ADDR_DW0: STA MAC register 0
  460. */
  461. #define MAC_ADDR_DW0 0x1008
  462. #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
  463. #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
  464. #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
  465. #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
  466. /*
  467. * MAC_ADDR_DW1: STA MAC register 1
  468. * UNICAST_TO_ME_MASK:
  469. * Used to mask off bits from byte 5 of the MAC address
  470. * to determine the UNICAST_TO_ME bit for RX frames.
  471. * The full mask is complemented by BSS_ID_MASK:
  472. * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
  473. */
  474. #define MAC_ADDR_DW1 0x100c
  475. #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
  476. #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
  477. #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
  478. /*
  479. * MAC_BSSID_DW0: BSSID register 0
  480. */
  481. #define MAC_BSSID_DW0 0x1010
  482. #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
  483. #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
  484. #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
  485. #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
  486. /*
  487. * MAC_BSSID_DW1: BSSID register 1
  488. * BSS_ID_MASK:
  489. * 0: 1-BSSID mode (BSS index = 0)
  490. * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
  491. * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
  492. * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
  493. * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
  494. * BSSID. This will make sure that those bits will be ignored
  495. * when determining the MY_BSS of RX frames.
  496. */
  497. #define MAC_BSSID_DW1 0x1014
  498. #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
  499. #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
  500. #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
  501. #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
  502. /*
  503. * MAX_LEN_CFG: Maximum frame length register.
  504. * MAX_MPDU: rt2860b max 16k bytes
  505. * MAX_PSDU: Maximum PSDU length
  506. * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
  507. */
  508. #define MAX_LEN_CFG 0x1018
  509. #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
  510. #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
  511. #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
  512. #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
  513. /*
  514. * BBP_CSR_CFG: BBP serial control register
  515. * VALUE: Register value to program into BBP
  516. * REG_NUM: Selected BBP register
  517. * READ_CONTROL: 0 write BBP, 1 read BBP
  518. * BUSY: ASIC is busy executing BBP commands
  519. * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
  520. * BBP_RW_MODE: 0 serial, 1 paralell
  521. */
  522. #define BBP_CSR_CFG 0x101c
  523. #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
  524. #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
  525. #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
  526. #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
  527. #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
  528. #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
  529. /*
  530. * RF_CSR_CFG0: RF control register
  531. * REGID_AND_VALUE: Register value to program into RF
  532. * BITWIDTH: Selected RF register
  533. * STANDBYMODE: 0 high when standby, 1 low when standby
  534. * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
  535. * BUSY: ASIC is busy executing RF commands
  536. */
  537. #define RF_CSR_CFG0 0x1020
  538. #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
  539. #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
  540. #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
  541. #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
  542. #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
  543. #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
  544. /*
  545. * RF_CSR_CFG1: RF control register
  546. * REGID_AND_VALUE: Register value to program into RF
  547. * RFGAP: Gap between BB_CONTROL_RF and RF_LE
  548. * 0: 3 system clock cycle (37.5usec)
  549. * 1: 5 system clock cycle (62.5usec)
  550. */
  551. #define RF_CSR_CFG1 0x1024
  552. #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
  553. #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
  554. /*
  555. * RF_CSR_CFG2: RF control register
  556. * VALUE: Register value to program into RF
  557. */
  558. #define RF_CSR_CFG2 0x1028
  559. #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
  560. /*
  561. * LED_CFG: LED control
  562. * color LED's:
  563. * 0: off
  564. * 1: blinking upon TX2
  565. * 2: periodic slow blinking
  566. * 3: always on
  567. * LED polarity:
  568. * 0: active low
  569. * 1: active high
  570. */
  571. #define LED_CFG 0x102c
  572. #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
  573. #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
  574. #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
  575. #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
  576. #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
  577. #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
  578. #define LED_CFG_LED_POLAR FIELD32(0x40000000)
  579. /*
  580. * XIFS_TIME_CFG: MAC timing
  581. * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
  582. * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
  583. * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
  584. * when MAC doesn't reference BBP signal BBRXEND
  585. * EIFS: unit 1us
  586. * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
  587. *
  588. */
  589. #define XIFS_TIME_CFG 0x1100
  590. #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
  591. #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
  592. #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
  593. #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
  594. #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
  595. /*
  596. * BKOFF_SLOT_CFG:
  597. */
  598. #define BKOFF_SLOT_CFG 0x1104
  599. #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
  600. #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
  601. /*
  602. * NAV_TIME_CFG:
  603. */
  604. #define NAV_TIME_CFG 0x1108
  605. #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
  606. #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
  607. #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
  608. #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
  609. /*
  610. * CH_TIME_CFG: count as channel busy
  611. */
  612. #define CH_TIME_CFG 0x110c
  613. /*
  614. * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
  615. */
  616. #define PBF_LIFE_TIMER 0x1110
  617. /*
  618. * BCN_TIME_CFG:
  619. * BEACON_INTERVAL: in unit of 1/16 TU
  620. * TSF_TICKING: Enable TSF auto counting
  621. * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
  622. * BEACON_GEN: Enable beacon generator
  623. */
  624. #define BCN_TIME_CFG 0x1114
  625. #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
  626. #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
  627. #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
  628. #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
  629. #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
  630. #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
  631. /*
  632. * TBTT_SYNC_CFG:
  633. */
  634. #define TBTT_SYNC_CFG 0x1118
  635. /*
  636. * TSF_TIMER_DW0: Local lsb TSF timer, read-only
  637. */
  638. #define TSF_TIMER_DW0 0x111c
  639. #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
  640. /*
  641. * TSF_TIMER_DW1: Local msb TSF timer, read-only
  642. */
  643. #define TSF_TIMER_DW1 0x1120
  644. #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
  645. /*
  646. * TBTT_TIMER: TImer remains till next TBTT, read-only
  647. */
  648. #define TBTT_TIMER 0x1124
  649. /*
  650. * INT_TIMER_CFG:
  651. */
  652. #define INT_TIMER_CFG 0x1128
  653. /*
  654. * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
  655. */
  656. #define INT_TIMER_EN 0x112c
  657. /*
  658. * CH_IDLE_STA: channel idle time
  659. */
  660. #define CH_IDLE_STA 0x1130
  661. /*
  662. * CH_BUSY_STA: channel busy time
  663. */
  664. #define CH_BUSY_STA 0x1134
  665. /*
  666. * MAC_STATUS_CFG:
  667. * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
  668. * if 1 or higher one of the 2 registers is busy.
  669. */
  670. #define MAC_STATUS_CFG 0x1200
  671. #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
  672. /*
  673. * PWR_PIN_CFG:
  674. */
  675. #define PWR_PIN_CFG 0x1204
  676. /*
  677. * AUTOWAKEUP_CFG: Manual power control / status register
  678. * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
  679. * AUTOWAKE: 0:sleep, 1:awake
  680. */
  681. #define AUTOWAKEUP_CFG 0x1208
  682. #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
  683. #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
  684. #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
  685. /*
  686. * EDCA_AC0_CFG:
  687. */
  688. #define EDCA_AC0_CFG 0x1300
  689. #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
  690. #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
  691. #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
  692. #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
  693. /*
  694. * EDCA_AC1_CFG:
  695. */
  696. #define EDCA_AC1_CFG 0x1304
  697. #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
  698. #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
  699. #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
  700. #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
  701. /*
  702. * EDCA_AC2_CFG:
  703. */
  704. #define EDCA_AC2_CFG 0x1308
  705. #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
  706. #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
  707. #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
  708. #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
  709. /*
  710. * EDCA_AC3_CFG:
  711. */
  712. #define EDCA_AC3_CFG 0x130c
  713. #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
  714. #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
  715. #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
  716. #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
  717. /*
  718. * EDCA_TID_AC_MAP:
  719. */
  720. #define EDCA_TID_AC_MAP 0x1310
  721. /*
  722. * TX_PWR_CFG_0:
  723. */
  724. #define TX_PWR_CFG_0 0x1314
  725. #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
  726. #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
  727. #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
  728. #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
  729. #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
  730. #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
  731. #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
  732. #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
  733. /*
  734. * TX_PWR_CFG_1:
  735. */
  736. #define TX_PWR_CFG_1 0x1318
  737. #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
  738. #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
  739. #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
  740. #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
  741. #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
  742. #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
  743. #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
  744. #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
  745. /*
  746. * TX_PWR_CFG_2:
  747. */
  748. #define TX_PWR_CFG_2 0x131c
  749. #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
  750. #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
  751. #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
  752. #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
  753. #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
  754. #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
  755. #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
  756. #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
  757. /*
  758. * TX_PWR_CFG_3:
  759. */
  760. #define TX_PWR_CFG_3 0x1320
  761. #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
  762. #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
  763. #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
  764. #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
  765. #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
  766. #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
  767. #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
  768. #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
  769. /*
  770. * TX_PWR_CFG_4:
  771. */
  772. #define TX_PWR_CFG_4 0x1324
  773. #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
  774. #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
  775. #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
  776. #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
  777. /*
  778. * TX_PIN_CFG:
  779. */
  780. #define TX_PIN_CFG 0x1328
  781. #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
  782. #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
  783. #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
  784. #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
  785. #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
  786. #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
  787. #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
  788. #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
  789. #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
  790. #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
  791. #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
  792. #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
  793. #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
  794. #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
  795. #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
  796. #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
  797. #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
  798. #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
  799. #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
  800. #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
  801. /*
  802. * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
  803. */
  804. #define TX_BAND_CFG 0x132c
  805. #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
  806. #define TX_BAND_CFG_A FIELD32(0x00000002)
  807. #define TX_BAND_CFG_BG FIELD32(0x00000004)
  808. /*
  809. * TX_SW_CFG0:
  810. */
  811. #define TX_SW_CFG0 0x1330
  812. /*
  813. * TX_SW_CFG1:
  814. */
  815. #define TX_SW_CFG1 0x1334
  816. /*
  817. * TX_SW_CFG2:
  818. */
  819. #define TX_SW_CFG2 0x1338
  820. /*
  821. * TXOP_THRES_CFG:
  822. */
  823. #define TXOP_THRES_CFG 0x133c
  824. /*
  825. * TXOP_CTRL_CFG:
  826. */
  827. #define TXOP_CTRL_CFG 0x1340
  828. /*
  829. * TX_RTS_CFG:
  830. * RTS_THRES: unit:byte
  831. * RTS_FBK_EN: enable rts rate fallback
  832. */
  833. #define TX_RTS_CFG 0x1344
  834. #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
  835. #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
  836. #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
  837. /*
  838. * TX_TIMEOUT_CFG:
  839. * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
  840. * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
  841. * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
  842. * it is recommended that:
  843. * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
  844. */
  845. #define TX_TIMEOUT_CFG 0x1348
  846. #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
  847. #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
  848. #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
  849. /*
  850. * TX_RTY_CFG:
  851. * SHORT_RTY_LIMIT: short retry limit
  852. * LONG_RTY_LIMIT: long retry limit
  853. * LONG_RTY_THRE: Long retry threshoold
  854. * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
  855. * 0:expired by retry limit, 1: expired by mpdu life timer
  856. * AGG_RTY_MODE: Aggregate MPDU retry mode
  857. * 0:expired by retry limit, 1: expired by mpdu life timer
  858. * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
  859. */
  860. #define TX_RTY_CFG 0x134c
  861. #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
  862. #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
  863. #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
  864. #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
  865. #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
  866. #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
  867. /*
  868. * TX_LINK_CFG:
  869. * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
  870. * MFB_ENABLE: TX apply remote MFB 1:enable
  871. * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
  872. * 0: not apply remote remote unsolicit (MFS=7)
  873. * TX_MRQ_EN: MCS request TX enable
  874. * TX_RDG_EN: RDG TX enable
  875. * TX_CF_ACK_EN: Piggyback CF-ACK enable
  876. * REMOTE_MFB: remote MCS feedback
  877. * REMOTE_MFS: remote MCS feedback sequence number
  878. */
  879. #define TX_LINK_CFG 0x1350
  880. #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
  881. #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
  882. #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
  883. #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
  884. #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
  885. #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
  886. #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
  887. #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
  888. /*
  889. * HT_FBK_CFG0:
  890. */
  891. #define HT_FBK_CFG0 0x1354
  892. #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
  893. #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
  894. #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
  895. #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
  896. #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
  897. #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
  898. #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
  899. #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
  900. /*
  901. * HT_FBK_CFG1:
  902. */
  903. #define HT_FBK_CFG1 0x1358
  904. #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
  905. #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
  906. #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
  907. #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
  908. #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
  909. #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
  910. #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
  911. #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
  912. /*
  913. * LG_FBK_CFG0:
  914. */
  915. #define LG_FBK_CFG0 0x135c
  916. #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
  917. #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
  918. #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
  919. #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
  920. #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
  921. #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
  922. #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
  923. #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
  924. /*
  925. * LG_FBK_CFG1:
  926. */
  927. #define LG_FBK_CFG1 0x1360
  928. #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
  929. #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
  930. #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
  931. #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
  932. /*
  933. * CCK_PROT_CFG: CCK Protection
  934. * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
  935. * PROTECT_CTRL: Protection control frame type for CCK TX
  936. * 0:none, 1:RTS/CTS, 2:CTS-to-self
  937. * PROTECT_NAV: TXOP protection type for CCK TX
  938. * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
  939. * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
  940. * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
  941. * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
  942. * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
  943. * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
  944. * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
  945. * RTS_TH_EN: RTS threshold enable on CCK TX
  946. */
  947. #define CCK_PROT_CFG 0x1364
  948. #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  949. #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  950. #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
  951. #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  952. #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  953. #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  954. #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  955. #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  956. #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  957. #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  958. /*
  959. * OFDM_PROT_CFG: OFDM Protection
  960. */
  961. #define OFDM_PROT_CFG 0x1368
  962. #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  963. #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  964. #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
  965. #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  966. #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  967. #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  968. #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  969. #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  970. #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  971. #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  972. /*
  973. * MM20_PROT_CFG: MM20 Protection
  974. */
  975. #define MM20_PROT_CFG 0x136c
  976. #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  977. #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  978. #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
  979. #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  980. #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  981. #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  982. #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  983. #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  984. #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  985. #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  986. /*
  987. * MM40_PROT_CFG: MM40 Protection
  988. */
  989. #define MM40_PROT_CFG 0x1370
  990. #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  991. #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  992. #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
  993. #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  994. #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  995. #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  996. #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  997. #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  998. #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  999. #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1000. /*
  1001. * GF20_PROT_CFG: GF20 Protection
  1002. */
  1003. #define GF20_PROT_CFG 0x1374
  1004. #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1005. #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1006. #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
  1007. #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1008. #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1009. #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1010. #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1011. #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1012. #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1013. #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1014. /*
  1015. * GF40_PROT_CFG: GF40 Protection
  1016. */
  1017. #define GF40_PROT_CFG 0x1378
  1018. #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
  1019. #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
  1020. #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
  1021. #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
  1022. #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
  1023. #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
  1024. #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
  1025. #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
  1026. #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
  1027. #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
  1028. /*
  1029. * EXP_CTS_TIME:
  1030. */
  1031. #define EXP_CTS_TIME 0x137c
  1032. /*
  1033. * EXP_ACK_TIME:
  1034. */
  1035. #define EXP_ACK_TIME 0x1380
  1036. /*
  1037. * RX_FILTER_CFG: RX configuration register.
  1038. */
  1039. #define RX_FILTER_CFG 0x1400
  1040. #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
  1041. #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
  1042. #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
  1043. #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
  1044. #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
  1045. #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
  1046. #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
  1047. #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
  1048. #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
  1049. #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
  1050. #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
  1051. #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
  1052. #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
  1053. #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
  1054. #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
  1055. #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
  1056. #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
  1057. /*
  1058. * AUTO_RSP_CFG:
  1059. * AUTORESPONDER: 0: disable, 1: enable
  1060. * BAC_ACK_POLICY: 0:long, 1:short preamble
  1061. * CTS_40_MMODE: Response CTS 40MHz duplicate mode
  1062. * CTS_40_MREF: Response CTS 40MHz duplicate mode
  1063. * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
  1064. * DUAL_CTS_EN: Power bit value in control frame
  1065. * ACK_CTS_PSM_BIT:Power bit value in control frame
  1066. */
  1067. #define AUTO_RSP_CFG 0x1404
  1068. #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
  1069. #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
  1070. #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
  1071. #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
  1072. #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
  1073. #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
  1074. #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
  1075. /*
  1076. * LEGACY_BASIC_RATE:
  1077. */
  1078. #define LEGACY_BASIC_RATE 0x1408
  1079. /*
  1080. * HT_BASIC_RATE:
  1081. */
  1082. #define HT_BASIC_RATE 0x140c
  1083. /*
  1084. * HT_CTRL_CFG:
  1085. */
  1086. #define HT_CTRL_CFG 0x1410
  1087. /*
  1088. * SIFS_COST_CFG:
  1089. */
  1090. #define SIFS_COST_CFG 0x1414
  1091. /*
  1092. * RX_PARSER_CFG:
  1093. * Set NAV for all received frames
  1094. */
  1095. #define RX_PARSER_CFG 0x1418
  1096. /*
  1097. * TX_SEC_CNT0:
  1098. */
  1099. #define TX_SEC_CNT0 0x1500
  1100. /*
  1101. * RX_SEC_CNT0:
  1102. */
  1103. #define RX_SEC_CNT0 0x1504
  1104. /*
  1105. * CCMP_FC_MUTE:
  1106. */
  1107. #define CCMP_FC_MUTE 0x1508
  1108. /*
  1109. * TXOP_HLDR_ADDR0:
  1110. */
  1111. #define TXOP_HLDR_ADDR0 0x1600
  1112. /*
  1113. * TXOP_HLDR_ADDR1:
  1114. */
  1115. #define TXOP_HLDR_ADDR1 0x1604
  1116. /*
  1117. * TXOP_HLDR_ET:
  1118. */
  1119. #define TXOP_HLDR_ET 0x1608
  1120. /*
  1121. * QOS_CFPOLL_RA_DW0:
  1122. */
  1123. #define QOS_CFPOLL_RA_DW0 0x160c
  1124. /*
  1125. * QOS_CFPOLL_RA_DW1:
  1126. */
  1127. #define QOS_CFPOLL_RA_DW1 0x1610
  1128. /*
  1129. * QOS_CFPOLL_QC:
  1130. */
  1131. #define QOS_CFPOLL_QC 0x1614
  1132. /*
  1133. * RX_STA_CNT0: RX PLCP error count & RX CRC error count
  1134. */
  1135. #define RX_STA_CNT0 0x1700
  1136. #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
  1137. #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
  1138. /*
  1139. * RX_STA_CNT1: RX False CCA count & RX LONG frame count
  1140. */
  1141. #define RX_STA_CNT1 0x1704
  1142. #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
  1143. #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
  1144. /*
  1145. * RX_STA_CNT2:
  1146. */
  1147. #define RX_STA_CNT2 0x1708
  1148. #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
  1149. #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
  1150. /*
  1151. * TX_STA_CNT0: TX Beacon count
  1152. */
  1153. #define TX_STA_CNT0 0x170c
  1154. #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
  1155. #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
  1156. /*
  1157. * TX_STA_CNT1: TX tx count
  1158. */
  1159. #define TX_STA_CNT1 0x1710
  1160. #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
  1161. #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
  1162. /*
  1163. * TX_STA_CNT2: TX tx count
  1164. */
  1165. #define TX_STA_CNT2 0x1714
  1166. #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
  1167. #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
  1168. /*
  1169. * TX_STA_FIFO: TX Result for specific PID status fifo register
  1170. */
  1171. #define TX_STA_FIFO 0x1718
  1172. #define TX_STA_FIFO_VALID FIELD32(0x00000001)
  1173. #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
  1174. #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
  1175. #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
  1176. #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
  1177. #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
  1178. #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
  1179. #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
  1180. #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
  1181. /*
  1182. * TX_AGG_CNT: Debug counter
  1183. */
  1184. #define TX_AGG_CNT 0x171c
  1185. #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
  1186. #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
  1187. /*
  1188. * TX_AGG_CNT0:
  1189. */
  1190. #define TX_AGG_CNT0 0x1720
  1191. #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
  1192. #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
  1193. /*
  1194. * TX_AGG_CNT1:
  1195. */
  1196. #define TX_AGG_CNT1 0x1724
  1197. #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
  1198. #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
  1199. /*
  1200. * TX_AGG_CNT2:
  1201. */
  1202. #define TX_AGG_CNT2 0x1728
  1203. #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
  1204. #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
  1205. /*
  1206. * TX_AGG_CNT3:
  1207. */
  1208. #define TX_AGG_CNT3 0x172c
  1209. #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
  1210. #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
  1211. /*
  1212. * TX_AGG_CNT4:
  1213. */
  1214. #define TX_AGG_CNT4 0x1730
  1215. #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
  1216. #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
  1217. /*
  1218. * TX_AGG_CNT5:
  1219. */
  1220. #define TX_AGG_CNT5 0x1734
  1221. #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
  1222. #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
  1223. /*
  1224. * TX_AGG_CNT6:
  1225. */
  1226. #define TX_AGG_CNT6 0x1738
  1227. #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
  1228. #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
  1229. /*
  1230. * TX_AGG_CNT7:
  1231. */
  1232. #define TX_AGG_CNT7 0x173c
  1233. #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
  1234. #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
  1235. /*
  1236. * MPDU_DENSITY_CNT:
  1237. * TX_ZERO_DEL: TX zero length delimiter count
  1238. * RX_ZERO_DEL: RX zero length delimiter count
  1239. */
  1240. #define MPDU_DENSITY_CNT 0x1740
  1241. #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
  1242. #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
  1243. /*
  1244. * Security key table memory.
  1245. * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
  1246. * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
  1247. * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
  1248. * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
  1249. * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
  1250. * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
  1251. */
  1252. #define MAC_WCID_BASE 0x1800
  1253. #define PAIRWISE_KEY_TABLE_BASE 0x4000
  1254. #define MAC_IVEIV_TABLE_BASE 0x6000
  1255. #define MAC_WCID_ATTRIBUTE_BASE 0x6800
  1256. #define SHARED_KEY_TABLE_BASE 0x6c00
  1257. #define SHARED_KEY_MODE_BASE 0x7000
  1258. #define MAC_WCID_ENTRY(__idx) \
  1259. ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
  1260. #define PAIRWISE_KEY_ENTRY(__idx) \
  1261. ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
  1262. #define MAC_IVEIV_ENTRY(__idx) \
  1263. ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
  1264. #define MAC_WCID_ATTR_ENTRY(__idx) \
  1265. ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
  1266. #define SHARED_KEY_ENTRY(__idx) \
  1267. ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
  1268. #define SHARED_KEY_MODE_ENTRY(__idx) \
  1269. ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
  1270. struct mac_wcid_entry {
  1271. u8 mac[6];
  1272. u8 reserved[2];
  1273. } __attribute__ ((packed));
  1274. struct hw_key_entry {
  1275. u8 key[16];
  1276. u8 tx_mic[8];
  1277. u8 rx_mic[8];
  1278. } __attribute__ ((packed));
  1279. struct mac_iveiv_entry {
  1280. u8 iv[8];
  1281. } __attribute__ ((packed));
  1282. /*
  1283. * MAC_WCID_ATTRIBUTE:
  1284. */
  1285. #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
  1286. #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
  1287. #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
  1288. #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
  1289. /*
  1290. * SHARED_KEY_MODE:
  1291. */
  1292. #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
  1293. #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
  1294. #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
  1295. #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
  1296. #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
  1297. #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
  1298. #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
  1299. #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
  1300. /*
  1301. * HOST-MCU communication
  1302. */
  1303. /*
  1304. * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
  1305. */
  1306. #define H2M_MAILBOX_CSR 0x7010
  1307. #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
  1308. #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
  1309. #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
  1310. #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
  1311. /*
  1312. * H2M_MAILBOX_CID:
  1313. */
  1314. #define H2M_MAILBOX_CID 0x7014
  1315. #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
  1316. #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
  1317. #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
  1318. #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
  1319. /*
  1320. * H2M_MAILBOX_STATUS:
  1321. */
  1322. #define H2M_MAILBOX_STATUS 0x701c
  1323. /*
  1324. * H2M_INT_SRC:
  1325. */
  1326. #define H2M_INT_SRC 0x7024
  1327. /*
  1328. * H2M_BBP_AGENT:
  1329. */
  1330. #define H2M_BBP_AGENT 0x7028
  1331. /*
  1332. * MCU_LEDCS: LED control for MCU Mailbox.
  1333. */
  1334. #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
  1335. #define MCU_LEDCS_POLARITY FIELD8(0x01)
  1336. /*
  1337. * HW_CS_CTS_BASE:
  1338. * Carrier-sense CTS frame base address.
  1339. * It's where mac stores carrier-sense frame for carrier-sense function.
  1340. */
  1341. #define HW_CS_CTS_BASE 0x7700
  1342. /*
  1343. * HW_DFS_CTS_BASE:
  1344. * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
  1345. */
  1346. #define HW_DFS_CTS_BASE 0x7780
  1347. /*
  1348. * TXRX control registers - base address 0x3000
  1349. */
  1350. /*
  1351. * TXRX_CSR1:
  1352. * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
  1353. */
  1354. #define TXRX_CSR1 0x77d0
  1355. /*
  1356. * HW_DEBUG_SETTING_BASE:
  1357. * since NULL frame won't be that long (256 byte)
  1358. * We steal 16 tail bytes to save debugging settings
  1359. */
  1360. #define HW_DEBUG_SETTING_BASE 0x77f0
  1361. #define HW_DEBUG_SETTING_BASE2 0x7770
  1362. /*
  1363. * HW_BEACON_BASE
  1364. * In order to support maximum 8 MBSS and its maximum length
  1365. * is 512 bytes for each beacon
  1366. * Three section discontinue memory segments will be used.
  1367. * 1. The original region for BCN 0~3
  1368. * 2. Extract memory from FCE table for BCN 4~5
  1369. * 3. Extract memory from Pair-wise key table for BCN 6~7
  1370. * It occupied those memory of wcid 238~253 for BCN 6
  1371. * and wcid 222~237 for BCN 7
  1372. *
  1373. * IMPORTANT NOTE: Not sure why legacy driver does this,
  1374. * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
  1375. */
  1376. #define HW_BEACON_BASE0 0x7800
  1377. #define HW_BEACON_BASE1 0x7a00
  1378. #define HW_BEACON_BASE2 0x7c00
  1379. #define HW_BEACON_BASE3 0x7e00
  1380. #define HW_BEACON_BASE4 0x7200
  1381. #define HW_BEACON_BASE5 0x7400
  1382. #define HW_BEACON_BASE6 0x5dc0
  1383. #define HW_BEACON_BASE7 0x5bc0
  1384. #define HW_BEACON_OFFSET(__index) \
  1385. ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
  1386. (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
  1387. (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
  1388. /*
  1389. * BBP registers.
  1390. * The wordsize of the BBP is 8 bits.
  1391. */
  1392. /*
  1393. * BBP 1: TX Antenna & Power
  1394. * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm,
  1395. * 3 - increase tx power by 6dBm
  1396. */
  1397. #define BBP1_TX_POWER FIELD8(0x07)
  1398. #define BBP1_TX_ANTENNA FIELD8(0x18)
  1399. /*
  1400. * BBP 3: RX Antenna
  1401. */
  1402. #define BBP3_RX_ANTENNA FIELD8(0x18)
  1403. #define BBP3_HT40_MINUS FIELD8(0x20)
  1404. /*
  1405. * BBP 4: Bandwidth
  1406. */
  1407. #define BBP4_TX_BF FIELD8(0x01)
  1408. #define BBP4_BANDWIDTH FIELD8(0x18)
  1409. /*
  1410. * BBP 138: Unknown
  1411. */
  1412. #define BBP138_RX_ADC1 FIELD8(0x02)
  1413. #define BBP138_RX_ADC2 FIELD8(0x04)
  1414. #define BBP138_TX_DAC1 FIELD8(0x20)
  1415. #define BBP138_TX_DAC2 FIELD8(0x40)
  1416. /*
  1417. * RFCSR registers
  1418. * The wordsize of the RFCSR is 8 bits.
  1419. */
  1420. /*
  1421. * RFCSR 1:
  1422. */
  1423. #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
  1424. #define RFCSR1_RX0_PD FIELD8(0x04)
  1425. #define RFCSR1_TX0_PD FIELD8(0x08)
  1426. #define RFCSR1_RX1_PD FIELD8(0x10)
  1427. #define RFCSR1_TX1_PD FIELD8(0x20)
  1428. /*
  1429. * RFCSR 6:
  1430. */
  1431. #define RFCSR6_R1 FIELD8(0x03)
  1432. #define RFCSR6_R2 FIELD8(0x40)
  1433. /*
  1434. * RFCSR 7:
  1435. */
  1436. #define RFCSR7_RF_TUNING FIELD8(0x01)
  1437. /*
  1438. * RFCSR 12:
  1439. */
  1440. #define RFCSR12_TX_POWER FIELD8(0x1f)
  1441. /*
  1442. * RFCSR 13:
  1443. */
  1444. #define RFCSR13_TX_POWER FIELD8(0x1f)
  1445. /*
  1446. * RFCSR 15:
  1447. */
  1448. #define RFCSR15_TX_LO2_EN FIELD8(0x08)
  1449. /*
  1450. * RFCSR 17:
  1451. */
  1452. #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
  1453. #define RFCSR17_TX_LO1_EN FIELD8(0x08)
  1454. #define RFCSR17_R FIELD8(0x20)
  1455. /*
  1456. * RFCSR 20:
  1457. */
  1458. #define RFCSR20_RX_LO1_EN FIELD8(0x08)
  1459. /*
  1460. * RFCSR 21:
  1461. */
  1462. #define RFCSR21_RX_LO2_EN FIELD8(0x08)
  1463. /*
  1464. * RFCSR 22:
  1465. */
  1466. #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
  1467. /*
  1468. * RFCSR 23:
  1469. */
  1470. #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
  1471. /*
  1472. * RFCSR 27:
  1473. */
  1474. #define RFCSR27_R1 FIELD8(0x03)
  1475. #define RFCSR27_R2 FIELD8(0x04)
  1476. #define RFCSR27_R3 FIELD8(0x30)
  1477. #define RFCSR27_R4 FIELD8(0x40)
  1478. /*
  1479. * RFCSR 30:
  1480. */
  1481. #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
  1482. /*
  1483. * RF registers
  1484. */
  1485. /*
  1486. * RF 2
  1487. */
  1488. #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
  1489. #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
  1490. #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
  1491. /*
  1492. * RF 3
  1493. */
  1494. #define RF3_TXPOWER_G FIELD32(0x00003e00)
  1495. #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
  1496. #define RF3_TXPOWER_A FIELD32(0x00003c00)
  1497. /*
  1498. * RF 4
  1499. */
  1500. #define RF4_TXPOWER_G FIELD32(0x000007c0)
  1501. #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
  1502. #define RF4_TXPOWER_A FIELD32(0x00000780)
  1503. #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
  1504. #define RF4_HT40 FIELD32(0x00200000)
  1505. /*
  1506. * EEPROM content.
  1507. * The wordsize of the EEPROM is 16 bits.
  1508. */
  1509. /*
  1510. * EEPROM Version
  1511. */
  1512. #define EEPROM_VERSION 0x0001
  1513. #define EEPROM_VERSION_FAE FIELD16(0x00ff)
  1514. #define EEPROM_VERSION_VERSION FIELD16(0xff00)
  1515. /*
  1516. * HW MAC address.
  1517. */
  1518. #define EEPROM_MAC_ADDR_0 0x0002
  1519. #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
  1520. #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
  1521. #define EEPROM_MAC_ADDR_1 0x0003
  1522. #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
  1523. #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
  1524. #define EEPROM_MAC_ADDR_2 0x0004
  1525. #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
  1526. #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
  1527. /*
  1528. * EEPROM ANTENNA config
  1529. * RXPATH: 1: 1R, 2: 2R, 3: 3R
  1530. * TXPATH: 1: 1T, 2: 2T
  1531. */
  1532. #define EEPROM_ANTENNA 0x001a
  1533. #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
  1534. #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
  1535. #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
  1536. /*
  1537. * EEPROM NIC config
  1538. * CARDBUS_ACCEL: 0 - enable, 1 - disable
  1539. */
  1540. #define EEPROM_NIC 0x001b
  1541. #define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
  1542. #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
  1543. #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
  1544. #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
  1545. #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
  1546. #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
  1547. #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
  1548. #define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
  1549. #define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
  1550. #define EEPROM_NIC_BW40M_A FIELD16(0x0200)
  1551. #define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800)
  1552. #define EEPROM_NIC_DAC_TEST FIELD16(0x8000)
  1553. /*
  1554. * EEPROM frequency
  1555. */
  1556. #define EEPROM_FREQ 0x001d
  1557. #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
  1558. #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
  1559. #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
  1560. /*
  1561. * EEPROM LED
  1562. * POLARITY_RDY_G: Polarity RDY_G setting.
  1563. * POLARITY_RDY_A: Polarity RDY_A setting.
  1564. * POLARITY_ACT: Polarity ACT setting.
  1565. * POLARITY_GPIO_0: Polarity GPIO0 setting.
  1566. * POLARITY_GPIO_1: Polarity GPIO1 setting.
  1567. * POLARITY_GPIO_2: Polarity GPIO2 setting.
  1568. * POLARITY_GPIO_3: Polarity GPIO3 setting.
  1569. * POLARITY_GPIO_4: Polarity GPIO4 setting.
  1570. * LED_MODE: Led mode.
  1571. */
  1572. #define EEPROM_LED1 0x001e
  1573. #define EEPROM_LED2 0x001f
  1574. #define EEPROM_LED3 0x0020
  1575. #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
  1576. #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
  1577. #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
  1578. #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
  1579. #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
  1580. #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
  1581. #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
  1582. #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
  1583. #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
  1584. /*
  1585. * EEPROM LNA
  1586. */
  1587. #define EEPROM_LNA 0x0022
  1588. #define EEPROM_LNA_BG FIELD16(0x00ff)
  1589. #define EEPROM_LNA_A0 FIELD16(0xff00)
  1590. /*
  1591. * EEPROM RSSI BG offset
  1592. */
  1593. #define EEPROM_RSSI_BG 0x0023
  1594. #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
  1595. #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
  1596. /*
  1597. * EEPROM RSSI BG2 offset
  1598. */
  1599. #define EEPROM_RSSI_BG2 0x0024
  1600. #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
  1601. #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
  1602. /*
  1603. * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
  1604. */
  1605. #define EEPROM_TXMIXER_GAIN_BG 0x0024
  1606. #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
  1607. /*
  1608. * EEPROM RSSI A offset
  1609. */
  1610. #define EEPROM_RSSI_A 0x0025
  1611. #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
  1612. #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
  1613. /*
  1614. * EEPROM RSSI A2 offset
  1615. */
  1616. #define EEPROM_RSSI_A2 0x0026
  1617. #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
  1618. #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
  1619. /*
  1620. * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
  1621. * This is delta in 40MHZ.
  1622. * VALUE: Tx Power dalta value (MAX=4)
  1623. * TYPE: 1: Plus the delta value, 0: minus the delta value
  1624. * TXPOWER: Enable:
  1625. */
  1626. #define EEPROM_TXPOWER_DELTA 0x0028
  1627. #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
  1628. #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
  1629. #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
  1630. /*
  1631. * EEPROM TXPOWER 802.11BG
  1632. */
  1633. #define EEPROM_TXPOWER_BG1 0x0029
  1634. #define EEPROM_TXPOWER_BG2 0x0030
  1635. #define EEPROM_TXPOWER_BG_SIZE 7
  1636. #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
  1637. #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
  1638. /*
  1639. * EEPROM TXPOWER 802.11A
  1640. */
  1641. #define EEPROM_TXPOWER_A1 0x003c
  1642. #define EEPROM_TXPOWER_A2 0x0053
  1643. #define EEPROM_TXPOWER_A_SIZE 6
  1644. #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
  1645. #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
  1646. /*
  1647. * EEPROM TXpower byrate: 20MHZ power
  1648. */
  1649. #define EEPROM_TXPOWER_BYRATE 0x006f
  1650. /*
  1651. * EEPROM BBP.
  1652. */
  1653. #define EEPROM_BBP_START 0x0078
  1654. #define EEPROM_BBP_SIZE 16
  1655. #define EEPROM_BBP_VALUE FIELD16(0x00ff)
  1656. #define EEPROM_BBP_REG_ID FIELD16(0xff00)
  1657. /*
  1658. * MCU mailbox commands.
  1659. */
  1660. #define MCU_SLEEP 0x30
  1661. #define MCU_WAKEUP 0x31
  1662. #define MCU_RADIO_OFF 0x35
  1663. #define MCU_CURRENT 0x36
  1664. #define MCU_LED 0x50
  1665. #define MCU_LED_STRENGTH 0x51
  1666. #define MCU_LED_1 0x52
  1667. #define MCU_LED_2 0x53
  1668. #define MCU_LED_3 0x54
  1669. #define MCU_RADAR 0x60
  1670. #define MCU_BOOT_SIGNAL 0x72
  1671. #define MCU_BBP_SIGNAL 0x80
  1672. #define MCU_POWER_SAVE 0x83
  1673. /*
  1674. * MCU mailbox tokens
  1675. */
  1676. #define TOKEN_WAKUP 3
  1677. /*
  1678. * DMA descriptor defines.
  1679. */
  1680. #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
  1681. #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
  1682. /*
  1683. * TX WI structure
  1684. */
  1685. /*
  1686. * Word0
  1687. * FRAG: 1 To inform TKIP engine this is a fragment.
  1688. * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
  1689. * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
  1690. * BW: Channel bandwidth 20MHz or 40 MHz
  1691. * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
  1692. */
  1693. #define TXWI_W0_FRAG FIELD32(0x00000001)
  1694. #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
  1695. #define TXWI_W0_CF_ACK FIELD32(0x00000004)
  1696. #define TXWI_W0_TS FIELD32(0x00000008)
  1697. #define TXWI_W0_AMPDU FIELD32(0x00000010)
  1698. #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
  1699. #define TXWI_W0_TX_OP FIELD32(0x00000300)
  1700. #define TXWI_W0_MCS FIELD32(0x007f0000)
  1701. #define TXWI_W0_BW FIELD32(0x00800000)
  1702. #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
  1703. #define TXWI_W0_STBC FIELD32(0x06000000)
  1704. #define TXWI_W0_IFS FIELD32(0x08000000)
  1705. #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
  1706. /*
  1707. * Word1
  1708. */
  1709. #define TXWI_W1_ACK FIELD32(0x00000001)
  1710. #define TXWI_W1_NSEQ FIELD32(0x00000002)
  1711. #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
  1712. #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
  1713. #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
  1714. #define TXWI_W1_PACKETID FIELD32(0xf0000000)
  1715. /*
  1716. * Word2
  1717. */
  1718. #define TXWI_W2_IV FIELD32(0xffffffff)
  1719. /*
  1720. * Word3
  1721. */
  1722. #define TXWI_W3_EIV FIELD32(0xffffffff)
  1723. /*
  1724. * RX WI structure
  1725. */
  1726. /*
  1727. * Word0
  1728. */
  1729. #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
  1730. #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
  1731. #define RXWI_W0_BSSID FIELD32(0x00001c00)
  1732. #define RXWI_W0_UDF FIELD32(0x0000e000)
  1733. #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
  1734. #define RXWI_W0_TID FIELD32(0xf0000000)
  1735. /*
  1736. * Word1
  1737. */
  1738. #define RXWI_W1_FRAG FIELD32(0x0000000f)
  1739. #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
  1740. #define RXWI_W1_MCS FIELD32(0x007f0000)
  1741. #define RXWI_W1_BW FIELD32(0x00800000)
  1742. #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
  1743. #define RXWI_W1_STBC FIELD32(0x06000000)
  1744. #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
  1745. /*
  1746. * Word2
  1747. */
  1748. #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
  1749. #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
  1750. #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
  1751. /*
  1752. * Word3
  1753. */
  1754. #define RXWI_W3_SNR0 FIELD32(0x000000ff)
  1755. #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
  1756. /*
  1757. * Macros for converting txpower from EEPROM to mac80211 value
  1758. * and from mac80211 value to register value.
  1759. */
  1760. #define MIN_G_TXPOWER 0
  1761. #define MIN_A_TXPOWER -7
  1762. #define MAX_G_TXPOWER 31
  1763. #define MAX_A_TXPOWER 15
  1764. #define DEFAULT_TXPOWER 5
  1765. #define TXPOWER_G_FROM_DEV(__txpower) \
  1766. ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
  1767. #define TXPOWER_G_TO_DEV(__txpower) \
  1768. clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
  1769. #define TXPOWER_A_FROM_DEV(__txpower) \
  1770. ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
  1771. #define TXPOWER_A_TO_DEV(__txpower) \
  1772. clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
  1773. #endif /* RT2800_H */