htc_drv_init.c 23 KB

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  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "htc.h"
  17. MODULE_AUTHOR("Atheros Communications");
  18. MODULE_LICENSE("Dual BSD/GPL");
  19. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  20. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  21. module_param_named(debug, ath9k_debug, uint, 0);
  22. MODULE_PARM_DESC(debug, "Debugging mask");
  23. int htc_modparam_nohwcrypt;
  24. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  25. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  26. #define CHAN2G(_freq, _idx) { \
  27. .center_freq = (_freq), \
  28. .hw_value = (_idx), \
  29. .max_power = 20, \
  30. }
  31. #define CHAN5G(_freq, _idx) { \
  32. .band = IEEE80211_BAND_5GHZ, \
  33. .center_freq = (_freq), \
  34. .hw_value = (_idx), \
  35. .max_power = 20, \
  36. }
  37. static struct ieee80211_channel ath9k_2ghz_channels[] = {
  38. CHAN2G(2412, 0), /* Channel 1 */
  39. CHAN2G(2417, 1), /* Channel 2 */
  40. CHAN2G(2422, 2), /* Channel 3 */
  41. CHAN2G(2427, 3), /* Channel 4 */
  42. CHAN2G(2432, 4), /* Channel 5 */
  43. CHAN2G(2437, 5), /* Channel 6 */
  44. CHAN2G(2442, 6), /* Channel 7 */
  45. CHAN2G(2447, 7), /* Channel 8 */
  46. CHAN2G(2452, 8), /* Channel 9 */
  47. CHAN2G(2457, 9), /* Channel 10 */
  48. CHAN2G(2462, 10), /* Channel 11 */
  49. CHAN2G(2467, 11), /* Channel 12 */
  50. CHAN2G(2472, 12), /* Channel 13 */
  51. CHAN2G(2484, 13), /* Channel 14 */
  52. };
  53. static struct ieee80211_channel ath9k_5ghz_channels[] = {
  54. /* _We_ call this UNII 1 */
  55. CHAN5G(5180, 14), /* Channel 36 */
  56. CHAN5G(5200, 15), /* Channel 40 */
  57. CHAN5G(5220, 16), /* Channel 44 */
  58. CHAN5G(5240, 17), /* Channel 48 */
  59. /* _We_ call this UNII 2 */
  60. CHAN5G(5260, 18), /* Channel 52 */
  61. CHAN5G(5280, 19), /* Channel 56 */
  62. CHAN5G(5300, 20), /* Channel 60 */
  63. CHAN5G(5320, 21), /* Channel 64 */
  64. /* _We_ call this "Middle band" */
  65. CHAN5G(5500, 22), /* Channel 100 */
  66. CHAN5G(5520, 23), /* Channel 104 */
  67. CHAN5G(5540, 24), /* Channel 108 */
  68. CHAN5G(5560, 25), /* Channel 112 */
  69. CHAN5G(5580, 26), /* Channel 116 */
  70. CHAN5G(5600, 27), /* Channel 120 */
  71. CHAN5G(5620, 28), /* Channel 124 */
  72. CHAN5G(5640, 29), /* Channel 128 */
  73. CHAN5G(5660, 30), /* Channel 132 */
  74. CHAN5G(5680, 31), /* Channel 136 */
  75. CHAN5G(5700, 32), /* Channel 140 */
  76. /* _We_ call this UNII 3 */
  77. CHAN5G(5745, 33), /* Channel 149 */
  78. CHAN5G(5765, 34), /* Channel 153 */
  79. CHAN5G(5785, 35), /* Channel 157 */
  80. CHAN5G(5805, 36), /* Channel 161 */
  81. CHAN5G(5825, 37), /* Channel 165 */
  82. };
  83. /* Atheros hardware rate code addition for short premble */
  84. #define SHPCHECK(__hw_rate, __flags) \
  85. ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  86. #define RATE(_bitrate, _hw_rate, _flags) { \
  87. .bitrate = (_bitrate), \
  88. .flags = (_flags), \
  89. .hw_value = (_hw_rate), \
  90. .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
  91. }
  92. static struct ieee80211_rate ath9k_legacy_rates[] = {
  93. RATE(10, 0x1b, 0),
  94. RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
  95. RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
  96. RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
  97. RATE(60, 0x0b, 0),
  98. RATE(90, 0x0f, 0),
  99. RATE(120, 0x0a, 0),
  100. RATE(180, 0x0e, 0),
  101. RATE(240, 0x09, 0),
  102. RATE(360, 0x0d, 0),
  103. RATE(480, 0x08, 0),
  104. RATE(540, 0x0c, 0),
  105. };
  106. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  107. {
  108. int time_left;
  109. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  110. atomic_dec(&priv->htc->tgt_ready);
  111. return 0;
  112. }
  113. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  114. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  115. if (!time_left) {
  116. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  117. return -ETIMEDOUT;
  118. }
  119. atomic_dec(&priv->htc->tgt_ready);
  120. return 0;
  121. }
  122. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  123. {
  124. ath9k_htc_exit_debug(priv->ah);
  125. ath9k_hw_deinit(priv->ah);
  126. tasklet_kill(&priv->wmi_tasklet);
  127. tasklet_kill(&priv->rx_tasklet);
  128. tasklet_kill(&priv->tx_tasklet);
  129. kfree(priv->ah);
  130. priv->ah = NULL;
  131. }
  132. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  133. {
  134. struct ieee80211_hw *hw = priv->hw;
  135. wiphy_rfkill_stop_polling(hw->wiphy);
  136. ath9k_deinit_leds(priv);
  137. ieee80211_unregister_hw(hw);
  138. ath9k_rx_cleanup(priv);
  139. ath9k_tx_cleanup(priv);
  140. ath9k_deinit_priv(priv);
  141. }
  142. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  143. u16 service_id,
  144. void (*tx) (void *,
  145. struct sk_buff *,
  146. enum htc_endpoint_id,
  147. bool txok),
  148. enum htc_endpoint_id *ep_id)
  149. {
  150. struct htc_service_connreq req;
  151. memset(&req, 0, sizeof(struct htc_service_connreq));
  152. req.service_id = service_id;
  153. req.ep_callbacks.priv = priv;
  154. req.ep_callbacks.rx = ath9k_htc_rxep;
  155. req.ep_callbacks.tx = tx;
  156. return htc_connect_service(priv->htc, &req, ep_id);
  157. }
  158. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
  159. {
  160. int ret;
  161. /* WMI CMD*/
  162. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  163. if (ret)
  164. goto err;
  165. /* Beacon */
  166. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  167. &priv->beacon_ep);
  168. if (ret)
  169. goto err;
  170. /* CAB */
  171. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  172. &priv->cab_ep);
  173. if (ret)
  174. goto err;
  175. /* UAPSD */
  176. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  177. &priv->uapsd_ep);
  178. if (ret)
  179. goto err;
  180. /* MGMT */
  181. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  182. &priv->mgmt_ep);
  183. if (ret)
  184. goto err;
  185. /* DATA BE */
  186. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  187. &priv->data_be_ep);
  188. if (ret)
  189. goto err;
  190. /* DATA BK */
  191. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  192. &priv->data_bk_ep);
  193. if (ret)
  194. goto err;
  195. /* DATA VI */
  196. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  197. &priv->data_vi_ep);
  198. if (ret)
  199. goto err;
  200. /* DATA VO */
  201. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  202. &priv->data_vo_ep);
  203. if (ret)
  204. goto err;
  205. /*
  206. * Setup required credits before initializing HTC.
  207. * This is a bit hacky, but, since queuing is done in
  208. * the HIF layer, shouldn't matter much.
  209. */
  210. switch(devid) {
  211. case 0x9271:
  212. case 0x1006:
  213. priv->htc->credits = 33;
  214. break;
  215. case 0x7010:
  216. priv->htc->credits = 45;
  217. break;
  218. default:
  219. dev_err(priv->dev, "ath9k_htc: Unsupported device id: 0x%x\n",
  220. devid);
  221. goto err;
  222. }
  223. ret = htc_init(priv->htc);
  224. if (ret)
  225. goto err;
  226. dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
  227. priv->htc->credits);
  228. return 0;
  229. err:
  230. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  231. return ret;
  232. }
  233. static int ath9k_reg_notifier(struct wiphy *wiphy,
  234. struct regulatory_request *request)
  235. {
  236. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  237. struct ath9k_htc_priv *priv = hw->priv;
  238. return ath_reg_notifier_apply(wiphy, request,
  239. ath9k_hw_regulatory(priv->ah));
  240. }
  241. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  242. {
  243. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  244. struct ath_common *common = ath9k_hw_common(ah);
  245. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  246. __be32 val, reg = cpu_to_be32(reg_offset);
  247. int r;
  248. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  249. (u8 *) &reg, sizeof(reg),
  250. (u8 *) &val, sizeof(val),
  251. 100);
  252. if (unlikely(r)) {
  253. ath_print(common, ATH_DBG_WMI,
  254. "REGISTER READ FAILED: (0x%04x, %d)\n",
  255. reg_offset, r);
  256. return -EIO;
  257. }
  258. return be32_to_cpu(val);
  259. }
  260. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  261. {
  262. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  263. struct ath_common *common = ath9k_hw_common(ah);
  264. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  265. __be32 buf[2] = {
  266. cpu_to_be32(reg_offset),
  267. cpu_to_be32(val),
  268. };
  269. int r;
  270. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  271. (u8 *) &buf, sizeof(buf),
  272. (u8 *) &val, sizeof(val),
  273. 100);
  274. if (unlikely(r)) {
  275. ath_print(common, ATH_DBG_WMI,
  276. "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  277. reg_offset, r);
  278. }
  279. }
  280. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  281. {
  282. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  283. struct ath_common *common = ath9k_hw_common(ah);
  284. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  285. u32 rsp_status;
  286. int r;
  287. mutex_lock(&priv->wmi->multi_write_mutex);
  288. /* Store the register/value */
  289. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  290. cpu_to_be32(reg_offset);
  291. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  292. cpu_to_be32(val);
  293. priv->wmi->multi_write_idx++;
  294. /* If the buffer is full, send it out. */
  295. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
  296. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  297. (u8 *) &priv->wmi->multi_write,
  298. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  299. (u8 *) &rsp_status, sizeof(rsp_status),
  300. 100);
  301. if (unlikely(r)) {
  302. ath_print(common, ATH_DBG_WMI,
  303. "REGISTER WRITE FAILED, multi len: %d\n",
  304. priv->wmi->multi_write_idx);
  305. }
  306. priv->wmi->multi_write_idx = 0;
  307. }
  308. mutex_unlock(&priv->wmi->multi_write_mutex);
  309. }
  310. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  311. {
  312. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  313. struct ath_common *common = ath9k_hw_common(ah);
  314. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  315. if (atomic_read(&priv->wmi->mwrite_cnt))
  316. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  317. else
  318. ath9k_regwrite_single(hw_priv, val, reg_offset);
  319. }
  320. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  321. {
  322. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  323. struct ath_common *common = ath9k_hw_common(ah);
  324. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  325. atomic_inc(&priv->wmi->mwrite_cnt);
  326. }
  327. static void ath9k_disable_regwrite_buffer(void *hw_priv)
  328. {
  329. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  330. struct ath_common *common = ath9k_hw_common(ah);
  331. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  332. atomic_dec(&priv->wmi->mwrite_cnt);
  333. }
  334. static void ath9k_regwrite_flush(void *hw_priv)
  335. {
  336. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  337. struct ath_common *common = ath9k_hw_common(ah);
  338. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  339. u32 rsp_status;
  340. int r;
  341. mutex_lock(&priv->wmi->multi_write_mutex);
  342. if (priv->wmi->multi_write_idx) {
  343. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  344. (u8 *) &priv->wmi->multi_write,
  345. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  346. (u8 *) &rsp_status, sizeof(rsp_status),
  347. 100);
  348. if (unlikely(r)) {
  349. ath_print(common, ATH_DBG_WMI,
  350. "REGISTER WRITE FAILED, multi len: %d\n",
  351. priv->wmi->multi_write_idx);
  352. }
  353. priv->wmi->multi_write_idx = 0;
  354. }
  355. mutex_unlock(&priv->wmi->multi_write_mutex);
  356. }
  357. static const struct ath_ops ath9k_common_ops = {
  358. .read = ath9k_regread,
  359. .write = ath9k_regwrite,
  360. .enable_write_buffer = ath9k_enable_regwrite_buffer,
  361. .disable_write_buffer = ath9k_disable_regwrite_buffer,
  362. .write_flush = ath9k_regwrite_flush,
  363. };
  364. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  365. {
  366. *csz = L1_CACHE_BYTES >> 2;
  367. }
  368. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  369. {
  370. struct ath_hw *ah = (struct ath_hw *) common->ah;
  371. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  372. if (!ath9k_hw_wait(ah,
  373. AR_EEPROM_STATUS_DATA,
  374. AR_EEPROM_STATUS_DATA_BUSY |
  375. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  376. AH_WAIT_TIMEOUT))
  377. return false;
  378. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  379. AR_EEPROM_STATUS_DATA_VAL);
  380. return true;
  381. }
  382. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  383. .ath_bus_type = ATH_USB,
  384. .read_cachesize = ath_usb_read_cachesize,
  385. .eeprom_read = ath_usb_eeprom_read,
  386. };
  387. static void setup_ht_cap(struct ath9k_htc_priv *priv,
  388. struct ieee80211_sta_ht_cap *ht_info)
  389. {
  390. struct ath_common *common = ath9k_hw_common(priv->ah);
  391. u8 tx_streams, rx_streams;
  392. int i;
  393. ht_info->ht_supported = true;
  394. ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  395. IEEE80211_HT_CAP_SM_PS |
  396. IEEE80211_HT_CAP_SGI_40 |
  397. IEEE80211_HT_CAP_DSSSCCK40;
  398. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
  399. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  400. ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
  401. ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
  402. ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
  403. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  404. /* ath9k_htc supports only 1 or 2 stream devices */
  405. tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
  406. rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
  407. ath_print(common, ATH_DBG_CONFIG,
  408. "TX streams %d, RX streams: %d\n",
  409. tx_streams, rx_streams);
  410. if (tx_streams != rx_streams) {
  411. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  412. ht_info->mcs.tx_params |= ((tx_streams - 1) <<
  413. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  414. }
  415. for (i = 0; i < rx_streams; i++)
  416. ht_info->mcs.rx_mask[i] = 0xff;
  417. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
  418. }
  419. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  420. {
  421. struct ath_common *common = ath9k_hw_common(priv->ah);
  422. int i;
  423. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  424. priv->hwq_map[i] = -1;
  425. priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
  426. if (priv->beaconq == -1) {
  427. ath_print(common, ATH_DBG_FATAL,
  428. "Unable to setup BEACON xmit queue\n");
  429. goto err;
  430. }
  431. priv->cabq = ath9k_htc_cabq_setup(priv);
  432. if (priv->cabq == -1) {
  433. ath_print(common, ATH_DBG_FATAL,
  434. "Unable to setup CAB xmit queue\n");
  435. goto err;
  436. }
  437. if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
  438. ath_print(common, ATH_DBG_FATAL,
  439. "Unable to setup xmit queue for BE traffic\n");
  440. goto err;
  441. }
  442. if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
  443. ath_print(common, ATH_DBG_FATAL,
  444. "Unable to setup xmit queue for BK traffic\n");
  445. goto err;
  446. }
  447. if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
  448. ath_print(common, ATH_DBG_FATAL,
  449. "Unable to setup xmit queue for VI traffic\n");
  450. goto err;
  451. }
  452. if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
  453. ath_print(common, ATH_DBG_FATAL,
  454. "Unable to setup xmit queue for VO traffic\n");
  455. goto err;
  456. }
  457. return 0;
  458. err:
  459. return -EINVAL;
  460. }
  461. static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
  462. {
  463. struct ath_common *common = ath9k_hw_common(priv->ah);
  464. int i = 0;
  465. /* Get the hardware key cache size. */
  466. common->keymax = priv->ah->caps.keycache_size;
  467. if (common->keymax > ATH_KEYMAX) {
  468. ath_print(common, ATH_DBG_ANY,
  469. "Warning, using only %u entries in %u key cache\n",
  470. ATH_KEYMAX, common->keymax);
  471. common->keymax = ATH_KEYMAX;
  472. }
  473. /*
  474. * Reset the key cache since some parts do not
  475. * reset the contents on initial power up.
  476. */
  477. for (i = 0; i < common->keymax; i++)
  478. ath9k_hw_keyreset(priv->ah, (u16) i);
  479. }
  480. static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
  481. {
  482. if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
  483. priv->sbands[IEEE80211_BAND_2GHZ].channels =
  484. ath9k_2ghz_channels;
  485. priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
  486. priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
  487. ARRAY_SIZE(ath9k_2ghz_channels);
  488. priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
  489. priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
  490. ARRAY_SIZE(ath9k_legacy_rates);
  491. }
  492. if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) {
  493. priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
  494. priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
  495. priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
  496. ARRAY_SIZE(ath9k_5ghz_channels);
  497. priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
  498. ath9k_legacy_rates + 4;
  499. priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
  500. ARRAY_SIZE(ath9k_legacy_rates) - 4;
  501. }
  502. }
  503. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  504. {
  505. struct ath_common *common = ath9k_hw_common(priv->ah);
  506. common->tx_chainmask = priv->ah->caps.tx_chainmask;
  507. common->rx_chainmask = priv->ah->caps.rx_chainmask;
  508. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  509. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  510. priv->op_flags |= OP_TXAGGR;
  511. priv->ah->opmode = NL80211_IFTYPE_STATION;
  512. }
  513. static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
  514. {
  515. struct ath_hw *ah = NULL;
  516. struct ath_common *common;
  517. int ret = 0, csz = 0;
  518. priv->op_flags |= OP_INVALID;
  519. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  520. if (!ah)
  521. return -ENOMEM;
  522. ah->hw_version.devid = devid;
  523. ah->hw_version.subsysid = 0; /* FIXME */
  524. priv->ah = ah;
  525. common = ath9k_hw_common(ah);
  526. common->ops = &ath9k_common_ops;
  527. common->bus_ops = &ath9k_usb_bus_ops;
  528. common->ah = ah;
  529. common->hw = priv->hw;
  530. common->priv = priv;
  531. common->debug_mask = ath9k_debug;
  532. spin_lock_init(&priv->wmi->wmi_lock);
  533. spin_lock_init(&priv->beacon_lock);
  534. spin_lock_init(&priv->tx_lock);
  535. mutex_init(&priv->mutex);
  536. mutex_init(&priv->aggr_work.mutex);
  537. mutex_init(&priv->htc_pm_lock);
  538. tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
  539. (unsigned long)priv);
  540. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  541. (unsigned long)priv);
  542. tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
  543. INIT_DELAYED_WORK(&priv->ath9k_aggr_work, ath9k_htc_aggr_work);
  544. INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
  545. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  546. /*
  547. * Cache line size is used to size and align various
  548. * structures used to communicate with the hardware.
  549. */
  550. ath_read_cachesize(common, &csz);
  551. common->cachelsz = csz << 2; /* convert to bytes */
  552. ret = ath9k_hw_init(ah);
  553. if (ret) {
  554. ath_print(common, ATH_DBG_FATAL,
  555. "Unable to initialize hardware; "
  556. "initialization status: %d\n", ret);
  557. goto err_hw;
  558. }
  559. ret = ath9k_htc_init_debug(ah);
  560. if (ret) {
  561. ath_print(common, ATH_DBG_FATAL,
  562. "Unable to create debugfs files\n");
  563. goto err_debug;
  564. }
  565. ret = ath9k_init_queues(priv);
  566. if (ret)
  567. goto err_queues;
  568. ath9k_init_crypto(priv);
  569. ath9k_init_channels_rates(priv);
  570. ath9k_init_misc(priv);
  571. return 0;
  572. err_queues:
  573. ath9k_htc_exit_debug(ah);
  574. err_debug:
  575. ath9k_hw_deinit(ah);
  576. err_hw:
  577. kfree(ah);
  578. priv->ah = NULL;
  579. return ret;
  580. }
  581. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  582. struct ieee80211_hw *hw)
  583. {
  584. struct ath_common *common = ath9k_hw_common(priv->ah);
  585. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  586. IEEE80211_HW_AMPDU_AGGREGATION |
  587. IEEE80211_HW_SPECTRUM_MGMT |
  588. IEEE80211_HW_HAS_RATE_CONTROL |
  589. IEEE80211_HW_RX_INCLUDES_FCS |
  590. IEEE80211_HW_SUPPORTS_PS |
  591. IEEE80211_HW_PS_NULLFUNC_STACK;
  592. hw->wiphy->interface_modes =
  593. BIT(NL80211_IFTYPE_STATION) |
  594. BIT(NL80211_IFTYPE_ADHOC);
  595. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  596. hw->queues = 4;
  597. hw->channel_change_time = 5000;
  598. hw->max_listen_interval = 10;
  599. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  600. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  601. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  602. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  603. sizeof(struct htc_frame_hdr) + 4;
  604. if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
  605. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  606. &priv->sbands[IEEE80211_BAND_2GHZ];
  607. if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
  608. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  609. &priv->sbands[IEEE80211_BAND_5GHZ];
  610. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
  611. if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
  612. setup_ht_cap(priv,
  613. &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
  614. if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes))
  615. setup_ht_cap(priv,
  616. &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
  617. }
  618. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  619. }
  620. static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
  621. {
  622. struct ieee80211_hw *hw = priv->hw;
  623. struct ath_common *common;
  624. struct ath_hw *ah;
  625. int error = 0;
  626. struct ath_regulatory *reg;
  627. /* Bring up device */
  628. error = ath9k_init_priv(priv, devid);
  629. if (error != 0)
  630. goto err_init;
  631. ah = priv->ah;
  632. common = ath9k_hw_common(ah);
  633. ath9k_set_hw_capab(priv, hw);
  634. /* Initialize regulatory */
  635. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  636. ath9k_reg_notifier);
  637. if (error)
  638. goto err_regd;
  639. reg = &common->regulatory;
  640. /* Setup TX */
  641. error = ath9k_tx_init(priv);
  642. if (error != 0)
  643. goto err_tx;
  644. /* Setup RX */
  645. error = ath9k_rx_init(priv);
  646. if (error != 0)
  647. goto err_rx;
  648. /* Register with mac80211 */
  649. error = ieee80211_register_hw(hw);
  650. if (error)
  651. goto err_register;
  652. /* Handle world regulatory */
  653. if (!ath_is_world_regd(reg)) {
  654. error = regulatory_hint(hw->wiphy, reg->alpha2);
  655. if (error)
  656. goto err_world;
  657. }
  658. ath9k_init_leds(priv);
  659. ath9k_start_rfkill_poll(priv);
  660. return 0;
  661. err_world:
  662. ieee80211_unregister_hw(hw);
  663. err_register:
  664. ath9k_rx_cleanup(priv);
  665. err_rx:
  666. ath9k_tx_cleanup(priv);
  667. err_tx:
  668. /* Nothing */
  669. err_regd:
  670. ath9k_deinit_priv(priv);
  671. err_init:
  672. return error;
  673. }
  674. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  675. u16 devid)
  676. {
  677. struct ieee80211_hw *hw;
  678. struct ath9k_htc_priv *priv;
  679. int ret;
  680. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  681. if (!hw)
  682. return -ENOMEM;
  683. priv = hw->priv;
  684. priv->hw = hw;
  685. priv->htc = htc_handle;
  686. priv->dev = dev;
  687. htc_handle->drv_priv = priv;
  688. SET_IEEE80211_DEV(hw, priv->dev);
  689. ret = ath9k_htc_wait_for_target(priv);
  690. if (ret)
  691. goto err_free;
  692. priv->wmi = ath9k_init_wmi(priv);
  693. if (!priv->wmi) {
  694. ret = -EINVAL;
  695. goto err_free;
  696. }
  697. ret = ath9k_init_htc_services(priv, devid);
  698. if (ret)
  699. goto err_init;
  700. /* The device may have been unplugged earlier. */
  701. priv->op_flags &= ~OP_UNPLUGGED;
  702. ret = ath9k_init_device(priv, devid);
  703. if (ret)
  704. goto err_init;
  705. return 0;
  706. err_init:
  707. ath9k_deinit_wmi(priv);
  708. err_free:
  709. ieee80211_free_hw(hw);
  710. return ret;
  711. }
  712. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  713. {
  714. if (htc_handle->drv_priv) {
  715. /* Check if the device has been yanked out. */
  716. if (hotunplug)
  717. htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
  718. ath9k_deinit_device(htc_handle->drv_priv);
  719. ath9k_deinit_wmi(htc_handle->drv_priv);
  720. ieee80211_free_hw(htc_handle->drv_priv->hw);
  721. }
  722. }
  723. #ifdef CONFIG_PM
  724. int ath9k_htc_resume(struct htc_target *htc_handle)
  725. {
  726. int ret;
  727. ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
  728. if (ret)
  729. return ret;
  730. ret = ath9k_init_htc_services(htc_handle->drv_priv,
  731. htc_handle->drv_priv->ah->hw_version.devid);
  732. return ret;
  733. }
  734. #endif
  735. static int __init ath9k_htc_init(void)
  736. {
  737. int error;
  738. error = ath9k_htc_debug_create_root();
  739. if (error < 0) {
  740. printk(KERN_ERR
  741. "ath9k_htc: Unable to create debugfs root: %d\n",
  742. error);
  743. goto err_dbg;
  744. }
  745. error = ath9k_hif_usb_init();
  746. if (error < 0) {
  747. printk(KERN_ERR
  748. "ath9k_htc: No USB devices found,"
  749. " driver not installed.\n");
  750. error = -ENODEV;
  751. goto err_usb;
  752. }
  753. return 0;
  754. err_usb:
  755. ath9k_htc_debug_remove_root();
  756. err_dbg:
  757. return error;
  758. }
  759. module_init(ath9k_htc_init);
  760. static void __exit ath9k_htc_exit(void)
  761. {
  762. ath9k_hif_usb_exit();
  763. ath9k_htc_debug_remove_root();
  764. printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
  765. }
  766. module_exit(ath9k_htc_exit);