netxen_nic_init.c 36 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. if (recv_ctx->rds_rings == NULL)
  163. goto skip_rds;
  164. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  165. rds_ring = &recv_ctx->rds_rings[ring];
  166. if (rds_ring->rx_buf_arr) {
  167. vfree(rds_ring->rx_buf_arr);
  168. rds_ring->rx_buf_arr = NULL;
  169. }
  170. }
  171. kfree(recv_ctx->rds_rings);
  172. skip_rds:
  173. if (adapter->tx_ring == NULL)
  174. return;
  175. tx_ring = adapter->tx_ring;
  176. if (tx_ring->cmd_buf_arr)
  177. vfree(tx_ring->cmd_buf_arr);
  178. }
  179. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  180. {
  181. struct netxen_recv_context *recv_ctx;
  182. struct nx_host_rds_ring *rds_ring;
  183. struct nx_host_sds_ring *sds_ring;
  184. struct nx_host_tx_ring *tx_ring;
  185. struct netxen_rx_buffer *rx_buf;
  186. int ring, i, size;
  187. struct netxen_cmd_buffer *cmd_buf_arr;
  188. struct net_device *netdev = adapter->netdev;
  189. struct pci_dev *pdev = adapter->pdev;
  190. size = sizeof(struct nx_host_tx_ring);
  191. tx_ring = kzalloc(size, GFP_KERNEL);
  192. if (tx_ring == NULL) {
  193. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  194. netdev->name);
  195. return -ENOMEM;
  196. }
  197. adapter->tx_ring = tx_ring;
  198. tx_ring->num_desc = adapter->num_txd;
  199. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  200. if (cmd_buf_arr == NULL) {
  201. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  202. netdev->name);
  203. return -ENOMEM;
  204. }
  205. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  206. tx_ring->cmd_buf_arr = cmd_buf_arr;
  207. recv_ctx = &adapter->recv_ctx;
  208. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  209. rds_ring = kzalloc(size, GFP_KERNEL);
  210. if (rds_ring == NULL) {
  211. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  212. netdev->name);
  213. return -ENOMEM;
  214. }
  215. recv_ctx->rds_rings = rds_ring;
  216. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  217. rds_ring = &recv_ctx->rds_rings[ring];
  218. switch (ring) {
  219. case RCV_RING_NORMAL:
  220. rds_ring->num_desc = adapter->num_rxd;
  221. if (adapter->ahw.cut_through) {
  222. rds_ring->dma_size =
  223. NX_CT_DEFAULT_RX_BUF_LEN;
  224. rds_ring->skb_size =
  225. NX_CT_DEFAULT_RX_BUF_LEN;
  226. } else {
  227. rds_ring->dma_size = RX_DMA_MAP_LEN;
  228. rds_ring->skb_size =
  229. MAX_RX_BUFFER_LENGTH;
  230. }
  231. break;
  232. case RCV_RING_JUMBO:
  233. rds_ring->num_desc = adapter->num_jumbo_rxd;
  234. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  235. rds_ring->dma_size =
  236. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  237. else
  238. rds_ring->dma_size =
  239. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  240. rds_ring->skb_size =
  241. rds_ring->dma_size + NET_IP_ALIGN;
  242. break;
  243. case RCV_RING_LRO:
  244. rds_ring->num_desc = adapter->num_lro_rxd;
  245. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  246. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  247. break;
  248. }
  249. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  250. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  251. if (rds_ring->rx_buf_arr == NULL) {
  252. printk(KERN_ERR "%s: Failed to allocate "
  253. "rx buffer ring %d\n",
  254. netdev->name, ring);
  255. /* free whatever was already allocated */
  256. goto err_out;
  257. }
  258. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  259. INIT_LIST_HEAD(&rds_ring->free_list);
  260. /*
  261. * Now go through all of them, set reference handles
  262. * and put them in the queues.
  263. */
  264. rx_buf = rds_ring->rx_buf_arr;
  265. for (i = 0; i < rds_ring->num_desc; i++) {
  266. list_add_tail(&rx_buf->list,
  267. &rds_ring->free_list);
  268. rx_buf->ref_handle = i;
  269. rx_buf->state = NETXEN_BUFFER_FREE;
  270. rx_buf++;
  271. }
  272. spin_lock_init(&rds_ring->lock);
  273. }
  274. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  275. sds_ring = &recv_ctx->sds_rings[ring];
  276. sds_ring->irq = adapter->msix_entries[ring].vector;
  277. sds_ring->adapter = adapter;
  278. sds_ring->num_desc = adapter->num_rxd;
  279. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  280. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  281. }
  282. return 0;
  283. err_out:
  284. netxen_free_sw_resources(adapter);
  285. return -ENOMEM;
  286. }
  287. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  288. {
  289. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  290. adapter->set_multi = netxen_p2_nic_set_multi;
  291. switch (adapter->ahw.port_type) {
  292. case NETXEN_NIC_GBE:
  293. adapter->enable_phy_interrupts =
  294. netxen_niu_gbe_enable_phy_interrupts;
  295. adapter->disable_phy_interrupts =
  296. netxen_niu_gbe_disable_phy_interrupts;
  297. adapter->set_mtu = netxen_nic_set_mtu_gb;
  298. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  299. adapter->phy_read = netxen_niu_gbe_phy_read;
  300. adapter->phy_write = netxen_niu_gbe_phy_write;
  301. adapter->init_port = netxen_niu_gbe_init_port;
  302. adapter->stop_port = netxen_niu_disable_gbe_port;
  303. break;
  304. case NETXEN_NIC_XGBE:
  305. adapter->enable_phy_interrupts =
  306. netxen_niu_xgbe_enable_phy_interrupts;
  307. adapter->disable_phy_interrupts =
  308. netxen_niu_xgbe_disable_phy_interrupts;
  309. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  310. adapter->init_port = netxen_niu_xg_init_port;
  311. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  312. adapter->stop_port = netxen_niu_disable_xg_port;
  313. break;
  314. default:
  315. break;
  316. }
  317. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  318. adapter->set_mtu = nx_fw_cmd_set_mtu;
  319. adapter->set_promisc = netxen_p3_nic_set_promisc;
  320. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  321. adapter->set_multi = netxen_p3_nic_set_multi;
  322. }
  323. }
  324. /*
  325. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  326. * address to external PCI CRB address.
  327. */
  328. static u32 netxen_decode_crb_addr(u32 addr)
  329. {
  330. int i;
  331. u32 base_addr, offset, pci_base;
  332. crb_addr_transform_setup();
  333. pci_base = NETXEN_ADDR_ERROR;
  334. base_addr = addr & 0xfff00000;
  335. offset = addr & 0x000fffff;
  336. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  337. if (crb_addr_xform[i] == base_addr) {
  338. pci_base = i << 20;
  339. break;
  340. }
  341. }
  342. if (pci_base == NETXEN_ADDR_ERROR)
  343. return pci_base;
  344. else
  345. return (pci_base + offset);
  346. }
  347. static long rom_max_timeout = 100;
  348. static long rom_lock_timeout = 10000;
  349. static int rom_lock(struct netxen_adapter *adapter)
  350. {
  351. int iter;
  352. u32 done = 0;
  353. int timeout = 0;
  354. while (!done) {
  355. /* acquire semaphore2 from PCI HW block */
  356. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  357. if (done == 1)
  358. break;
  359. if (timeout >= rom_lock_timeout)
  360. return -EIO;
  361. timeout++;
  362. /*
  363. * Yield CPU
  364. */
  365. if (!in_atomic())
  366. schedule();
  367. else {
  368. for (iter = 0; iter < 20; iter++)
  369. cpu_relax(); /*This a nop instr on i386 */
  370. }
  371. }
  372. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  373. return 0;
  374. }
  375. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  376. {
  377. long timeout = 0;
  378. long done = 0;
  379. cond_resched();
  380. while (done == 0) {
  381. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  382. done &= 2;
  383. timeout++;
  384. if (timeout >= rom_max_timeout) {
  385. printk("Timeout reached waiting for rom done");
  386. return -EIO;
  387. }
  388. }
  389. return 0;
  390. }
  391. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  392. {
  393. /* release semaphore2 */
  394. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  395. }
  396. static int do_rom_fast_read(struct netxen_adapter *adapter,
  397. int addr, int *valp)
  398. {
  399. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  400. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  401. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  402. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  403. if (netxen_wait_rom_done(adapter)) {
  404. printk("Error waiting for rom done\n");
  405. return -EIO;
  406. }
  407. /* reset abyte_cnt and dummy_byte_cnt */
  408. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  409. udelay(10);
  410. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  411. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  412. return 0;
  413. }
  414. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  415. u8 *bytes, size_t size)
  416. {
  417. int addridx;
  418. int ret = 0;
  419. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  420. int v;
  421. ret = do_rom_fast_read(adapter, addridx, &v);
  422. if (ret != 0)
  423. break;
  424. *(__le32 *)bytes = cpu_to_le32(v);
  425. bytes += 4;
  426. }
  427. return ret;
  428. }
  429. int
  430. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  431. u8 *bytes, size_t size)
  432. {
  433. int ret;
  434. ret = rom_lock(adapter);
  435. if (ret < 0)
  436. return ret;
  437. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  438. netxen_rom_unlock(adapter);
  439. return ret;
  440. }
  441. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  442. {
  443. int ret;
  444. if (rom_lock(adapter) != 0)
  445. return -EIO;
  446. ret = do_rom_fast_read(adapter, addr, valp);
  447. netxen_rom_unlock(adapter);
  448. return ret;
  449. }
  450. #define NETXEN_BOARDTYPE 0x4008
  451. #define NETXEN_BOARDNUM 0x400c
  452. #define NETXEN_CHIPNUM 0x4010
  453. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  454. {
  455. int addr, val;
  456. int i, n, init_delay = 0;
  457. struct crb_addr_pair *buf;
  458. unsigned offset;
  459. u32 off;
  460. /* resetall */
  461. rom_lock(adapter);
  462. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  463. netxen_rom_unlock(adapter);
  464. if (verbose) {
  465. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  466. printk("P2 ROM board type: 0x%08x\n", val);
  467. else
  468. printk("Could not read board type\n");
  469. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  470. printk("P2 ROM board num: 0x%08x\n", val);
  471. else
  472. printk("Could not read board number\n");
  473. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  474. printk("P2 ROM chip num: 0x%08x\n", val);
  475. else
  476. printk("Could not read chip number\n");
  477. }
  478. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  479. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  480. (n != 0xcafecafe) ||
  481. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  482. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  483. "n: %08x\n", netxen_nic_driver_name, n);
  484. return -EIO;
  485. }
  486. offset = n & 0xffffU;
  487. n = (n >> 16) & 0xffffU;
  488. } else {
  489. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  490. !(n & 0x80000000)) {
  491. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  492. "n: %08x\n", netxen_nic_driver_name, n);
  493. return -EIO;
  494. }
  495. offset = 1;
  496. n &= ~0x80000000;
  497. }
  498. if (n < 1024) {
  499. if (verbose)
  500. printk(KERN_DEBUG "%s: %d CRB init values found"
  501. " in ROM.\n", netxen_nic_driver_name, n);
  502. } else {
  503. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  504. " initialized.\n", __func__, n);
  505. return -EIO;
  506. }
  507. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  508. if (buf == NULL) {
  509. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  510. netxen_nic_driver_name);
  511. return -ENOMEM;
  512. }
  513. for (i = 0; i < n; i++) {
  514. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  515. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  516. kfree(buf);
  517. return -EIO;
  518. }
  519. buf[i].addr = addr;
  520. buf[i].data = val;
  521. if (verbose)
  522. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  523. netxen_nic_driver_name,
  524. (u32)netxen_decode_crb_addr(addr), val);
  525. }
  526. for (i = 0; i < n; i++) {
  527. off = netxen_decode_crb_addr(buf[i].addr);
  528. if (off == NETXEN_ADDR_ERROR) {
  529. printk(KERN_ERR"CRB init value out of range %x\n",
  530. buf[i].addr);
  531. continue;
  532. }
  533. off += NETXEN_PCI_CRBSPACE;
  534. /* skipping cold reboot MAGIC */
  535. if (off == NETXEN_CAM_RAM(0x1fc))
  536. continue;
  537. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  538. /* do not reset PCI */
  539. if (off == (ROMUSB_GLB + 0xbc))
  540. continue;
  541. if (off == (ROMUSB_GLB + 0xa8))
  542. continue;
  543. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  544. continue;
  545. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  546. continue;
  547. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  548. continue;
  549. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  550. buf[i].data = 0x1020;
  551. /* skip the function enable register */
  552. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  553. continue;
  554. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  555. continue;
  556. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  557. continue;
  558. }
  559. if (off == NETXEN_ADDR_ERROR) {
  560. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  561. netxen_nic_driver_name, buf[i].addr);
  562. continue;
  563. }
  564. init_delay = 1;
  565. /* After writing this register, HW needs time for CRB */
  566. /* to quiet down (else crb_window returns 0xffffffff) */
  567. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  568. init_delay = 1000;
  569. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  570. /* hold xdma in reset also */
  571. buf[i].data = NETXEN_NIC_XDMA_RESET;
  572. buf[i].data = 0x8000ff;
  573. }
  574. }
  575. NXWR32(adapter, off, buf[i].data);
  576. msleep(init_delay);
  577. }
  578. kfree(buf);
  579. /* disable_peg_cache_all */
  580. /* unreset_net_cache */
  581. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  582. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  583. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  584. }
  585. /* p2dn replyCount */
  586. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  587. /* disable_peg_cache 0 */
  588. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  589. /* disable_peg_cache 1 */
  590. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  591. /* peg_clr_all */
  592. /* peg_clr 0 */
  593. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  594. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  595. /* peg_clr 1 */
  596. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  597. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  598. /* peg_clr 2 */
  599. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  600. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  601. /* peg_clr 3 */
  602. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  603. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  604. return 0;
  605. }
  606. int
  607. netxen_load_firmware(struct netxen_adapter *adapter)
  608. {
  609. u64 *ptr64;
  610. u32 i, flashaddr, size;
  611. const struct firmware *fw = adapter->fw;
  612. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  613. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  614. if (fw) {
  615. __le64 data;
  616. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  617. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  618. flashaddr = NETXEN_BOOTLD_START;
  619. for (i = 0; i < size; i++) {
  620. data = cpu_to_le64(ptr64[i]);
  621. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  622. flashaddr += 8;
  623. }
  624. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  625. size = (__force u32)cpu_to_le32(size) / 8;
  626. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  627. flashaddr = NETXEN_IMAGE_START;
  628. for (i = 0; i < size; i++) {
  629. data = cpu_to_le64(ptr64[i]);
  630. if (adapter->pci_mem_write(adapter,
  631. flashaddr, &data, 8))
  632. return -EIO;
  633. flashaddr += 8;
  634. }
  635. } else {
  636. u32 data;
  637. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  638. flashaddr = NETXEN_BOOTLD_START;
  639. for (i = 0; i < size; i++) {
  640. if (netxen_rom_fast_read(adapter,
  641. flashaddr, (int *)&data) != 0)
  642. return -EIO;
  643. if (adapter->pci_mem_write(adapter,
  644. flashaddr, &data, 4))
  645. return -EIO;
  646. flashaddr += 4;
  647. }
  648. }
  649. msleep(1);
  650. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  651. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  652. else {
  653. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  654. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  655. }
  656. return 0;
  657. }
  658. static int
  659. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  660. {
  661. __le32 val;
  662. u32 major, minor, build, ver, min_ver, bios;
  663. struct pci_dev *pdev = adapter->pdev;
  664. const struct firmware *fw = adapter->fw;
  665. if (fw->size < NX_FW_MIN_SIZE)
  666. return -EINVAL;
  667. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  668. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  669. return -EINVAL;
  670. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  671. major = (__force u32)val & 0xff;
  672. minor = ((__force u32)val >> 8) & 0xff;
  673. build = (__force u32)val >> 16;
  674. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  675. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  676. else
  677. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  678. ver = NETXEN_VERSION_CODE(major, minor, build);
  679. if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  680. dev_err(&pdev->dev,
  681. "%s: firmware version %d.%d.%d unsupported\n",
  682. fwname, major, minor, build);
  683. return -EINVAL;
  684. }
  685. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  686. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  687. if ((__force u32)val != bios) {
  688. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  689. fwname);
  690. return -EINVAL;
  691. }
  692. /* check if flashed firmware is newer */
  693. if (netxen_rom_fast_read(adapter,
  694. NX_FW_VERSION_OFFSET, (int *)&val))
  695. return -EIO;
  696. major = (__force u32)val & 0xff;
  697. minor = ((__force u32)val >> 8) & 0xff;
  698. build = (__force u32)val >> 16;
  699. if (NETXEN_VERSION_CODE(major, minor, build) > ver)
  700. return -EINVAL;
  701. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  702. return 0;
  703. }
  704. static char *fw_name[] = { "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin" };
  705. void netxen_request_firmware(struct netxen_adapter *adapter)
  706. {
  707. u32 capability, flashed_ver;
  708. int fw_type;
  709. struct pci_dev *pdev = adapter->pdev;
  710. int rc = 0;
  711. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  712. fw_type = NX_P2_MN_ROMIMAGE;
  713. goto request_fw;
  714. } else {
  715. fw_type = NX_P3_CT_ROMIMAGE;
  716. goto request_fw;
  717. }
  718. request_mn:
  719. capability = 0;
  720. netxen_rom_fast_read(adapter,
  721. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  722. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  723. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  724. if (capability & NX_PEG_TUNE_MN_PRESENT) {
  725. fw_type = NX_P3_MN_ROMIMAGE;
  726. goto request_fw;
  727. }
  728. }
  729. request_fw:
  730. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  731. if (rc != 0) {
  732. if (fw_type == NX_P3_CT_ROMIMAGE) {
  733. msleep(1);
  734. goto request_mn;
  735. }
  736. adapter->fw = NULL;
  737. goto done;
  738. }
  739. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  740. if (rc != 0) {
  741. release_firmware(adapter->fw);
  742. if (fw_type == NX_P3_CT_ROMIMAGE) {
  743. msleep(1);
  744. goto request_mn;
  745. }
  746. adapter->fw = NULL;
  747. goto done;
  748. }
  749. done:
  750. if (adapter->fw)
  751. dev_info(&pdev->dev, "loading firmware from file %s\n",
  752. fw_name[fw_type]);
  753. else
  754. dev_info(&pdev->dev, "loading firmware from flash\n");
  755. }
  756. void
  757. netxen_release_firmware(struct netxen_adapter *adapter)
  758. {
  759. if (adapter->fw)
  760. release_firmware(adapter->fw);
  761. }
  762. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  763. {
  764. uint64_t addr;
  765. uint32_t hi;
  766. uint32_t lo;
  767. adapter->dummy_dma.addr =
  768. pci_alloc_consistent(adapter->pdev,
  769. NETXEN_HOST_DUMMY_DMA_SIZE,
  770. &adapter->dummy_dma.phys_addr);
  771. if (adapter->dummy_dma.addr == NULL) {
  772. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  773. __func__);
  774. return -ENOMEM;
  775. }
  776. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  777. hi = (addr >> 32) & 0xffffffff;
  778. lo = addr & 0xffffffff;
  779. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  780. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  781. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  782. uint32_t temp = 0;
  783. NXWR32(adapter, CRB_HOST_DUMMY_BUF, temp);
  784. }
  785. return 0;
  786. }
  787. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  788. {
  789. int i = 100;
  790. if (!adapter->dummy_dma.addr)
  791. return;
  792. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  793. do {
  794. if (dma_watchdog_shutdown_request(adapter) == 1)
  795. break;
  796. msleep(50);
  797. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  798. break;
  799. } while (--i);
  800. }
  801. if (i) {
  802. pci_free_consistent(adapter->pdev,
  803. NETXEN_HOST_DUMMY_DMA_SIZE,
  804. adapter->dummy_dma.addr,
  805. adapter->dummy_dma.phys_addr);
  806. adapter->dummy_dma.addr = NULL;
  807. } else {
  808. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  809. adapter->netdev->name);
  810. }
  811. }
  812. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  813. {
  814. u32 val = 0;
  815. int retries = 60;
  816. if (!pegtune_val) {
  817. do {
  818. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  819. if (val == PHAN_INITIALIZE_COMPLETE ||
  820. val == PHAN_INITIALIZE_ACK)
  821. return 0;
  822. msleep(500);
  823. } while (--retries);
  824. if (!retries) {
  825. pegtune_val = NXRD32(adapter,
  826. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  827. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  828. "pegtune_val=%x\n", pegtune_val);
  829. return -1;
  830. }
  831. }
  832. return 0;
  833. }
  834. static int
  835. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  836. {
  837. u32 val = 0;
  838. int retries = 2000;
  839. do {
  840. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  841. if (val == PHAN_PEG_RCV_INITIALIZED)
  842. return 0;
  843. msleep(10);
  844. } while (--retries);
  845. if (!retries) {
  846. printk(KERN_ERR "Receive Peg initialization not "
  847. "complete, state: 0x%x.\n", val);
  848. return -EIO;
  849. }
  850. return 0;
  851. }
  852. int netxen_init_firmware(struct netxen_adapter *adapter)
  853. {
  854. int err;
  855. err = netxen_receive_peg_ready(adapter);
  856. if (err)
  857. return err;
  858. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  859. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  860. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  861. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  862. if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222)) {
  863. adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
  864. }
  865. return err;
  866. }
  867. static void
  868. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  869. {
  870. u32 cable_OUI;
  871. u16 cable_len;
  872. u16 link_speed;
  873. u8 link_status, module, duplex, autoneg;
  874. struct net_device *netdev = adapter->netdev;
  875. adapter->has_link_events = 1;
  876. cable_OUI = msg->body[1] & 0xffffffff;
  877. cable_len = (msg->body[1] >> 32) & 0xffff;
  878. link_speed = (msg->body[1] >> 48) & 0xffff;
  879. link_status = msg->body[2] & 0xff;
  880. duplex = (msg->body[2] >> 16) & 0xff;
  881. autoneg = (msg->body[2] >> 24) & 0xff;
  882. module = (msg->body[2] >> 8) & 0xff;
  883. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  884. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  885. netdev->name, cable_OUI, cable_len);
  886. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  887. printk(KERN_INFO "%s: unsupported cable length %d\n",
  888. netdev->name, cable_len);
  889. }
  890. netxen_advert_link_change(adapter, link_status);
  891. /* update link parameters */
  892. if (duplex == LINKEVENT_FULL_DUPLEX)
  893. adapter->link_duplex = DUPLEX_FULL;
  894. else
  895. adapter->link_duplex = DUPLEX_HALF;
  896. adapter->module_type = module;
  897. adapter->link_autoneg = autoneg;
  898. adapter->link_speed = link_speed;
  899. }
  900. static void
  901. netxen_handle_fw_message(int desc_cnt, int index,
  902. struct nx_host_sds_ring *sds_ring)
  903. {
  904. nx_fw_msg_t msg;
  905. struct status_desc *desc;
  906. int i = 0, opcode;
  907. while (desc_cnt > 0 && i < 8) {
  908. desc = &sds_ring->desc_head[index];
  909. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  910. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  911. index = get_next_index(index, sds_ring->num_desc);
  912. desc_cnt--;
  913. }
  914. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  915. switch (opcode) {
  916. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  917. netxen_handle_linkevent(sds_ring->adapter, &msg);
  918. break;
  919. default:
  920. break;
  921. }
  922. }
  923. static int
  924. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  925. struct nx_host_rds_ring *rds_ring,
  926. struct netxen_rx_buffer *buffer)
  927. {
  928. struct sk_buff *skb;
  929. dma_addr_t dma;
  930. struct pci_dev *pdev = adapter->pdev;
  931. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  932. if (!buffer->skb)
  933. return 1;
  934. skb = buffer->skb;
  935. if (!adapter->ahw.cut_through)
  936. skb_reserve(skb, 2);
  937. dma = pci_map_single(pdev, skb->data,
  938. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  939. if (pci_dma_mapping_error(pdev, dma)) {
  940. dev_kfree_skb_any(skb);
  941. buffer->skb = NULL;
  942. return 1;
  943. }
  944. buffer->skb = skb;
  945. buffer->dma = dma;
  946. buffer->state = NETXEN_BUFFER_BUSY;
  947. return 0;
  948. }
  949. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  950. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  951. {
  952. struct netxen_rx_buffer *buffer;
  953. struct sk_buff *skb;
  954. buffer = &rds_ring->rx_buf_arr[index];
  955. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  956. PCI_DMA_FROMDEVICE);
  957. skb = buffer->skb;
  958. if (!skb)
  959. goto no_skb;
  960. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  961. adapter->stats.csummed++;
  962. skb->ip_summed = CHECKSUM_UNNECESSARY;
  963. } else
  964. skb->ip_summed = CHECKSUM_NONE;
  965. skb->dev = adapter->netdev;
  966. buffer->skb = NULL;
  967. no_skb:
  968. buffer->state = NETXEN_BUFFER_FREE;
  969. return skb;
  970. }
  971. static struct netxen_rx_buffer *
  972. netxen_process_rcv(struct netxen_adapter *adapter,
  973. int ring, int index, int length, int cksum, int pkt_offset,
  974. struct nx_host_sds_ring *sds_ring)
  975. {
  976. struct net_device *netdev = adapter->netdev;
  977. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  978. struct netxen_rx_buffer *buffer;
  979. struct sk_buff *skb;
  980. struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
  981. if (unlikely(index > rds_ring->num_desc))
  982. return NULL;
  983. buffer = &rds_ring->rx_buf_arr[index];
  984. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  985. if (!skb)
  986. return buffer;
  987. if (length > rds_ring->skb_size)
  988. skb_put(skb, rds_ring->skb_size);
  989. else
  990. skb_put(skb, length);
  991. if (pkt_offset)
  992. skb_pull(skb, pkt_offset);
  993. skb->protocol = eth_type_trans(skb, netdev);
  994. napi_gro_receive(&sds_ring->napi, skb);
  995. adapter->stats.no_rcv++;
  996. adapter->stats.rxbytes += length;
  997. return buffer;
  998. }
  999. #define netxen_merge_rx_buffers(list, head) \
  1000. do { list_splice_tail_init(list, head); } while (0);
  1001. int
  1002. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1003. {
  1004. struct netxen_adapter *adapter = sds_ring->adapter;
  1005. struct list_head *cur;
  1006. struct status_desc *desc;
  1007. struct netxen_rx_buffer *rxbuf;
  1008. u32 consumer = sds_ring->consumer;
  1009. int count = 0;
  1010. u64 sts_data;
  1011. int opcode, ring, index, length, cksum, pkt_offset, desc_cnt;
  1012. while (count < max) {
  1013. desc = &sds_ring->desc_head[consumer];
  1014. sts_data = le64_to_cpu(desc->status_desc_data[0]);
  1015. if (!(sts_data & STATUS_OWNER_HOST))
  1016. break;
  1017. desc_cnt = netxen_get_sts_desc_cnt(sts_data);
  1018. ring = netxen_get_sts_type(sts_data);
  1019. if (ring > RCV_RING_JUMBO)
  1020. goto skip;
  1021. opcode = netxen_get_sts_opcode(sts_data);
  1022. switch (opcode) {
  1023. case NETXEN_NIC_RXPKT_DESC:
  1024. case NETXEN_OLD_RXPKT_DESC:
  1025. break;
  1026. case NETXEN_NIC_RESPONSE_DESC:
  1027. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1028. default:
  1029. goto skip;
  1030. }
  1031. WARN_ON(desc_cnt > 1);
  1032. index = netxen_get_sts_refhandle(sts_data);
  1033. length = netxen_get_sts_totallength(sts_data);
  1034. cksum = netxen_get_sts_status(sts_data);
  1035. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  1036. rxbuf = netxen_process_rcv(adapter, ring, index,
  1037. length, cksum, pkt_offset, sds_ring);
  1038. if (rxbuf)
  1039. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1040. skip:
  1041. for (; desc_cnt > 0; desc_cnt--) {
  1042. desc = &sds_ring->desc_head[consumer];
  1043. desc->status_desc_data[0] =
  1044. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1045. consumer = get_next_index(consumer, sds_ring->num_desc);
  1046. }
  1047. count++;
  1048. }
  1049. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1050. struct nx_host_rds_ring *rds_ring =
  1051. &adapter->recv_ctx.rds_rings[ring];
  1052. if (!list_empty(&sds_ring->free_list[ring])) {
  1053. list_for_each(cur, &sds_ring->free_list[ring]) {
  1054. rxbuf = list_entry(cur,
  1055. struct netxen_rx_buffer, list);
  1056. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1057. }
  1058. spin_lock(&rds_ring->lock);
  1059. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1060. &rds_ring->free_list);
  1061. spin_unlock(&rds_ring->lock);
  1062. }
  1063. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1064. }
  1065. if (count) {
  1066. sds_ring->consumer = consumer;
  1067. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1068. }
  1069. return count;
  1070. }
  1071. /* Process Command status ring */
  1072. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1073. {
  1074. u32 sw_consumer, hw_consumer;
  1075. int count = 0, i;
  1076. struct netxen_cmd_buffer *buffer;
  1077. struct pci_dev *pdev = adapter->pdev;
  1078. struct net_device *netdev = adapter->netdev;
  1079. struct netxen_skb_frag *frag;
  1080. int done = 0;
  1081. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1082. if (!spin_trylock(&adapter->tx_clean_lock))
  1083. return 1;
  1084. sw_consumer = tx_ring->sw_consumer;
  1085. barrier(); /* hw_consumer can change underneath */
  1086. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1087. while (sw_consumer != hw_consumer) {
  1088. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1089. if (buffer->skb) {
  1090. frag = &buffer->frag_array[0];
  1091. pci_unmap_single(pdev, frag->dma, frag->length,
  1092. PCI_DMA_TODEVICE);
  1093. frag->dma = 0ULL;
  1094. for (i = 1; i < buffer->frag_count; i++) {
  1095. frag++; /* Get the next frag */
  1096. pci_unmap_page(pdev, frag->dma, frag->length,
  1097. PCI_DMA_TODEVICE);
  1098. frag->dma = 0ULL;
  1099. }
  1100. adapter->stats.xmitfinished++;
  1101. dev_kfree_skb_any(buffer->skb);
  1102. buffer->skb = NULL;
  1103. }
  1104. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1105. if (++count >= MAX_STATUS_HANDLE)
  1106. break;
  1107. }
  1108. tx_ring->sw_consumer = sw_consumer;
  1109. if (count && netif_running(netdev)) {
  1110. smp_mb();
  1111. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1112. netif_tx_lock(netdev);
  1113. netif_wake_queue(netdev);
  1114. smp_mb();
  1115. netif_tx_unlock(netdev);
  1116. }
  1117. }
  1118. /*
  1119. * If everything is freed up to consumer then check if the ring is full
  1120. * If the ring is full then check if more needs to be freed and
  1121. * schedule the call back again.
  1122. *
  1123. * This happens when there are 2 CPUs. One could be freeing and the
  1124. * other filling it. If the ring is full when we get out of here and
  1125. * the card has already interrupted the host then the host can miss the
  1126. * interrupt.
  1127. *
  1128. * There is still a possible race condition and the host could miss an
  1129. * interrupt. The card has to take care of this.
  1130. */
  1131. barrier(); /* hw_consumer can change underneath */
  1132. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1133. done = (sw_consumer == hw_consumer);
  1134. spin_unlock(&adapter->tx_clean_lock);
  1135. return (done);
  1136. }
  1137. void
  1138. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1139. struct nx_host_rds_ring *rds_ring)
  1140. {
  1141. struct rcv_desc *pdesc;
  1142. struct netxen_rx_buffer *buffer;
  1143. int producer, count = 0;
  1144. netxen_ctx_msg msg = 0;
  1145. struct list_head *head;
  1146. producer = rds_ring->producer;
  1147. spin_lock(&rds_ring->lock);
  1148. head = &rds_ring->free_list;
  1149. while (!list_empty(head)) {
  1150. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1151. if (!buffer->skb) {
  1152. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1153. break;
  1154. }
  1155. count++;
  1156. list_del(&buffer->list);
  1157. /* make a rcv descriptor */
  1158. pdesc = &rds_ring->desc_head[producer];
  1159. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1160. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1161. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1162. producer = get_next_index(producer, rds_ring->num_desc);
  1163. }
  1164. spin_unlock(&rds_ring->lock);
  1165. if (count) {
  1166. rds_ring->producer = producer;
  1167. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1168. (producer-1) & (rds_ring->num_desc-1));
  1169. if (adapter->fw_major < 4) {
  1170. /*
  1171. * Write a doorbell msg to tell phanmon of change in
  1172. * receive ring producer
  1173. * Only for firmware version < 4.0.0
  1174. */
  1175. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1176. netxen_set_msg_privid(msg);
  1177. netxen_set_msg_count(msg,
  1178. ((producer - 1) &
  1179. (rds_ring->num_desc - 1)));
  1180. netxen_set_msg_ctxid(msg, adapter->portnum);
  1181. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1182. writel(msg,
  1183. DB_NORMALIZE(adapter,
  1184. NETXEN_RCV_PRODUCER_OFFSET));
  1185. }
  1186. }
  1187. }
  1188. static void
  1189. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1190. struct nx_host_rds_ring *rds_ring)
  1191. {
  1192. struct rcv_desc *pdesc;
  1193. struct netxen_rx_buffer *buffer;
  1194. int producer, count = 0;
  1195. struct list_head *head;
  1196. producer = rds_ring->producer;
  1197. if (!spin_trylock(&rds_ring->lock))
  1198. return;
  1199. head = &rds_ring->free_list;
  1200. while (!list_empty(head)) {
  1201. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1202. if (!buffer->skb) {
  1203. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1204. break;
  1205. }
  1206. count++;
  1207. list_del(&buffer->list);
  1208. /* make a rcv descriptor */
  1209. pdesc = &rds_ring->desc_head[producer];
  1210. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1211. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1212. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1213. producer = get_next_index(producer, rds_ring->num_desc);
  1214. }
  1215. if (count) {
  1216. rds_ring->producer = producer;
  1217. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1218. (producer - 1) & (rds_ring->num_desc - 1));
  1219. }
  1220. spin_unlock(&rds_ring->lock);
  1221. }
  1222. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1223. {
  1224. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1225. return;
  1226. }