timer-gp.c 9.2 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/timer-gp.c
  3. *
  4. * OMAP2 GP timer support.
  5. *
  6. * Copyright (C) 2009 Nokia Corporation
  7. *
  8. * Update to use new clocksource/clockevent layers
  9. * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10. * Copyright (C) 2007 MontaVista Software, Inc.
  11. *
  12. * Original driver:
  13. * Copyright (C) 2005 Nokia Corporation
  14. * Author: Paul Mundt <paul.mundt@nokia.com>
  15. * Juha Yrjölä <juha.yrjola@nokia.com>
  16. * OMAP Dual-mode timer framework support by Timo Teras
  17. *
  18. * Some parts based off of TI's 24xx code:
  19. *
  20. * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21. *
  22. * Roughly modelled after the OMAP1 MPU timer code.
  23. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24. *
  25. * This file is subject to the terms and conditions of the GNU General Public
  26. * License. See the file "COPYING" in the main directory of this archive
  27. * for more details.
  28. */
  29. #include <linux/init.h>
  30. #include <linux/time.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/err.h>
  33. #include <linux/clk.h>
  34. #include <linux/delay.h>
  35. #include <linux/irq.h>
  36. #include <linux/clocksource.h>
  37. #include <linux/clockchips.h>
  38. #include <asm/mach/time.h>
  39. #include <plat/dmtimer.h>
  40. #include <asm/localtimer.h>
  41. #include <asm/sched_clock.h>
  42. #include <plat/common.h>
  43. #include <plat/omap_hwmod.h>
  44. #include "timer-gp.h"
  45. /* Parent clocks, eventually these will come from the clock framework */
  46. #define OMAP2_MPU_SOURCE "sys_ck"
  47. #define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
  48. #define OMAP4_MPU_SOURCE "sys_clkin_ck"
  49. #define OMAP2_32K_SOURCE "func_32k_ck"
  50. #define OMAP3_32K_SOURCE "omap_32k_fck"
  51. #define OMAP4_32K_SOURCE "sys_32k_ck"
  52. #ifdef CONFIG_OMAP_32K_TIMER
  53. #define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
  54. #define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
  55. #define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
  56. #define OMAP3_SECURE_TIMER 12
  57. #else
  58. #define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
  59. #define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
  60. #define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
  61. #define OMAP3_SECURE_TIMER 1
  62. #endif
  63. /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  64. #define MAX_GPTIMER_ID 12
  65. u32 sys_timer_reserved;
  66. /* Clockevent code */
  67. static struct omap_dm_timer clkev;
  68. static struct clock_event_device clockevent_gpt;
  69. static u8 __initdata gptimer_id = 1;
  70. static u8 __initdata inited;
  71. static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  72. {
  73. struct clock_event_device *evt = &clockevent_gpt;
  74. __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
  75. evt->event_handler(evt);
  76. return IRQ_HANDLED;
  77. }
  78. static struct irqaction omap2_gp_timer_irq = {
  79. .name = "gp timer",
  80. .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  81. .handler = omap2_gp_timer_interrupt,
  82. };
  83. static int omap2_gp_timer_set_next_event(unsigned long cycles,
  84. struct clock_event_device *evt)
  85. {
  86. __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
  87. 0xffffffff - cycles, 1);
  88. return 0;
  89. }
  90. static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
  91. struct clock_event_device *evt)
  92. {
  93. u32 period;
  94. __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
  95. switch (mode) {
  96. case CLOCK_EVT_MODE_PERIODIC:
  97. period = clkev.rate / HZ;
  98. period -= 1;
  99. /* Looks like we need to first set the load value separately */
  100. __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
  101. 0xffffffff - period, 1);
  102. __omap_dm_timer_load_start(clkev.io_base,
  103. OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
  104. 0xffffffff - period, 1);
  105. break;
  106. case CLOCK_EVT_MODE_ONESHOT:
  107. break;
  108. case CLOCK_EVT_MODE_UNUSED:
  109. case CLOCK_EVT_MODE_SHUTDOWN:
  110. case CLOCK_EVT_MODE_RESUME:
  111. break;
  112. }
  113. }
  114. static struct clock_event_device clockevent_gpt = {
  115. .name = "gp timer",
  116. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  117. .shift = 32,
  118. .set_next_event = omap2_gp_timer_set_next_event,
  119. .set_mode = omap2_gp_timer_set_mode,
  120. };
  121. /**
  122. * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
  123. * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
  124. *
  125. * Define the GPTIMER that the system should use for the tick timer.
  126. * Meant to be called from board-*.c files in the event that GPTIMER1, the
  127. * default, is unsuitable. Returns -EINVAL on error or 0 on success.
  128. */
  129. int __init omap2_gp_clockevent_set_gptimer(u8 id)
  130. {
  131. if (id < 1 || id > MAX_GPTIMER_ID)
  132. return -EINVAL;
  133. BUG_ON(inited);
  134. gptimer_id = id;
  135. return 0;
  136. }
  137. static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
  138. int gptimer_id,
  139. const char *fck_source)
  140. {
  141. char name[10]; /* 10 = sizeof("gptXX_Xck0") */
  142. struct omap_hwmod *oh;
  143. size_t size;
  144. int res = 0;
  145. sprintf(name, "timer%d", gptimer_id);
  146. omap_hwmod_setup_one(name);
  147. oh = omap_hwmod_lookup(name);
  148. if (!oh)
  149. return -ENODEV;
  150. timer->irq = oh->mpu_irqs[0].irq;
  151. timer->phys_base = oh->slaves[0]->addr->pa_start;
  152. size = oh->slaves[0]->addr->pa_end - timer->phys_base;
  153. /* Static mapping, never released */
  154. timer->io_base = ioremap(timer->phys_base, size);
  155. if (!timer->io_base)
  156. return -ENXIO;
  157. /* After the dmtimer is using hwmod these clocks won't be needed */
  158. sprintf(name, "gpt%d_fck", gptimer_id);
  159. timer->fclk = clk_get(NULL, name);
  160. if (IS_ERR(timer->fclk))
  161. return -ENODEV;
  162. sprintf(name, "gpt%d_ick", gptimer_id);
  163. timer->iclk = clk_get(NULL, name);
  164. if (IS_ERR(timer->iclk)) {
  165. clk_put(timer->fclk);
  166. return -ENODEV;
  167. }
  168. omap_hwmod_enable(oh);
  169. sys_timer_reserved |= (1 << (gptimer_id - 1));
  170. if (gptimer_id != 12) {
  171. struct clk *src;
  172. src = clk_get(NULL, fck_source);
  173. if (IS_ERR(src)) {
  174. res = -EINVAL;
  175. } else {
  176. res = __omap_dm_timer_set_source(timer->fclk, src);
  177. if (IS_ERR_VALUE(res))
  178. pr_warning("%s: timer%i cannot set source\n",
  179. __func__, gptimer_id);
  180. clk_put(src);
  181. }
  182. }
  183. __omap_dm_timer_reset(timer->io_base, 1, 1);
  184. timer->posted = 1;
  185. timer->rate = clk_get_rate(timer->fclk);
  186. timer->reserved = 1;
  187. return res;
  188. }
  189. static void __init omap2_gp_clockevent_init(int gptimer_id,
  190. const char *fck_source)
  191. {
  192. int res;
  193. inited = 1;
  194. res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
  195. BUG_ON(res);
  196. omap2_gp_timer_irq.dev_id = (void *)&clkev;
  197. setup_irq(clkev.irq, &omap2_gp_timer_irq);
  198. __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
  199. clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
  200. clockevent_gpt.shift);
  201. clockevent_gpt.max_delta_ns =
  202. clockevent_delta2ns(0xffffffff, &clockevent_gpt);
  203. clockevent_gpt.min_delta_ns =
  204. clockevent_delta2ns(3, &clockevent_gpt);
  205. /* Timer internal resynch latency. */
  206. clockevent_gpt.cpumask = cpumask_of(0);
  207. clockevents_register_device(&clockevent_gpt);
  208. pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
  209. gptimer_id, clkev.rate);
  210. }
  211. /* Clocksource code */
  212. #ifdef CONFIG_OMAP_32K_TIMER
  213. /*
  214. * When 32k-timer is enabled, don't use GPTimer for clocksource
  215. * instead, just leave default clocksource which uses the 32k
  216. * sync counter. See clocksource setup in plat-omap/counter_32k.c
  217. */
  218. static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
  219. {
  220. omap_init_clocksource_32k();
  221. }
  222. #else
  223. static struct omap_dm_timer clksrc;
  224. /*
  225. * clocksource
  226. */
  227. static DEFINE_CLOCK_DATA(cd);
  228. static cycle_t clocksource_read_cycles(struct clocksource *cs)
  229. {
  230. return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
  231. }
  232. static struct clocksource clocksource_gpt = {
  233. .name = "gp timer",
  234. .rating = 300,
  235. .read = clocksource_read_cycles,
  236. .mask = CLOCKSOURCE_MASK(32),
  237. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  238. };
  239. static void notrace dmtimer_update_sched_clock(void)
  240. {
  241. u32 cyc;
  242. cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
  243. update_sched_clock(&cd, cyc, (u32)~0);
  244. }
  245. unsigned long long notrace sched_clock(void)
  246. {
  247. u32 cyc = 0;
  248. if (clksrc.reserved)
  249. cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
  250. return cyc_to_sched_clock(&cd, cyc, (u32)~0);
  251. }
  252. /* Setup free-running counter for clocksource */
  253. static void __init omap2_gp_clocksource_init(int gptimer_id,
  254. const char *fck_source)
  255. {
  256. int res;
  257. res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
  258. BUG_ON(res);
  259. pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
  260. gptimer_id, clksrc.rate);
  261. __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
  262. init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
  263. if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
  264. pr_err("Could not register clocksource %s\n",
  265. clocksource_gpt.name);
  266. }
  267. #endif
  268. #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
  269. clksrc_nr, clksrc_src) \
  270. static void __init omap##name##_timer_init(void) \
  271. { \
  272. omap2_gp_clockevent_init((clkev_nr), clkev_src); \
  273. omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
  274. }
  275. #define OMAP_SYS_TIMER(name) \
  276. struct sys_timer omap##name##_timer = { \
  277. .init = omap##name##_timer_init, \
  278. };
  279. #ifdef CONFIG_ARCH_OMAP2
  280. OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
  281. OMAP_SYS_TIMER(2)
  282. #endif
  283. #ifdef CONFIG_ARCH_OMAP3
  284. OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
  285. OMAP_SYS_TIMER(3)
  286. OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
  287. 2, OMAP3_MPU_SOURCE)
  288. OMAP_SYS_TIMER(3_secure)
  289. #endif
  290. #ifdef CONFIG_ARCH_OMAP4
  291. static void __init omap4_timer_init(void)
  292. {
  293. #ifdef CONFIG_LOCAL_TIMERS
  294. twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
  295. BUG_ON(!twd_base);
  296. #endif
  297. omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
  298. omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
  299. }
  300. OMAP_SYS_TIMER(4)
  301. #endif