board-3430sdp.c 20 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/board-3430sdp.c
  3. *
  4. * Copyright (C) 2007 Texas Instruments
  5. *
  6. * Modified from mach-omap2/board-generic.c
  7. *
  8. * Initial code: Syed Mohammed Khasim
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/input.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/i2c/twl.h>
  22. #include <linux/regulator/machine.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/mmc/host.h>
  26. #include <mach/hardware.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include <plat/mcspi.h>
  31. #include <plat/board.h>
  32. #include <plat/usb.h>
  33. #include <plat/common.h>
  34. #include <plat/dma.h>
  35. #include <plat/gpmc.h>
  36. #include <video/omapdss.h>
  37. #include <video/omap-panel-generic-dpi.h>
  38. #include <plat/gpmc-smc91x.h>
  39. #include "board-flash.h"
  40. #include "mux.h"
  41. #include "sdram-qimonda-hyb18m512160af-6.h"
  42. #include "hsmmc.h"
  43. #include "pm.h"
  44. #include "control.h"
  45. #include "common-board-devices.h"
  46. #define CONFIG_DISABLE_HFCLK 1
  47. #define SDP3430_TS_GPIO_IRQ_SDPV1 3
  48. #define SDP3430_TS_GPIO_IRQ_SDPV2 2
  49. #define ENABLE_VAUX3_DEDICATED 0x03
  50. #define ENABLE_VAUX3_DEV_GRP 0x20
  51. #define TWL4030_MSECURE_GPIO 22
  52. static uint32_t board_keymap[] = {
  53. KEY(0, 0, KEY_LEFT),
  54. KEY(0, 1, KEY_RIGHT),
  55. KEY(0, 2, KEY_A),
  56. KEY(0, 3, KEY_B),
  57. KEY(0, 4, KEY_C),
  58. KEY(1, 0, KEY_DOWN),
  59. KEY(1, 1, KEY_UP),
  60. KEY(1, 2, KEY_E),
  61. KEY(1, 3, KEY_F),
  62. KEY(1, 4, KEY_G),
  63. KEY(2, 0, KEY_ENTER),
  64. KEY(2, 1, KEY_I),
  65. KEY(2, 2, KEY_J),
  66. KEY(2, 3, KEY_K),
  67. KEY(2, 4, KEY_3),
  68. KEY(3, 0, KEY_M),
  69. KEY(3, 1, KEY_N),
  70. KEY(3, 2, KEY_O),
  71. KEY(3, 3, KEY_P),
  72. KEY(3, 4, KEY_Q),
  73. KEY(4, 0, KEY_R),
  74. KEY(4, 1, KEY_4),
  75. KEY(4, 2, KEY_T),
  76. KEY(4, 3, KEY_U),
  77. KEY(4, 4, KEY_D),
  78. KEY(5, 0, KEY_V),
  79. KEY(5, 1, KEY_W),
  80. KEY(5, 2, KEY_L),
  81. KEY(5, 3, KEY_S),
  82. KEY(5, 4, KEY_H),
  83. 0
  84. };
  85. static struct matrix_keymap_data board_map_data = {
  86. .keymap = board_keymap,
  87. .keymap_size = ARRAY_SIZE(board_keymap),
  88. };
  89. static struct twl4030_keypad_data sdp3430_kp_data = {
  90. .keymap_data = &board_map_data,
  91. .rows = 5,
  92. .cols = 6,
  93. .rep = 1,
  94. };
  95. #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
  96. #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
  97. static struct gpio sdp3430_dss_gpios[] __initdata = {
  98. {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
  99. {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
  100. };
  101. static int lcd_enabled;
  102. static int dvi_enabled;
  103. static void __init sdp3430_display_init(void)
  104. {
  105. int r;
  106. r = gpio_request_array(sdp3430_dss_gpios,
  107. ARRAY_SIZE(sdp3430_dss_gpios));
  108. if (r)
  109. printk(KERN_ERR "failed to get LCD control GPIOs\n");
  110. }
  111. static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
  112. {
  113. if (dvi_enabled) {
  114. printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
  115. return -EINVAL;
  116. }
  117. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
  118. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
  119. lcd_enabled = 1;
  120. return 0;
  121. }
  122. static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
  123. {
  124. lcd_enabled = 0;
  125. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
  126. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
  127. }
  128. static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
  129. {
  130. if (lcd_enabled) {
  131. printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
  132. return -EINVAL;
  133. }
  134. dvi_enabled = 1;
  135. return 0;
  136. }
  137. static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev)
  138. {
  139. dvi_enabled = 0;
  140. }
  141. static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
  142. {
  143. return 0;
  144. }
  145. static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
  146. {
  147. }
  148. static struct omap_dss_device sdp3430_lcd_device = {
  149. .name = "lcd",
  150. .driver_name = "sharp_ls_panel",
  151. .type = OMAP_DISPLAY_TYPE_DPI,
  152. .phy.dpi.data_lines = 16,
  153. .platform_enable = sdp3430_panel_enable_lcd,
  154. .platform_disable = sdp3430_panel_disable_lcd,
  155. };
  156. static struct panel_generic_dpi_data dvi_panel = {
  157. .name = "generic",
  158. .platform_enable = sdp3430_panel_enable_dvi,
  159. .platform_disable = sdp3430_panel_disable_dvi,
  160. };
  161. static struct omap_dss_device sdp3430_dvi_device = {
  162. .name = "dvi",
  163. .type = OMAP_DISPLAY_TYPE_DPI,
  164. .driver_name = "generic_dpi_panel",
  165. .data = &dvi_panel,
  166. .phy.dpi.data_lines = 24,
  167. };
  168. static struct omap_dss_device sdp3430_tv_device = {
  169. .name = "tv",
  170. .driver_name = "venc",
  171. .type = OMAP_DISPLAY_TYPE_VENC,
  172. .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
  173. .platform_enable = sdp3430_panel_enable_tv,
  174. .platform_disable = sdp3430_panel_disable_tv,
  175. };
  176. static struct omap_dss_device *sdp3430_dss_devices[] = {
  177. &sdp3430_lcd_device,
  178. &sdp3430_dvi_device,
  179. &sdp3430_tv_device,
  180. };
  181. static struct omap_dss_board_info sdp3430_dss_data = {
  182. .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
  183. .devices = sdp3430_dss_devices,
  184. .default_device = &sdp3430_lcd_device,
  185. };
  186. static struct omap_board_config_kernel sdp3430_config[] __initdata = {
  187. };
  188. static void __init omap_3430sdp_init_early(void)
  189. {
  190. omap2_init_common_infrastructure();
  191. omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
  192. }
  193. static int sdp3430_batt_table[] = {
  194. /* 0 C*/
  195. 30800, 29500, 28300, 27100,
  196. 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
  197. 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
  198. 11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
  199. 8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
  200. 5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
  201. 4040, 3910, 3790, 3670, 3550
  202. };
  203. static struct twl4030_bci_platform_data sdp3430_bci_data = {
  204. .battery_tmp_tbl = sdp3430_batt_table,
  205. .tblsize = ARRAY_SIZE(sdp3430_batt_table),
  206. };
  207. static struct omap2_hsmmc_info mmc[] = {
  208. {
  209. .mmc = 1,
  210. /* 8 bits (default) requires S6.3 == ON,
  211. * so the SIM card isn't used; else 4 bits.
  212. */
  213. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  214. .gpio_wp = 4,
  215. },
  216. {
  217. .mmc = 2,
  218. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  219. .gpio_wp = 7,
  220. },
  221. {} /* Terminator */
  222. };
  223. static int sdp3430_twl_gpio_setup(struct device *dev,
  224. unsigned gpio, unsigned ngpio)
  225. {
  226. /* gpio + 0 is "mmc0_cd" (input/IRQ),
  227. * gpio + 1 is "mmc1_cd" (input/IRQ)
  228. */
  229. mmc[0].gpio_cd = gpio + 0;
  230. mmc[1].gpio_cd = gpio + 1;
  231. omap2_hsmmc_init(mmc);
  232. /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
  233. gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
  234. /* gpio + 15 is "sub_lcd_nRST" (output) */
  235. gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
  236. return 0;
  237. }
  238. static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
  239. .gpio_base = OMAP_MAX_GPIO_LINES,
  240. .irq_base = TWL4030_GPIO_IRQ_BASE,
  241. .irq_end = TWL4030_GPIO_IRQ_END,
  242. .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
  243. | BIT(16) | BIT(17),
  244. .setup = sdp3430_twl_gpio_setup,
  245. };
  246. static struct twl4030_usb_data sdp3430_usb_data = {
  247. .usb_mode = T2_USB_MODE_ULPI,
  248. };
  249. static struct twl4030_madc_platform_data sdp3430_madc_data = {
  250. .irq_line = 1,
  251. };
  252. /* regulator consumer mappings */
  253. /* ads7846 on SPI */
  254. static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
  255. REGULATOR_SUPPLY("vcc", "spi1.0"),
  256. };
  257. static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
  258. REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
  259. };
  260. /* VPLL2 for digital video outputs */
  261. static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
  262. REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
  263. REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
  264. };
  265. static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
  266. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
  267. };
  268. static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
  269. REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
  270. };
  271. static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
  272. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
  273. };
  274. /*
  275. * Apply all the fixed voltages since most versions of U-Boot
  276. * don't bother with that initialization.
  277. */
  278. /* VAUX1 for mainboard (irda and sub-lcd) */
  279. static struct regulator_init_data sdp3430_vaux1 = {
  280. .constraints = {
  281. .min_uV = 2800000,
  282. .max_uV = 2800000,
  283. .apply_uV = true,
  284. .valid_modes_mask = REGULATOR_MODE_NORMAL
  285. | REGULATOR_MODE_STANDBY,
  286. .valid_ops_mask = REGULATOR_CHANGE_MODE
  287. | REGULATOR_CHANGE_STATUS,
  288. },
  289. };
  290. /* VAUX2 for camera module */
  291. static struct regulator_init_data sdp3430_vaux2 = {
  292. .constraints = {
  293. .min_uV = 2800000,
  294. .max_uV = 2800000,
  295. .apply_uV = true,
  296. .valid_modes_mask = REGULATOR_MODE_NORMAL
  297. | REGULATOR_MODE_STANDBY,
  298. .valid_ops_mask = REGULATOR_CHANGE_MODE
  299. | REGULATOR_CHANGE_STATUS,
  300. },
  301. };
  302. /* VAUX3 for LCD board */
  303. static struct regulator_init_data sdp3430_vaux3 = {
  304. .constraints = {
  305. .min_uV = 2800000,
  306. .max_uV = 2800000,
  307. .apply_uV = true,
  308. .valid_modes_mask = REGULATOR_MODE_NORMAL
  309. | REGULATOR_MODE_STANDBY,
  310. .valid_ops_mask = REGULATOR_CHANGE_MODE
  311. | REGULATOR_CHANGE_STATUS,
  312. },
  313. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
  314. .consumer_supplies = sdp3430_vaux3_supplies,
  315. };
  316. /* VAUX4 for OMAP VDD_CSI2 (camera) */
  317. static struct regulator_init_data sdp3430_vaux4 = {
  318. .constraints = {
  319. .min_uV = 1800000,
  320. .max_uV = 1800000,
  321. .apply_uV = true,
  322. .valid_modes_mask = REGULATOR_MODE_NORMAL
  323. | REGULATOR_MODE_STANDBY,
  324. .valid_ops_mask = REGULATOR_CHANGE_MODE
  325. | REGULATOR_CHANGE_STATUS,
  326. },
  327. };
  328. /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
  329. static struct regulator_init_data sdp3430_vmmc1 = {
  330. .constraints = {
  331. .min_uV = 1850000,
  332. .max_uV = 3150000,
  333. .valid_modes_mask = REGULATOR_MODE_NORMAL
  334. | REGULATOR_MODE_STANDBY,
  335. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  336. | REGULATOR_CHANGE_MODE
  337. | REGULATOR_CHANGE_STATUS,
  338. },
  339. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
  340. .consumer_supplies = sdp3430_vmmc1_supplies,
  341. };
  342. /* VMMC2 for MMC2 card */
  343. static struct regulator_init_data sdp3430_vmmc2 = {
  344. .constraints = {
  345. .min_uV = 1850000,
  346. .max_uV = 1850000,
  347. .apply_uV = true,
  348. .valid_modes_mask = REGULATOR_MODE_NORMAL
  349. | REGULATOR_MODE_STANDBY,
  350. .valid_ops_mask = REGULATOR_CHANGE_MODE
  351. | REGULATOR_CHANGE_STATUS,
  352. },
  353. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
  354. .consumer_supplies = sdp3430_vmmc2_supplies,
  355. };
  356. /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
  357. static struct regulator_init_data sdp3430_vsim = {
  358. .constraints = {
  359. .min_uV = 1800000,
  360. .max_uV = 3000000,
  361. .valid_modes_mask = REGULATOR_MODE_NORMAL
  362. | REGULATOR_MODE_STANDBY,
  363. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  364. | REGULATOR_CHANGE_MODE
  365. | REGULATOR_CHANGE_STATUS,
  366. },
  367. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
  368. .consumer_supplies = sdp3430_vsim_supplies,
  369. };
  370. /* VDAC for DSS driving S-Video */
  371. static struct regulator_init_data sdp3430_vdac = {
  372. .constraints = {
  373. .min_uV = 1800000,
  374. .max_uV = 1800000,
  375. .apply_uV = true,
  376. .valid_modes_mask = REGULATOR_MODE_NORMAL
  377. | REGULATOR_MODE_STANDBY,
  378. .valid_ops_mask = REGULATOR_CHANGE_MODE
  379. | REGULATOR_CHANGE_STATUS,
  380. },
  381. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
  382. .consumer_supplies = sdp3430_vdda_dac_supplies,
  383. };
  384. static struct regulator_init_data sdp3430_vpll2 = {
  385. .constraints = {
  386. .name = "VDVI",
  387. .min_uV = 1800000,
  388. .max_uV = 1800000,
  389. .apply_uV = true,
  390. .valid_modes_mask = REGULATOR_MODE_NORMAL
  391. | REGULATOR_MODE_STANDBY,
  392. .valid_ops_mask = REGULATOR_CHANGE_MODE
  393. | REGULATOR_CHANGE_STATUS,
  394. },
  395. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
  396. .consumer_supplies = sdp3430_vpll2_supplies,
  397. };
  398. static struct twl4030_codec_audio_data sdp3430_audio;
  399. static struct twl4030_codec_data sdp3430_codec = {
  400. .audio_mclk = 26000000,
  401. .audio = &sdp3430_audio,
  402. };
  403. static struct twl4030_platform_data sdp3430_twldata = {
  404. .irq_base = TWL4030_IRQ_BASE,
  405. .irq_end = TWL4030_IRQ_END,
  406. /* platform_data for children goes here */
  407. .bci = &sdp3430_bci_data,
  408. .gpio = &sdp3430_gpio_data,
  409. .madc = &sdp3430_madc_data,
  410. .keypad = &sdp3430_kp_data,
  411. .usb = &sdp3430_usb_data,
  412. .codec = &sdp3430_codec,
  413. .vaux1 = &sdp3430_vaux1,
  414. .vaux2 = &sdp3430_vaux2,
  415. .vaux3 = &sdp3430_vaux3,
  416. .vaux4 = &sdp3430_vaux4,
  417. .vmmc1 = &sdp3430_vmmc1,
  418. .vmmc2 = &sdp3430_vmmc2,
  419. .vsim = &sdp3430_vsim,
  420. .vdac = &sdp3430_vdac,
  421. .vpll2 = &sdp3430_vpll2,
  422. };
  423. static int __init omap3430_i2c_init(void)
  424. {
  425. /* i2c1 for PMIC only */
  426. omap3_pmic_init("twl4030", &sdp3430_twldata);
  427. /* i2c2 on camera connector (for sensor control) and optional isp1301 */
  428. omap_register_i2c_bus(2, 400, NULL, 0);
  429. /* i2c3 on display connector (for DVI, tfp410) */
  430. omap_register_i2c_bus(3, 400, NULL, 0);
  431. return 0;
  432. }
  433. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  434. static struct omap_smc91x_platform_data board_smc91x_data = {
  435. .cs = 3,
  436. .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
  437. IORESOURCE_IRQ_LOWLEVEL,
  438. };
  439. static void __init board_smc91x_init(void)
  440. {
  441. if (omap_rev() > OMAP3430_REV_ES1_0)
  442. board_smc91x_data.gpio_irq = 6;
  443. else
  444. board_smc91x_data.gpio_irq = 29;
  445. gpmc_smc91x_init(&board_smc91x_data);
  446. }
  447. #else
  448. static inline void board_smc91x_init(void)
  449. {
  450. }
  451. #endif
  452. static void enable_board_wakeup_source(void)
  453. {
  454. /* T2 interrupt line (keypad) */
  455. omap_mux_init_signal("sys_nirq",
  456. OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
  457. }
  458. static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
  459. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  460. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  461. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  462. .phy_reset = true,
  463. .reset_gpio_port[0] = 57,
  464. .reset_gpio_port[1] = 61,
  465. .reset_gpio_port[2] = -EINVAL
  466. };
  467. #ifdef CONFIG_OMAP_MUX
  468. static struct omap_board_mux board_mux[] __initdata = {
  469. { .reg_offset = OMAP_MUX_TERMINATOR },
  470. };
  471. static struct omap_device_pad serial1_pads[] __initdata = {
  472. /*
  473. * Note that off output enable is an active low
  474. * signal. So setting this means pin is a
  475. * input enabled in off mode
  476. */
  477. OMAP_MUX_STATIC("uart1_cts.uart1_cts",
  478. OMAP_PIN_INPUT |
  479. OMAP_PIN_OFF_INPUT_PULLDOWN |
  480. OMAP_OFFOUT_EN |
  481. OMAP_MUX_MODE0),
  482. OMAP_MUX_STATIC("uart1_rts.uart1_rts",
  483. OMAP_PIN_OUTPUT |
  484. OMAP_OFF_EN |
  485. OMAP_MUX_MODE0),
  486. OMAP_MUX_STATIC("uart1_rx.uart1_rx",
  487. OMAP_PIN_INPUT |
  488. OMAP_PIN_OFF_INPUT_PULLDOWN |
  489. OMAP_OFFOUT_EN |
  490. OMAP_MUX_MODE0),
  491. OMAP_MUX_STATIC("uart1_tx.uart1_tx",
  492. OMAP_PIN_OUTPUT |
  493. OMAP_OFF_EN |
  494. OMAP_MUX_MODE0),
  495. };
  496. static struct omap_device_pad serial2_pads[] __initdata = {
  497. OMAP_MUX_STATIC("uart2_cts.uart2_cts",
  498. OMAP_PIN_INPUT_PULLUP |
  499. OMAP_PIN_OFF_INPUT_PULLDOWN |
  500. OMAP_OFFOUT_EN |
  501. OMAP_MUX_MODE0),
  502. OMAP_MUX_STATIC("uart2_rts.uart2_rts",
  503. OMAP_PIN_OUTPUT |
  504. OMAP_OFF_EN |
  505. OMAP_MUX_MODE0),
  506. OMAP_MUX_STATIC("uart2_rx.uart2_rx",
  507. OMAP_PIN_INPUT |
  508. OMAP_PIN_OFF_INPUT_PULLDOWN |
  509. OMAP_OFFOUT_EN |
  510. OMAP_MUX_MODE0),
  511. OMAP_MUX_STATIC("uart2_tx.uart2_tx",
  512. OMAP_PIN_OUTPUT |
  513. OMAP_OFF_EN |
  514. OMAP_MUX_MODE0),
  515. };
  516. static struct omap_device_pad serial3_pads[] __initdata = {
  517. OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
  518. OMAP_PIN_INPUT_PULLDOWN |
  519. OMAP_PIN_OFF_INPUT_PULLDOWN |
  520. OMAP_OFFOUT_EN |
  521. OMAP_MUX_MODE0),
  522. OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
  523. OMAP_PIN_OUTPUT |
  524. OMAP_OFF_EN |
  525. OMAP_MUX_MODE0),
  526. OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
  527. OMAP_PIN_INPUT |
  528. OMAP_PIN_OFF_INPUT_PULLDOWN |
  529. OMAP_OFFOUT_EN |
  530. OMAP_MUX_MODE0),
  531. OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
  532. OMAP_PIN_OUTPUT |
  533. OMAP_OFF_EN |
  534. OMAP_MUX_MODE0),
  535. };
  536. static struct omap_board_data serial1_data __initdata = {
  537. .id = 0,
  538. .pads = serial1_pads,
  539. .pads_cnt = ARRAY_SIZE(serial1_pads),
  540. };
  541. static struct omap_board_data serial2_data __initdata = {
  542. .id = 1,
  543. .pads = serial2_pads,
  544. .pads_cnt = ARRAY_SIZE(serial2_pads),
  545. };
  546. static struct omap_board_data serial3_data __initdata = {
  547. .id = 2,
  548. .pads = serial3_pads,
  549. .pads_cnt = ARRAY_SIZE(serial3_pads),
  550. };
  551. static inline void board_serial_init(void)
  552. {
  553. omap_serial_init_port(&serial1_data);
  554. omap_serial_init_port(&serial2_data);
  555. omap_serial_init_port(&serial3_data);
  556. }
  557. #else
  558. #define board_mux NULL
  559. static inline void board_serial_init(void)
  560. {
  561. omap_serial_init();
  562. }
  563. #endif
  564. /*
  565. * SDP3430 V2 Board CS organization
  566. * Different from SDP3430 V1. Now 4 switches used to specify CS
  567. *
  568. * See also the Switch S8 settings in the comments.
  569. */
  570. static char chip_sel_3430[][GPMC_CS_NUM] = {
  571. {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  572. {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  573. {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  574. };
  575. static struct mtd_partition sdp_nor_partitions[] = {
  576. /* bootloader (U-Boot, etc) in first sector */
  577. {
  578. .name = "Bootloader-NOR",
  579. .offset = 0,
  580. .size = SZ_256K,
  581. .mask_flags = MTD_WRITEABLE, /* force read-only */
  582. },
  583. /* bootloader params in the next sector */
  584. {
  585. .name = "Params-NOR",
  586. .offset = MTDPART_OFS_APPEND,
  587. .size = SZ_256K,
  588. .mask_flags = 0,
  589. },
  590. /* kernel */
  591. {
  592. .name = "Kernel-NOR",
  593. .offset = MTDPART_OFS_APPEND,
  594. .size = SZ_2M,
  595. .mask_flags = 0
  596. },
  597. /* file system */
  598. {
  599. .name = "Filesystem-NOR",
  600. .offset = MTDPART_OFS_APPEND,
  601. .size = MTDPART_SIZ_FULL,
  602. .mask_flags = 0
  603. }
  604. };
  605. static struct mtd_partition sdp_onenand_partitions[] = {
  606. {
  607. .name = "X-Loader-OneNAND",
  608. .offset = 0,
  609. .size = 4 * (64 * 2048),
  610. .mask_flags = MTD_WRITEABLE /* force read-only */
  611. },
  612. {
  613. .name = "U-Boot-OneNAND",
  614. .offset = MTDPART_OFS_APPEND,
  615. .size = 2 * (64 * 2048),
  616. .mask_flags = MTD_WRITEABLE /* force read-only */
  617. },
  618. {
  619. .name = "U-Boot Environment-OneNAND",
  620. .offset = MTDPART_OFS_APPEND,
  621. .size = 1 * (64 * 2048),
  622. },
  623. {
  624. .name = "Kernel-OneNAND",
  625. .offset = MTDPART_OFS_APPEND,
  626. .size = 16 * (64 * 2048),
  627. },
  628. {
  629. .name = "File System-OneNAND",
  630. .offset = MTDPART_OFS_APPEND,
  631. .size = MTDPART_SIZ_FULL,
  632. },
  633. };
  634. static struct mtd_partition sdp_nand_partitions[] = {
  635. /* All the partition sizes are listed in terms of NAND block size */
  636. {
  637. .name = "X-Loader-NAND",
  638. .offset = 0,
  639. .size = 4 * (64 * 2048),
  640. .mask_flags = MTD_WRITEABLE, /* force read-only */
  641. },
  642. {
  643. .name = "U-Boot-NAND",
  644. .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
  645. .size = 10 * (64 * 2048),
  646. .mask_flags = MTD_WRITEABLE, /* force read-only */
  647. },
  648. {
  649. .name = "Boot Env-NAND",
  650. .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
  651. .size = 6 * (64 * 2048),
  652. },
  653. {
  654. .name = "Kernel-NAND",
  655. .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
  656. .size = 40 * (64 * 2048),
  657. },
  658. {
  659. .name = "File System - NAND",
  660. .size = MTDPART_SIZ_FULL,
  661. .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
  662. },
  663. };
  664. static struct flash_partitions sdp_flash_partitions[] = {
  665. {
  666. .parts = sdp_nor_partitions,
  667. .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
  668. },
  669. {
  670. .parts = sdp_onenand_partitions,
  671. .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
  672. },
  673. {
  674. .parts = sdp_nand_partitions,
  675. .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
  676. },
  677. };
  678. static void __init omap_3430sdp_init(void)
  679. {
  680. int gpio_pendown;
  681. omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
  682. omap_board_config = sdp3430_config;
  683. omap_board_config_size = ARRAY_SIZE(sdp3430_config);
  684. omap3430_i2c_init();
  685. omap_display_init(&sdp3430_dss_data);
  686. if (omap_rev() > OMAP3430_REV_ES1_0)
  687. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
  688. else
  689. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
  690. omap_ads7846_init(1, gpio_pendown, 310, NULL);
  691. board_serial_init();
  692. usb_musb_init(NULL);
  693. board_smc91x_init();
  694. board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
  695. sdp3430_display_init();
  696. enable_board_wakeup_source();
  697. usbhs_init(&usbhs_bdata);
  698. }
  699. MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
  700. /* Maintainer: Syed Khasim - Texas Instruments Inc */
  701. .boot_params = 0x80000100,
  702. .reserve = omap_reserve,
  703. .map_io = omap3_map_io,
  704. .init_early = omap_3430sdp_init_early,
  705. .init_irq = omap3_init_irq,
  706. .init_machine = omap_3430sdp_init,
  707. .timer = &omap3_timer,
  708. MACHINE_END