rtc-s3c.c 17 KB

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  1. /* drivers/rtc/rtc-s3c.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * Copyright (c) 2004,2006 Simtec Electronics
  7. * Ben Dooks, <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * S3C2410/S3C2440/S3C24XX Internal RTC Driver
  15. */
  16. #include <linux/module.h>
  17. #include <linux/fs.h>
  18. #include <linux/string.h>
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/rtc.h>
  23. #include <linux/bcd.h>
  24. #include <linux/clk.h>
  25. #include <linux/log2.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <linux/uaccess.h>
  29. #include <linux/io.h>
  30. #include <mach/hardware.h>
  31. #include <asm/irq.h>
  32. #include <plat/regs-rtc.h>
  33. enum s3c_cpu_type {
  34. TYPE_S3C2410,
  35. TYPE_S3C2416,
  36. TYPE_S3C2443,
  37. TYPE_S3C64XX,
  38. };
  39. struct s3c_rtc_drv_data {
  40. int cpu_type;
  41. };
  42. /* I have yet to find an S3C implementation with more than one
  43. * of these rtc blocks in */
  44. static struct clk *rtc_clk;
  45. static void __iomem *s3c_rtc_base;
  46. static int s3c_rtc_alarmno = NO_IRQ;
  47. static int s3c_rtc_tickno = NO_IRQ;
  48. static bool wake_en;
  49. static enum s3c_cpu_type s3c_rtc_cpu_type;
  50. static DEFINE_SPINLOCK(s3c_rtc_pie_lock);
  51. static void s3c_rtc_alarm_clk_enable(bool enable)
  52. {
  53. static DEFINE_SPINLOCK(s3c_rtc_alarm_clk_lock);
  54. static bool alarm_clk_enabled;
  55. unsigned long irq_flags;
  56. spin_lock_irqsave(&s3c_rtc_alarm_clk_lock, irq_flags);
  57. if (enable) {
  58. if (!alarm_clk_enabled) {
  59. clk_enable(rtc_clk);
  60. alarm_clk_enabled = true;
  61. }
  62. } else {
  63. if (alarm_clk_enabled) {
  64. clk_disable(rtc_clk);
  65. alarm_clk_enabled = false;
  66. }
  67. }
  68. spin_unlock_irqrestore(&s3c_rtc_alarm_clk_lock, irq_flags);
  69. }
  70. /* IRQ Handlers */
  71. static irqreturn_t s3c_rtc_alarmirq(int irq, void *id)
  72. {
  73. struct rtc_device *rdev = id;
  74. clk_enable(rtc_clk);
  75. rtc_update_irq(rdev, 1, RTC_AF | RTC_IRQF);
  76. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  77. writeb(S3C2410_INTP_ALM, s3c_rtc_base + S3C2410_INTP);
  78. clk_disable(rtc_clk);
  79. s3c_rtc_alarm_clk_enable(false);
  80. return IRQ_HANDLED;
  81. }
  82. static irqreturn_t s3c_rtc_tickirq(int irq, void *id)
  83. {
  84. struct rtc_device *rdev = id;
  85. clk_enable(rtc_clk);
  86. rtc_update_irq(rdev, 1, RTC_PF | RTC_IRQF);
  87. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  88. writeb(S3C2410_INTP_TIC, s3c_rtc_base + S3C2410_INTP);
  89. clk_disable(rtc_clk);
  90. return IRQ_HANDLED;
  91. }
  92. /* Update control registers */
  93. static int s3c_rtc_setaie(struct device *dev, unsigned int enabled)
  94. {
  95. unsigned int tmp;
  96. dev_dbg(dev, "%s: aie=%d\n", __func__, enabled);
  97. clk_enable(rtc_clk);
  98. tmp = readb(s3c_rtc_base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN;
  99. if (enabled)
  100. tmp |= S3C2410_RTCALM_ALMEN;
  101. writeb(tmp, s3c_rtc_base + S3C2410_RTCALM);
  102. clk_disable(rtc_clk);
  103. s3c_rtc_alarm_clk_enable(enabled);
  104. return 0;
  105. }
  106. static int s3c_rtc_setfreq(struct device *dev, int freq)
  107. {
  108. struct platform_device *pdev = to_platform_device(dev);
  109. struct rtc_device *rtc_dev = platform_get_drvdata(pdev);
  110. unsigned int tmp = 0;
  111. int val;
  112. if (!is_power_of_2(freq))
  113. return -EINVAL;
  114. clk_enable(rtc_clk);
  115. spin_lock_irq(&s3c_rtc_pie_lock);
  116. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  117. tmp = readb(s3c_rtc_base + S3C2410_TICNT);
  118. tmp &= S3C2410_TICNT_ENABLE;
  119. }
  120. val = (rtc_dev->max_user_freq / freq) - 1;
  121. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  122. tmp |= S3C2443_TICNT_PART(val);
  123. writel(S3C2443_TICNT1_PART(val), s3c_rtc_base + S3C2443_TICNT1);
  124. if (s3c_rtc_cpu_type == TYPE_S3C2416)
  125. writel(S3C2416_TICNT2_PART(val), s3c_rtc_base + S3C2416_TICNT2);
  126. } else {
  127. tmp |= val;
  128. }
  129. writel(tmp, s3c_rtc_base + S3C2410_TICNT);
  130. spin_unlock_irq(&s3c_rtc_pie_lock);
  131. clk_disable(rtc_clk);
  132. return 0;
  133. }
  134. /* Time read/write */
  135. static int s3c_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  136. {
  137. unsigned int have_retried = 0;
  138. void __iomem *base = s3c_rtc_base;
  139. clk_enable(rtc_clk);
  140. retry_get_time:
  141. rtc_tm->tm_min = readb(base + S3C2410_RTCMIN);
  142. rtc_tm->tm_hour = readb(base + S3C2410_RTCHOUR);
  143. rtc_tm->tm_mday = readb(base + S3C2410_RTCDATE);
  144. rtc_tm->tm_mon = readb(base + S3C2410_RTCMON);
  145. rtc_tm->tm_year = readb(base + S3C2410_RTCYEAR);
  146. rtc_tm->tm_sec = readb(base + S3C2410_RTCSEC);
  147. /* the only way to work out whether the system was mid-update
  148. * when we read it is to check the second counter, and if it
  149. * is zero, then we re-try the entire read
  150. */
  151. if (rtc_tm->tm_sec == 0 && !have_retried) {
  152. have_retried = 1;
  153. goto retry_get_time;
  154. }
  155. rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
  156. rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
  157. rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
  158. rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
  159. rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon);
  160. rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
  161. rtc_tm->tm_year += 100;
  162. dev_dbg(dev, "read time %04d.%02d.%02d %02d:%02d:%02d\n",
  163. 1900 + rtc_tm->tm_year, rtc_tm->tm_mon, rtc_tm->tm_mday,
  164. rtc_tm->tm_hour, rtc_tm->tm_min, rtc_tm->tm_sec);
  165. rtc_tm->tm_mon -= 1;
  166. clk_disable(rtc_clk);
  167. return rtc_valid_tm(rtc_tm);
  168. }
  169. static int s3c_rtc_settime(struct device *dev, struct rtc_time *tm)
  170. {
  171. void __iomem *base = s3c_rtc_base;
  172. int year = tm->tm_year - 100;
  173. dev_dbg(dev, "set time %04d.%02d.%02d %02d:%02d:%02d\n",
  174. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  175. tm->tm_hour, tm->tm_min, tm->tm_sec);
  176. /* we get around y2k by simply not supporting it */
  177. if (year < 0 || year >= 100) {
  178. dev_err(dev, "rtc only supports 100 years\n");
  179. return -EINVAL;
  180. }
  181. clk_enable(rtc_clk);
  182. writeb(bin2bcd(tm->tm_sec), base + S3C2410_RTCSEC);
  183. writeb(bin2bcd(tm->tm_min), base + S3C2410_RTCMIN);
  184. writeb(bin2bcd(tm->tm_hour), base + S3C2410_RTCHOUR);
  185. writeb(bin2bcd(tm->tm_mday), base + S3C2410_RTCDATE);
  186. writeb(bin2bcd(tm->tm_mon + 1), base + S3C2410_RTCMON);
  187. writeb(bin2bcd(year), base + S3C2410_RTCYEAR);
  188. clk_disable(rtc_clk);
  189. return 0;
  190. }
  191. static int s3c_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
  192. {
  193. struct rtc_time *alm_tm = &alrm->time;
  194. void __iomem *base = s3c_rtc_base;
  195. unsigned int alm_en;
  196. clk_enable(rtc_clk);
  197. alm_tm->tm_sec = readb(base + S3C2410_ALMSEC);
  198. alm_tm->tm_min = readb(base + S3C2410_ALMMIN);
  199. alm_tm->tm_hour = readb(base + S3C2410_ALMHOUR);
  200. alm_tm->tm_mon = readb(base + S3C2410_ALMMON);
  201. alm_tm->tm_mday = readb(base + S3C2410_ALMDATE);
  202. alm_tm->tm_year = readb(base + S3C2410_ALMYEAR);
  203. alm_en = readb(base + S3C2410_RTCALM);
  204. alrm->enabled = (alm_en & S3C2410_RTCALM_ALMEN) ? 1 : 0;
  205. dev_dbg(dev, "read alarm %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  206. alm_en,
  207. 1900 + alm_tm->tm_year, alm_tm->tm_mon, alm_tm->tm_mday,
  208. alm_tm->tm_hour, alm_tm->tm_min, alm_tm->tm_sec);
  209. /* decode the alarm enable field */
  210. if (alm_en & S3C2410_RTCALM_SECEN)
  211. alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
  212. else
  213. alm_tm->tm_sec = -1;
  214. if (alm_en & S3C2410_RTCALM_MINEN)
  215. alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
  216. else
  217. alm_tm->tm_min = -1;
  218. if (alm_en & S3C2410_RTCALM_HOUREN)
  219. alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
  220. else
  221. alm_tm->tm_hour = -1;
  222. if (alm_en & S3C2410_RTCALM_DAYEN)
  223. alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
  224. else
  225. alm_tm->tm_mday = -1;
  226. if (alm_en & S3C2410_RTCALM_MONEN) {
  227. alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon);
  228. alm_tm->tm_mon -= 1;
  229. } else {
  230. alm_tm->tm_mon = -1;
  231. }
  232. if (alm_en & S3C2410_RTCALM_YEAREN)
  233. alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
  234. else
  235. alm_tm->tm_year = -1;
  236. clk_disable(rtc_clk);
  237. return 0;
  238. }
  239. static int s3c_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  240. {
  241. struct rtc_time *tm = &alrm->time;
  242. void __iomem *base = s3c_rtc_base;
  243. unsigned int alrm_en;
  244. clk_enable(rtc_clk);
  245. dev_dbg(dev, "s3c_rtc_setalarm: %d, %04d.%02d.%02d %02d:%02d:%02d\n",
  246. alrm->enabled,
  247. 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
  248. tm->tm_hour, tm->tm_min, tm->tm_sec);
  249. alrm_en = readb(base + S3C2410_RTCALM) & S3C2410_RTCALM_ALMEN;
  250. writeb(0x00, base + S3C2410_RTCALM);
  251. if (tm->tm_sec < 60 && tm->tm_sec >= 0) {
  252. alrm_en |= S3C2410_RTCALM_SECEN;
  253. writeb(bin2bcd(tm->tm_sec), base + S3C2410_ALMSEC);
  254. }
  255. if (tm->tm_min < 60 && tm->tm_min >= 0) {
  256. alrm_en |= S3C2410_RTCALM_MINEN;
  257. writeb(bin2bcd(tm->tm_min), base + S3C2410_ALMMIN);
  258. }
  259. if (tm->tm_hour < 24 && tm->tm_hour >= 0) {
  260. alrm_en |= S3C2410_RTCALM_HOUREN;
  261. writeb(bin2bcd(tm->tm_hour), base + S3C2410_ALMHOUR);
  262. }
  263. dev_dbg(dev, "setting S3C2410_RTCALM to %08x\n", alrm_en);
  264. writeb(alrm_en, base + S3C2410_RTCALM);
  265. s3c_rtc_setaie(dev, alrm->enabled);
  266. clk_disable(rtc_clk);
  267. return 0;
  268. }
  269. static int s3c_rtc_proc(struct device *dev, struct seq_file *seq)
  270. {
  271. unsigned int ticnt;
  272. clk_enable(rtc_clk);
  273. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  274. ticnt = readw(s3c_rtc_base + S3C2410_RTCCON);
  275. ticnt &= S3C64XX_RTCCON_TICEN;
  276. } else {
  277. ticnt = readb(s3c_rtc_base + S3C2410_TICNT);
  278. ticnt &= S3C2410_TICNT_ENABLE;
  279. }
  280. seq_printf(seq, "periodic_IRQ\t: %s\n", ticnt ? "yes" : "no");
  281. clk_disable(rtc_clk);
  282. return 0;
  283. }
  284. static const struct rtc_class_ops s3c_rtcops = {
  285. .read_time = s3c_rtc_gettime,
  286. .set_time = s3c_rtc_settime,
  287. .read_alarm = s3c_rtc_getalarm,
  288. .set_alarm = s3c_rtc_setalarm,
  289. .proc = s3c_rtc_proc,
  290. .alarm_irq_enable = s3c_rtc_setaie,
  291. };
  292. static void s3c_rtc_enable(struct platform_device *pdev, int en)
  293. {
  294. void __iomem *base = s3c_rtc_base;
  295. unsigned int tmp;
  296. if (s3c_rtc_base == NULL)
  297. return;
  298. clk_enable(rtc_clk);
  299. if (!en) {
  300. tmp = readw(base + S3C2410_RTCCON);
  301. if (s3c_rtc_cpu_type == TYPE_S3C64XX)
  302. tmp &= ~S3C64XX_RTCCON_TICEN;
  303. tmp &= ~S3C2410_RTCCON_RTCEN;
  304. writew(tmp, base + S3C2410_RTCCON);
  305. if (s3c_rtc_cpu_type != TYPE_S3C64XX) {
  306. tmp = readb(base + S3C2410_TICNT);
  307. tmp &= ~S3C2410_TICNT_ENABLE;
  308. writeb(tmp, base + S3C2410_TICNT);
  309. }
  310. } else {
  311. /* re-enable the device, and check it is ok */
  312. if ((readw(base+S3C2410_RTCCON) & S3C2410_RTCCON_RTCEN) == 0) {
  313. dev_info(&pdev->dev, "rtc disabled, re-enabling\n");
  314. tmp = readw(base + S3C2410_RTCCON);
  315. writew(tmp | S3C2410_RTCCON_RTCEN,
  316. base + S3C2410_RTCCON);
  317. }
  318. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CNTSEL)) {
  319. dev_info(&pdev->dev, "removing RTCCON_CNTSEL\n");
  320. tmp = readw(base + S3C2410_RTCCON);
  321. writew(tmp & ~S3C2410_RTCCON_CNTSEL,
  322. base + S3C2410_RTCCON);
  323. }
  324. if ((readw(base + S3C2410_RTCCON) & S3C2410_RTCCON_CLKRST)) {
  325. dev_info(&pdev->dev, "removing RTCCON_CLKRST\n");
  326. tmp = readw(base + S3C2410_RTCCON);
  327. writew(tmp & ~S3C2410_RTCCON_CLKRST,
  328. base + S3C2410_RTCCON);
  329. }
  330. }
  331. clk_disable(rtc_clk);
  332. }
  333. static int s3c_rtc_remove(struct platform_device *dev)
  334. {
  335. struct rtc_device *rtc = platform_get_drvdata(dev);
  336. platform_set_drvdata(dev, NULL);
  337. rtc_device_unregister(rtc);
  338. s3c_rtc_setaie(&dev->dev, 0);
  339. rtc_clk = NULL;
  340. return 0;
  341. }
  342. static const struct of_device_id s3c_rtc_dt_match[];
  343. static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
  344. {
  345. #ifdef CONFIG_OF
  346. struct s3c_rtc_drv_data *data;
  347. if (pdev->dev.of_node) {
  348. const struct of_device_id *match;
  349. match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
  350. data = (struct s3c_rtc_drv_data *) match->data;
  351. return data->cpu_type;
  352. }
  353. #endif
  354. return platform_get_device_id(pdev)->driver_data;
  355. }
  356. static int s3c_rtc_probe(struct platform_device *pdev)
  357. {
  358. struct rtc_device *rtc;
  359. struct rtc_time rtc_tm;
  360. struct resource *res;
  361. int ret;
  362. int tmp;
  363. dev_dbg(&pdev->dev, "%s: probe=%p\n", __func__, pdev);
  364. /* find the IRQs */
  365. s3c_rtc_tickno = platform_get_irq(pdev, 1);
  366. if (s3c_rtc_tickno < 0) {
  367. dev_err(&pdev->dev, "no irq for rtc tick\n");
  368. return s3c_rtc_tickno;
  369. }
  370. s3c_rtc_alarmno = platform_get_irq(pdev, 0);
  371. if (s3c_rtc_alarmno < 0) {
  372. dev_err(&pdev->dev, "no irq for alarm\n");
  373. return s3c_rtc_alarmno;
  374. }
  375. dev_dbg(&pdev->dev, "s3c2410_rtc: tick irq %d, alarm irq %d\n",
  376. s3c_rtc_tickno, s3c_rtc_alarmno);
  377. /* get the memory region */
  378. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  379. if (res == NULL) {
  380. dev_err(&pdev->dev, "failed to get memory region resource\n");
  381. return -ENOENT;
  382. }
  383. s3c_rtc_base = devm_request_and_ioremap(&pdev->dev, res);
  384. if (s3c_rtc_base == NULL) {
  385. dev_err(&pdev->dev, "failed to ioremap memory region\n");
  386. return -EINVAL;
  387. }
  388. rtc_clk = devm_clk_get(&pdev->dev, "rtc");
  389. if (IS_ERR(rtc_clk)) {
  390. dev_err(&pdev->dev, "failed to find rtc clock source\n");
  391. ret = PTR_ERR(rtc_clk);
  392. rtc_clk = NULL;
  393. return ret;
  394. }
  395. clk_enable(rtc_clk);
  396. /* check to see if everything is setup correctly */
  397. s3c_rtc_enable(pdev, 1);
  398. dev_dbg(&pdev->dev, "s3c2410_rtc: RTCCON=%02x\n",
  399. readw(s3c_rtc_base + S3C2410_RTCCON));
  400. device_init_wakeup(&pdev->dev, 1);
  401. /* register RTC and exit */
  402. rtc = rtc_device_register("s3c", &pdev->dev, &s3c_rtcops,
  403. THIS_MODULE);
  404. if (IS_ERR(rtc)) {
  405. dev_err(&pdev->dev, "cannot attach rtc\n");
  406. ret = PTR_ERR(rtc);
  407. goto err_nortc;
  408. }
  409. s3c_rtc_cpu_type = s3c_rtc_get_driver_data(pdev);
  410. /* Check RTC Time */
  411. s3c_rtc_gettime(NULL, &rtc_tm);
  412. if (rtc_valid_tm(&rtc_tm)) {
  413. rtc_tm.tm_year = 100;
  414. rtc_tm.tm_mon = 0;
  415. rtc_tm.tm_mday = 1;
  416. rtc_tm.tm_hour = 0;
  417. rtc_tm.tm_min = 0;
  418. rtc_tm.tm_sec = 0;
  419. s3c_rtc_settime(NULL, &rtc_tm);
  420. dev_warn(&pdev->dev, "warning: invalid RTC value so initializing it\n");
  421. }
  422. if (s3c_rtc_cpu_type != TYPE_S3C2410)
  423. rtc->max_user_freq = 32768;
  424. else
  425. rtc->max_user_freq = 128;
  426. if (s3c_rtc_cpu_type == TYPE_S3C2416 || s3c_rtc_cpu_type == TYPE_S3C2443) {
  427. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  428. tmp |= S3C2443_RTCCON_TICSEL;
  429. writew(tmp, s3c_rtc_base + S3C2410_RTCCON);
  430. }
  431. platform_set_drvdata(pdev, rtc);
  432. s3c_rtc_setfreq(&pdev->dev, 1);
  433. ret = devm_request_irq(&pdev->dev, s3c_rtc_alarmno, s3c_rtc_alarmirq,
  434. 0, "s3c2410-rtc alarm", rtc);
  435. if (ret) {
  436. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_alarmno, ret);
  437. goto err_alarm_irq;
  438. }
  439. ret = devm_request_irq(&pdev->dev, s3c_rtc_tickno, s3c_rtc_tickirq,
  440. 0, "s3c2410-rtc tick", rtc);
  441. if (ret) {
  442. dev_err(&pdev->dev, "IRQ%d error %d\n", s3c_rtc_tickno, ret);
  443. goto err_alarm_irq;
  444. }
  445. clk_disable(rtc_clk);
  446. return 0;
  447. err_alarm_irq:
  448. platform_set_drvdata(pdev, NULL);
  449. rtc_device_unregister(rtc);
  450. err_nortc:
  451. s3c_rtc_enable(pdev, 0);
  452. clk_disable(rtc_clk);
  453. return ret;
  454. }
  455. #ifdef CONFIG_PM
  456. /* RTC Power management control */
  457. static int ticnt_save, ticnt_en_save;
  458. static int s3c_rtc_suspend(struct platform_device *pdev, pm_message_t state)
  459. {
  460. clk_enable(rtc_clk);
  461. /* save TICNT for anyone using periodic interrupts */
  462. ticnt_save = readb(s3c_rtc_base + S3C2410_TICNT);
  463. if (s3c_rtc_cpu_type == TYPE_S3C64XX) {
  464. ticnt_en_save = readw(s3c_rtc_base + S3C2410_RTCCON);
  465. ticnt_en_save &= S3C64XX_RTCCON_TICEN;
  466. }
  467. s3c_rtc_enable(pdev, 0);
  468. if (device_may_wakeup(&pdev->dev) && !wake_en) {
  469. if (enable_irq_wake(s3c_rtc_alarmno) == 0)
  470. wake_en = true;
  471. else
  472. dev_err(&pdev->dev, "enable_irq_wake failed\n");
  473. }
  474. clk_disable(rtc_clk);
  475. return 0;
  476. }
  477. static int s3c_rtc_resume(struct platform_device *pdev)
  478. {
  479. unsigned int tmp;
  480. clk_enable(rtc_clk);
  481. s3c_rtc_enable(pdev, 1);
  482. writeb(ticnt_save, s3c_rtc_base + S3C2410_TICNT);
  483. if (s3c_rtc_cpu_type == TYPE_S3C64XX && ticnt_en_save) {
  484. tmp = readw(s3c_rtc_base + S3C2410_RTCCON);
  485. writew(tmp | ticnt_en_save, s3c_rtc_base + S3C2410_RTCCON);
  486. }
  487. if (device_may_wakeup(&pdev->dev) && wake_en) {
  488. disable_irq_wake(s3c_rtc_alarmno);
  489. wake_en = false;
  490. }
  491. clk_disable(rtc_clk);
  492. return 0;
  493. }
  494. #else
  495. #define s3c_rtc_suspend NULL
  496. #define s3c_rtc_resume NULL
  497. #endif
  498. #ifdef CONFIG_OF
  499. static struct s3c_rtc_drv_data s3c_rtc_drv_data_array[] = {
  500. [TYPE_S3C2410] = { TYPE_S3C2410 },
  501. [TYPE_S3C2416] = { TYPE_S3C2416 },
  502. [TYPE_S3C2443] = { TYPE_S3C2443 },
  503. [TYPE_S3C64XX] = { TYPE_S3C64XX },
  504. };
  505. static const struct of_device_id s3c_rtc_dt_match[] = {
  506. {
  507. .compatible = "samsung,s3c2410-rtc",
  508. .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
  509. }, {
  510. .compatible = "samsung,s3c2416-rtc",
  511. .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
  512. }, {
  513. .compatible = "samsung,s3c2443-rtc",
  514. .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
  515. }, {
  516. .compatible = "samsung,s3c6410-rtc",
  517. .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
  518. },
  519. {},
  520. };
  521. MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
  522. #endif
  523. static struct platform_device_id s3c_rtc_driver_ids[] = {
  524. {
  525. .name = "s3c2410-rtc",
  526. .driver_data = TYPE_S3C2410,
  527. }, {
  528. .name = "s3c2416-rtc",
  529. .driver_data = TYPE_S3C2416,
  530. }, {
  531. .name = "s3c2443-rtc",
  532. .driver_data = TYPE_S3C2443,
  533. }, {
  534. .name = "s3c64xx-rtc",
  535. .driver_data = TYPE_S3C64XX,
  536. },
  537. { }
  538. };
  539. MODULE_DEVICE_TABLE(platform, s3c_rtc_driver_ids);
  540. static struct platform_driver s3c_rtc_driver = {
  541. .probe = s3c_rtc_probe,
  542. .remove = s3c_rtc_remove,
  543. .suspend = s3c_rtc_suspend,
  544. .resume = s3c_rtc_resume,
  545. .id_table = s3c_rtc_driver_ids,
  546. .driver = {
  547. .name = "s3c-rtc",
  548. .owner = THIS_MODULE,
  549. .of_match_table = of_match_ptr(s3c_rtc_dt_match),
  550. },
  551. };
  552. module_platform_driver(s3c_rtc_driver);
  553. MODULE_DESCRIPTION("Samsung S3C RTC Driver");
  554. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  555. MODULE_LICENSE("GPL");
  556. MODULE_ALIAS("platform:s3c2410-rtc");