rtc-ds1307.c 25 KB

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  1. /*
  2. * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
  3. *
  4. * Copyright (C) 2005 James Chapman (ds1337 core)
  5. * Copyright (C) 2006 David Brownell
  6. * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/slab.h>
  15. #include <linux/i2c.h>
  16. #include <linux/string.h>
  17. #include <linux/rtc.h>
  18. #include <linux/bcd.h>
  19. #include <linux/rtc/ds1307.h>
  20. /*
  21. * We can't determine type by probing, but if we expect pre-Linux code
  22. * to have set the chip up as a clock (turning on the oscillator and
  23. * setting the date and time), Linux can ignore the non-clock features.
  24. * That's a natural job for a factory or repair bench.
  25. */
  26. enum ds_type {
  27. ds_1307,
  28. ds_1337,
  29. ds_1338,
  30. ds_1339,
  31. ds_1340,
  32. ds_1388,
  33. ds_3231,
  34. m41t00,
  35. mcp7941x,
  36. rx_8025,
  37. last_ds_type /* always last */
  38. /* rs5c372 too? different address... */
  39. };
  40. /* RTC registers don't differ much, except for the century flag */
  41. #define DS1307_REG_SECS 0x00 /* 00-59 */
  42. # define DS1307_BIT_CH 0x80
  43. # define DS1340_BIT_nEOSC 0x80
  44. # define MCP7941X_BIT_ST 0x80
  45. #define DS1307_REG_MIN 0x01 /* 00-59 */
  46. #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
  47. # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
  48. # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
  49. # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
  50. # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
  51. #define DS1307_REG_WDAY 0x03 /* 01-07 */
  52. # define MCP7941X_BIT_VBATEN 0x08
  53. #define DS1307_REG_MDAY 0x04 /* 01-31 */
  54. #define DS1307_REG_MONTH 0x05 /* 01-12 */
  55. # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
  56. #define DS1307_REG_YEAR 0x06 /* 00-99 */
  57. /*
  58. * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
  59. * start at 7, and they differ a LOT. Only control and status matter for
  60. * basic RTC date and time functionality; be careful using them.
  61. */
  62. #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
  63. # define DS1307_BIT_OUT 0x80
  64. # define DS1338_BIT_OSF 0x20
  65. # define DS1307_BIT_SQWE 0x10
  66. # define DS1307_BIT_RS1 0x02
  67. # define DS1307_BIT_RS0 0x01
  68. #define DS1337_REG_CONTROL 0x0e
  69. # define DS1337_BIT_nEOSC 0x80
  70. # define DS1339_BIT_BBSQI 0x20
  71. # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
  72. # define DS1337_BIT_RS2 0x10
  73. # define DS1337_BIT_RS1 0x08
  74. # define DS1337_BIT_INTCN 0x04
  75. # define DS1337_BIT_A2IE 0x02
  76. # define DS1337_BIT_A1IE 0x01
  77. #define DS1340_REG_CONTROL 0x07
  78. # define DS1340_BIT_OUT 0x80
  79. # define DS1340_BIT_FT 0x40
  80. # define DS1340_BIT_CALIB_SIGN 0x20
  81. # define DS1340_M_CALIBRATION 0x1f
  82. #define DS1340_REG_FLAG 0x09
  83. # define DS1340_BIT_OSF 0x80
  84. #define DS1337_REG_STATUS 0x0f
  85. # define DS1337_BIT_OSF 0x80
  86. # define DS1337_BIT_A2I 0x02
  87. # define DS1337_BIT_A1I 0x01
  88. #define DS1339_REG_ALARM1_SECS 0x07
  89. #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
  90. #define RX8025_REG_CTRL1 0x0e
  91. # define RX8025_BIT_2412 0x20
  92. #define RX8025_REG_CTRL2 0x0f
  93. # define RX8025_BIT_PON 0x10
  94. # define RX8025_BIT_VDET 0x40
  95. # define RX8025_BIT_XST 0x20
  96. struct ds1307 {
  97. u8 offset; /* register's offset */
  98. u8 regs[11];
  99. u16 nvram_offset;
  100. struct bin_attribute *nvram;
  101. enum ds_type type;
  102. unsigned long flags;
  103. #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
  104. #define HAS_ALARM 1 /* bit 1 == irq claimed */
  105. struct i2c_client *client;
  106. struct rtc_device *rtc;
  107. struct work_struct work;
  108. s32 (*read_block_data)(const struct i2c_client *client, u8 command,
  109. u8 length, u8 *values);
  110. s32 (*write_block_data)(const struct i2c_client *client, u8 command,
  111. u8 length, const u8 *values);
  112. };
  113. struct chip_desc {
  114. unsigned alarm:1;
  115. u16 nvram_offset;
  116. u16 nvram_size;
  117. u16 trickle_charger_reg;
  118. };
  119. static const struct chip_desc chips[last_ds_type] = {
  120. [ds_1307] = {
  121. .nvram_offset = 8,
  122. .nvram_size = 56,
  123. },
  124. [ds_1337] = {
  125. .alarm = 1,
  126. },
  127. [ds_1338] = {
  128. .nvram_offset = 8,
  129. .nvram_size = 56,
  130. },
  131. [ds_1339] = {
  132. .alarm = 1,
  133. .trickle_charger_reg = 0x10,
  134. },
  135. [ds_1340] = {
  136. .trickle_charger_reg = 0x08,
  137. },
  138. [ds_1388] = {
  139. .trickle_charger_reg = 0x0a,
  140. },
  141. [ds_3231] = {
  142. .alarm = 1,
  143. },
  144. [mcp7941x] = {
  145. /* this is battery backed SRAM */
  146. .nvram_offset = 0x20,
  147. .nvram_size = 0x40,
  148. },
  149. };
  150. static const struct i2c_device_id ds1307_id[] = {
  151. { "ds1307", ds_1307 },
  152. { "ds1337", ds_1337 },
  153. { "ds1338", ds_1338 },
  154. { "ds1339", ds_1339 },
  155. { "ds1388", ds_1388 },
  156. { "ds1340", ds_1340 },
  157. { "ds3231", ds_3231 },
  158. { "m41t00", m41t00 },
  159. { "mcp7941x", mcp7941x },
  160. { "pt7c4338", ds_1307 },
  161. { "rx8025", rx_8025 },
  162. { }
  163. };
  164. MODULE_DEVICE_TABLE(i2c, ds1307_id);
  165. /*----------------------------------------------------------------------*/
  166. #define BLOCK_DATA_MAX_TRIES 10
  167. static s32 ds1307_read_block_data_once(const struct i2c_client *client,
  168. u8 command, u8 length, u8 *values)
  169. {
  170. s32 i, data;
  171. for (i = 0; i < length; i++) {
  172. data = i2c_smbus_read_byte_data(client, command + i);
  173. if (data < 0)
  174. return data;
  175. values[i] = data;
  176. }
  177. return i;
  178. }
  179. static s32 ds1307_read_block_data(const struct i2c_client *client, u8 command,
  180. u8 length, u8 *values)
  181. {
  182. u8 oldvalues[I2C_SMBUS_BLOCK_MAX];
  183. s32 ret;
  184. int tries = 0;
  185. dev_dbg(&client->dev, "ds1307_read_block_data (length=%d)\n", length);
  186. ret = ds1307_read_block_data_once(client, command, length, values);
  187. if (ret < 0)
  188. return ret;
  189. do {
  190. if (++tries > BLOCK_DATA_MAX_TRIES) {
  191. dev_err(&client->dev,
  192. "ds1307_read_block_data failed\n");
  193. return -EIO;
  194. }
  195. memcpy(oldvalues, values, length);
  196. ret = ds1307_read_block_data_once(client, command, length,
  197. values);
  198. if (ret < 0)
  199. return ret;
  200. } while (memcmp(oldvalues, values, length));
  201. return length;
  202. }
  203. static s32 ds1307_write_block_data(const struct i2c_client *client, u8 command,
  204. u8 length, const u8 *values)
  205. {
  206. u8 currvalues[I2C_SMBUS_BLOCK_MAX];
  207. int tries = 0;
  208. dev_dbg(&client->dev, "ds1307_write_block_data (length=%d)\n", length);
  209. do {
  210. s32 i, ret;
  211. if (++tries > BLOCK_DATA_MAX_TRIES) {
  212. dev_err(&client->dev,
  213. "ds1307_write_block_data failed\n");
  214. return -EIO;
  215. }
  216. for (i = 0; i < length; i++) {
  217. ret = i2c_smbus_write_byte_data(client, command + i,
  218. values[i]);
  219. if (ret < 0)
  220. return ret;
  221. }
  222. ret = ds1307_read_block_data_once(client, command, length,
  223. currvalues);
  224. if (ret < 0)
  225. return ret;
  226. } while (memcmp(currvalues, values, length));
  227. return length;
  228. }
  229. /*----------------------------------------------------------------------*/
  230. /*
  231. * The IRQ logic includes a "real" handler running in IRQ context just
  232. * long enough to schedule this workqueue entry. We need a task context
  233. * to talk to the RTC, since I2C I/O calls require that; and disable the
  234. * IRQ until we clear its status on the chip, so that this handler can
  235. * work with any type of triggering (not just falling edge).
  236. *
  237. * The ds1337 and ds1339 both have two alarms, but we only use the first
  238. * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
  239. * signal; ds1339 chips have only one alarm signal.
  240. */
  241. static void ds1307_work(struct work_struct *work)
  242. {
  243. struct ds1307 *ds1307;
  244. struct i2c_client *client;
  245. struct mutex *lock;
  246. int stat, control;
  247. ds1307 = container_of(work, struct ds1307, work);
  248. client = ds1307->client;
  249. lock = &ds1307->rtc->ops_lock;
  250. mutex_lock(lock);
  251. stat = i2c_smbus_read_byte_data(client, DS1337_REG_STATUS);
  252. if (stat < 0)
  253. goto out;
  254. if (stat & DS1337_BIT_A1I) {
  255. stat &= ~DS1337_BIT_A1I;
  256. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS, stat);
  257. control = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  258. if (control < 0)
  259. goto out;
  260. control &= ~DS1337_BIT_A1IE;
  261. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, control);
  262. rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
  263. }
  264. out:
  265. if (test_bit(HAS_ALARM, &ds1307->flags))
  266. enable_irq(client->irq);
  267. mutex_unlock(lock);
  268. }
  269. static irqreturn_t ds1307_irq(int irq, void *dev_id)
  270. {
  271. struct i2c_client *client = dev_id;
  272. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  273. disable_irq_nosync(irq);
  274. schedule_work(&ds1307->work);
  275. return IRQ_HANDLED;
  276. }
  277. /*----------------------------------------------------------------------*/
  278. static int ds1307_get_time(struct device *dev, struct rtc_time *t)
  279. {
  280. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  281. int tmp;
  282. /* read the RTC date and time registers all at once */
  283. tmp = ds1307->read_block_data(ds1307->client,
  284. ds1307->offset, 7, ds1307->regs);
  285. if (tmp != 7) {
  286. dev_err(dev, "%s error %d\n", "read", tmp);
  287. return -EIO;
  288. }
  289. dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
  290. t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
  291. t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
  292. tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
  293. t->tm_hour = bcd2bin(tmp);
  294. t->tm_wday = bcd2bin(ds1307->regs[DS1307_REG_WDAY] & 0x07) - 1;
  295. t->tm_mday = bcd2bin(ds1307->regs[DS1307_REG_MDAY] & 0x3f);
  296. tmp = ds1307->regs[DS1307_REG_MONTH] & 0x1f;
  297. t->tm_mon = bcd2bin(tmp) - 1;
  298. /* assume 20YY not 19YY, and ignore DS1337_BIT_CENTURY */
  299. t->tm_year = bcd2bin(ds1307->regs[DS1307_REG_YEAR]) + 100;
  300. dev_dbg(dev, "%s secs=%d, mins=%d, "
  301. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  302. "read", t->tm_sec, t->tm_min,
  303. t->tm_hour, t->tm_mday,
  304. t->tm_mon, t->tm_year, t->tm_wday);
  305. /* initial clock setting can be undefined */
  306. return rtc_valid_tm(t);
  307. }
  308. static int ds1307_set_time(struct device *dev, struct rtc_time *t)
  309. {
  310. struct ds1307 *ds1307 = dev_get_drvdata(dev);
  311. int result;
  312. int tmp;
  313. u8 *buf = ds1307->regs;
  314. dev_dbg(dev, "%s secs=%d, mins=%d, "
  315. "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
  316. "write", t->tm_sec, t->tm_min,
  317. t->tm_hour, t->tm_mday,
  318. t->tm_mon, t->tm_year, t->tm_wday);
  319. buf[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
  320. buf[DS1307_REG_MIN] = bin2bcd(t->tm_min);
  321. buf[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
  322. buf[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
  323. buf[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
  324. buf[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
  325. /* assume 20YY not 19YY */
  326. tmp = t->tm_year - 100;
  327. buf[DS1307_REG_YEAR] = bin2bcd(tmp);
  328. switch (ds1307->type) {
  329. case ds_1337:
  330. case ds_1339:
  331. case ds_3231:
  332. buf[DS1307_REG_MONTH] |= DS1337_BIT_CENTURY;
  333. break;
  334. case ds_1340:
  335. buf[DS1307_REG_HOUR] |= DS1340_BIT_CENTURY_EN
  336. | DS1340_BIT_CENTURY;
  337. break;
  338. case mcp7941x:
  339. /*
  340. * these bits were cleared when preparing the date/time
  341. * values and need to be set again before writing the
  342. * buffer out to the device.
  343. */
  344. buf[DS1307_REG_SECS] |= MCP7941X_BIT_ST;
  345. buf[DS1307_REG_WDAY] |= MCP7941X_BIT_VBATEN;
  346. break;
  347. default:
  348. break;
  349. }
  350. dev_dbg(dev, "%s: %7ph\n", "write", buf);
  351. result = ds1307->write_block_data(ds1307->client,
  352. ds1307->offset, 7, buf);
  353. if (result < 0) {
  354. dev_err(dev, "%s error %d\n", "write", result);
  355. return result;
  356. }
  357. return 0;
  358. }
  359. static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
  360. {
  361. struct i2c_client *client = to_i2c_client(dev);
  362. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  363. int ret;
  364. if (!test_bit(HAS_ALARM, &ds1307->flags))
  365. return -EINVAL;
  366. /* read all ALARM1, ALARM2, and status registers at once */
  367. ret = ds1307->read_block_data(client,
  368. DS1339_REG_ALARM1_SECS, 9, ds1307->regs);
  369. if (ret != 9) {
  370. dev_err(dev, "%s error %d\n", "alarm read", ret);
  371. return -EIO;
  372. }
  373. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  374. "alarm read",
  375. ds1307->regs[0], ds1307->regs[1],
  376. ds1307->regs[2], ds1307->regs[3],
  377. ds1307->regs[4], ds1307->regs[5],
  378. ds1307->regs[6], ds1307->regs[7],
  379. ds1307->regs[8]);
  380. /*
  381. * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
  382. * and that all four fields are checked matches
  383. */
  384. t->time.tm_sec = bcd2bin(ds1307->regs[0] & 0x7f);
  385. t->time.tm_min = bcd2bin(ds1307->regs[1] & 0x7f);
  386. t->time.tm_hour = bcd2bin(ds1307->regs[2] & 0x3f);
  387. t->time.tm_mday = bcd2bin(ds1307->regs[3] & 0x3f);
  388. t->time.tm_mon = -1;
  389. t->time.tm_year = -1;
  390. t->time.tm_wday = -1;
  391. t->time.tm_yday = -1;
  392. t->time.tm_isdst = -1;
  393. /* ... and status */
  394. t->enabled = !!(ds1307->regs[7] & DS1337_BIT_A1IE);
  395. t->pending = !!(ds1307->regs[8] & DS1337_BIT_A1I);
  396. dev_dbg(dev, "%s secs=%d, mins=%d, "
  397. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  398. "alarm read", t->time.tm_sec, t->time.tm_min,
  399. t->time.tm_hour, t->time.tm_mday,
  400. t->enabled, t->pending);
  401. return 0;
  402. }
  403. static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
  404. {
  405. struct i2c_client *client = to_i2c_client(dev);
  406. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  407. unsigned char *buf = ds1307->regs;
  408. u8 control, status;
  409. int ret;
  410. if (!test_bit(HAS_ALARM, &ds1307->flags))
  411. return -EINVAL;
  412. dev_dbg(dev, "%s secs=%d, mins=%d, "
  413. "hours=%d, mday=%d, enabled=%d, pending=%d\n",
  414. "alarm set", t->time.tm_sec, t->time.tm_min,
  415. t->time.tm_hour, t->time.tm_mday,
  416. t->enabled, t->pending);
  417. /* read current status of both alarms and the chip */
  418. ret = ds1307->read_block_data(client,
  419. DS1339_REG_ALARM1_SECS, 9, buf);
  420. if (ret != 9) {
  421. dev_err(dev, "%s error %d\n", "alarm write", ret);
  422. return -EIO;
  423. }
  424. control = ds1307->regs[7];
  425. status = ds1307->regs[8];
  426. dev_dbg(dev, "%s: %02x %02x %02x %02x, %02x %02x %02x, %02x %02x\n",
  427. "alarm set (old status)",
  428. ds1307->regs[0], ds1307->regs[1],
  429. ds1307->regs[2], ds1307->regs[3],
  430. ds1307->regs[4], ds1307->regs[5],
  431. ds1307->regs[6], control, status);
  432. /* set ALARM1, using 24 hour and day-of-month modes */
  433. buf[0] = bin2bcd(t->time.tm_sec);
  434. buf[1] = bin2bcd(t->time.tm_min);
  435. buf[2] = bin2bcd(t->time.tm_hour);
  436. buf[3] = bin2bcd(t->time.tm_mday);
  437. /* set ALARM2 to non-garbage */
  438. buf[4] = 0;
  439. buf[5] = 0;
  440. buf[6] = 0;
  441. /* optionally enable ALARM1 */
  442. buf[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
  443. if (t->enabled) {
  444. dev_dbg(dev, "alarm IRQ armed\n");
  445. buf[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
  446. }
  447. buf[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
  448. ret = ds1307->write_block_data(client,
  449. DS1339_REG_ALARM1_SECS, 9, buf);
  450. if (ret < 0) {
  451. dev_err(dev, "can't set alarm time\n");
  452. return ret;
  453. }
  454. return 0;
  455. }
  456. static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
  457. {
  458. struct i2c_client *client = to_i2c_client(dev);
  459. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  460. int ret;
  461. if (!test_bit(HAS_ALARM, &ds1307->flags))
  462. return -ENOTTY;
  463. ret = i2c_smbus_read_byte_data(client, DS1337_REG_CONTROL);
  464. if (ret < 0)
  465. return ret;
  466. if (enabled)
  467. ret |= DS1337_BIT_A1IE;
  468. else
  469. ret &= ~DS1337_BIT_A1IE;
  470. ret = i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL, ret);
  471. if (ret < 0)
  472. return ret;
  473. return 0;
  474. }
  475. static const struct rtc_class_ops ds13xx_rtc_ops = {
  476. .read_time = ds1307_get_time,
  477. .set_time = ds1307_set_time,
  478. .read_alarm = ds1337_read_alarm,
  479. .set_alarm = ds1337_set_alarm,
  480. .alarm_irq_enable = ds1307_alarm_irq_enable,
  481. };
  482. /*----------------------------------------------------------------------*/
  483. static ssize_t
  484. ds1307_nvram_read(struct file *filp, struct kobject *kobj,
  485. struct bin_attribute *attr,
  486. char *buf, loff_t off, size_t count)
  487. {
  488. struct i2c_client *client;
  489. struct ds1307 *ds1307;
  490. int result;
  491. client = kobj_to_i2c_client(kobj);
  492. ds1307 = i2c_get_clientdata(client);
  493. if (unlikely(off >= ds1307->nvram->size))
  494. return 0;
  495. if ((off + count) > ds1307->nvram->size)
  496. count = ds1307->nvram->size - off;
  497. if (unlikely(!count))
  498. return count;
  499. result = ds1307->read_block_data(client, ds1307->nvram_offset + off,
  500. count, buf);
  501. if (result < 0)
  502. dev_err(&client->dev, "%s error %d\n", "nvram read", result);
  503. return result;
  504. }
  505. static ssize_t
  506. ds1307_nvram_write(struct file *filp, struct kobject *kobj,
  507. struct bin_attribute *attr,
  508. char *buf, loff_t off, size_t count)
  509. {
  510. struct i2c_client *client;
  511. struct ds1307 *ds1307;
  512. int result;
  513. client = kobj_to_i2c_client(kobj);
  514. ds1307 = i2c_get_clientdata(client);
  515. if (unlikely(off >= ds1307->nvram->size))
  516. return -EFBIG;
  517. if ((off + count) > ds1307->nvram->size)
  518. count = ds1307->nvram->size - off;
  519. if (unlikely(!count))
  520. return count;
  521. result = ds1307->write_block_data(client, ds1307->nvram_offset + off,
  522. count, buf);
  523. if (result < 0) {
  524. dev_err(&client->dev, "%s error %d\n", "nvram write", result);
  525. return result;
  526. }
  527. return count;
  528. }
  529. /*----------------------------------------------------------------------*/
  530. static int ds1307_probe(struct i2c_client *client,
  531. const struct i2c_device_id *id)
  532. {
  533. struct ds1307 *ds1307;
  534. int err = -ENODEV;
  535. int tmp;
  536. const struct chip_desc *chip = &chips[id->driver_data];
  537. struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
  538. int want_irq = false;
  539. unsigned char *buf;
  540. struct ds1307_platform_data *pdata = client->dev.platform_data;
  541. static const int bbsqi_bitpos[] = {
  542. [ds_1337] = 0,
  543. [ds_1339] = DS1339_BIT_BBSQI,
  544. [ds_3231] = DS3231_BIT_BBSQW,
  545. };
  546. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)
  547. && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
  548. return -EIO;
  549. ds1307 = kzalloc(sizeof(struct ds1307), GFP_KERNEL);
  550. if (!ds1307)
  551. return -ENOMEM;
  552. i2c_set_clientdata(client, ds1307);
  553. ds1307->client = client;
  554. ds1307->type = id->driver_data;
  555. if (pdata && pdata->trickle_charger_setup && chip->trickle_charger_reg)
  556. i2c_smbus_write_byte_data(client, chip->trickle_charger_reg,
  557. DS13XX_TRICKLE_CHARGER_MAGIC | pdata->trickle_charger_setup);
  558. buf = ds1307->regs;
  559. if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK)) {
  560. ds1307->read_block_data = i2c_smbus_read_i2c_block_data;
  561. ds1307->write_block_data = i2c_smbus_write_i2c_block_data;
  562. } else {
  563. ds1307->read_block_data = ds1307_read_block_data;
  564. ds1307->write_block_data = ds1307_write_block_data;
  565. }
  566. switch (ds1307->type) {
  567. case ds_1337:
  568. case ds_1339:
  569. case ds_3231:
  570. /* get registers that the "rtc" read below won't read... */
  571. tmp = ds1307->read_block_data(ds1307->client,
  572. DS1337_REG_CONTROL, 2, buf);
  573. if (tmp != 2) {
  574. pr_debug("read error %d\n", tmp);
  575. err = -EIO;
  576. goto exit_free;
  577. }
  578. /* oscillator off? turn it on, so clock can tick. */
  579. if (ds1307->regs[0] & DS1337_BIT_nEOSC)
  580. ds1307->regs[0] &= ~DS1337_BIT_nEOSC;
  581. /*
  582. * Using IRQ? Disable the square wave and both alarms.
  583. * For some variants, be sure alarms can trigger when we're
  584. * running on Vbackup (BBSQI/BBSQW)
  585. */
  586. if (ds1307->client->irq > 0 && chip->alarm) {
  587. INIT_WORK(&ds1307->work, ds1307_work);
  588. ds1307->regs[0] |= DS1337_BIT_INTCN
  589. | bbsqi_bitpos[ds1307->type];
  590. ds1307->regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
  591. want_irq = true;
  592. }
  593. i2c_smbus_write_byte_data(client, DS1337_REG_CONTROL,
  594. ds1307->regs[0]);
  595. /* oscillator fault? clear flag, and warn */
  596. if (ds1307->regs[1] & DS1337_BIT_OSF) {
  597. i2c_smbus_write_byte_data(client, DS1337_REG_STATUS,
  598. ds1307->regs[1] & ~DS1337_BIT_OSF);
  599. dev_warn(&client->dev, "SET TIME!\n");
  600. }
  601. break;
  602. case rx_8025:
  603. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  604. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  605. if (tmp != 2) {
  606. pr_debug("read error %d\n", tmp);
  607. err = -EIO;
  608. goto exit_free;
  609. }
  610. /* oscillator off? turn it on, so clock can tick. */
  611. if (!(ds1307->regs[1] & RX8025_BIT_XST)) {
  612. ds1307->regs[1] |= RX8025_BIT_XST;
  613. i2c_smbus_write_byte_data(client,
  614. RX8025_REG_CTRL2 << 4 | 0x08,
  615. ds1307->regs[1]);
  616. dev_warn(&client->dev,
  617. "oscillator stop detected - SET TIME!\n");
  618. }
  619. if (ds1307->regs[1] & RX8025_BIT_PON) {
  620. ds1307->regs[1] &= ~RX8025_BIT_PON;
  621. i2c_smbus_write_byte_data(client,
  622. RX8025_REG_CTRL2 << 4 | 0x08,
  623. ds1307->regs[1]);
  624. dev_warn(&client->dev, "power-on detected\n");
  625. }
  626. if (ds1307->regs[1] & RX8025_BIT_VDET) {
  627. ds1307->regs[1] &= ~RX8025_BIT_VDET;
  628. i2c_smbus_write_byte_data(client,
  629. RX8025_REG_CTRL2 << 4 | 0x08,
  630. ds1307->regs[1]);
  631. dev_warn(&client->dev, "voltage drop detected\n");
  632. }
  633. /* make sure we are running in 24hour mode */
  634. if (!(ds1307->regs[0] & RX8025_BIT_2412)) {
  635. u8 hour;
  636. /* switch to 24 hour mode */
  637. i2c_smbus_write_byte_data(client,
  638. RX8025_REG_CTRL1 << 4 | 0x08,
  639. ds1307->regs[0] |
  640. RX8025_BIT_2412);
  641. tmp = i2c_smbus_read_i2c_block_data(ds1307->client,
  642. RX8025_REG_CTRL1 << 4 | 0x08, 2, buf);
  643. if (tmp != 2) {
  644. pr_debug("read error %d\n", tmp);
  645. err = -EIO;
  646. goto exit_free;
  647. }
  648. /* correct hour */
  649. hour = bcd2bin(ds1307->regs[DS1307_REG_HOUR]);
  650. if (hour == 12)
  651. hour = 0;
  652. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  653. hour += 12;
  654. i2c_smbus_write_byte_data(client,
  655. DS1307_REG_HOUR << 4 | 0x08,
  656. hour);
  657. }
  658. break;
  659. case ds_1388:
  660. ds1307->offset = 1; /* Seconds starts at 1 */
  661. break;
  662. default:
  663. break;
  664. }
  665. read_rtc:
  666. /* read RTC registers */
  667. tmp = ds1307->read_block_data(ds1307->client, ds1307->offset, 8, buf);
  668. if (tmp != 8) {
  669. pr_debug("read error %d\n", tmp);
  670. err = -EIO;
  671. goto exit_free;
  672. }
  673. /*
  674. * minimal sanity checking; some chips (like DS1340) don't
  675. * specify the extra bits as must-be-zero, but there are
  676. * still a few values that are clearly out-of-range.
  677. */
  678. tmp = ds1307->regs[DS1307_REG_SECS];
  679. switch (ds1307->type) {
  680. case ds_1307:
  681. case m41t00:
  682. /* clock halted? turn it on, so clock can tick. */
  683. if (tmp & DS1307_BIT_CH) {
  684. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  685. dev_warn(&client->dev, "SET TIME!\n");
  686. goto read_rtc;
  687. }
  688. break;
  689. case ds_1338:
  690. /* clock halted? turn it on, so clock can tick. */
  691. if (tmp & DS1307_BIT_CH)
  692. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  693. /* oscillator fault? clear flag, and warn */
  694. if (ds1307->regs[DS1307_REG_CONTROL] & DS1338_BIT_OSF) {
  695. i2c_smbus_write_byte_data(client, DS1307_REG_CONTROL,
  696. ds1307->regs[DS1307_REG_CONTROL]
  697. & ~DS1338_BIT_OSF);
  698. dev_warn(&client->dev, "SET TIME!\n");
  699. goto read_rtc;
  700. }
  701. break;
  702. case ds_1340:
  703. /* clock halted? turn it on, so clock can tick. */
  704. if (tmp & DS1340_BIT_nEOSC)
  705. i2c_smbus_write_byte_data(client, DS1307_REG_SECS, 0);
  706. tmp = i2c_smbus_read_byte_data(client, DS1340_REG_FLAG);
  707. if (tmp < 0) {
  708. pr_debug("read error %d\n", tmp);
  709. err = -EIO;
  710. goto exit_free;
  711. }
  712. /* oscillator fault? clear flag, and warn */
  713. if (tmp & DS1340_BIT_OSF) {
  714. i2c_smbus_write_byte_data(client, DS1340_REG_FLAG, 0);
  715. dev_warn(&client->dev, "SET TIME!\n");
  716. }
  717. break;
  718. case mcp7941x:
  719. /* make sure that the backup battery is enabled */
  720. if (!(ds1307->regs[DS1307_REG_WDAY] & MCP7941X_BIT_VBATEN)) {
  721. i2c_smbus_write_byte_data(client, DS1307_REG_WDAY,
  722. ds1307->regs[DS1307_REG_WDAY]
  723. | MCP7941X_BIT_VBATEN);
  724. }
  725. /* clock halted? turn it on, so clock can tick. */
  726. if (!(tmp & MCP7941X_BIT_ST)) {
  727. i2c_smbus_write_byte_data(client, DS1307_REG_SECS,
  728. MCP7941X_BIT_ST);
  729. dev_warn(&client->dev, "SET TIME!\n");
  730. goto read_rtc;
  731. }
  732. break;
  733. default:
  734. break;
  735. }
  736. tmp = ds1307->regs[DS1307_REG_HOUR];
  737. switch (ds1307->type) {
  738. case ds_1340:
  739. case m41t00:
  740. /*
  741. * NOTE: ignores century bits; fix before deploying
  742. * systems that will run through year 2100.
  743. */
  744. break;
  745. case rx_8025:
  746. break;
  747. default:
  748. if (!(tmp & DS1307_BIT_12HR))
  749. break;
  750. /*
  751. * Be sure we're in 24 hour mode. Multi-master systems
  752. * take note...
  753. */
  754. tmp = bcd2bin(tmp & 0x1f);
  755. if (tmp == 12)
  756. tmp = 0;
  757. if (ds1307->regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
  758. tmp += 12;
  759. i2c_smbus_write_byte_data(client,
  760. ds1307->offset + DS1307_REG_HOUR,
  761. bin2bcd(tmp));
  762. }
  763. ds1307->rtc = rtc_device_register(client->name, &client->dev,
  764. &ds13xx_rtc_ops, THIS_MODULE);
  765. if (IS_ERR(ds1307->rtc)) {
  766. err = PTR_ERR(ds1307->rtc);
  767. dev_err(&client->dev,
  768. "unable to register the class device\n");
  769. goto exit_free;
  770. }
  771. if (want_irq) {
  772. err = request_irq(client->irq, ds1307_irq, IRQF_SHARED,
  773. ds1307->rtc->name, client);
  774. if (err) {
  775. dev_err(&client->dev,
  776. "unable to request IRQ!\n");
  777. goto exit_irq;
  778. }
  779. device_set_wakeup_capable(&client->dev, 1);
  780. set_bit(HAS_ALARM, &ds1307->flags);
  781. dev_dbg(&client->dev, "got IRQ %d\n", client->irq);
  782. }
  783. if (chip->nvram_size) {
  784. ds1307->nvram = kzalloc(sizeof(struct bin_attribute),
  785. GFP_KERNEL);
  786. if (!ds1307->nvram) {
  787. err = -ENOMEM;
  788. goto exit_nvram;
  789. }
  790. ds1307->nvram->attr.name = "nvram";
  791. ds1307->nvram->attr.mode = S_IRUGO | S_IWUSR;
  792. sysfs_bin_attr_init(ds1307->nvram);
  793. ds1307->nvram->read = ds1307_nvram_read,
  794. ds1307->nvram->write = ds1307_nvram_write,
  795. ds1307->nvram->size = chip->nvram_size;
  796. ds1307->nvram_offset = chip->nvram_offset;
  797. err = sysfs_create_bin_file(&client->dev.kobj, ds1307->nvram);
  798. if (err) {
  799. kfree(ds1307->nvram);
  800. goto exit_nvram;
  801. }
  802. set_bit(HAS_NVRAM, &ds1307->flags);
  803. dev_info(&client->dev, "%zu bytes nvram\n", ds1307->nvram->size);
  804. }
  805. return 0;
  806. exit_nvram:
  807. exit_irq:
  808. rtc_device_unregister(ds1307->rtc);
  809. exit_free:
  810. kfree(ds1307);
  811. return err;
  812. }
  813. static int ds1307_remove(struct i2c_client *client)
  814. {
  815. struct ds1307 *ds1307 = i2c_get_clientdata(client);
  816. if (test_and_clear_bit(HAS_ALARM, &ds1307->flags)) {
  817. free_irq(client->irq, client);
  818. cancel_work_sync(&ds1307->work);
  819. }
  820. if (test_and_clear_bit(HAS_NVRAM, &ds1307->flags)) {
  821. sysfs_remove_bin_file(&client->dev.kobj, ds1307->nvram);
  822. kfree(ds1307->nvram);
  823. }
  824. rtc_device_unregister(ds1307->rtc);
  825. kfree(ds1307);
  826. return 0;
  827. }
  828. static struct i2c_driver ds1307_driver = {
  829. .driver = {
  830. .name = "rtc-ds1307",
  831. .owner = THIS_MODULE,
  832. },
  833. .probe = ds1307_probe,
  834. .remove = ds1307_remove,
  835. .id_table = ds1307_id,
  836. };
  837. module_i2c_driver(ds1307_driver);
  838. MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
  839. MODULE_LICENSE("GPL");