process.c 12 KB

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  1. /*
  2. * Blackfin architecture-dependent process handling
  3. *
  4. * Copyright 2004-2009 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later
  7. */
  8. #include <linux/module.h>
  9. #include <linux/unistd.h>
  10. #include <linux/user.h>
  11. #include <linux/uaccess.h>
  12. #include <linux/slab.h>
  13. #include <linux/sched.h>
  14. #include <linux/tick.h>
  15. #include <linux/fs.h>
  16. #include <linux/err.h>
  17. #include <asm/blackfin.h>
  18. #include <asm/fixed_code.h>
  19. #include <asm/mem_map.h>
  20. #include <asm/irq.h>
  21. asmlinkage void ret_from_fork(void);
  22. /* Points to the SDRAM backup memory for the stack that is currently in
  23. * L1 scratchpad memory.
  24. */
  25. void *current_l1_stack_save;
  26. /* The number of tasks currently using a L1 stack area. The SRAM is
  27. * allocated/deallocated whenever this changes from/to zero.
  28. */
  29. int nr_l1stack_tasks;
  30. /* Start and length of the area in L1 scratchpad memory which we've allocated
  31. * for process stacks.
  32. */
  33. void *l1_stack_base;
  34. unsigned long l1_stack_len;
  35. void (*pm_power_off)(void) = NULL;
  36. EXPORT_SYMBOL(pm_power_off);
  37. /*
  38. * The idle loop on BFIN
  39. */
  40. #ifdef CONFIG_IDLE_L1
  41. static void default_idle(void)__attribute__((l1_text));
  42. void cpu_idle(void)__attribute__((l1_text));
  43. #endif
  44. /*
  45. * This is our default idle handler. We need to disable
  46. * interrupts here to ensure we don't miss a wakeup call.
  47. */
  48. static void default_idle(void)
  49. {
  50. #ifdef CONFIG_IPIPE
  51. ipipe_suspend_domain();
  52. #endif
  53. hard_local_irq_disable();
  54. if (!need_resched())
  55. idle_with_irq_disabled();
  56. hard_local_irq_enable();
  57. }
  58. /*
  59. * The idle thread. We try to conserve power, while trying to keep
  60. * overall latency low. The architecture specific idle is passed
  61. * a value to indicate the level of "idleness" of the system.
  62. */
  63. void cpu_idle(void)
  64. {
  65. /* endless idle loop with no priority at all */
  66. while (1) {
  67. #ifdef CONFIG_HOTPLUG_CPU
  68. if (cpu_is_offline(smp_processor_id()))
  69. cpu_die();
  70. #endif
  71. if (!idle)
  72. idle = default_idle;
  73. tick_nohz_idle_enter();
  74. rcu_idle_enter();
  75. while (!need_resched())
  76. idle();
  77. rcu_idle_exit();
  78. tick_nohz_idle_exit();
  79. preempt_enable_no_resched();
  80. schedule();
  81. preempt_disable();
  82. }
  83. }
  84. /*
  85. * Do necessary setup to start up a newly executed thread.
  86. *
  87. * pass the data segment into user programs if it exists,
  88. * it can't hurt anything as far as I can tell
  89. */
  90. void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
  91. {
  92. regs->pc = new_ip;
  93. if (current->mm)
  94. regs->p5 = current->mm->start_data;
  95. #ifndef CONFIG_SMP
  96. task_thread_info(current)->l1_task_info.stack_start =
  97. (void *)current->mm->context.stack_start;
  98. task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
  99. memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
  100. sizeof(*L1_SCRATCH_TASK_INFO));
  101. #endif
  102. wrusp(new_sp);
  103. }
  104. EXPORT_SYMBOL_GPL(start_thread);
  105. void flush_thread(void)
  106. {
  107. }
  108. asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
  109. {
  110. #ifdef __ARCH_SYNC_CORE_DCACHE
  111. if (current->nr_cpus_allowed == num_possible_cpus())
  112. set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
  113. #endif
  114. if (newsp)
  115. newsp -= 12;
  116. return do_fork(clone_flags, newsp, 0, NULL, NULL);
  117. }
  118. int
  119. copy_thread(unsigned long clone_flags,
  120. unsigned long usp, unsigned long topstk,
  121. struct task_struct *p)
  122. {
  123. struct pt_regs *childregs;
  124. unsigned long *v;
  125. childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
  126. v = ((unsigned long *)childregs) - 2;
  127. if (unlikely(p->flags & PF_KTHREAD)) {
  128. memset(childregs, 0, sizeof(struct pt_regs));
  129. v[0] = usp;
  130. v[1] = topstk;
  131. childregs->orig_p0 = -1;
  132. childregs->ipend = 0x8000;
  133. __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
  134. p->thread.usp = 0;
  135. } else {
  136. *childregs = *current_pt_regs();
  137. childregs->r0 = 0;
  138. p->thread.usp = usp ? : rdusp();
  139. v[0] = v[1] = 0;
  140. }
  141. p->thread.ksp = (unsigned long)v;
  142. p->thread.pc = (unsigned long)ret_from_fork;
  143. return 0;
  144. }
  145. unsigned long get_wchan(struct task_struct *p)
  146. {
  147. unsigned long fp, pc;
  148. unsigned long stack_page;
  149. int count = 0;
  150. if (!p || p == current || p->state == TASK_RUNNING)
  151. return 0;
  152. stack_page = (unsigned long)p;
  153. fp = p->thread.usp;
  154. do {
  155. if (fp < stack_page + sizeof(struct thread_info) ||
  156. fp >= 8184 + stack_page)
  157. return 0;
  158. pc = ((unsigned long *)fp)[1];
  159. if (!in_sched_functions(pc))
  160. return pc;
  161. fp = *(unsigned long *)fp;
  162. }
  163. while (count++ < 16);
  164. return 0;
  165. }
  166. void finish_atomic_sections (struct pt_regs *regs)
  167. {
  168. int __user *up0 = (int __user *)regs->p0;
  169. switch (regs->pc) {
  170. default:
  171. /* not in middle of an atomic step, so resume like normal */
  172. return;
  173. case ATOMIC_XCHG32 + 2:
  174. put_user(regs->r1, up0);
  175. break;
  176. case ATOMIC_CAS32 + 2:
  177. case ATOMIC_CAS32 + 4:
  178. if (regs->r0 == regs->r1)
  179. case ATOMIC_CAS32 + 6:
  180. put_user(regs->r2, up0);
  181. break;
  182. case ATOMIC_ADD32 + 2:
  183. regs->r0 = regs->r1 + regs->r0;
  184. /* fall through */
  185. case ATOMIC_ADD32 + 4:
  186. put_user(regs->r0, up0);
  187. break;
  188. case ATOMIC_SUB32 + 2:
  189. regs->r0 = regs->r1 - regs->r0;
  190. /* fall through */
  191. case ATOMIC_SUB32 + 4:
  192. put_user(regs->r0, up0);
  193. break;
  194. case ATOMIC_IOR32 + 2:
  195. regs->r0 = regs->r1 | regs->r0;
  196. /* fall through */
  197. case ATOMIC_IOR32 + 4:
  198. put_user(regs->r0, up0);
  199. break;
  200. case ATOMIC_AND32 + 2:
  201. regs->r0 = regs->r1 & regs->r0;
  202. /* fall through */
  203. case ATOMIC_AND32 + 4:
  204. put_user(regs->r0, up0);
  205. break;
  206. case ATOMIC_XOR32 + 2:
  207. regs->r0 = regs->r1 ^ regs->r0;
  208. /* fall through */
  209. case ATOMIC_XOR32 + 4:
  210. put_user(regs->r0, up0);
  211. break;
  212. }
  213. /*
  214. * We've finished the atomic section, and the only thing left for
  215. * userspace is to do a RTS, so we might as well handle that too
  216. * since we need to update the PC anyways.
  217. */
  218. regs->pc = regs->rets;
  219. }
  220. static inline
  221. int in_mem(unsigned long addr, unsigned long size,
  222. unsigned long start, unsigned long end)
  223. {
  224. return addr >= start && addr + size <= end;
  225. }
  226. static inline
  227. int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
  228. unsigned long const_addr, unsigned long const_size)
  229. {
  230. return const_size &&
  231. in_mem(addr, size, const_addr + off, const_addr + const_size);
  232. }
  233. static inline
  234. int in_mem_const(unsigned long addr, unsigned long size,
  235. unsigned long const_addr, unsigned long const_size)
  236. {
  237. return in_mem_const_off(addr, size, 0, const_addr, const_size);
  238. }
  239. #ifdef CONFIG_BF60x
  240. #define ASYNC_ENABLED(bnum, bctlnum) 1
  241. #else
  242. #define ASYNC_ENABLED(bnum, bctlnum) \
  243. ({ \
  244. (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
  245. bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
  246. 1; \
  247. })
  248. #endif
  249. /*
  250. * We can't read EBIU banks that aren't enabled or we end up hanging
  251. * on the access to the async space. Make sure we validate accesses
  252. * that cross async banks too.
  253. * 0 - found, but unusable
  254. * 1 - found & usable
  255. * 2 - not found
  256. */
  257. static
  258. int in_async(unsigned long addr, unsigned long size)
  259. {
  260. if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
  261. if (!ASYNC_ENABLED(0, 0))
  262. return 0;
  263. if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
  264. return 1;
  265. size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
  266. addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
  267. }
  268. if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
  269. if (!ASYNC_ENABLED(1, 0))
  270. return 0;
  271. if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
  272. return 1;
  273. size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
  274. addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
  275. }
  276. if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
  277. if (!ASYNC_ENABLED(2, 1))
  278. return 0;
  279. if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
  280. return 1;
  281. size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
  282. addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
  283. }
  284. if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
  285. if (ASYNC_ENABLED(3, 1))
  286. return 0;
  287. if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
  288. return 1;
  289. return 0;
  290. }
  291. /* not within async bounds */
  292. return 2;
  293. }
  294. int bfin_mem_access_type(unsigned long addr, unsigned long size)
  295. {
  296. int cpu = raw_smp_processor_id();
  297. /* Check that things do not wrap around */
  298. if (addr > ULONG_MAX - size)
  299. return -EFAULT;
  300. if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
  301. return BFIN_MEM_ACCESS_CORE;
  302. if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
  303. return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
  304. if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
  305. return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
  306. if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
  307. return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
  308. if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
  309. return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
  310. #ifdef COREB_L1_CODE_START
  311. if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
  312. return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
  313. if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
  314. return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
  315. if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
  316. return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
  317. if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
  318. return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
  319. #endif
  320. if (in_mem_const(addr, size, L2_START, L2_LENGTH))
  321. return BFIN_MEM_ACCESS_CORE;
  322. if (addr >= SYSMMR_BASE)
  323. return BFIN_MEM_ACCESS_CORE_ONLY;
  324. switch (in_async(addr, size)) {
  325. case 0: return -EFAULT;
  326. case 1: return BFIN_MEM_ACCESS_CORE;
  327. case 2: /* fall through */;
  328. }
  329. if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
  330. return BFIN_MEM_ACCESS_CORE;
  331. if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
  332. return BFIN_MEM_ACCESS_DMA;
  333. return -EFAULT;
  334. }
  335. #if defined(CONFIG_ACCESS_CHECK)
  336. #ifdef CONFIG_ACCESS_OK_L1
  337. __attribute__((l1_text))
  338. #endif
  339. /* Return 1 if access to memory range is OK, 0 otherwise */
  340. int _access_ok(unsigned long addr, unsigned long size)
  341. {
  342. int aret;
  343. if (size == 0)
  344. return 1;
  345. /* Check that things do not wrap around */
  346. if (addr > ULONG_MAX - size)
  347. return 0;
  348. if (segment_eq(get_fs(), KERNEL_DS))
  349. return 1;
  350. #ifdef CONFIG_MTD_UCLINUX
  351. if (1)
  352. #else
  353. if (0)
  354. #endif
  355. {
  356. if (in_mem(addr, size, memory_start, memory_end))
  357. return 1;
  358. if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
  359. return 1;
  360. # ifndef CONFIG_ROMFS_ON_MTD
  361. if (0)
  362. # endif
  363. /* For XIP, allow user space to use pointers within the ROMFS. */
  364. if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
  365. return 1;
  366. } else {
  367. if (in_mem(addr, size, memory_start, physical_mem_end))
  368. return 1;
  369. }
  370. if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
  371. return 1;
  372. if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
  373. return 1;
  374. if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
  375. return 1;
  376. if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
  377. return 1;
  378. if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
  379. return 1;
  380. #ifdef COREB_L1_CODE_START
  381. if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
  382. return 1;
  383. if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
  384. return 1;
  385. if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
  386. return 1;
  387. if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
  388. return 1;
  389. #endif
  390. #ifndef CONFIG_EXCEPTION_L1_SCRATCH
  391. if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
  392. return 1;
  393. #endif
  394. aret = in_async(addr, size);
  395. if (aret < 2)
  396. return aret;
  397. if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
  398. return 1;
  399. if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
  400. return 1;
  401. if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
  402. return 1;
  403. return 0;
  404. }
  405. EXPORT_SYMBOL(_access_ok);
  406. #endif /* CONFIG_ACCESS_CHECK */