forcedeth.c 178 KB

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  1. /*
  2. * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
  3. *
  4. * Note: This driver is a cleanroom reimplementation based on reverse
  5. * engineered documentation written by Carl-Daniel Hailfinger
  6. * and Andrew de Quincey.
  7. *
  8. * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  9. * trademarks of NVIDIA Corporation in the United States and other
  10. * countries.
  11. *
  12. * Copyright (C) 2003,4,5 Manfred Spraul
  13. * Copyright (C) 2004 Andrew de Quincey (wol support)
  14. * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15. * IRQ rate fixes, bigendian fixes, cleanups, verification)
  16. * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. * Known bugs:
  33. * We suspect that on some hardware no TX done interrupts are generated.
  34. * This means recovery from netif_stop_queue only happens if the hw timer
  35. * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36. * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37. * If your hardware reliably generates tx done interrupts, then you can remove
  38. * DEV_NEED_TIMERIRQ from the driver_data flags.
  39. * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40. * superfluous timer interrupts from the nic.
  41. */
  42. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  43. #define FORCEDETH_VERSION "0.64"
  44. #define DRV_NAME "forcedeth"
  45. #include <linux/module.h>
  46. #include <linux/types.h>
  47. #include <linux/pci.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/netdevice.h>
  50. #include <linux/etherdevice.h>
  51. #include <linux/delay.h>
  52. #include <linux/sched.h>
  53. #include <linux/spinlock.h>
  54. #include <linux/ethtool.h>
  55. #include <linux/timer.h>
  56. #include <linux/skbuff.h>
  57. #include <linux/mii.h>
  58. #include <linux/random.h>
  59. #include <linux/init.h>
  60. #include <linux/if_vlan.h>
  61. #include <linux/dma-mapping.h>
  62. #include <linux/slab.h>
  63. #include <linux/uaccess.h>
  64. #include <linux/prefetch.h>
  65. #include <linux/io.h>
  66. #include <asm/irq.h>
  67. #include <asm/system.h>
  68. #define TX_WORK_PER_LOOP 64
  69. #define RX_WORK_PER_LOOP 64
  70. /*
  71. * Hardware access:
  72. */
  73. #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
  74. #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
  75. #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
  76. #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
  77. #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
  78. #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
  79. #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
  80. #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
  81. #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
  82. #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
  83. #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
  84. #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
  85. #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
  86. #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
  87. #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
  88. #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
  89. #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
  90. #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
  91. #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
  92. #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
  93. #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
  94. #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
  95. #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
  96. #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
  97. #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
  98. #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
  99. #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
  100. enum {
  101. NvRegIrqStatus = 0x000,
  102. #define NVREG_IRQSTAT_MIIEVENT 0x040
  103. #define NVREG_IRQSTAT_MASK 0x83ff
  104. NvRegIrqMask = 0x004,
  105. #define NVREG_IRQ_RX_ERROR 0x0001
  106. #define NVREG_IRQ_RX 0x0002
  107. #define NVREG_IRQ_RX_NOBUF 0x0004
  108. #define NVREG_IRQ_TX_ERR 0x0008
  109. #define NVREG_IRQ_TX_OK 0x0010
  110. #define NVREG_IRQ_TIMER 0x0020
  111. #define NVREG_IRQ_LINK 0x0040
  112. #define NVREG_IRQ_RX_FORCED 0x0080
  113. #define NVREG_IRQ_TX_FORCED 0x0100
  114. #define NVREG_IRQ_RECOVER_ERROR 0x8200
  115. #define NVREG_IRQMASK_THROUGHPUT 0x00df
  116. #define NVREG_IRQMASK_CPU 0x0060
  117. #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
  118. #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
  119. #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
  120. NvRegUnknownSetupReg6 = 0x008,
  121. #define NVREG_UNKSETUP6_VAL 3
  122. /*
  123. * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
  124. * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
  125. */
  126. NvRegPollingInterval = 0x00c,
  127. #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
  128. #define NVREG_POLL_DEFAULT_CPU 13
  129. NvRegMSIMap0 = 0x020,
  130. NvRegMSIMap1 = 0x024,
  131. NvRegMSIIrqMask = 0x030,
  132. #define NVREG_MSI_VECTOR_0_ENABLED 0x01
  133. NvRegMisc1 = 0x080,
  134. #define NVREG_MISC1_PAUSE_TX 0x01
  135. #define NVREG_MISC1_HD 0x02
  136. #define NVREG_MISC1_FORCE 0x3b0f3c
  137. NvRegMacReset = 0x34,
  138. #define NVREG_MAC_RESET_ASSERT 0x0F3
  139. NvRegTransmitterControl = 0x084,
  140. #define NVREG_XMITCTL_START 0x01
  141. #define NVREG_XMITCTL_MGMT_ST 0x40000000
  142. #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
  143. #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
  144. #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
  145. #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
  146. #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
  147. #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
  148. #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
  149. #define NVREG_XMITCTL_HOST_LOADED 0x00004000
  150. #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
  151. #define NVREG_XMITCTL_DATA_START 0x00100000
  152. #define NVREG_XMITCTL_DATA_READY 0x00010000
  153. #define NVREG_XMITCTL_DATA_ERROR 0x00020000
  154. NvRegTransmitterStatus = 0x088,
  155. #define NVREG_XMITSTAT_BUSY 0x01
  156. NvRegPacketFilterFlags = 0x8c,
  157. #define NVREG_PFF_PAUSE_RX 0x08
  158. #define NVREG_PFF_ALWAYS 0x7F0000
  159. #define NVREG_PFF_PROMISC 0x80
  160. #define NVREG_PFF_MYADDR 0x20
  161. #define NVREG_PFF_LOOPBACK 0x10
  162. NvRegOffloadConfig = 0x90,
  163. #define NVREG_OFFLOAD_HOMEPHY 0x601
  164. #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
  165. NvRegReceiverControl = 0x094,
  166. #define NVREG_RCVCTL_START 0x01
  167. #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
  168. NvRegReceiverStatus = 0x98,
  169. #define NVREG_RCVSTAT_BUSY 0x01
  170. NvRegSlotTime = 0x9c,
  171. #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
  172. #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
  173. #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
  174. #define NVREG_SLOTTIME_HALF 0x0000ff00
  175. #define NVREG_SLOTTIME_DEFAULT 0x00007f00
  176. #define NVREG_SLOTTIME_MASK 0x000000ff
  177. NvRegTxDeferral = 0xA0,
  178. #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
  179. #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
  180. #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
  181. #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
  182. #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
  183. #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
  184. NvRegRxDeferral = 0xA4,
  185. #define NVREG_RX_DEFERRAL_DEFAULT 0x16
  186. NvRegMacAddrA = 0xA8,
  187. NvRegMacAddrB = 0xAC,
  188. NvRegMulticastAddrA = 0xB0,
  189. #define NVREG_MCASTADDRA_FORCE 0x01
  190. NvRegMulticastAddrB = 0xB4,
  191. NvRegMulticastMaskA = 0xB8,
  192. #define NVREG_MCASTMASKA_NONE 0xffffffff
  193. NvRegMulticastMaskB = 0xBC,
  194. #define NVREG_MCASTMASKB_NONE 0xffff
  195. NvRegPhyInterface = 0xC0,
  196. #define PHY_RGMII 0x10000000
  197. NvRegBackOffControl = 0xC4,
  198. #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
  199. #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
  200. #define NVREG_BKOFFCTRL_SELECT 24
  201. #define NVREG_BKOFFCTRL_GEAR 12
  202. NvRegTxRingPhysAddr = 0x100,
  203. NvRegRxRingPhysAddr = 0x104,
  204. NvRegRingSizes = 0x108,
  205. #define NVREG_RINGSZ_TXSHIFT 0
  206. #define NVREG_RINGSZ_RXSHIFT 16
  207. NvRegTransmitPoll = 0x10c,
  208. #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
  209. NvRegLinkSpeed = 0x110,
  210. #define NVREG_LINKSPEED_FORCE 0x10000
  211. #define NVREG_LINKSPEED_10 1000
  212. #define NVREG_LINKSPEED_100 100
  213. #define NVREG_LINKSPEED_1000 50
  214. #define NVREG_LINKSPEED_MASK (0xFFF)
  215. NvRegUnknownSetupReg5 = 0x130,
  216. #define NVREG_UNKSETUP5_BIT31 (1<<31)
  217. NvRegTxWatermark = 0x13c,
  218. #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
  219. #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
  220. #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
  221. NvRegTxRxControl = 0x144,
  222. #define NVREG_TXRXCTL_KICK 0x0001
  223. #define NVREG_TXRXCTL_BIT1 0x0002
  224. #define NVREG_TXRXCTL_BIT2 0x0004
  225. #define NVREG_TXRXCTL_IDLE 0x0008
  226. #define NVREG_TXRXCTL_RESET 0x0010
  227. #define NVREG_TXRXCTL_RXCHECK 0x0400
  228. #define NVREG_TXRXCTL_DESC_1 0
  229. #define NVREG_TXRXCTL_DESC_2 0x002100
  230. #define NVREG_TXRXCTL_DESC_3 0xc02200
  231. #define NVREG_TXRXCTL_VLANSTRIP 0x00040
  232. #define NVREG_TXRXCTL_VLANINS 0x00080
  233. NvRegTxRingPhysAddrHigh = 0x148,
  234. NvRegRxRingPhysAddrHigh = 0x14C,
  235. NvRegTxPauseFrame = 0x170,
  236. #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
  237. #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
  238. #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
  239. #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
  240. NvRegTxPauseFrameLimit = 0x174,
  241. #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
  242. NvRegMIIStatus = 0x180,
  243. #define NVREG_MIISTAT_ERROR 0x0001
  244. #define NVREG_MIISTAT_LINKCHANGE 0x0008
  245. #define NVREG_MIISTAT_MASK_RW 0x0007
  246. #define NVREG_MIISTAT_MASK_ALL 0x000f
  247. NvRegMIIMask = 0x184,
  248. #define NVREG_MII_LINKCHANGE 0x0008
  249. NvRegAdapterControl = 0x188,
  250. #define NVREG_ADAPTCTL_START 0x02
  251. #define NVREG_ADAPTCTL_LINKUP 0x04
  252. #define NVREG_ADAPTCTL_PHYVALID 0x40000
  253. #define NVREG_ADAPTCTL_RUNNING 0x100000
  254. #define NVREG_ADAPTCTL_PHYSHIFT 24
  255. NvRegMIISpeed = 0x18c,
  256. #define NVREG_MIISPEED_BIT8 (1<<8)
  257. #define NVREG_MIIDELAY 5
  258. NvRegMIIControl = 0x190,
  259. #define NVREG_MIICTL_INUSE 0x08000
  260. #define NVREG_MIICTL_WRITE 0x00400
  261. #define NVREG_MIICTL_ADDRSHIFT 5
  262. NvRegMIIData = 0x194,
  263. NvRegTxUnicast = 0x1a0,
  264. NvRegTxMulticast = 0x1a4,
  265. NvRegTxBroadcast = 0x1a8,
  266. NvRegWakeUpFlags = 0x200,
  267. #define NVREG_WAKEUPFLAGS_VAL 0x7770
  268. #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
  269. #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
  270. #define NVREG_WAKEUPFLAGS_D3SHIFT 12
  271. #define NVREG_WAKEUPFLAGS_D2SHIFT 8
  272. #define NVREG_WAKEUPFLAGS_D1SHIFT 4
  273. #define NVREG_WAKEUPFLAGS_D0SHIFT 0
  274. #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
  275. #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
  276. #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
  277. #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
  278. NvRegMgmtUnitGetVersion = 0x204,
  279. #define NVREG_MGMTUNITGETVERSION 0x01
  280. NvRegMgmtUnitVersion = 0x208,
  281. #define NVREG_MGMTUNITVERSION 0x08
  282. NvRegPowerCap = 0x268,
  283. #define NVREG_POWERCAP_D3SUPP (1<<30)
  284. #define NVREG_POWERCAP_D2SUPP (1<<26)
  285. #define NVREG_POWERCAP_D1SUPP (1<<25)
  286. NvRegPowerState = 0x26c,
  287. #define NVREG_POWERSTATE_POWEREDUP 0x8000
  288. #define NVREG_POWERSTATE_VALID 0x0100
  289. #define NVREG_POWERSTATE_MASK 0x0003
  290. #define NVREG_POWERSTATE_D0 0x0000
  291. #define NVREG_POWERSTATE_D1 0x0001
  292. #define NVREG_POWERSTATE_D2 0x0002
  293. #define NVREG_POWERSTATE_D3 0x0003
  294. NvRegMgmtUnitControl = 0x278,
  295. #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
  296. NvRegTxCnt = 0x280,
  297. NvRegTxZeroReXmt = 0x284,
  298. NvRegTxOneReXmt = 0x288,
  299. NvRegTxManyReXmt = 0x28c,
  300. NvRegTxLateCol = 0x290,
  301. NvRegTxUnderflow = 0x294,
  302. NvRegTxLossCarrier = 0x298,
  303. NvRegTxExcessDef = 0x29c,
  304. NvRegTxRetryErr = 0x2a0,
  305. NvRegRxFrameErr = 0x2a4,
  306. NvRegRxExtraByte = 0x2a8,
  307. NvRegRxLateCol = 0x2ac,
  308. NvRegRxRunt = 0x2b0,
  309. NvRegRxFrameTooLong = 0x2b4,
  310. NvRegRxOverflow = 0x2b8,
  311. NvRegRxFCSErr = 0x2bc,
  312. NvRegRxFrameAlignErr = 0x2c0,
  313. NvRegRxLenErr = 0x2c4,
  314. NvRegRxUnicast = 0x2c8,
  315. NvRegRxMulticast = 0x2cc,
  316. NvRegRxBroadcast = 0x2d0,
  317. NvRegTxDef = 0x2d4,
  318. NvRegTxFrame = 0x2d8,
  319. NvRegRxCnt = 0x2dc,
  320. NvRegTxPause = 0x2e0,
  321. NvRegRxPause = 0x2e4,
  322. NvRegRxDropFrame = 0x2e8,
  323. NvRegVlanControl = 0x300,
  324. #define NVREG_VLANCONTROL_ENABLE 0x2000
  325. NvRegMSIXMap0 = 0x3e0,
  326. NvRegMSIXMap1 = 0x3e4,
  327. NvRegMSIXIrqStatus = 0x3f0,
  328. NvRegPowerState2 = 0x600,
  329. #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
  330. #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
  331. #define NVREG_POWERSTATE2_PHY_RESET 0x0004
  332. #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
  333. };
  334. /* Big endian: should work, but is untested */
  335. struct ring_desc {
  336. __le32 buf;
  337. __le32 flaglen;
  338. };
  339. struct ring_desc_ex {
  340. __le32 bufhigh;
  341. __le32 buflow;
  342. __le32 txvlan;
  343. __le32 flaglen;
  344. };
  345. union ring_type {
  346. struct ring_desc *orig;
  347. struct ring_desc_ex *ex;
  348. };
  349. #define FLAG_MASK_V1 0xffff0000
  350. #define FLAG_MASK_V2 0xffffc000
  351. #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
  352. #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
  353. #define NV_TX_LASTPACKET (1<<16)
  354. #define NV_TX_RETRYERROR (1<<19)
  355. #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
  356. #define NV_TX_FORCED_INTERRUPT (1<<24)
  357. #define NV_TX_DEFERRED (1<<26)
  358. #define NV_TX_CARRIERLOST (1<<27)
  359. #define NV_TX_LATECOLLISION (1<<28)
  360. #define NV_TX_UNDERFLOW (1<<29)
  361. #define NV_TX_ERROR (1<<30)
  362. #define NV_TX_VALID (1<<31)
  363. #define NV_TX2_LASTPACKET (1<<29)
  364. #define NV_TX2_RETRYERROR (1<<18)
  365. #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
  366. #define NV_TX2_FORCED_INTERRUPT (1<<30)
  367. #define NV_TX2_DEFERRED (1<<25)
  368. #define NV_TX2_CARRIERLOST (1<<26)
  369. #define NV_TX2_LATECOLLISION (1<<27)
  370. #define NV_TX2_UNDERFLOW (1<<28)
  371. /* error and valid are the same for both */
  372. #define NV_TX2_ERROR (1<<30)
  373. #define NV_TX2_VALID (1<<31)
  374. #define NV_TX2_TSO (1<<28)
  375. #define NV_TX2_TSO_SHIFT 14
  376. #define NV_TX2_TSO_MAX_SHIFT 14
  377. #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
  378. #define NV_TX2_CHECKSUM_L3 (1<<27)
  379. #define NV_TX2_CHECKSUM_L4 (1<<26)
  380. #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
  381. #define NV_RX_DESCRIPTORVALID (1<<16)
  382. #define NV_RX_MISSEDFRAME (1<<17)
  383. #define NV_RX_SUBSTRACT1 (1<<18)
  384. #define NV_RX_ERROR1 (1<<23)
  385. #define NV_RX_ERROR2 (1<<24)
  386. #define NV_RX_ERROR3 (1<<25)
  387. #define NV_RX_ERROR4 (1<<26)
  388. #define NV_RX_CRCERR (1<<27)
  389. #define NV_RX_OVERFLOW (1<<28)
  390. #define NV_RX_FRAMINGERR (1<<29)
  391. #define NV_RX_ERROR (1<<30)
  392. #define NV_RX_AVAIL (1<<31)
  393. #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
  394. #define NV_RX2_CHECKSUMMASK (0x1C000000)
  395. #define NV_RX2_CHECKSUM_IP (0x10000000)
  396. #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
  397. #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
  398. #define NV_RX2_DESCRIPTORVALID (1<<29)
  399. #define NV_RX2_SUBSTRACT1 (1<<25)
  400. #define NV_RX2_ERROR1 (1<<18)
  401. #define NV_RX2_ERROR2 (1<<19)
  402. #define NV_RX2_ERROR3 (1<<20)
  403. #define NV_RX2_ERROR4 (1<<21)
  404. #define NV_RX2_CRCERR (1<<22)
  405. #define NV_RX2_OVERFLOW (1<<23)
  406. #define NV_RX2_FRAMINGERR (1<<24)
  407. /* error and avail are the same for both */
  408. #define NV_RX2_ERROR (1<<30)
  409. #define NV_RX2_AVAIL (1<<31)
  410. #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
  411. #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
  412. #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
  413. /* Miscellaneous hardware related defines: */
  414. #define NV_PCI_REGSZ_VER1 0x270
  415. #define NV_PCI_REGSZ_VER2 0x2d4
  416. #define NV_PCI_REGSZ_VER3 0x604
  417. #define NV_PCI_REGSZ_MAX 0x604
  418. /* various timeout delays: all in usec */
  419. #define NV_TXRX_RESET_DELAY 4
  420. #define NV_TXSTOP_DELAY1 10
  421. #define NV_TXSTOP_DELAY1MAX 500000
  422. #define NV_TXSTOP_DELAY2 100
  423. #define NV_RXSTOP_DELAY1 10
  424. #define NV_RXSTOP_DELAY1MAX 500000
  425. #define NV_RXSTOP_DELAY2 100
  426. #define NV_SETUP5_DELAY 5
  427. #define NV_SETUP5_DELAYMAX 50000
  428. #define NV_POWERUP_DELAY 5
  429. #define NV_POWERUP_DELAYMAX 5000
  430. #define NV_MIIBUSY_DELAY 50
  431. #define NV_MIIPHY_DELAY 10
  432. #define NV_MIIPHY_DELAYMAX 10000
  433. #define NV_MAC_RESET_DELAY 64
  434. #define NV_WAKEUPPATTERNS 5
  435. #define NV_WAKEUPMASKENTRIES 4
  436. /* General driver defaults */
  437. #define NV_WATCHDOG_TIMEO (5*HZ)
  438. #define RX_RING_DEFAULT 512
  439. #define TX_RING_DEFAULT 256
  440. #define RX_RING_MIN 128
  441. #define TX_RING_MIN 64
  442. #define RING_MAX_DESC_VER_1 1024
  443. #define RING_MAX_DESC_VER_2_3 16384
  444. /* rx/tx mac addr + type + vlan + align + slack*/
  445. #define NV_RX_HEADERS (64)
  446. /* even more slack. */
  447. #define NV_RX_ALLOC_PAD (64)
  448. /* maximum mtu size */
  449. #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
  450. #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
  451. #define OOM_REFILL (1+HZ/20)
  452. #define POLL_WAIT (1+HZ/100)
  453. #define LINK_TIMEOUT (3*HZ)
  454. #define STATS_INTERVAL (10*HZ)
  455. /*
  456. * desc_ver values:
  457. * The nic supports three different descriptor types:
  458. * - DESC_VER_1: Original
  459. * - DESC_VER_2: support for jumbo frames.
  460. * - DESC_VER_3: 64-bit format.
  461. */
  462. #define DESC_VER_1 1
  463. #define DESC_VER_2 2
  464. #define DESC_VER_3 3
  465. /* PHY defines */
  466. #define PHY_OUI_MARVELL 0x5043
  467. #define PHY_OUI_CICADA 0x03f1
  468. #define PHY_OUI_VITESSE 0x01c1
  469. #define PHY_OUI_REALTEK 0x0732
  470. #define PHY_OUI_REALTEK2 0x0020
  471. #define PHYID1_OUI_MASK 0x03ff
  472. #define PHYID1_OUI_SHFT 6
  473. #define PHYID2_OUI_MASK 0xfc00
  474. #define PHYID2_OUI_SHFT 10
  475. #define PHYID2_MODEL_MASK 0x03f0
  476. #define PHY_MODEL_REALTEK_8211 0x0110
  477. #define PHY_REV_MASK 0x0001
  478. #define PHY_REV_REALTEK_8211B 0x0000
  479. #define PHY_REV_REALTEK_8211C 0x0001
  480. #define PHY_MODEL_REALTEK_8201 0x0200
  481. #define PHY_MODEL_MARVELL_E3016 0x0220
  482. #define PHY_MARVELL_E3016_INITMASK 0x0300
  483. #define PHY_CICADA_INIT1 0x0f000
  484. #define PHY_CICADA_INIT2 0x0e00
  485. #define PHY_CICADA_INIT3 0x01000
  486. #define PHY_CICADA_INIT4 0x0200
  487. #define PHY_CICADA_INIT5 0x0004
  488. #define PHY_CICADA_INIT6 0x02000
  489. #define PHY_VITESSE_INIT_REG1 0x1f
  490. #define PHY_VITESSE_INIT_REG2 0x10
  491. #define PHY_VITESSE_INIT_REG3 0x11
  492. #define PHY_VITESSE_INIT_REG4 0x12
  493. #define PHY_VITESSE_INIT_MSK1 0xc
  494. #define PHY_VITESSE_INIT_MSK2 0x0180
  495. #define PHY_VITESSE_INIT1 0x52b5
  496. #define PHY_VITESSE_INIT2 0xaf8a
  497. #define PHY_VITESSE_INIT3 0x8
  498. #define PHY_VITESSE_INIT4 0x8f8a
  499. #define PHY_VITESSE_INIT5 0xaf86
  500. #define PHY_VITESSE_INIT6 0x8f86
  501. #define PHY_VITESSE_INIT7 0xaf82
  502. #define PHY_VITESSE_INIT8 0x0100
  503. #define PHY_VITESSE_INIT9 0x8f82
  504. #define PHY_VITESSE_INIT10 0x0
  505. #define PHY_REALTEK_INIT_REG1 0x1f
  506. #define PHY_REALTEK_INIT_REG2 0x19
  507. #define PHY_REALTEK_INIT_REG3 0x13
  508. #define PHY_REALTEK_INIT_REG4 0x14
  509. #define PHY_REALTEK_INIT_REG5 0x18
  510. #define PHY_REALTEK_INIT_REG6 0x11
  511. #define PHY_REALTEK_INIT_REG7 0x01
  512. #define PHY_REALTEK_INIT1 0x0000
  513. #define PHY_REALTEK_INIT2 0x8e00
  514. #define PHY_REALTEK_INIT3 0x0001
  515. #define PHY_REALTEK_INIT4 0xad17
  516. #define PHY_REALTEK_INIT5 0xfb54
  517. #define PHY_REALTEK_INIT6 0xf5c7
  518. #define PHY_REALTEK_INIT7 0x1000
  519. #define PHY_REALTEK_INIT8 0x0003
  520. #define PHY_REALTEK_INIT9 0x0008
  521. #define PHY_REALTEK_INIT10 0x0005
  522. #define PHY_REALTEK_INIT11 0x0200
  523. #define PHY_REALTEK_INIT_MSK1 0x0003
  524. #define PHY_GIGABIT 0x0100
  525. #define PHY_TIMEOUT 0x1
  526. #define PHY_ERROR 0x2
  527. #define PHY_100 0x1
  528. #define PHY_1000 0x2
  529. #define PHY_HALF 0x100
  530. #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
  531. #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
  532. #define NV_PAUSEFRAME_RX_ENABLE 0x0004
  533. #define NV_PAUSEFRAME_TX_ENABLE 0x0008
  534. #define NV_PAUSEFRAME_RX_REQ 0x0010
  535. #define NV_PAUSEFRAME_TX_REQ 0x0020
  536. #define NV_PAUSEFRAME_AUTONEG 0x0040
  537. /* MSI/MSI-X defines */
  538. #define NV_MSI_X_MAX_VECTORS 8
  539. #define NV_MSI_X_VECTORS_MASK 0x000f
  540. #define NV_MSI_CAPABLE 0x0010
  541. #define NV_MSI_X_CAPABLE 0x0020
  542. #define NV_MSI_ENABLED 0x0040
  543. #define NV_MSI_X_ENABLED 0x0080
  544. #define NV_MSI_X_VECTOR_ALL 0x0
  545. #define NV_MSI_X_VECTOR_RX 0x0
  546. #define NV_MSI_X_VECTOR_TX 0x1
  547. #define NV_MSI_X_VECTOR_OTHER 0x2
  548. #define NV_MSI_PRIV_OFFSET 0x68
  549. #define NV_MSI_PRIV_VALUE 0xffffffff
  550. #define NV_RESTART_TX 0x1
  551. #define NV_RESTART_RX 0x2
  552. #define NV_TX_LIMIT_COUNT 16
  553. #define NV_DYNAMIC_THRESHOLD 4
  554. #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
  555. /* statistics */
  556. struct nv_ethtool_str {
  557. char name[ETH_GSTRING_LEN];
  558. };
  559. static const struct nv_ethtool_str nv_estats_str[] = {
  560. { "tx_bytes" },
  561. { "tx_zero_rexmt" },
  562. { "tx_one_rexmt" },
  563. { "tx_many_rexmt" },
  564. { "tx_late_collision" },
  565. { "tx_fifo_errors" },
  566. { "tx_carrier_errors" },
  567. { "tx_excess_deferral" },
  568. { "tx_retry_error" },
  569. { "rx_frame_error" },
  570. { "rx_extra_byte" },
  571. { "rx_late_collision" },
  572. { "rx_runt" },
  573. { "rx_frame_too_long" },
  574. { "rx_over_errors" },
  575. { "rx_crc_errors" },
  576. { "rx_frame_align_error" },
  577. { "rx_length_error" },
  578. { "rx_unicast" },
  579. { "rx_multicast" },
  580. { "rx_broadcast" },
  581. { "rx_packets" },
  582. { "rx_errors_total" },
  583. { "tx_errors_total" },
  584. /* version 2 stats */
  585. { "tx_deferral" },
  586. { "tx_packets" },
  587. { "rx_bytes" },
  588. { "tx_pause" },
  589. { "rx_pause" },
  590. { "rx_drop_frame" },
  591. /* version 3 stats */
  592. { "tx_unicast" },
  593. { "tx_multicast" },
  594. { "tx_broadcast" }
  595. };
  596. struct nv_ethtool_stats {
  597. u64 tx_bytes;
  598. u64 tx_zero_rexmt;
  599. u64 tx_one_rexmt;
  600. u64 tx_many_rexmt;
  601. u64 tx_late_collision;
  602. u64 tx_fifo_errors;
  603. u64 tx_carrier_errors;
  604. u64 tx_excess_deferral;
  605. u64 tx_retry_error;
  606. u64 rx_frame_error;
  607. u64 rx_extra_byte;
  608. u64 rx_late_collision;
  609. u64 rx_runt;
  610. u64 rx_frame_too_long;
  611. u64 rx_over_errors;
  612. u64 rx_crc_errors;
  613. u64 rx_frame_align_error;
  614. u64 rx_length_error;
  615. u64 rx_unicast;
  616. u64 rx_multicast;
  617. u64 rx_broadcast;
  618. u64 rx_packets;
  619. u64 rx_errors_total;
  620. u64 tx_errors_total;
  621. /* version 2 stats */
  622. u64 tx_deferral;
  623. u64 tx_packets;
  624. u64 rx_bytes;
  625. u64 tx_pause;
  626. u64 rx_pause;
  627. u64 rx_drop_frame;
  628. /* version 3 stats */
  629. u64 tx_unicast;
  630. u64 tx_multicast;
  631. u64 tx_broadcast;
  632. };
  633. #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
  634. #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
  635. #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
  636. /* diagnostics */
  637. #define NV_TEST_COUNT_BASE 3
  638. #define NV_TEST_COUNT_EXTENDED 4
  639. static const struct nv_ethtool_str nv_etests_str[] = {
  640. { "link (online/offline)" },
  641. { "register (offline) " },
  642. { "interrupt (offline) " },
  643. { "loopback (offline) " }
  644. };
  645. struct register_test {
  646. __u32 reg;
  647. __u32 mask;
  648. };
  649. static const struct register_test nv_registers_test[] = {
  650. { NvRegUnknownSetupReg6, 0x01 },
  651. { NvRegMisc1, 0x03c },
  652. { NvRegOffloadConfig, 0x03ff },
  653. { NvRegMulticastAddrA, 0xffffffff },
  654. { NvRegTxWatermark, 0x0ff },
  655. { NvRegWakeUpFlags, 0x07777 },
  656. { 0, 0 }
  657. };
  658. struct nv_skb_map {
  659. struct sk_buff *skb;
  660. dma_addr_t dma;
  661. unsigned int dma_len:31;
  662. unsigned int dma_single:1;
  663. struct ring_desc_ex *first_tx_desc;
  664. struct nv_skb_map *next_tx_ctx;
  665. };
  666. /*
  667. * SMP locking:
  668. * All hardware access under netdev_priv(dev)->lock, except the performance
  669. * critical parts:
  670. * - rx is (pseudo-) lockless: it relies on the single-threading provided
  671. * by the arch code for interrupts.
  672. * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
  673. * needs netdev_priv(dev)->lock :-(
  674. * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
  675. */
  676. /* in dev: base, irq */
  677. struct fe_priv {
  678. spinlock_t lock;
  679. struct net_device *dev;
  680. struct napi_struct napi;
  681. /* General data:
  682. * Locking: spin_lock(&np->lock); */
  683. struct nv_ethtool_stats estats;
  684. int in_shutdown;
  685. u32 linkspeed;
  686. int duplex;
  687. int autoneg;
  688. int fixed_mode;
  689. int phyaddr;
  690. int wolenabled;
  691. unsigned int phy_oui;
  692. unsigned int phy_model;
  693. unsigned int phy_rev;
  694. u16 gigabit;
  695. int intr_test;
  696. int recover_error;
  697. int quiet_count;
  698. /* General data: RO fields */
  699. dma_addr_t ring_addr;
  700. struct pci_dev *pci_dev;
  701. u32 orig_mac[2];
  702. u32 events;
  703. u32 irqmask;
  704. u32 desc_ver;
  705. u32 txrxctl_bits;
  706. u32 vlanctl_bits;
  707. u32 driver_data;
  708. u32 device_id;
  709. u32 register_size;
  710. u32 mac_in_use;
  711. int mgmt_version;
  712. int mgmt_sema;
  713. void __iomem *base;
  714. /* rx specific fields.
  715. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  716. */
  717. union ring_type get_rx, put_rx, first_rx, last_rx;
  718. struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
  719. struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
  720. struct nv_skb_map *rx_skb;
  721. union ring_type rx_ring;
  722. unsigned int rx_buf_sz;
  723. unsigned int pkt_limit;
  724. struct timer_list oom_kick;
  725. struct timer_list nic_poll;
  726. struct timer_list stats_poll;
  727. u32 nic_poll_irq;
  728. int rx_ring_size;
  729. /* media detection workaround.
  730. * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
  731. */
  732. int need_linktimer;
  733. unsigned long link_timeout;
  734. /*
  735. * tx specific fields.
  736. */
  737. union ring_type get_tx, put_tx, first_tx, last_tx;
  738. struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
  739. struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
  740. struct nv_skb_map *tx_skb;
  741. union ring_type tx_ring;
  742. u32 tx_flags;
  743. int tx_ring_size;
  744. int tx_limit;
  745. u32 tx_pkts_in_progress;
  746. struct nv_skb_map *tx_change_owner;
  747. struct nv_skb_map *tx_end_flip;
  748. int tx_stop;
  749. /* msi/msi-x fields */
  750. u32 msi_flags;
  751. struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
  752. /* flow control */
  753. u32 pause_flags;
  754. /* power saved state */
  755. u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
  756. /* for different msi-x irq type */
  757. char name_rx[IFNAMSIZ + 3]; /* -rx */
  758. char name_tx[IFNAMSIZ + 3]; /* -tx */
  759. char name_other[IFNAMSIZ + 6]; /* -other */
  760. };
  761. /*
  762. * Maximum number of loops until we assume that a bit in the irq mask
  763. * is stuck. Overridable with module param.
  764. */
  765. static int max_interrupt_work = 4;
  766. /*
  767. * Optimization can be either throuput mode or cpu mode
  768. *
  769. * Throughput Mode: Every tx and rx packet will generate an interrupt.
  770. * CPU Mode: Interrupts are controlled by a timer.
  771. */
  772. enum {
  773. NV_OPTIMIZATION_MODE_THROUGHPUT,
  774. NV_OPTIMIZATION_MODE_CPU,
  775. NV_OPTIMIZATION_MODE_DYNAMIC
  776. };
  777. static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
  778. /*
  779. * Poll interval for timer irq
  780. *
  781. * This interval determines how frequent an interrupt is generated.
  782. * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
  783. * Min = 0, and Max = 65535
  784. */
  785. static int poll_interval = -1;
  786. /*
  787. * MSI interrupts
  788. */
  789. enum {
  790. NV_MSI_INT_DISABLED,
  791. NV_MSI_INT_ENABLED
  792. };
  793. static int msi = NV_MSI_INT_ENABLED;
  794. /*
  795. * MSIX interrupts
  796. */
  797. enum {
  798. NV_MSIX_INT_DISABLED,
  799. NV_MSIX_INT_ENABLED
  800. };
  801. static int msix = NV_MSIX_INT_ENABLED;
  802. /*
  803. * DMA 64bit
  804. */
  805. enum {
  806. NV_DMA_64BIT_DISABLED,
  807. NV_DMA_64BIT_ENABLED
  808. };
  809. static int dma_64bit = NV_DMA_64BIT_ENABLED;
  810. /*
  811. * Crossover Detection
  812. * Realtek 8201 phy + some OEM boards do not work properly.
  813. */
  814. enum {
  815. NV_CROSSOVER_DETECTION_DISABLED,
  816. NV_CROSSOVER_DETECTION_ENABLED
  817. };
  818. static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
  819. /*
  820. * Power down phy when interface is down (persists through reboot;
  821. * older Linux and other OSes may not power it up again)
  822. */
  823. static int phy_power_down;
  824. static inline struct fe_priv *get_nvpriv(struct net_device *dev)
  825. {
  826. return netdev_priv(dev);
  827. }
  828. static inline u8 __iomem *get_hwbase(struct net_device *dev)
  829. {
  830. return ((struct fe_priv *)netdev_priv(dev))->base;
  831. }
  832. static inline void pci_push(u8 __iomem *base)
  833. {
  834. /* force out pending posted writes */
  835. readl(base);
  836. }
  837. static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
  838. {
  839. return le32_to_cpu(prd->flaglen)
  840. & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
  841. }
  842. static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
  843. {
  844. return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
  845. }
  846. static bool nv_optimized(struct fe_priv *np)
  847. {
  848. if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
  849. return false;
  850. return true;
  851. }
  852. static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
  853. int delay, int delaymax)
  854. {
  855. u8 __iomem *base = get_hwbase(dev);
  856. pci_push(base);
  857. do {
  858. udelay(delay);
  859. delaymax -= delay;
  860. if (delaymax < 0)
  861. return 1;
  862. } while ((readl(base + offset) & mask) != target);
  863. return 0;
  864. }
  865. #define NV_SETUP_RX_RING 0x01
  866. #define NV_SETUP_TX_RING 0x02
  867. static inline u32 dma_low(dma_addr_t addr)
  868. {
  869. return addr;
  870. }
  871. static inline u32 dma_high(dma_addr_t addr)
  872. {
  873. return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
  874. }
  875. static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
  876. {
  877. struct fe_priv *np = get_nvpriv(dev);
  878. u8 __iomem *base = get_hwbase(dev);
  879. if (!nv_optimized(np)) {
  880. if (rxtx_flags & NV_SETUP_RX_RING)
  881. writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
  882. if (rxtx_flags & NV_SETUP_TX_RING)
  883. writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
  884. } else {
  885. if (rxtx_flags & NV_SETUP_RX_RING) {
  886. writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
  887. writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
  888. }
  889. if (rxtx_flags & NV_SETUP_TX_RING) {
  890. writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
  891. writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
  892. }
  893. }
  894. }
  895. static void free_rings(struct net_device *dev)
  896. {
  897. struct fe_priv *np = get_nvpriv(dev);
  898. if (!nv_optimized(np)) {
  899. if (np->rx_ring.orig)
  900. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  901. np->rx_ring.orig, np->ring_addr);
  902. } else {
  903. if (np->rx_ring.ex)
  904. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  905. np->rx_ring.ex, np->ring_addr);
  906. }
  907. kfree(np->rx_skb);
  908. kfree(np->tx_skb);
  909. }
  910. static int using_multi_irqs(struct net_device *dev)
  911. {
  912. struct fe_priv *np = get_nvpriv(dev);
  913. if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
  914. ((np->msi_flags & NV_MSI_X_ENABLED) &&
  915. ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
  916. return 0;
  917. else
  918. return 1;
  919. }
  920. static void nv_txrx_gate(struct net_device *dev, bool gate)
  921. {
  922. struct fe_priv *np = get_nvpriv(dev);
  923. u8 __iomem *base = get_hwbase(dev);
  924. u32 powerstate;
  925. if (!np->mac_in_use &&
  926. (np->driver_data & DEV_HAS_POWER_CNTRL)) {
  927. powerstate = readl(base + NvRegPowerState2);
  928. if (gate)
  929. powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
  930. else
  931. powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
  932. writel(powerstate, base + NvRegPowerState2);
  933. }
  934. }
  935. static void nv_enable_irq(struct net_device *dev)
  936. {
  937. struct fe_priv *np = get_nvpriv(dev);
  938. if (!using_multi_irqs(dev)) {
  939. if (np->msi_flags & NV_MSI_X_ENABLED)
  940. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  941. else
  942. enable_irq(np->pci_dev->irq);
  943. } else {
  944. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  945. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  946. enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  947. }
  948. }
  949. static void nv_disable_irq(struct net_device *dev)
  950. {
  951. struct fe_priv *np = get_nvpriv(dev);
  952. if (!using_multi_irqs(dev)) {
  953. if (np->msi_flags & NV_MSI_X_ENABLED)
  954. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  955. else
  956. disable_irq(np->pci_dev->irq);
  957. } else {
  958. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  959. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  960. disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  961. }
  962. }
  963. /* In MSIX mode, a write to irqmask behaves as XOR */
  964. static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
  965. {
  966. u8 __iomem *base = get_hwbase(dev);
  967. writel(mask, base + NvRegIrqMask);
  968. }
  969. static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
  970. {
  971. struct fe_priv *np = get_nvpriv(dev);
  972. u8 __iomem *base = get_hwbase(dev);
  973. if (np->msi_flags & NV_MSI_X_ENABLED) {
  974. writel(mask, base + NvRegIrqMask);
  975. } else {
  976. if (np->msi_flags & NV_MSI_ENABLED)
  977. writel(0, base + NvRegMSIIrqMask);
  978. writel(0, base + NvRegIrqMask);
  979. }
  980. }
  981. static void nv_napi_enable(struct net_device *dev)
  982. {
  983. struct fe_priv *np = get_nvpriv(dev);
  984. napi_enable(&np->napi);
  985. }
  986. static void nv_napi_disable(struct net_device *dev)
  987. {
  988. struct fe_priv *np = get_nvpriv(dev);
  989. napi_disable(&np->napi);
  990. }
  991. #define MII_READ (-1)
  992. /* mii_rw: read/write a register on the PHY.
  993. *
  994. * Caller must guarantee serialization
  995. */
  996. static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
  997. {
  998. u8 __iomem *base = get_hwbase(dev);
  999. u32 reg;
  1000. int retval;
  1001. writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
  1002. reg = readl(base + NvRegMIIControl);
  1003. if (reg & NVREG_MIICTL_INUSE) {
  1004. writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
  1005. udelay(NV_MIIBUSY_DELAY);
  1006. }
  1007. reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
  1008. if (value != MII_READ) {
  1009. writel(value, base + NvRegMIIData);
  1010. reg |= NVREG_MIICTL_WRITE;
  1011. }
  1012. writel(reg, base + NvRegMIIControl);
  1013. if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
  1014. NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
  1015. retval = -1;
  1016. } else if (value != MII_READ) {
  1017. /* it was a write operation - fewer failures are detectable */
  1018. retval = 0;
  1019. } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
  1020. retval = -1;
  1021. } else {
  1022. retval = readl(base + NvRegMIIData);
  1023. }
  1024. return retval;
  1025. }
  1026. static int phy_reset(struct net_device *dev, u32 bmcr_setup)
  1027. {
  1028. struct fe_priv *np = netdev_priv(dev);
  1029. u32 miicontrol;
  1030. unsigned int tries = 0;
  1031. miicontrol = BMCR_RESET | bmcr_setup;
  1032. if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
  1033. return -1;
  1034. /* wait for 500ms */
  1035. msleep(500);
  1036. /* must wait till reset is deasserted */
  1037. while (miicontrol & BMCR_RESET) {
  1038. usleep_range(10000, 20000);
  1039. miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1040. /* FIXME: 100 tries seem excessive */
  1041. if (tries++ > 100)
  1042. return -1;
  1043. }
  1044. return 0;
  1045. }
  1046. static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
  1047. {
  1048. static const struct {
  1049. int reg;
  1050. int init;
  1051. } ri[] = {
  1052. { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
  1053. { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
  1054. { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
  1055. { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
  1056. { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
  1057. { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
  1058. { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
  1059. };
  1060. int i;
  1061. for (i = 0; i < ARRAY_SIZE(ri); i++) {
  1062. if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
  1063. return PHY_ERROR;
  1064. }
  1065. return 0;
  1066. }
  1067. static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
  1068. {
  1069. u32 reg;
  1070. u8 __iomem *base = get_hwbase(dev);
  1071. u32 powerstate = readl(base + NvRegPowerState2);
  1072. /* need to perform hw phy reset */
  1073. powerstate |= NVREG_POWERSTATE2_PHY_RESET;
  1074. writel(powerstate, base + NvRegPowerState2);
  1075. msleep(25);
  1076. powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
  1077. writel(powerstate, base + NvRegPowerState2);
  1078. msleep(25);
  1079. reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
  1080. reg |= PHY_REALTEK_INIT9;
  1081. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
  1082. return PHY_ERROR;
  1083. if (mii_rw(dev, np->phyaddr,
  1084. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
  1085. return PHY_ERROR;
  1086. reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
  1087. if (!(reg & PHY_REALTEK_INIT11)) {
  1088. reg |= PHY_REALTEK_INIT11;
  1089. if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
  1090. return PHY_ERROR;
  1091. }
  1092. if (mii_rw(dev, np->phyaddr,
  1093. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
  1094. return PHY_ERROR;
  1095. return 0;
  1096. }
  1097. static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
  1098. {
  1099. u32 phy_reserved;
  1100. if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
  1101. phy_reserved = mii_rw(dev, np->phyaddr,
  1102. PHY_REALTEK_INIT_REG6, MII_READ);
  1103. phy_reserved |= PHY_REALTEK_INIT7;
  1104. if (mii_rw(dev, np->phyaddr,
  1105. PHY_REALTEK_INIT_REG6, phy_reserved))
  1106. return PHY_ERROR;
  1107. }
  1108. return 0;
  1109. }
  1110. static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
  1111. {
  1112. u32 phy_reserved;
  1113. if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
  1114. if (mii_rw(dev, np->phyaddr,
  1115. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
  1116. return PHY_ERROR;
  1117. phy_reserved = mii_rw(dev, np->phyaddr,
  1118. PHY_REALTEK_INIT_REG2, MII_READ);
  1119. phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
  1120. phy_reserved |= PHY_REALTEK_INIT3;
  1121. if (mii_rw(dev, np->phyaddr,
  1122. PHY_REALTEK_INIT_REG2, phy_reserved))
  1123. return PHY_ERROR;
  1124. if (mii_rw(dev, np->phyaddr,
  1125. PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
  1126. return PHY_ERROR;
  1127. }
  1128. return 0;
  1129. }
  1130. static int init_cicada(struct net_device *dev, struct fe_priv *np,
  1131. u32 phyinterface)
  1132. {
  1133. u32 phy_reserved;
  1134. if (phyinterface & PHY_RGMII) {
  1135. phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
  1136. phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
  1137. phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
  1138. if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
  1139. return PHY_ERROR;
  1140. phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1141. phy_reserved |= PHY_CICADA_INIT5;
  1142. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
  1143. return PHY_ERROR;
  1144. }
  1145. phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
  1146. phy_reserved |= PHY_CICADA_INIT6;
  1147. if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
  1148. return PHY_ERROR;
  1149. return 0;
  1150. }
  1151. static int init_vitesse(struct net_device *dev, struct fe_priv *np)
  1152. {
  1153. u32 phy_reserved;
  1154. if (mii_rw(dev, np->phyaddr,
  1155. PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
  1156. return PHY_ERROR;
  1157. if (mii_rw(dev, np->phyaddr,
  1158. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
  1159. return PHY_ERROR;
  1160. phy_reserved = mii_rw(dev, np->phyaddr,
  1161. PHY_VITESSE_INIT_REG4, MII_READ);
  1162. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
  1163. return PHY_ERROR;
  1164. phy_reserved = mii_rw(dev, np->phyaddr,
  1165. PHY_VITESSE_INIT_REG3, MII_READ);
  1166. phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
  1167. phy_reserved |= PHY_VITESSE_INIT3;
  1168. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
  1169. return PHY_ERROR;
  1170. if (mii_rw(dev, np->phyaddr,
  1171. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
  1172. return PHY_ERROR;
  1173. if (mii_rw(dev, np->phyaddr,
  1174. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
  1175. return PHY_ERROR;
  1176. phy_reserved = mii_rw(dev, np->phyaddr,
  1177. PHY_VITESSE_INIT_REG4, MII_READ);
  1178. phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
  1179. phy_reserved |= PHY_VITESSE_INIT3;
  1180. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
  1181. return PHY_ERROR;
  1182. phy_reserved = mii_rw(dev, np->phyaddr,
  1183. PHY_VITESSE_INIT_REG3, MII_READ);
  1184. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
  1185. return PHY_ERROR;
  1186. if (mii_rw(dev, np->phyaddr,
  1187. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
  1188. return PHY_ERROR;
  1189. if (mii_rw(dev, np->phyaddr,
  1190. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
  1191. return PHY_ERROR;
  1192. phy_reserved = mii_rw(dev, np->phyaddr,
  1193. PHY_VITESSE_INIT_REG4, MII_READ);
  1194. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
  1195. return PHY_ERROR;
  1196. phy_reserved = mii_rw(dev, np->phyaddr,
  1197. PHY_VITESSE_INIT_REG3, MII_READ);
  1198. phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
  1199. phy_reserved |= PHY_VITESSE_INIT8;
  1200. if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
  1201. return PHY_ERROR;
  1202. if (mii_rw(dev, np->phyaddr,
  1203. PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
  1204. return PHY_ERROR;
  1205. if (mii_rw(dev, np->phyaddr,
  1206. PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
  1207. return PHY_ERROR;
  1208. return 0;
  1209. }
  1210. static int phy_init(struct net_device *dev)
  1211. {
  1212. struct fe_priv *np = get_nvpriv(dev);
  1213. u8 __iomem *base = get_hwbase(dev);
  1214. u32 phyinterface;
  1215. u32 mii_status, mii_control, mii_control_1000, reg;
  1216. /* phy errata for E3016 phy */
  1217. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  1218. reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
  1219. reg &= ~PHY_MARVELL_E3016_INITMASK;
  1220. if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
  1221. netdev_info(dev, "%s: phy write to errata reg failed\n",
  1222. pci_name(np->pci_dev));
  1223. return PHY_ERROR;
  1224. }
  1225. }
  1226. if (np->phy_oui == PHY_OUI_REALTEK) {
  1227. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1228. np->phy_rev == PHY_REV_REALTEK_8211B) {
  1229. if (init_realtek_8211b(dev, np)) {
  1230. netdev_info(dev, "%s: phy init failed\n",
  1231. pci_name(np->pci_dev));
  1232. return PHY_ERROR;
  1233. }
  1234. } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1235. np->phy_rev == PHY_REV_REALTEK_8211C) {
  1236. if (init_realtek_8211c(dev, np)) {
  1237. netdev_info(dev, "%s: phy init failed\n",
  1238. pci_name(np->pci_dev));
  1239. return PHY_ERROR;
  1240. }
  1241. } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
  1242. if (init_realtek_8201(dev, np)) {
  1243. netdev_info(dev, "%s: phy init failed\n",
  1244. pci_name(np->pci_dev));
  1245. return PHY_ERROR;
  1246. }
  1247. }
  1248. }
  1249. /* set advertise register */
  1250. reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  1251. reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
  1252. ADVERTISE_100HALF | ADVERTISE_100FULL |
  1253. ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
  1254. if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
  1255. netdev_info(dev, "%s: phy write to advertise failed\n",
  1256. pci_name(np->pci_dev));
  1257. return PHY_ERROR;
  1258. }
  1259. /* get phy interface type */
  1260. phyinterface = readl(base + NvRegPhyInterface);
  1261. /* see if gigabit phy */
  1262. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  1263. if (mii_status & PHY_GIGABIT) {
  1264. np->gigabit = PHY_GIGABIT;
  1265. mii_control_1000 = mii_rw(dev, np->phyaddr,
  1266. MII_CTRL1000, MII_READ);
  1267. mii_control_1000 &= ~ADVERTISE_1000HALF;
  1268. if (phyinterface & PHY_RGMII)
  1269. mii_control_1000 |= ADVERTISE_1000FULL;
  1270. else
  1271. mii_control_1000 &= ~ADVERTISE_1000FULL;
  1272. if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
  1273. netdev_info(dev, "%s: phy init failed\n",
  1274. pci_name(np->pci_dev));
  1275. return PHY_ERROR;
  1276. }
  1277. } else
  1278. np->gigabit = 0;
  1279. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1280. mii_control |= BMCR_ANENABLE;
  1281. if (np->phy_oui == PHY_OUI_REALTEK &&
  1282. np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1283. np->phy_rev == PHY_REV_REALTEK_8211C) {
  1284. /* start autoneg since we already performed hw reset above */
  1285. mii_control |= BMCR_ANRESTART;
  1286. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
  1287. netdev_info(dev, "%s: phy init failed\n",
  1288. pci_name(np->pci_dev));
  1289. return PHY_ERROR;
  1290. }
  1291. } else {
  1292. /* reset the phy
  1293. * (certain phys need bmcr to be setup with reset)
  1294. */
  1295. if (phy_reset(dev, mii_control)) {
  1296. netdev_info(dev, "%s: phy reset failed\n",
  1297. pci_name(np->pci_dev));
  1298. return PHY_ERROR;
  1299. }
  1300. }
  1301. /* phy vendor specific configuration */
  1302. if ((np->phy_oui == PHY_OUI_CICADA)) {
  1303. if (init_cicada(dev, np, phyinterface)) {
  1304. netdev_info(dev, "%s: phy init failed\n",
  1305. pci_name(np->pci_dev));
  1306. return PHY_ERROR;
  1307. }
  1308. } else if (np->phy_oui == PHY_OUI_VITESSE) {
  1309. if (init_vitesse(dev, np)) {
  1310. netdev_info(dev, "%s: phy init failed\n",
  1311. pci_name(np->pci_dev));
  1312. return PHY_ERROR;
  1313. }
  1314. } else if (np->phy_oui == PHY_OUI_REALTEK) {
  1315. if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
  1316. np->phy_rev == PHY_REV_REALTEK_8211B) {
  1317. /* reset could have cleared these out, set them back */
  1318. if (init_realtek_8211b(dev, np)) {
  1319. netdev_info(dev, "%s: phy init failed\n",
  1320. pci_name(np->pci_dev));
  1321. return PHY_ERROR;
  1322. }
  1323. } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
  1324. if (init_realtek_8201(dev, np) ||
  1325. init_realtek_8201_cross(dev, np)) {
  1326. netdev_info(dev, "%s: phy init failed\n",
  1327. pci_name(np->pci_dev));
  1328. return PHY_ERROR;
  1329. }
  1330. }
  1331. }
  1332. /* some phys clear out pause advertisement on reset, set it back */
  1333. mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
  1334. /* restart auto negotiation, power down phy */
  1335. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  1336. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  1337. if (phy_power_down)
  1338. mii_control |= BMCR_PDOWN;
  1339. if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
  1340. return PHY_ERROR;
  1341. return 0;
  1342. }
  1343. static void nv_start_rx(struct net_device *dev)
  1344. {
  1345. struct fe_priv *np = netdev_priv(dev);
  1346. u8 __iomem *base = get_hwbase(dev);
  1347. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1348. /* Already running? Stop it. */
  1349. if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
  1350. rx_ctrl &= ~NVREG_RCVCTL_START;
  1351. writel(rx_ctrl, base + NvRegReceiverControl);
  1352. pci_push(base);
  1353. }
  1354. writel(np->linkspeed, base + NvRegLinkSpeed);
  1355. pci_push(base);
  1356. rx_ctrl |= NVREG_RCVCTL_START;
  1357. if (np->mac_in_use)
  1358. rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
  1359. writel(rx_ctrl, base + NvRegReceiverControl);
  1360. pci_push(base);
  1361. }
  1362. static void nv_stop_rx(struct net_device *dev)
  1363. {
  1364. struct fe_priv *np = netdev_priv(dev);
  1365. u8 __iomem *base = get_hwbase(dev);
  1366. u32 rx_ctrl = readl(base + NvRegReceiverControl);
  1367. if (!np->mac_in_use)
  1368. rx_ctrl &= ~NVREG_RCVCTL_START;
  1369. else
  1370. rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
  1371. writel(rx_ctrl, base + NvRegReceiverControl);
  1372. if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
  1373. NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
  1374. netdev_info(dev, "%s: ReceiverStatus remained busy\n",
  1375. __func__);
  1376. udelay(NV_RXSTOP_DELAY2);
  1377. if (!np->mac_in_use)
  1378. writel(0, base + NvRegLinkSpeed);
  1379. }
  1380. static void nv_start_tx(struct net_device *dev)
  1381. {
  1382. struct fe_priv *np = netdev_priv(dev);
  1383. u8 __iomem *base = get_hwbase(dev);
  1384. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1385. tx_ctrl |= NVREG_XMITCTL_START;
  1386. if (np->mac_in_use)
  1387. tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
  1388. writel(tx_ctrl, base + NvRegTransmitterControl);
  1389. pci_push(base);
  1390. }
  1391. static void nv_stop_tx(struct net_device *dev)
  1392. {
  1393. struct fe_priv *np = netdev_priv(dev);
  1394. u8 __iomem *base = get_hwbase(dev);
  1395. u32 tx_ctrl = readl(base + NvRegTransmitterControl);
  1396. if (!np->mac_in_use)
  1397. tx_ctrl &= ~NVREG_XMITCTL_START;
  1398. else
  1399. tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
  1400. writel(tx_ctrl, base + NvRegTransmitterControl);
  1401. if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
  1402. NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
  1403. netdev_info(dev, "%s: TransmitterStatus remained busy\n",
  1404. __func__);
  1405. udelay(NV_TXSTOP_DELAY2);
  1406. if (!np->mac_in_use)
  1407. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  1408. base + NvRegTransmitPoll);
  1409. }
  1410. static void nv_start_rxtx(struct net_device *dev)
  1411. {
  1412. nv_start_rx(dev);
  1413. nv_start_tx(dev);
  1414. }
  1415. static void nv_stop_rxtx(struct net_device *dev)
  1416. {
  1417. nv_stop_rx(dev);
  1418. nv_stop_tx(dev);
  1419. }
  1420. static void nv_txrx_reset(struct net_device *dev)
  1421. {
  1422. struct fe_priv *np = netdev_priv(dev);
  1423. u8 __iomem *base = get_hwbase(dev);
  1424. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1425. pci_push(base);
  1426. udelay(NV_TXRX_RESET_DELAY);
  1427. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1428. pci_push(base);
  1429. }
  1430. static void nv_mac_reset(struct net_device *dev)
  1431. {
  1432. struct fe_priv *np = netdev_priv(dev);
  1433. u8 __iomem *base = get_hwbase(dev);
  1434. u32 temp1, temp2, temp3;
  1435. writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
  1436. pci_push(base);
  1437. /* save registers since they will be cleared on reset */
  1438. temp1 = readl(base + NvRegMacAddrA);
  1439. temp2 = readl(base + NvRegMacAddrB);
  1440. temp3 = readl(base + NvRegTransmitPoll);
  1441. writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
  1442. pci_push(base);
  1443. udelay(NV_MAC_RESET_DELAY);
  1444. writel(0, base + NvRegMacReset);
  1445. pci_push(base);
  1446. udelay(NV_MAC_RESET_DELAY);
  1447. /* restore saved registers */
  1448. writel(temp1, base + NvRegMacAddrA);
  1449. writel(temp2, base + NvRegMacAddrB);
  1450. writel(temp3, base + NvRegTransmitPoll);
  1451. writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
  1452. pci_push(base);
  1453. }
  1454. static void nv_get_hw_stats(struct net_device *dev)
  1455. {
  1456. struct fe_priv *np = netdev_priv(dev);
  1457. u8 __iomem *base = get_hwbase(dev);
  1458. np->estats.tx_bytes += readl(base + NvRegTxCnt);
  1459. np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
  1460. np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
  1461. np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
  1462. np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
  1463. np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
  1464. np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
  1465. np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
  1466. np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
  1467. np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
  1468. np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
  1469. np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
  1470. np->estats.rx_runt += readl(base + NvRegRxRunt);
  1471. np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
  1472. np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
  1473. np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
  1474. np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
  1475. np->estats.rx_length_error += readl(base + NvRegRxLenErr);
  1476. np->estats.rx_unicast += readl(base + NvRegRxUnicast);
  1477. np->estats.rx_multicast += readl(base + NvRegRxMulticast);
  1478. np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
  1479. np->estats.rx_packets =
  1480. np->estats.rx_unicast +
  1481. np->estats.rx_multicast +
  1482. np->estats.rx_broadcast;
  1483. np->estats.rx_errors_total =
  1484. np->estats.rx_crc_errors +
  1485. np->estats.rx_over_errors +
  1486. np->estats.rx_frame_error +
  1487. (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
  1488. np->estats.rx_late_collision +
  1489. np->estats.rx_runt +
  1490. np->estats.rx_frame_too_long;
  1491. np->estats.tx_errors_total =
  1492. np->estats.tx_late_collision +
  1493. np->estats.tx_fifo_errors +
  1494. np->estats.tx_carrier_errors +
  1495. np->estats.tx_excess_deferral +
  1496. np->estats.tx_retry_error;
  1497. if (np->driver_data & DEV_HAS_STATISTICS_V2) {
  1498. np->estats.tx_deferral += readl(base + NvRegTxDef);
  1499. np->estats.tx_packets += readl(base + NvRegTxFrame);
  1500. np->estats.rx_bytes += readl(base + NvRegRxCnt);
  1501. np->estats.tx_pause += readl(base + NvRegTxPause);
  1502. np->estats.rx_pause += readl(base + NvRegRxPause);
  1503. np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
  1504. }
  1505. if (np->driver_data & DEV_HAS_STATISTICS_V3) {
  1506. np->estats.tx_unicast += readl(base + NvRegTxUnicast);
  1507. np->estats.tx_multicast += readl(base + NvRegTxMulticast);
  1508. np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
  1509. }
  1510. }
  1511. /*
  1512. * nv_get_stats: dev->get_stats function
  1513. * Get latest stats value from the nic.
  1514. * Called with read_lock(&dev_base_lock) held for read -
  1515. * only synchronized against unregister_netdevice.
  1516. */
  1517. static struct net_device_stats *nv_get_stats(struct net_device *dev)
  1518. {
  1519. struct fe_priv *np = netdev_priv(dev);
  1520. /* If the nic supports hw counters then retrieve latest values */
  1521. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
  1522. nv_get_hw_stats(dev);
  1523. /* copy to net_device stats */
  1524. dev->stats.tx_bytes = np->estats.tx_bytes;
  1525. dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
  1526. dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
  1527. dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
  1528. dev->stats.rx_over_errors = np->estats.rx_over_errors;
  1529. dev->stats.rx_errors = np->estats.rx_errors_total;
  1530. dev->stats.tx_errors = np->estats.tx_errors_total;
  1531. }
  1532. return &dev->stats;
  1533. }
  1534. /*
  1535. * nv_alloc_rx: fill rx ring entries.
  1536. * Return 1 if the allocations for the skbs failed and the
  1537. * rx engine is without Available descriptors
  1538. */
  1539. static int nv_alloc_rx(struct net_device *dev)
  1540. {
  1541. struct fe_priv *np = netdev_priv(dev);
  1542. struct ring_desc *less_rx;
  1543. less_rx = np->get_rx.orig;
  1544. if (less_rx-- == np->first_rx.orig)
  1545. less_rx = np->last_rx.orig;
  1546. while (np->put_rx.orig != less_rx) {
  1547. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1548. if (skb) {
  1549. np->put_rx_ctx->skb = skb;
  1550. np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
  1551. skb->data,
  1552. skb_tailroom(skb),
  1553. PCI_DMA_FROMDEVICE);
  1554. np->put_rx_ctx->dma_len = skb_tailroom(skb);
  1555. np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
  1556. wmb();
  1557. np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
  1558. if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
  1559. np->put_rx.orig = np->first_rx.orig;
  1560. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1561. np->put_rx_ctx = np->first_rx_ctx;
  1562. } else
  1563. return 1;
  1564. }
  1565. return 0;
  1566. }
  1567. static int nv_alloc_rx_optimized(struct net_device *dev)
  1568. {
  1569. struct fe_priv *np = netdev_priv(dev);
  1570. struct ring_desc_ex *less_rx;
  1571. less_rx = np->get_rx.ex;
  1572. if (less_rx-- == np->first_rx.ex)
  1573. less_rx = np->last_rx.ex;
  1574. while (np->put_rx.ex != less_rx) {
  1575. struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
  1576. if (skb) {
  1577. np->put_rx_ctx->skb = skb;
  1578. np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
  1579. skb->data,
  1580. skb_tailroom(skb),
  1581. PCI_DMA_FROMDEVICE);
  1582. np->put_rx_ctx->dma_len = skb_tailroom(skb);
  1583. np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
  1584. np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
  1585. wmb();
  1586. np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
  1587. if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
  1588. np->put_rx.ex = np->first_rx.ex;
  1589. if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
  1590. np->put_rx_ctx = np->first_rx_ctx;
  1591. } else
  1592. return 1;
  1593. }
  1594. return 0;
  1595. }
  1596. /* If rx bufs are exhausted called after 50ms to attempt to refresh */
  1597. static void nv_do_rx_refill(unsigned long data)
  1598. {
  1599. struct net_device *dev = (struct net_device *) data;
  1600. struct fe_priv *np = netdev_priv(dev);
  1601. /* Just reschedule NAPI rx processing */
  1602. napi_schedule(&np->napi);
  1603. }
  1604. static void nv_init_rx(struct net_device *dev)
  1605. {
  1606. struct fe_priv *np = netdev_priv(dev);
  1607. int i;
  1608. np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
  1609. if (!nv_optimized(np))
  1610. np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
  1611. else
  1612. np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
  1613. np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
  1614. np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
  1615. for (i = 0; i < np->rx_ring_size; i++) {
  1616. if (!nv_optimized(np)) {
  1617. np->rx_ring.orig[i].flaglen = 0;
  1618. np->rx_ring.orig[i].buf = 0;
  1619. } else {
  1620. np->rx_ring.ex[i].flaglen = 0;
  1621. np->rx_ring.ex[i].txvlan = 0;
  1622. np->rx_ring.ex[i].bufhigh = 0;
  1623. np->rx_ring.ex[i].buflow = 0;
  1624. }
  1625. np->rx_skb[i].skb = NULL;
  1626. np->rx_skb[i].dma = 0;
  1627. }
  1628. }
  1629. static void nv_init_tx(struct net_device *dev)
  1630. {
  1631. struct fe_priv *np = netdev_priv(dev);
  1632. int i;
  1633. np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
  1634. if (!nv_optimized(np))
  1635. np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
  1636. else
  1637. np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
  1638. np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
  1639. np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
  1640. np->tx_pkts_in_progress = 0;
  1641. np->tx_change_owner = NULL;
  1642. np->tx_end_flip = NULL;
  1643. np->tx_stop = 0;
  1644. for (i = 0; i < np->tx_ring_size; i++) {
  1645. if (!nv_optimized(np)) {
  1646. np->tx_ring.orig[i].flaglen = 0;
  1647. np->tx_ring.orig[i].buf = 0;
  1648. } else {
  1649. np->tx_ring.ex[i].flaglen = 0;
  1650. np->tx_ring.ex[i].txvlan = 0;
  1651. np->tx_ring.ex[i].bufhigh = 0;
  1652. np->tx_ring.ex[i].buflow = 0;
  1653. }
  1654. np->tx_skb[i].skb = NULL;
  1655. np->tx_skb[i].dma = 0;
  1656. np->tx_skb[i].dma_len = 0;
  1657. np->tx_skb[i].dma_single = 0;
  1658. np->tx_skb[i].first_tx_desc = NULL;
  1659. np->tx_skb[i].next_tx_ctx = NULL;
  1660. }
  1661. }
  1662. static int nv_init_ring(struct net_device *dev)
  1663. {
  1664. struct fe_priv *np = netdev_priv(dev);
  1665. nv_init_tx(dev);
  1666. nv_init_rx(dev);
  1667. if (!nv_optimized(np))
  1668. return nv_alloc_rx(dev);
  1669. else
  1670. return nv_alloc_rx_optimized(dev);
  1671. }
  1672. static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
  1673. {
  1674. if (tx_skb->dma) {
  1675. if (tx_skb->dma_single)
  1676. pci_unmap_single(np->pci_dev, tx_skb->dma,
  1677. tx_skb->dma_len,
  1678. PCI_DMA_TODEVICE);
  1679. else
  1680. pci_unmap_page(np->pci_dev, tx_skb->dma,
  1681. tx_skb->dma_len,
  1682. PCI_DMA_TODEVICE);
  1683. tx_skb->dma = 0;
  1684. }
  1685. }
  1686. static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
  1687. {
  1688. nv_unmap_txskb(np, tx_skb);
  1689. if (tx_skb->skb) {
  1690. dev_kfree_skb_any(tx_skb->skb);
  1691. tx_skb->skb = NULL;
  1692. return 1;
  1693. }
  1694. return 0;
  1695. }
  1696. static void nv_drain_tx(struct net_device *dev)
  1697. {
  1698. struct fe_priv *np = netdev_priv(dev);
  1699. unsigned int i;
  1700. for (i = 0; i < np->tx_ring_size; i++) {
  1701. if (!nv_optimized(np)) {
  1702. np->tx_ring.orig[i].flaglen = 0;
  1703. np->tx_ring.orig[i].buf = 0;
  1704. } else {
  1705. np->tx_ring.ex[i].flaglen = 0;
  1706. np->tx_ring.ex[i].txvlan = 0;
  1707. np->tx_ring.ex[i].bufhigh = 0;
  1708. np->tx_ring.ex[i].buflow = 0;
  1709. }
  1710. if (nv_release_txskb(np, &np->tx_skb[i]))
  1711. dev->stats.tx_dropped++;
  1712. np->tx_skb[i].dma = 0;
  1713. np->tx_skb[i].dma_len = 0;
  1714. np->tx_skb[i].dma_single = 0;
  1715. np->tx_skb[i].first_tx_desc = NULL;
  1716. np->tx_skb[i].next_tx_ctx = NULL;
  1717. }
  1718. np->tx_pkts_in_progress = 0;
  1719. np->tx_change_owner = NULL;
  1720. np->tx_end_flip = NULL;
  1721. }
  1722. static void nv_drain_rx(struct net_device *dev)
  1723. {
  1724. struct fe_priv *np = netdev_priv(dev);
  1725. int i;
  1726. for (i = 0; i < np->rx_ring_size; i++) {
  1727. if (!nv_optimized(np)) {
  1728. np->rx_ring.orig[i].flaglen = 0;
  1729. np->rx_ring.orig[i].buf = 0;
  1730. } else {
  1731. np->rx_ring.ex[i].flaglen = 0;
  1732. np->rx_ring.ex[i].txvlan = 0;
  1733. np->rx_ring.ex[i].bufhigh = 0;
  1734. np->rx_ring.ex[i].buflow = 0;
  1735. }
  1736. wmb();
  1737. if (np->rx_skb[i].skb) {
  1738. pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
  1739. (skb_end_pointer(np->rx_skb[i].skb) -
  1740. np->rx_skb[i].skb->data),
  1741. PCI_DMA_FROMDEVICE);
  1742. dev_kfree_skb(np->rx_skb[i].skb);
  1743. np->rx_skb[i].skb = NULL;
  1744. }
  1745. }
  1746. }
  1747. static void nv_drain_rxtx(struct net_device *dev)
  1748. {
  1749. nv_drain_tx(dev);
  1750. nv_drain_rx(dev);
  1751. }
  1752. static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
  1753. {
  1754. return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
  1755. }
  1756. static void nv_legacybackoff_reseed(struct net_device *dev)
  1757. {
  1758. u8 __iomem *base = get_hwbase(dev);
  1759. u32 reg;
  1760. u32 low;
  1761. int tx_status = 0;
  1762. reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
  1763. get_random_bytes(&low, sizeof(low));
  1764. reg |= low & NVREG_SLOTTIME_MASK;
  1765. /* Need to stop tx before change takes effect.
  1766. * Caller has already gained np->lock.
  1767. */
  1768. tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
  1769. if (tx_status)
  1770. nv_stop_tx(dev);
  1771. nv_stop_rx(dev);
  1772. writel(reg, base + NvRegSlotTime);
  1773. if (tx_status)
  1774. nv_start_tx(dev);
  1775. nv_start_rx(dev);
  1776. }
  1777. /* Gear Backoff Seeds */
  1778. #define BACKOFF_SEEDSET_ROWS 8
  1779. #define BACKOFF_SEEDSET_LFSRS 15
  1780. /* Known Good seed sets */
  1781. static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
  1782. {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
  1783. {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
  1784. {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
  1785. {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
  1786. {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
  1787. {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
  1788. {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
  1789. {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
  1790. static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
  1791. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1792. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1793. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
  1794. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1795. {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
  1796. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1797. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
  1798. {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
  1799. static void nv_gear_backoff_reseed(struct net_device *dev)
  1800. {
  1801. u8 __iomem *base = get_hwbase(dev);
  1802. u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
  1803. u32 temp, seedset, combinedSeed;
  1804. int i;
  1805. /* Setup seed for free running LFSR */
  1806. /* We are going to read the time stamp counter 3 times
  1807. and swizzle bits around to increase randomness */
  1808. get_random_bytes(&miniseed1, sizeof(miniseed1));
  1809. miniseed1 &= 0x0fff;
  1810. if (miniseed1 == 0)
  1811. miniseed1 = 0xabc;
  1812. get_random_bytes(&miniseed2, sizeof(miniseed2));
  1813. miniseed2 &= 0x0fff;
  1814. if (miniseed2 == 0)
  1815. miniseed2 = 0xabc;
  1816. miniseed2_reversed =
  1817. ((miniseed2 & 0xF00) >> 8) |
  1818. (miniseed2 & 0x0F0) |
  1819. ((miniseed2 & 0x00F) << 8);
  1820. get_random_bytes(&miniseed3, sizeof(miniseed3));
  1821. miniseed3 &= 0x0fff;
  1822. if (miniseed3 == 0)
  1823. miniseed3 = 0xabc;
  1824. miniseed3_reversed =
  1825. ((miniseed3 & 0xF00) >> 8) |
  1826. (miniseed3 & 0x0F0) |
  1827. ((miniseed3 & 0x00F) << 8);
  1828. combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
  1829. (miniseed2 ^ miniseed3_reversed);
  1830. /* Seeds can not be zero */
  1831. if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
  1832. combinedSeed |= 0x08;
  1833. if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
  1834. combinedSeed |= 0x8000;
  1835. /* No need to disable tx here */
  1836. temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
  1837. temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
  1838. temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
  1839. writel(temp, base + NvRegBackOffControl);
  1840. /* Setup seeds for all gear LFSRs. */
  1841. get_random_bytes(&seedset, sizeof(seedset));
  1842. seedset = seedset % BACKOFF_SEEDSET_ROWS;
  1843. for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
  1844. temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
  1845. temp |= main_seedset[seedset][i-1] & 0x3ff;
  1846. temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
  1847. writel(temp, base + NvRegBackOffControl);
  1848. }
  1849. }
  1850. /*
  1851. * nv_start_xmit: dev->hard_start_xmit function
  1852. * Called with netif_tx_lock held.
  1853. */
  1854. static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1855. {
  1856. struct fe_priv *np = netdev_priv(dev);
  1857. u32 tx_flags = 0;
  1858. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  1859. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1860. unsigned int i;
  1861. u32 offset = 0;
  1862. u32 bcnt;
  1863. u32 size = skb_headlen(skb);
  1864. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1865. u32 empty_slots;
  1866. struct ring_desc *put_tx;
  1867. struct ring_desc *start_tx;
  1868. struct ring_desc *prev_tx;
  1869. struct nv_skb_map *prev_tx_ctx;
  1870. unsigned long flags;
  1871. /* add fragments to entries count */
  1872. for (i = 0; i < fragments; i++) {
  1873. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1874. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1875. }
  1876. spin_lock_irqsave(&np->lock, flags);
  1877. empty_slots = nv_get_empty_tx_slots(np);
  1878. if (unlikely(empty_slots <= entries)) {
  1879. netif_stop_queue(dev);
  1880. np->tx_stop = 1;
  1881. spin_unlock_irqrestore(&np->lock, flags);
  1882. return NETDEV_TX_BUSY;
  1883. }
  1884. spin_unlock_irqrestore(&np->lock, flags);
  1885. start_tx = put_tx = np->put_tx.orig;
  1886. /* setup the header buffer */
  1887. do {
  1888. prev_tx = put_tx;
  1889. prev_tx_ctx = np->put_tx_ctx;
  1890. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1891. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1892. PCI_DMA_TODEVICE);
  1893. np->put_tx_ctx->dma_len = bcnt;
  1894. np->put_tx_ctx->dma_single = 1;
  1895. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1896. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1897. tx_flags = np->tx_flags;
  1898. offset += bcnt;
  1899. size -= bcnt;
  1900. if (unlikely(put_tx++ == np->last_tx.orig))
  1901. put_tx = np->first_tx.orig;
  1902. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1903. np->put_tx_ctx = np->first_tx_ctx;
  1904. } while (size);
  1905. /* setup the fragments */
  1906. for (i = 0; i < fragments; i++) {
  1907. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  1908. u32 size = frag->size;
  1909. offset = 0;
  1910. do {
  1911. prev_tx = put_tx;
  1912. prev_tx_ctx = np->put_tx_ctx;
  1913. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1914. np->put_tx_ctx->dma = skb_frag_dma_map(
  1915. &np->pci_dev->dev,
  1916. frag, offset,
  1917. bcnt,
  1918. DMA_TO_DEVICE);
  1919. np->put_tx_ctx->dma_len = bcnt;
  1920. np->put_tx_ctx->dma_single = 0;
  1921. put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
  1922. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1923. offset += bcnt;
  1924. size -= bcnt;
  1925. if (unlikely(put_tx++ == np->last_tx.orig))
  1926. put_tx = np->first_tx.orig;
  1927. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  1928. np->put_tx_ctx = np->first_tx_ctx;
  1929. } while (size);
  1930. }
  1931. /* set last fragment flag */
  1932. prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
  1933. /* save skb in this slot's context area */
  1934. prev_tx_ctx->skb = skb;
  1935. if (skb_is_gso(skb))
  1936. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  1937. else
  1938. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  1939. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  1940. spin_lock_irqsave(&np->lock, flags);
  1941. /* set tx flags */
  1942. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  1943. np->put_tx.orig = put_tx;
  1944. spin_unlock_irqrestore(&np->lock, flags);
  1945. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  1946. return NETDEV_TX_OK;
  1947. }
  1948. static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
  1949. struct net_device *dev)
  1950. {
  1951. struct fe_priv *np = netdev_priv(dev);
  1952. u32 tx_flags = 0;
  1953. u32 tx_flags_extra;
  1954. unsigned int fragments = skb_shinfo(skb)->nr_frags;
  1955. unsigned int i;
  1956. u32 offset = 0;
  1957. u32 bcnt;
  1958. u32 size = skb_headlen(skb);
  1959. u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1960. u32 empty_slots;
  1961. struct ring_desc_ex *put_tx;
  1962. struct ring_desc_ex *start_tx;
  1963. struct ring_desc_ex *prev_tx;
  1964. struct nv_skb_map *prev_tx_ctx;
  1965. struct nv_skb_map *start_tx_ctx;
  1966. unsigned long flags;
  1967. /* add fragments to entries count */
  1968. for (i = 0; i < fragments; i++) {
  1969. entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
  1970. ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
  1971. }
  1972. spin_lock_irqsave(&np->lock, flags);
  1973. empty_slots = nv_get_empty_tx_slots(np);
  1974. if (unlikely(empty_slots <= entries)) {
  1975. netif_stop_queue(dev);
  1976. np->tx_stop = 1;
  1977. spin_unlock_irqrestore(&np->lock, flags);
  1978. return NETDEV_TX_BUSY;
  1979. }
  1980. spin_unlock_irqrestore(&np->lock, flags);
  1981. start_tx = put_tx = np->put_tx.ex;
  1982. start_tx_ctx = np->put_tx_ctx;
  1983. /* setup the header buffer */
  1984. do {
  1985. prev_tx = put_tx;
  1986. prev_tx_ctx = np->put_tx_ctx;
  1987. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  1988. np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
  1989. PCI_DMA_TODEVICE);
  1990. np->put_tx_ctx->dma_len = bcnt;
  1991. np->put_tx_ctx->dma_single = 1;
  1992. put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
  1993. put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
  1994. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  1995. tx_flags = NV_TX2_VALID;
  1996. offset += bcnt;
  1997. size -= bcnt;
  1998. if (unlikely(put_tx++ == np->last_tx.ex))
  1999. put_tx = np->first_tx.ex;
  2000. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  2001. np->put_tx_ctx = np->first_tx_ctx;
  2002. } while (size);
  2003. /* setup the fragments */
  2004. for (i = 0; i < fragments; i++) {
  2005. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  2006. u32 size = frag->size;
  2007. offset = 0;
  2008. do {
  2009. prev_tx = put_tx;
  2010. prev_tx_ctx = np->put_tx_ctx;
  2011. bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
  2012. np->put_tx_ctx->dma = skb_frag_dma_map(
  2013. &np->pci_dev->dev,
  2014. frag, offset,
  2015. bcnt,
  2016. DMA_TO_DEVICE);
  2017. np->put_tx_ctx->dma_len = bcnt;
  2018. np->put_tx_ctx->dma_single = 0;
  2019. put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
  2020. put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
  2021. put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
  2022. offset += bcnt;
  2023. size -= bcnt;
  2024. if (unlikely(put_tx++ == np->last_tx.ex))
  2025. put_tx = np->first_tx.ex;
  2026. if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
  2027. np->put_tx_ctx = np->first_tx_ctx;
  2028. } while (size);
  2029. }
  2030. /* set last fragment flag */
  2031. prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
  2032. /* save skb in this slot's context area */
  2033. prev_tx_ctx->skb = skb;
  2034. if (skb_is_gso(skb))
  2035. tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
  2036. else
  2037. tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
  2038. NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
  2039. /* vlan tag */
  2040. if (vlan_tx_tag_present(skb))
  2041. start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
  2042. vlan_tx_tag_get(skb));
  2043. else
  2044. start_tx->txvlan = 0;
  2045. spin_lock_irqsave(&np->lock, flags);
  2046. if (np->tx_limit) {
  2047. /* Limit the number of outstanding tx. Setup all fragments, but
  2048. * do not set the VALID bit on the first descriptor. Save a pointer
  2049. * to that descriptor and also for next skb_map element.
  2050. */
  2051. if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
  2052. if (!np->tx_change_owner)
  2053. np->tx_change_owner = start_tx_ctx;
  2054. /* remove VALID bit */
  2055. tx_flags &= ~NV_TX2_VALID;
  2056. start_tx_ctx->first_tx_desc = start_tx;
  2057. start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
  2058. np->tx_end_flip = np->put_tx_ctx;
  2059. } else {
  2060. np->tx_pkts_in_progress++;
  2061. }
  2062. }
  2063. /* set tx flags */
  2064. start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
  2065. np->put_tx.ex = put_tx;
  2066. spin_unlock_irqrestore(&np->lock, flags);
  2067. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2068. return NETDEV_TX_OK;
  2069. }
  2070. static inline void nv_tx_flip_ownership(struct net_device *dev)
  2071. {
  2072. struct fe_priv *np = netdev_priv(dev);
  2073. np->tx_pkts_in_progress--;
  2074. if (np->tx_change_owner) {
  2075. np->tx_change_owner->first_tx_desc->flaglen |=
  2076. cpu_to_le32(NV_TX2_VALID);
  2077. np->tx_pkts_in_progress++;
  2078. np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
  2079. if (np->tx_change_owner == np->tx_end_flip)
  2080. np->tx_change_owner = NULL;
  2081. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2082. }
  2083. }
  2084. /*
  2085. * nv_tx_done: check for completed packets, release the skbs.
  2086. *
  2087. * Caller must own np->lock.
  2088. */
  2089. static int nv_tx_done(struct net_device *dev, int limit)
  2090. {
  2091. struct fe_priv *np = netdev_priv(dev);
  2092. u32 flags;
  2093. int tx_work = 0;
  2094. struct ring_desc *orig_get_tx = np->get_tx.orig;
  2095. while ((np->get_tx.orig != np->put_tx.orig) &&
  2096. !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
  2097. (tx_work < limit)) {
  2098. nv_unmap_txskb(np, np->get_tx_ctx);
  2099. if (np->desc_ver == DESC_VER_1) {
  2100. if (flags & NV_TX_LASTPACKET) {
  2101. if (flags & NV_TX_ERROR) {
  2102. if (flags & NV_TX_UNDERFLOW)
  2103. dev->stats.tx_fifo_errors++;
  2104. if (flags & NV_TX_CARRIERLOST)
  2105. dev->stats.tx_carrier_errors++;
  2106. if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
  2107. nv_legacybackoff_reseed(dev);
  2108. dev->stats.tx_errors++;
  2109. } else {
  2110. dev->stats.tx_packets++;
  2111. dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
  2112. }
  2113. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2114. np->get_tx_ctx->skb = NULL;
  2115. tx_work++;
  2116. }
  2117. } else {
  2118. if (flags & NV_TX2_LASTPACKET) {
  2119. if (flags & NV_TX2_ERROR) {
  2120. if (flags & NV_TX2_UNDERFLOW)
  2121. dev->stats.tx_fifo_errors++;
  2122. if (flags & NV_TX2_CARRIERLOST)
  2123. dev->stats.tx_carrier_errors++;
  2124. if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
  2125. nv_legacybackoff_reseed(dev);
  2126. dev->stats.tx_errors++;
  2127. } else {
  2128. dev->stats.tx_packets++;
  2129. dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
  2130. }
  2131. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2132. np->get_tx_ctx->skb = NULL;
  2133. tx_work++;
  2134. }
  2135. }
  2136. if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
  2137. np->get_tx.orig = np->first_tx.orig;
  2138. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  2139. np->get_tx_ctx = np->first_tx_ctx;
  2140. }
  2141. if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
  2142. np->tx_stop = 0;
  2143. netif_wake_queue(dev);
  2144. }
  2145. return tx_work;
  2146. }
  2147. static int nv_tx_done_optimized(struct net_device *dev, int limit)
  2148. {
  2149. struct fe_priv *np = netdev_priv(dev);
  2150. u32 flags;
  2151. int tx_work = 0;
  2152. struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
  2153. while ((np->get_tx.ex != np->put_tx.ex) &&
  2154. !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
  2155. (tx_work < limit)) {
  2156. nv_unmap_txskb(np, np->get_tx_ctx);
  2157. if (flags & NV_TX2_LASTPACKET) {
  2158. if (!(flags & NV_TX2_ERROR))
  2159. dev->stats.tx_packets++;
  2160. else {
  2161. if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
  2162. if (np->driver_data & DEV_HAS_GEAR_MODE)
  2163. nv_gear_backoff_reseed(dev);
  2164. else
  2165. nv_legacybackoff_reseed(dev);
  2166. }
  2167. }
  2168. dev_kfree_skb_any(np->get_tx_ctx->skb);
  2169. np->get_tx_ctx->skb = NULL;
  2170. tx_work++;
  2171. if (np->tx_limit)
  2172. nv_tx_flip_ownership(dev);
  2173. }
  2174. if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
  2175. np->get_tx.ex = np->first_tx.ex;
  2176. if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
  2177. np->get_tx_ctx = np->first_tx_ctx;
  2178. }
  2179. if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
  2180. np->tx_stop = 0;
  2181. netif_wake_queue(dev);
  2182. }
  2183. return tx_work;
  2184. }
  2185. /*
  2186. * nv_tx_timeout: dev->tx_timeout function
  2187. * Called with netif_tx_lock held.
  2188. */
  2189. static void nv_tx_timeout(struct net_device *dev)
  2190. {
  2191. struct fe_priv *np = netdev_priv(dev);
  2192. u8 __iomem *base = get_hwbase(dev);
  2193. u32 status;
  2194. union ring_type put_tx;
  2195. int saved_tx_limit;
  2196. int i;
  2197. if (np->msi_flags & NV_MSI_X_ENABLED)
  2198. status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  2199. else
  2200. status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  2201. netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
  2202. netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
  2203. netdev_info(dev, "Dumping tx registers\n");
  2204. for (i = 0; i <= np->register_size; i += 32) {
  2205. netdev_info(dev,
  2206. "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  2207. i,
  2208. readl(base + i + 0), readl(base + i + 4),
  2209. readl(base + i + 8), readl(base + i + 12),
  2210. readl(base + i + 16), readl(base + i + 20),
  2211. readl(base + i + 24), readl(base + i + 28));
  2212. }
  2213. netdev_info(dev, "Dumping tx ring\n");
  2214. for (i = 0; i < np->tx_ring_size; i += 4) {
  2215. if (!nv_optimized(np)) {
  2216. netdev_info(dev,
  2217. "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
  2218. i,
  2219. le32_to_cpu(np->tx_ring.orig[i].buf),
  2220. le32_to_cpu(np->tx_ring.orig[i].flaglen),
  2221. le32_to_cpu(np->tx_ring.orig[i+1].buf),
  2222. le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
  2223. le32_to_cpu(np->tx_ring.orig[i+2].buf),
  2224. le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
  2225. le32_to_cpu(np->tx_ring.orig[i+3].buf),
  2226. le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
  2227. } else {
  2228. netdev_info(dev,
  2229. "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
  2230. i,
  2231. le32_to_cpu(np->tx_ring.ex[i].bufhigh),
  2232. le32_to_cpu(np->tx_ring.ex[i].buflow),
  2233. le32_to_cpu(np->tx_ring.ex[i].flaglen),
  2234. le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
  2235. le32_to_cpu(np->tx_ring.ex[i+1].buflow),
  2236. le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
  2237. le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
  2238. le32_to_cpu(np->tx_ring.ex[i+2].buflow),
  2239. le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
  2240. le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
  2241. le32_to_cpu(np->tx_ring.ex[i+3].buflow),
  2242. le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
  2243. }
  2244. }
  2245. spin_lock_irq(&np->lock);
  2246. /* 1) stop tx engine */
  2247. nv_stop_tx(dev);
  2248. /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
  2249. saved_tx_limit = np->tx_limit;
  2250. np->tx_limit = 0; /* prevent giving HW any limited pkts */
  2251. np->tx_stop = 0; /* prevent waking tx queue */
  2252. if (!nv_optimized(np))
  2253. nv_tx_done(dev, np->tx_ring_size);
  2254. else
  2255. nv_tx_done_optimized(dev, np->tx_ring_size);
  2256. /* save current HW position */
  2257. if (np->tx_change_owner)
  2258. put_tx.ex = np->tx_change_owner->first_tx_desc;
  2259. else
  2260. put_tx = np->put_tx;
  2261. /* 3) clear all tx state */
  2262. nv_drain_tx(dev);
  2263. nv_init_tx(dev);
  2264. /* 4) restore state to current HW position */
  2265. np->get_tx = np->put_tx = put_tx;
  2266. np->tx_limit = saved_tx_limit;
  2267. /* 5) restart tx engine */
  2268. nv_start_tx(dev);
  2269. netif_wake_queue(dev);
  2270. spin_unlock_irq(&np->lock);
  2271. }
  2272. /*
  2273. * Called when the nic notices a mismatch between the actual data len on the
  2274. * wire and the len indicated in the 802 header
  2275. */
  2276. static int nv_getlen(struct net_device *dev, void *packet, int datalen)
  2277. {
  2278. int hdrlen; /* length of the 802 header */
  2279. int protolen; /* length as stored in the proto field */
  2280. /* 1) calculate len according to header */
  2281. if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
  2282. protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
  2283. hdrlen = VLAN_HLEN;
  2284. } else {
  2285. protolen = ntohs(((struct ethhdr *)packet)->h_proto);
  2286. hdrlen = ETH_HLEN;
  2287. }
  2288. if (protolen > ETH_DATA_LEN)
  2289. return datalen; /* Value in proto field not a len, no checks possible */
  2290. protolen += hdrlen;
  2291. /* consistency checks: */
  2292. if (datalen > ETH_ZLEN) {
  2293. if (datalen >= protolen) {
  2294. /* more data on wire than in 802 header, trim of
  2295. * additional data.
  2296. */
  2297. return protolen;
  2298. } else {
  2299. /* less data on wire than mentioned in header.
  2300. * Discard the packet.
  2301. */
  2302. return -1;
  2303. }
  2304. } else {
  2305. /* short packet. Accept only if 802 values are also short */
  2306. if (protolen > ETH_ZLEN) {
  2307. return -1;
  2308. }
  2309. return datalen;
  2310. }
  2311. }
  2312. static int nv_rx_process(struct net_device *dev, int limit)
  2313. {
  2314. struct fe_priv *np = netdev_priv(dev);
  2315. u32 flags;
  2316. int rx_work = 0;
  2317. struct sk_buff *skb;
  2318. int len;
  2319. while ((np->get_rx.orig != np->put_rx.orig) &&
  2320. !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
  2321. (rx_work < limit)) {
  2322. /*
  2323. * the packet is for us - immediately tear down the pci mapping.
  2324. * TODO: check if a prefetch of the first cacheline improves
  2325. * the performance.
  2326. */
  2327. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2328. np->get_rx_ctx->dma_len,
  2329. PCI_DMA_FROMDEVICE);
  2330. skb = np->get_rx_ctx->skb;
  2331. np->get_rx_ctx->skb = NULL;
  2332. /* look at what we actually got: */
  2333. if (np->desc_ver == DESC_VER_1) {
  2334. if (likely(flags & NV_RX_DESCRIPTORVALID)) {
  2335. len = flags & LEN_MASK_V1;
  2336. if (unlikely(flags & NV_RX_ERROR)) {
  2337. if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
  2338. len = nv_getlen(dev, skb->data, len);
  2339. if (len < 0) {
  2340. dev->stats.rx_errors++;
  2341. dev_kfree_skb(skb);
  2342. goto next_pkt;
  2343. }
  2344. }
  2345. /* framing errors are soft errors */
  2346. else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
  2347. if (flags & NV_RX_SUBSTRACT1)
  2348. len--;
  2349. }
  2350. /* the rest are hard errors */
  2351. else {
  2352. if (flags & NV_RX_MISSEDFRAME)
  2353. dev->stats.rx_missed_errors++;
  2354. if (flags & NV_RX_CRCERR)
  2355. dev->stats.rx_crc_errors++;
  2356. if (flags & NV_RX_OVERFLOW)
  2357. dev->stats.rx_over_errors++;
  2358. dev->stats.rx_errors++;
  2359. dev_kfree_skb(skb);
  2360. goto next_pkt;
  2361. }
  2362. }
  2363. } else {
  2364. dev_kfree_skb(skb);
  2365. goto next_pkt;
  2366. }
  2367. } else {
  2368. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2369. len = flags & LEN_MASK_V2;
  2370. if (unlikely(flags & NV_RX2_ERROR)) {
  2371. if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
  2372. len = nv_getlen(dev, skb->data, len);
  2373. if (len < 0) {
  2374. dev->stats.rx_errors++;
  2375. dev_kfree_skb(skb);
  2376. goto next_pkt;
  2377. }
  2378. }
  2379. /* framing errors are soft errors */
  2380. else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
  2381. if (flags & NV_RX2_SUBSTRACT1)
  2382. len--;
  2383. }
  2384. /* the rest are hard errors */
  2385. else {
  2386. if (flags & NV_RX2_CRCERR)
  2387. dev->stats.rx_crc_errors++;
  2388. if (flags & NV_RX2_OVERFLOW)
  2389. dev->stats.rx_over_errors++;
  2390. dev->stats.rx_errors++;
  2391. dev_kfree_skb(skb);
  2392. goto next_pkt;
  2393. }
  2394. }
  2395. if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
  2396. ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
  2397. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2398. } else {
  2399. dev_kfree_skb(skb);
  2400. goto next_pkt;
  2401. }
  2402. }
  2403. /* got a valid packet - forward it to the network core */
  2404. skb_put(skb, len);
  2405. skb->protocol = eth_type_trans(skb, dev);
  2406. napi_gro_receive(&np->napi, skb);
  2407. dev->stats.rx_packets++;
  2408. dev->stats.rx_bytes += len;
  2409. next_pkt:
  2410. if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
  2411. np->get_rx.orig = np->first_rx.orig;
  2412. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2413. np->get_rx_ctx = np->first_rx_ctx;
  2414. rx_work++;
  2415. }
  2416. return rx_work;
  2417. }
  2418. static int nv_rx_process_optimized(struct net_device *dev, int limit)
  2419. {
  2420. struct fe_priv *np = netdev_priv(dev);
  2421. u32 flags;
  2422. u32 vlanflags = 0;
  2423. int rx_work = 0;
  2424. struct sk_buff *skb;
  2425. int len;
  2426. while ((np->get_rx.ex != np->put_rx.ex) &&
  2427. !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
  2428. (rx_work < limit)) {
  2429. /*
  2430. * the packet is for us - immediately tear down the pci mapping.
  2431. * TODO: check if a prefetch of the first cacheline improves
  2432. * the performance.
  2433. */
  2434. pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
  2435. np->get_rx_ctx->dma_len,
  2436. PCI_DMA_FROMDEVICE);
  2437. skb = np->get_rx_ctx->skb;
  2438. np->get_rx_ctx->skb = NULL;
  2439. /* look at what we actually got: */
  2440. if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
  2441. len = flags & LEN_MASK_V2;
  2442. if (unlikely(flags & NV_RX2_ERROR)) {
  2443. if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
  2444. len = nv_getlen(dev, skb->data, len);
  2445. if (len < 0) {
  2446. dev_kfree_skb(skb);
  2447. goto next_pkt;
  2448. }
  2449. }
  2450. /* framing errors are soft errors */
  2451. else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
  2452. if (flags & NV_RX2_SUBSTRACT1)
  2453. len--;
  2454. }
  2455. /* the rest are hard errors */
  2456. else {
  2457. dev_kfree_skb(skb);
  2458. goto next_pkt;
  2459. }
  2460. }
  2461. if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
  2462. ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
  2463. skb->ip_summed = CHECKSUM_UNNECESSARY;
  2464. /* got a valid packet - forward it to the network core */
  2465. skb_put(skb, len);
  2466. skb->protocol = eth_type_trans(skb, dev);
  2467. prefetch(skb->data);
  2468. vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
  2469. /*
  2470. * There's need to check for NETIF_F_HW_VLAN_RX here.
  2471. * Even if vlan rx accel is disabled,
  2472. * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
  2473. */
  2474. if (dev->features & NETIF_F_HW_VLAN_RX &&
  2475. vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
  2476. u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
  2477. __vlan_hwaccel_put_tag(skb, vid);
  2478. }
  2479. napi_gro_receive(&np->napi, skb);
  2480. dev->stats.rx_packets++;
  2481. dev->stats.rx_bytes += len;
  2482. } else {
  2483. dev_kfree_skb(skb);
  2484. }
  2485. next_pkt:
  2486. if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
  2487. np->get_rx.ex = np->first_rx.ex;
  2488. if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
  2489. np->get_rx_ctx = np->first_rx_ctx;
  2490. rx_work++;
  2491. }
  2492. return rx_work;
  2493. }
  2494. static void set_bufsize(struct net_device *dev)
  2495. {
  2496. struct fe_priv *np = netdev_priv(dev);
  2497. if (dev->mtu <= ETH_DATA_LEN)
  2498. np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
  2499. else
  2500. np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
  2501. }
  2502. /*
  2503. * nv_change_mtu: dev->change_mtu function
  2504. * Called with dev_base_lock held for read.
  2505. */
  2506. static int nv_change_mtu(struct net_device *dev, int new_mtu)
  2507. {
  2508. struct fe_priv *np = netdev_priv(dev);
  2509. int old_mtu;
  2510. if (new_mtu < 64 || new_mtu > np->pkt_limit)
  2511. return -EINVAL;
  2512. old_mtu = dev->mtu;
  2513. dev->mtu = new_mtu;
  2514. /* return early if the buffer sizes will not change */
  2515. if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
  2516. return 0;
  2517. if (old_mtu == new_mtu)
  2518. return 0;
  2519. /* synchronized against open : rtnl_lock() held by caller */
  2520. if (netif_running(dev)) {
  2521. u8 __iomem *base = get_hwbase(dev);
  2522. /*
  2523. * It seems that the nic preloads valid ring entries into an
  2524. * internal buffer. The procedure for flushing everything is
  2525. * guessed, there is probably a simpler approach.
  2526. * Changing the MTU is a rare event, it shouldn't matter.
  2527. */
  2528. nv_disable_irq(dev);
  2529. nv_napi_disable(dev);
  2530. netif_tx_lock_bh(dev);
  2531. netif_addr_lock(dev);
  2532. spin_lock(&np->lock);
  2533. /* stop engines */
  2534. nv_stop_rxtx(dev);
  2535. nv_txrx_reset(dev);
  2536. /* drain rx queue */
  2537. nv_drain_rxtx(dev);
  2538. /* reinit driver view of the rx queue */
  2539. set_bufsize(dev);
  2540. if (nv_init_ring(dev)) {
  2541. if (!np->in_shutdown)
  2542. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  2543. }
  2544. /* reinit nic view of the rx queue */
  2545. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  2546. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  2547. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  2548. base + NvRegRingSizes);
  2549. pci_push(base);
  2550. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  2551. pci_push(base);
  2552. /* restart rx engine */
  2553. nv_start_rxtx(dev);
  2554. spin_unlock(&np->lock);
  2555. netif_addr_unlock(dev);
  2556. netif_tx_unlock_bh(dev);
  2557. nv_napi_enable(dev);
  2558. nv_enable_irq(dev);
  2559. }
  2560. return 0;
  2561. }
  2562. static void nv_copy_mac_to_hw(struct net_device *dev)
  2563. {
  2564. u8 __iomem *base = get_hwbase(dev);
  2565. u32 mac[2];
  2566. mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
  2567. (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
  2568. mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
  2569. writel(mac[0], base + NvRegMacAddrA);
  2570. writel(mac[1], base + NvRegMacAddrB);
  2571. }
  2572. /*
  2573. * nv_set_mac_address: dev->set_mac_address function
  2574. * Called with rtnl_lock() held.
  2575. */
  2576. static int nv_set_mac_address(struct net_device *dev, void *addr)
  2577. {
  2578. struct fe_priv *np = netdev_priv(dev);
  2579. struct sockaddr *macaddr = (struct sockaddr *)addr;
  2580. if (!is_valid_ether_addr(macaddr->sa_data))
  2581. return -EADDRNOTAVAIL;
  2582. /* synchronized against open : rtnl_lock() held by caller */
  2583. memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
  2584. if (netif_running(dev)) {
  2585. netif_tx_lock_bh(dev);
  2586. netif_addr_lock(dev);
  2587. spin_lock_irq(&np->lock);
  2588. /* stop rx engine */
  2589. nv_stop_rx(dev);
  2590. /* set mac address */
  2591. nv_copy_mac_to_hw(dev);
  2592. /* restart rx engine */
  2593. nv_start_rx(dev);
  2594. spin_unlock_irq(&np->lock);
  2595. netif_addr_unlock(dev);
  2596. netif_tx_unlock_bh(dev);
  2597. } else {
  2598. nv_copy_mac_to_hw(dev);
  2599. }
  2600. return 0;
  2601. }
  2602. /*
  2603. * nv_set_multicast: dev->set_multicast function
  2604. * Called with netif_tx_lock held.
  2605. */
  2606. static void nv_set_multicast(struct net_device *dev)
  2607. {
  2608. struct fe_priv *np = netdev_priv(dev);
  2609. u8 __iomem *base = get_hwbase(dev);
  2610. u32 addr[2];
  2611. u32 mask[2];
  2612. u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
  2613. memset(addr, 0, sizeof(addr));
  2614. memset(mask, 0, sizeof(mask));
  2615. if (dev->flags & IFF_PROMISC) {
  2616. pff |= NVREG_PFF_PROMISC;
  2617. } else {
  2618. pff |= NVREG_PFF_MYADDR;
  2619. if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
  2620. u32 alwaysOff[2];
  2621. u32 alwaysOn[2];
  2622. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
  2623. if (dev->flags & IFF_ALLMULTI) {
  2624. alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
  2625. } else {
  2626. struct netdev_hw_addr *ha;
  2627. netdev_for_each_mc_addr(ha, dev) {
  2628. unsigned char *addr = ha->addr;
  2629. u32 a, b;
  2630. a = le32_to_cpu(*(__le32 *) addr);
  2631. b = le16_to_cpu(*(__le16 *) (&addr[4]));
  2632. alwaysOn[0] &= a;
  2633. alwaysOff[0] &= ~a;
  2634. alwaysOn[1] &= b;
  2635. alwaysOff[1] &= ~b;
  2636. }
  2637. }
  2638. addr[0] = alwaysOn[0];
  2639. addr[1] = alwaysOn[1];
  2640. mask[0] = alwaysOn[0] | alwaysOff[0];
  2641. mask[1] = alwaysOn[1] | alwaysOff[1];
  2642. } else {
  2643. mask[0] = NVREG_MCASTMASKA_NONE;
  2644. mask[1] = NVREG_MCASTMASKB_NONE;
  2645. }
  2646. }
  2647. addr[0] |= NVREG_MCASTADDRA_FORCE;
  2648. pff |= NVREG_PFF_ALWAYS;
  2649. spin_lock_irq(&np->lock);
  2650. nv_stop_rx(dev);
  2651. writel(addr[0], base + NvRegMulticastAddrA);
  2652. writel(addr[1], base + NvRegMulticastAddrB);
  2653. writel(mask[0], base + NvRegMulticastMaskA);
  2654. writel(mask[1], base + NvRegMulticastMaskB);
  2655. writel(pff, base + NvRegPacketFilterFlags);
  2656. nv_start_rx(dev);
  2657. spin_unlock_irq(&np->lock);
  2658. }
  2659. static void nv_update_pause(struct net_device *dev, u32 pause_flags)
  2660. {
  2661. struct fe_priv *np = netdev_priv(dev);
  2662. u8 __iomem *base = get_hwbase(dev);
  2663. np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
  2664. if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
  2665. u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
  2666. if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
  2667. writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
  2668. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2669. } else {
  2670. writel(pff, base + NvRegPacketFilterFlags);
  2671. }
  2672. }
  2673. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
  2674. u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
  2675. if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
  2676. u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
  2677. if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
  2678. pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
  2679. if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
  2680. pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
  2681. /* limit the number of tx pause frames to a default of 8 */
  2682. writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
  2683. }
  2684. writel(pause_enable, base + NvRegTxPauseFrame);
  2685. writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
  2686. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2687. } else {
  2688. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  2689. writel(regmisc, base + NvRegMisc1);
  2690. }
  2691. }
  2692. }
  2693. /**
  2694. * nv_update_linkspeed: Setup the MAC according to the link partner
  2695. * @dev: Network device to be configured
  2696. *
  2697. * The function queries the PHY and checks if there is a link partner.
  2698. * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
  2699. * set to 10 MBit HD.
  2700. *
  2701. * The function returns 0 if there is no link partner and 1 if there is
  2702. * a good link partner.
  2703. */
  2704. static int nv_update_linkspeed(struct net_device *dev)
  2705. {
  2706. struct fe_priv *np = netdev_priv(dev);
  2707. u8 __iomem *base = get_hwbase(dev);
  2708. int adv = 0;
  2709. int lpa = 0;
  2710. int adv_lpa, adv_pause, lpa_pause;
  2711. int newls = np->linkspeed;
  2712. int newdup = np->duplex;
  2713. int mii_status;
  2714. int retval = 0;
  2715. u32 control_1000, status_1000, phyreg, pause_flags, txreg;
  2716. u32 txrxFlags = 0;
  2717. u32 phy_exp;
  2718. /* BMSR_LSTATUS is latched, read it twice:
  2719. * we want the current value.
  2720. */
  2721. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2722. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  2723. if (!(mii_status & BMSR_LSTATUS)) {
  2724. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2725. newdup = 0;
  2726. retval = 0;
  2727. goto set_speed;
  2728. }
  2729. if (np->autoneg == 0) {
  2730. if (np->fixed_mode & LPA_100FULL) {
  2731. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2732. newdup = 1;
  2733. } else if (np->fixed_mode & LPA_100HALF) {
  2734. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2735. newdup = 0;
  2736. } else if (np->fixed_mode & LPA_10FULL) {
  2737. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2738. newdup = 1;
  2739. } else {
  2740. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2741. newdup = 0;
  2742. }
  2743. retval = 1;
  2744. goto set_speed;
  2745. }
  2746. /* check auto negotiation is complete */
  2747. if (!(mii_status & BMSR_ANEGCOMPLETE)) {
  2748. /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
  2749. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2750. newdup = 0;
  2751. retval = 0;
  2752. goto set_speed;
  2753. }
  2754. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  2755. lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
  2756. retval = 1;
  2757. if (np->gigabit == PHY_GIGABIT) {
  2758. control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  2759. status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
  2760. if ((control_1000 & ADVERTISE_1000FULL) &&
  2761. (status_1000 & LPA_1000FULL)) {
  2762. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
  2763. newdup = 1;
  2764. goto set_speed;
  2765. }
  2766. }
  2767. /* FIXME: handle parallel detection properly */
  2768. adv_lpa = lpa & adv;
  2769. if (adv_lpa & LPA_100FULL) {
  2770. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2771. newdup = 1;
  2772. } else if (adv_lpa & LPA_100HALF) {
  2773. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
  2774. newdup = 0;
  2775. } else if (adv_lpa & LPA_10FULL) {
  2776. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2777. newdup = 1;
  2778. } else if (adv_lpa & LPA_10HALF) {
  2779. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2780. newdup = 0;
  2781. } else {
  2782. newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  2783. newdup = 0;
  2784. }
  2785. set_speed:
  2786. if (np->duplex == newdup && np->linkspeed == newls)
  2787. return retval;
  2788. np->duplex = newdup;
  2789. np->linkspeed = newls;
  2790. /* The transmitter and receiver must be restarted for safe update */
  2791. if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
  2792. txrxFlags |= NV_RESTART_TX;
  2793. nv_stop_tx(dev);
  2794. }
  2795. if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
  2796. txrxFlags |= NV_RESTART_RX;
  2797. nv_stop_rx(dev);
  2798. }
  2799. if (np->gigabit == PHY_GIGABIT) {
  2800. phyreg = readl(base + NvRegSlotTime);
  2801. phyreg &= ~(0x3FF00);
  2802. if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
  2803. ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
  2804. phyreg |= NVREG_SLOTTIME_10_100_FULL;
  2805. else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
  2806. phyreg |= NVREG_SLOTTIME_1000_FULL;
  2807. writel(phyreg, base + NvRegSlotTime);
  2808. }
  2809. phyreg = readl(base + NvRegPhyInterface);
  2810. phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
  2811. if (np->duplex == 0)
  2812. phyreg |= PHY_HALF;
  2813. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
  2814. phyreg |= PHY_100;
  2815. else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2816. phyreg |= PHY_1000;
  2817. writel(phyreg, base + NvRegPhyInterface);
  2818. phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
  2819. if (phyreg & PHY_RGMII) {
  2820. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
  2821. txreg = NVREG_TX_DEFERRAL_RGMII_1000;
  2822. } else {
  2823. if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
  2824. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
  2825. txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
  2826. else
  2827. txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
  2828. } else {
  2829. txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
  2830. }
  2831. }
  2832. } else {
  2833. if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
  2834. txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
  2835. else
  2836. txreg = NVREG_TX_DEFERRAL_DEFAULT;
  2837. }
  2838. writel(txreg, base + NvRegTxDeferral);
  2839. if (np->desc_ver == DESC_VER_1) {
  2840. txreg = NVREG_TX_WM_DESC1_DEFAULT;
  2841. } else {
  2842. if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
  2843. txreg = NVREG_TX_WM_DESC2_3_1000;
  2844. else
  2845. txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
  2846. }
  2847. writel(txreg, base + NvRegTxWatermark);
  2848. writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
  2849. base + NvRegMisc1);
  2850. pci_push(base);
  2851. writel(np->linkspeed, base + NvRegLinkSpeed);
  2852. pci_push(base);
  2853. pause_flags = 0;
  2854. /* setup pause frame */
  2855. if (np->duplex != 0) {
  2856. if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
  2857. adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  2858. lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
  2859. switch (adv_pause) {
  2860. case ADVERTISE_PAUSE_CAP:
  2861. if (lpa_pause & LPA_PAUSE_CAP) {
  2862. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2863. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2864. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2865. }
  2866. break;
  2867. case ADVERTISE_PAUSE_ASYM:
  2868. if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
  2869. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2870. break;
  2871. case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
  2872. if (lpa_pause & LPA_PAUSE_CAP) {
  2873. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2874. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  2875. pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  2876. }
  2877. if (lpa_pause == LPA_PAUSE_ASYM)
  2878. pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  2879. break;
  2880. }
  2881. } else {
  2882. pause_flags = np->pause_flags;
  2883. }
  2884. }
  2885. nv_update_pause(dev, pause_flags);
  2886. if (txrxFlags & NV_RESTART_TX)
  2887. nv_start_tx(dev);
  2888. if (txrxFlags & NV_RESTART_RX)
  2889. nv_start_rx(dev);
  2890. return retval;
  2891. }
  2892. static void nv_linkchange(struct net_device *dev)
  2893. {
  2894. if (nv_update_linkspeed(dev)) {
  2895. if (!netif_carrier_ok(dev)) {
  2896. netif_carrier_on(dev);
  2897. netdev_info(dev, "link up\n");
  2898. nv_txrx_gate(dev, false);
  2899. nv_start_rx(dev);
  2900. }
  2901. } else {
  2902. if (netif_carrier_ok(dev)) {
  2903. netif_carrier_off(dev);
  2904. netdev_info(dev, "link down\n");
  2905. nv_txrx_gate(dev, true);
  2906. nv_stop_rx(dev);
  2907. }
  2908. }
  2909. }
  2910. static void nv_link_irq(struct net_device *dev)
  2911. {
  2912. u8 __iomem *base = get_hwbase(dev);
  2913. u32 miistat;
  2914. miistat = readl(base + NvRegMIIStatus);
  2915. writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
  2916. if (miistat & (NVREG_MIISTAT_LINKCHANGE))
  2917. nv_linkchange(dev);
  2918. }
  2919. static void nv_msi_workaround(struct fe_priv *np)
  2920. {
  2921. /* Need to toggle the msi irq mask within the ethernet device,
  2922. * otherwise, future interrupts will not be detected.
  2923. */
  2924. if (np->msi_flags & NV_MSI_ENABLED) {
  2925. u8 __iomem *base = np->base;
  2926. writel(0, base + NvRegMSIIrqMask);
  2927. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  2928. }
  2929. }
  2930. static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
  2931. {
  2932. struct fe_priv *np = netdev_priv(dev);
  2933. if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
  2934. if (total_work > NV_DYNAMIC_THRESHOLD) {
  2935. /* transition to poll based interrupts */
  2936. np->quiet_count = 0;
  2937. if (np->irqmask != NVREG_IRQMASK_CPU) {
  2938. np->irqmask = NVREG_IRQMASK_CPU;
  2939. return 1;
  2940. }
  2941. } else {
  2942. if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
  2943. np->quiet_count++;
  2944. } else {
  2945. /* reached a period of low activity, switch
  2946. to per tx/rx packet interrupts */
  2947. if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
  2948. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  2949. return 1;
  2950. }
  2951. }
  2952. }
  2953. }
  2954. return 0;
  2955. }
  2956. static irqreturn_t nv_nic_irq(int foo, void *data)
  2957. {
  2958. struct net_device *dev = (struct net_device *) data;
  2959. struct fe_priv *np = netdev_priv(dev);
  2960. u8 __iomem *base = get_hwbase(dev);
  2961. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2962. np->events = readl(base + NvRegIrqStatus);
  2963. writel(np->events, base + NvRegIrqStatus);
  2964. } else {
  2965. np->events = readl(base + NvRegMSIXIrqStatus);
  2966. writel(np->events, base + NvRegMSIXIrqStatus);
  2967. }
  2968. if (!(np->events & np->irqmask))
  2969. return IRQ_NONE;
  2970. nv_msi_workaround(np);
  2971. if (napi_schedule_prep(&np->napi)) {
  2972. /*
  2973. * Disable further irq's (msix not enabled with napi)
  2974. */
  2975. writel(0, base + NvRegIrqMask);
  2976. __napi_schedule(&np->napi);
  2977. }
  2978. return IRQ_HANDLED;
  2979. }
  2980. /**
  2981. * All _optimized functions are used to help increase performance
  2982. * (reduce CPU and increase throughput). They use descripter version 3,
  2983. * compiler directives, and reduce memory accesses.
  2984. */
  2985. static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
  2986. {
  2987. struct net_device *dev = (struct net_device *) data;
  2988. struct fe_priv *np = netdev_priv(dev);
  2989. u8 __iomem *base = get_hwbase(dev);
  2990. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  2991. np->events = readl(base + NvRegIrqStatus);
  2992. writel(np->events, base + NvRegIrqStatus);
  2993. } else {
  2994. np->events = readl(base + NvRegMSIXIrqStatus);
  2995. writel(np->events, base + NvRegMSIXIrqStatus);
  2996. }
  2997. if (!(np->events & np->irqmask))
  2998. return IRQ_NONE;
  2999. nv_msi_workaround(np);
  3000. if (napi_schedule_prep(&np->napi)) {
  3001. /*
  3002. * Disable further irq's (msix not enabled with napi)
  3003. */
  3004. writel(0, base + NvRegIrqMask);
  3005. __napi_schedule(&np->napi);
  3006. }
  3007. return IRQ_HANDLED;
  3008. }
  3009. static irqreturn_t nv_nic_irq_tx(int foo, void *data)
  3010. {
  3011. struct net_device *dev = (struct net_device *) data;
  3012. struct fe_priv *np = netdev_priv(dev);
  3013. u8 __iomem *base = get_hwbase(dev);
  3014. u32 events;
  3015. int i;
  3016. unsigned long flags;
  3017. for (i = 0;; i++) {
  3018. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
  3019. writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
  3020. if (!(events & np->irqmask))
  3021. break;
  3022. spin_lock_irqsave(&np->lock, flags);
  3023. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  3024. spin_unlock_irqrestore(&np->lock, flags);
  3025. if (unlikely(i > max_interrupt_work)) {
  3026. spin_lock_irqsave(&np->lock, flags);
  3027. /* disable interrupts on the nic */
  3028. writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
  3029. pci_push(base);
  3030. if (!np->in_shutdown) {
  3031. np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
  3032. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3033. }
  3034. spin_unlock_irqrestore(&np->lock, flags);
  3035. netdev_dbg(dev, "%s: too many iterations (%d)\n",
  3036. __func__, i);
  3037. break;
  3038. }
  3039. }
  3040. return IRQ_RETVAL(i);
  3041. }
  3042. static int nv_napi_poll(struct napi_struct *napi, int budget)
  3043. {
  3044. struct fe_priv *np = container_of(napi, struct fe_priv, napi);
  3045. struct net_device *dev = np->dev;
  3046. u8 __iomem *base = get_hwbase(dev);
  3047. unsigned long flags;
  3048. int retcode;
  3049. int rx_count, tx_work = 0, rx_work = 0;
  3050. do {
  3051. if (!nv_optimized(np)) {
  3052. spin_lock_irqsave(&np->lock, flags);
  3053. tx_work += nv_tx_done(dev, np->tx_ring_size);
  3054. spin_unlock_irqrestore(&np->lock, flags);
  3055. rx_count = nv_rx_process(dev, budget - rx_work);
  3056. retcode = nv_alloc_rx(dev);
  3057. } else {
  3058. spin_lock_irqsave(&np->lock, flags);
  3059. tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
  3060. spin_unlock_irqrestore(&np->lock, flags);
  3061. rx_count = nv_rx_process_optimized(dev,
  3062. budget - rx_work);
  3063. retcode = nv_alloc_rx_optimized(dev);
  3064. }
  3065. } while (retcode == 0 &&
  3066. rx_count > 0 && (rx_work += rx_count) < budget);
  3067. if (retcode) {
  3068. spin_lock_irqsave(&np->lock, flags);
  3069. if (!np->in_shutdown)
  3070. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3071. spin_unlock_irqrestore(&np->lock, flags);
  3072. }
  3073. nv_change_interrupt_mode(dev, tx_work + rx_work);
  3074. if (unlikely(np->events & NVREG_IRQ_LINK)) {
  3075. spin_lock_irqsave(&np->lock, flags);
  3076. nv_link_irq(dev);
  3077. spin_unlock_irqrestore(&np->lock, flags);
  3078. }
  3079. if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
  3080. spin_lock_irqsave(&np->lock, flags);
  3081. nv_linkchange(dev);
  3082. spin_unlock_irqrestore(&np->lock, flags);
  3083. np->link_timeout = jiffies + LINK_TIMEOUT;
  3084. }
  3085. if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
  3086. spin_lock_irqsave(&np->lock, flags);
  3087. if (!np->in_shutdown) {
  3088. np->nic_poll_irq = np->irqmask;
  3089. np->recover_error = 1;
  3090. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3091. }
  3092. spin_unlock_irqrestore(&np->lock, flags);
  3093. napi_complete(napi);
  3094. return rx_work;
  3095. }
  3096. if (rx_work < budget) {
  3097. /* re-enable interrupts
  3098. (msix not enabled in napi) */
  3099. napi_complete(napi);
  3100. writel(np->irqmask, base + NvRegIrqMask);
  3101. }
  3102. return rx_work;
  3103. }
  3104. static irqreturn_t nv_nic_irq_rx(int foo, void *data)
  3105. {
  3106. struct net_device *dev = (struct net_device *) data;
  3107. struct fe_priv *np = netdev_priv(dev);
  3108. u8 __iomem *base = get_hwbase(dev);
  3109. u32 events;
  3110. int i;
  3111. unsigned long flags;
  3112. for (i = 0;; i++) {
  3113. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
  3114. writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
  3115. if (!(events & np->irqmask))
  3116. break;
  3117. if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
  3118. if (unlikely(nv_alloc_rx_optimized(dev))) {
  3119. spin_lock_irqsave(&np->lock, flags);
  3120. if (!np->in_shutdown)
  3121. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3122. spin_unlock_irqrestore(&np->lock, flags);
  3123. }
  3124. }
  3125. if (unlikely(i > max_interrupt_work)) {
  3126. spin_lock_irqsave(&np->lock, flags);
  3127. /* disable interrupts on the nic */
  3128. writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
  3129. pci_push(base);
  3130. if (!np->in_shutdown) {
  3131. np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
  3132. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3133. }
  3134. spin_unlock_irqrestore(&np->lock, flags);
  3135. netdev_dbg(dev, "%s: too many iterations (%d)\n",
  3136. __func__, i);
  3137. break;
  3138. }
  3139. }
  3140. return IRQ_RETVAL(i);
  3141. }
  3142. static irqreturn_t nv_nic_irq_other(int foo, void *data)
  3143. {
  3144. struct net_device *dev = (struct net_device *) data;
  3145. struct fe_priv *np = netdev_priv(dev);
  3146. u8 __iomem *base = get_hwbase(dev);
  3147. u32 events;
  3148. int i;
  3149. unsigned long flags;
  3150. for (i = 0;; i++) {
  3151. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
  3152. writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
  3153. if (!(events & np->irqmask))
  3154. break;
  3155. /* check tx in case we reached max loop limit in tx isr */
  3156. spin_lock_irqsave(&np->lock, flags);
  3157. nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
  3158. spin_unlock_irqrestore(&np->lock, flags);
  3159. if (events & NVREG_IRQ_LINK) {
  3160. spin_lock_irqsave(&np->lock, flags);
  3161. nv_link_irq(dev);
  3162. spin_unlock_irqrestore(&np->lock, flags);
  3163. }
  3164. if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
  3165. spin_lock_irqsave(&np->lock, flags);
  3166. nv_linkchange(dev);
  3167. spin_unlock_irqrestore(&np->lock, flags);
  3168. np->link_timeout = jiffies + LINK_TIMEOUT;
  3169. }
  3170. if (events & NVREG_IRQ_RECOVER_ERROR) {
  3171. spin_lock_irq(&np->lock);
  3172. /* disable interrupts on the nic */
  3173. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  3174. pci_push(base);
  3175. if (!np->in_shutdown) {
  3176. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  3177. np->recover_error = 1;
  3178. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3179. }
  3180. spin_unlock_irq(&np->lock);
  3181. break;
  3182. }
  3183. if (unlikely(i > max_interrupt_work)) {
  3184. spin_lock_irqsave(&np->lock, flags);
  3185. /* disable interrupts on the nic */
  3186. writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
  3187. pci_push(base);
  3188. if (!np->in_shutdown) {
  3189. np->nic_poll_irq |= NVREG_IRQ_OTHER;
  3190. mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
  3191. }
  3192. spin_unlock_irqrestore(&np->lock, flags);
  3193. netdev_dbg(dev, "%s: too many iterations (%d)\n",
  3194. __func__, i);
  3195. break;
  3196. }
  3197. }
  3198. return IRQ_RETVAL(i);
  3199. }
  3200. static irqreturn_t nv_nic_irq_test(int foo, void *data)
  3201. {
  3202. struct net_device *dev = (struct net_device *) data;
  3203. struct fe_priv *np = netdev_priv(dev);
  3204. u8 __iomem *base = get_hwbase(dev);
  3205. u32 events;
  3206. if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
  3207. events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
  3208. writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
  3209. } else {
  3210. events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
  3211. writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
  3212. }
  3213. pci_push(base);
  3214. if (!(events & NVREG_IRQ_TIMER))
  3215. return IRQ_RETVAL(0);
  3216. nv_msi_workaround(np);
  3217. spin_lock(&np->lock);
  3218. np->intr_test = 1;
  3219. spin_unlock(&np->lock);
  3220. return IRQ_RETVAL(1);
  3221. }
  3222. static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
  3223. {
  3224. u8 __iomem *base = get_hwbase(dev);
  3225. int i;
  3226. u32 msixmap = 0;
  3227. /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
  3228. * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
  3229. * the remaining 8 interrupts.
  3230. */
  3231. for (i = 0; i < 8; i++) {
  3232. if ((irqmask >> i) & 0x1)
  3233. msixmap |= vector << (i << 2);
  3234. }
  3235. writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
  3236. msixmap = 0;
  3237. for (i = 0; i < 8; i++) {
  3238. if ((irqmask >> (i + 8)) & 0x1)
  3239. msixmap |= vector << (i << 2);
  3240. }
  3241. writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
  3242. }
  3243. static int nv_request_irq(struct net_device *dev, int intr_test)
  3244. {
  3245. struct fe_priv *np = get_nvpriv(dev);
  3246. u8 __iomem *base = get_hwbase(dev);
  3247. int ret = 1;
  3248. int i;
  3249. irqreturn_t (*handler)(int foo, void *data);
  3250. if (intr_test) {
  3251. handler = nv_nic_irq_test;
  3252. } else {
  3253. if (nv_optimized(np))
  3254. handler = nv_nic_irq_optimized;
  3255. else
  3256. handler = nv_nic_irq;
  3257. }
  3258. if (np->msi_flags & NV_MSI_X_CAPABLE) {
  3259. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
  3260. np->msi_x_entry[i].entry = i;
  3261. ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
  3262. if (ret == 0) {
  3263. np->msi_flags |= NV_MSI_X_ENABLED;
  3264. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
  3265. /* Request irq for rx handling */
  3266. sprintf(np->name_rx, "%s-rx", dev->name);
  3267. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
  3268. nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
  3269. netdev_info(dev,
  3270. "request_irq failed for rx %d\n",
  3271. ret);
  3272. pci_disable_msix(np->pci_dev);
  3273. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3274. goto out_err;
  3275. }
  3276. /* Request irq for tx handling */
  3277. sprintf(np->name_tx, "%s-tx", dev->name);
  3278. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
  3279. nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
  3280. netdev_info(dev,
  3281. "request_irq failed for tx %d\n",
  3282. ret);
  3283. pci_disable_msix(np->pci_dev);
  3284. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3285. goto out_free_rx;
  3286. }
  3287. /* Request irq for link and timer handling */
  3288. sprintf(np->name_other, "%s-other", dev->name);
  3289. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
  3290. nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
  3291. netdev_info(dev,
  3292. "request_irq failed for link %d\n",
  3293. ret);
  3294. pci_disable_msix(np->pci_dev);
  3295. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3296. goto out_free_tx;
  3297. }
  3298. /* map interrupts to their respective vector */
  3299. writel(0, base + NvRegMSIXMap0);
  3300. writel(0, base + NvRegMSIXMap1);
  3301. set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
  3302. set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
  3303. set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
  3304. } else {
  3305. /* Request irq for all interrupts */
  3306. if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3307. netdev_info(dev,
  3308. "request_irq failed %d\n",
  3309. ret);
  3310. pci_disable_msix(np->pci_dev);
  3311. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3312. goto out_err;
  3313. }
  3314. /* map interrupts to vector 0 */
  3315. writel(0, base + NvRegMSIXMap0);
  3316. writel(0, base + NvRegMSIXMap1);
  3317. }
  3318. }
  3319. }
  3320. if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
  3321. ret = pci_enable_msi(np->pci_dev);
  3322. if (ret == 0) {
  3323. np->msi_flags |= NV_MSI_ENABLED;
  3324. dev->irq = np->pci_dev->irq;
  3325. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
  3326. netdev_info(dev, "request_irq failed %d\n",
  3327. ret);
  3328. pci_disable_msi(np->pci_dev);
  3329. np->msi_flags &= ~NV_MSI_ENABLED;
  3330. dev->irq = np->pci_dev->irq;
  3331. goto out_err;
  3332. }
  3333. /* map interrupts to vector 0 */
  3334. writel(0, base + NvRegMSIMap0);
  3335. writel(0, base + NvRegMSIMap1);
  3336. /* enable msi vector 0 */
  3337. writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
  3338. }
  3339. }
  3340. if (ret != 0) {
  3341. if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
  3342. goto out_err;
  3343. }
  3344. return 0;
  3345. out_free_tx:
  3346. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
  3347. out_free_rx:
  3348. free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
  3349. out_err:
  3350. return 1;
  3351. }
  3352. static void nv_free_irq(struct net_device *dev)
  3353. {
  3354. struct fe_priv *np = get_nvpriv(dev);
  3355. int i;
  3356. if (np->msi_flags & NV_MSI_X_ENABLED) {
  3357. for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
  3358. free_irq(np->msi_x_entry[i].vector, dev);
  3359. pci_disable_msix(np->pci_dev);
  3360. np->msi_flags &= ~NV_MSI_X_ENABLED;
  3361. } else {
  3362. free_irq(np->pci_dev->irq, dev);
  3363. if (np->msi_flags & NV_MSI_ENABLED) {
  3364. pci_disable_msi(np->pci_dev);
  3365. np->msi_flags &= ~NV_MSI_ENABLED;
  3366. }
  3367. }
  3368. }
  3369. static void nv_do_nic_poll(unsigned long data)
  3370. {
  3371. struct net_device *dev = (struct net_device *) data;
  3372. struct fe_priv *np = netdev_priv(dev);
  3373. u8 __iomem *base = get_hwbase(dev);
  3374. u32 mask = 0;
  3375. /*
  3376. * First disable irq(s) and then
  3377. * reenable interrupts on the nic, we have to do this before calling
  3378. * nv_nic_irq because that may decide to do otherwise
  3379. */
  3380. if (!using_multi_irqs(dev)) {
  3381. if (np->msi_flags & NV_MSI_X_ENABLED)
  3382. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3383. else
  3384. disable_irq_lockdep(np->pci_dev->irq);
  3385. mask = np->irqmask;
  3386. } else {
  3387. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3388. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3389. mask |= NVREG_IRQ_RX_ALL;
  3390. }
  3391. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3392. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3393. mask |= NVREG_IRQ_TX_ALL;
  3394. }
  3395. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3396. disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3397. mask |= NVREG_IRQ_OTHER;
  3398. }
  3399. }
  3400. /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
  3401. if (np->recover_error) {
  3402. np->recover_error = 0;
  3403. netdev_info(dev, "MAC in recoverable error state\n");
  3404. if (netif_running(dev)) {
  3405. netif_tx_lock_bh(dev);
  3406. netif_addr_lock(dev);
  3407. spin_lock(&np->lock);
  3408. /* stop engines */
  3409. nv_stop_rxtx(dev);
  3410. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  3411. nv_mac_reset(dev);
  3412. nv_txrx_reset(dev);
  3413. /* drain rx queue */
  3414. nv_drain_rxtx(dev);
  3415. /* reinit driver view of the rx queue */
  3416. set_bufsize(dev);
  3417. if (nv_init_ring(dev)) {
  3418. if (!np->in_shutdown)
  3419. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3420. }
  3421. /* reinit nic view of the rx queue */
  3422. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3423. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3424. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3425. base + NvRegRingSizes);
  3426. pci_push(base);
  3427. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3428. pci_push(base);
  3429. /* clear interrupts */
  3430. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  3431. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  3432. else
  3433. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  3434. /* restart rx engine */
  3435. nv_start_rxtx(dev);
  3436. spin_unlock(&np->lock);
  3437. netif_addr_unlock(dev);
  3438. netif_tx_unlock_bh(dev);
  3439. }
  3440. }
  3441. writel(mask, base + NvRegIrqMask);
  3442. pci_push(base);
  3443. if (!using_multi_irqs(dev)) {
  3444. np->nic_poll_irq = 0;
  3445. if (nv_optimized(np))
  3446. nv_nic_irq_optimized(0, dev);
  3447. else
  3448. nv_nic_irq(0, dev);
  3449. if (np->msi_flags & NV_MSI_X_ENABLED)
  3450. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
  3451. else
  3452. enable_irq_lockdep(np->pci_dev->irq);
  3453. } else {
  3454. if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
  3455. np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
  3456. nv_nic_irq_rx(0, dev);
  3457. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
  3458. }
  3459. if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
  3460. np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
  3461. nv_nic_irq_tx(0, dev);
  3462. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
  3463. }
  3464. if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
  3465. np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
  3466. nv_nic_irq_other(0, dev);
  3467. enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
  3468. }
  3469. }
  3470. }
  3471. #ifdef CONFIG_NET_POLL_CONTROLLER
  3472. static void nv_poll_controller(struct net_device *dev)
  3473. {
  3474. nv_do_nic_poll((unsigned long) dev);
  3475. }
  3476. #endif
  3477. static void nv_do_stats_poll(unsigned long data)
  3478. {
  3479. struct net_device *dev = (struct net_device *) data;
  3480. struct fe_priv *np = netdev_priv(dev);
  3481. nv_get_hw_stats(dev);
  3482. if (!np->in_shutdown)
  3483. mod_timer(&np->stats_poll,
  3484. round_jiffies(jiffies + STATS_INTERVAL));
  3485. }
  3486. static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  3487. {
  3488. struct fe_priv *np = netdev_priv(dev);
  3489. strcpy(info->driver, DRV_NAME);
  3490. strcpy(info->version, FORCEDETH_VERSION);
  3491. strcpy(info->bus_info, pci_name(np->pci_dev));
  3492. }
  3493. static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3494. {
  3495. struct fe_priv *np = netdev_priv(dev);
  3496. wolinfo->supported = WAKE_MAGIC;
  3497. spin_lock_irq(&np->lock);
  3498. if (np->wolenabled)
  3499. wolinfo->wolopts = WAKE_MAGIC;
  3500. spin_unlock_irq(&np->lock);
  3501. }
  3502. static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
  3503. {
  3504. struct fe_priv *np = netdev_priv(dev);
  3505. u8 __iomem *base = get_hwbase(dev);
  3506. u32 flags = 0;
  3507. if (wolinfo->wolopts == 0) {
  3508. np->wolenabled = 0;
  3509. } else if (wolinfo->wolopts & WAKE_MAGIC) {
  3510. np->wolenabled = 1;
  3511. flags = NVREG_WAKEUPFLAGS_ENABLE;
  3512. }
  3513. if (netif_running(dev)) {
  3514. spin_lock_irq(&np->lock);
  3515. writel(flags, base + NvRegWakeUpFlags);
  3516. spin_unlock_irq(&np->lock);
  3517. }
  3518. device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
  3519. return 0;
  3520. }
  3521. static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3522. {
  3523. struct fe_priv *np = netdev_priv(dev);
  3524. u32 speed;
  3525. int adv;
  3526. spin_lock_irq(&np->lock);
  3527. ecmd->port = PORT_MII;
  3528. if (!netif_running(dev)) {
  3529. /* We do not track link speed / duplex setting if the
  3530. * interface is disabled. Force a link check */
  3531. if (nv_update_linkspeed(dev)) {
  3532. if (!netif_carrier_ok(dev))
  3533. netif_carrier_on(dev);
  3534. } else {
  3535. if (netif_carrier_ok(dev))
  3536. netif_carrier_off(dev);
  3537. }
  3538. }
  3539. if (netif_carrier_ok(dev)) {
  3540. switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
  3541. case NVREG_LINKSPEED_10:
  3542. speed = SPEED_10;
  3543. break;
  3544. case NVREG_LINKSPEED_100:
  3545. speed = SPEED_100;
  3546. break;
  3547. case NVREG_LINKSPEED_1000:
  3548. speed = SPEED_1000;
  3549. break;
  3550. default:
  3551. speed = -1;
  3552. break;
  3553. }
  3554. ecmd->duplex = DUPLEX_HALF;
  3555. if (np->duplex)
  3556. ecmd->duplex = DUPLEX_FULL;
  3557. } else {
  3558. speed = -1;
  3559. ecmd->duplex = -1;
  3560. }
  3561. ethtool_cmd_speed_set(ecmd, speed);
  3562. ecmd->autoneg = np->autoneg;
  3563. ecmd->advertising = ADVERTISED_MII;
  3564. if (np->autoneg) {
  3565. ecmd->advertising |= ADVERTISED_Autoneg;
  3566. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3567. if (adv & ADVERTISE_10HALF)
  3568. ecmd->advertising |= ADVERTISED_10baseT_Half;
  3569. if (adv & ADVERTISE_10FULL)
  3570. ecmd->advertising |= ADVERTISED_10baseT_Full;
  3571. if (adv & ADVERTISE_100HALF)
  3572. ecmd->advertising |= ADVERTISED_100baseT_Half;
  3573. if (adv & ADVERTISE_100FULL)
  3574. ecmd->advertising |= ADVERTISED_100baseT_Full;
  3575. if (np->gigabit == PHY_GIGABIT) {
  3576. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3577. if (adv & ADVERTISE_1000FULL)
  3578. ecmd->advertising |= ADVERTISED_1000baseT_Full;
  3579. }
  3580. }
  3581. ecmd->supported = (SUPPORTED_Autoneg |
  3582. SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
  3583. SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  3584. SUPPORTED_MII);
  3585. if (np->gigabit == PHY_GIGABIT)
  3586. ecmd->supported |= SUPPORTED_1000baseT_Full;
  3587. ecmd->phy_address = np->phyaddr;
  3588. ecmd->transceiver = XCVR_EXTERNAL;
  3589. /* ignore maxtxpkt, maxrxpkt for now */
  3590. spin_unlock_irq(&np->lock);
  3591. return 0;
  3592. }
  3593. static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
  3594. {
  3595. struct fe_priv *np = netdev_priv(dev);
  3596. u32 speed = ethtool_cmd_speed(ecmd);
  3597. if (ecmd->port != PORT_MII)
  3598. return -EINVAL;
  3599. if (ecmd->transceiver != XCVR_EXTERNAL)
  3600. return -EINVAL;
  3601. if (ecmd->phy_address != np->phyaddr) {
  3602. /* TODO: support switching between multiple phys. Should be
  3603. * trivial, but not enabled due to lack of test hardware. */
  3604. return -EINVAL;
  3605. }
  3606. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3607. u32 mask;
  3608. mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
  3609. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
  3610. if (np->gigabit == PHY_GIGABIT)
  3611. mask |= ADVERTISED_1000baseT_Full;
  3612. if ((ecmd->advertising & mask) == 0)
  3613. return -EINVAL;
  3614. } else if (ecmd->autoneg == AUTONEG_DISABLE) {
  3615. /* Note: autonegotiation disable, speed 1000 intentionally
  3616. * forbidden - no one should need that. */
  3617. if (speed != SPEED_10 && speed != SPEED_100)
  3618. return -EINVAL;
  3619. if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
  3620. return -EINVAL;
  3621. } else {
  3622. return -EINVAL;
  3623. }
  3624. netif_carrier_off(dev);
  3625. if (netif_running(dev)) {
  3626. unsigned long flags;
  3627. nv_disable_irq(dev);
  3628. netif_tx_lock_bh(dev);
  3629. netif_addr_lock(dev);
  3630. /* with plain spinlock lockdep complains */
  3631. spin_lock_irqsave(&np->lock, flags);
  3632. /* stop engines */
  3633. /* FIXME:
  3634. * this can take some time, and interrupts are disabled
  3635. * due to spin_lock_irqsave, but let's hope no daemon
  3636. * is going to change the settings very often...
  3637. * Worst case:
  3638. * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
  3639. * + some minor delays, which is up to a second approximately
  3640. */
  3641. nv_stop_rxtx(dev);
  3642. spin_unlock_irqrestore(&np->lock, flags);
  3643. netif_addr_unlock(dev);
  3644. netif_tx_unlock_bh(dev);
  3645. }
  3646. if (ecmd->autoneg == AUTONEG_ENABLE) {
  3647. int adv, bmcr;
  3648. np->autoneg = 1;
  3649. /* advertise only what has been requested */
  3650. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3651. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3652. if (ecmd->advertising & ADVERTISED_10baseT_Half)
  3653. adv |= ADVERTISE_10HALF;
  3654. if (ecmd->advertising & ADVERTISED_10baseT_Full)
  3655. adv |= ADVERTISE_10FULL;
  3656. if (ecmd->advertising & ADVERTISED_100baseT_Half)
  3657. adv |= ADVERTISE_100HALF;
  3658. if (ecmd->advertising & ADVERTISED_100baseT_Full)
  3659. adv |= ADVERTISE_100FULL;
  3660. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
  3661. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3662. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3663. adv |= ADVERTISE_PAUSE_ASYM;
  3664. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3665. if (np->gigabit == PHY_GIGABIT) {
  3666. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3667. adv &= ~ADVERTISE_1000FULL;
  3668. if (ecmd->advertising & ADVERTISED_1000baseT_Full)
  3669. adv |= ADVERTISE_1000FULL;
  3670. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3671. }
  3672. if (netif_running(dev))
  3673. netdev_info(dev, "link down\n");
  3674. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3675. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3676. bmcr |= BMCR_ANENABLE;
  3677. /* reset the phy in order for settings to stick,
  3678. * and cause autoneg to start */
  3679. if (phy_reset(dev, bmcr)) {
  3680. netdev_info(dev, "phy reset failed\n");
  3681. return -EINVAL;
  3682. }
  3683. } else {
  3684. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3685. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3686. }
  3687. } else {
  3688. int adv, bmcr;
  3689. np->autoneg = 0;
  3690. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3691. adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3692. if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
  3693. adv |= ADVERTISE_10HALF;
  3694. if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
  3695. adv |= ADVERTISE_10FULL;
  3696. if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
  3697. adv |= ADVERTISE_100HALF;
  3698. if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
  3699. adv |= ADVERTISE_100FULL;
  3700. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3701. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
  3702. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3703. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3704. }
  3705. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
  3706. adv |= ADVERTISE_PAUSE_ASYM;
  3707. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3708. }
  3709. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3710. np->fixed_mode = adv;
  3711. if (np->gigabit == PHY_GIGABIT) {
  3712. adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
  3713. adv &= ~ADVERTISE_1000FULL;
  3714. mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
  3715. }
  3716. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3717. bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
  3718. if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
  3719. bmcr |= BMCR_FULLDPLX;
  3720. if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
  3721. bmcr |= BMCR_SPEED100;
  3722. if (np->phy_oui == PHY_OUI_MARVELL) {
  3723. /* reset the phy in order for forced mode settings to stick */
  3724. if (phy_reset(dev, bmcr)) {
  3725. netdev_info(dev, "phy reset failed\n");
  3726. return -EINVAL;
  3727. }
  3728. } else {
  3729. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3730. if (netif_running(dev)) {
  3731. /* Wait a bit and then reconfigure the nic. */
  3732. udelay(10);
  3733. nv_linkchange(dev);
  3734. }
  3735. }
  3736. }
  3737. if (netif_running(dev)) {
  3738. nv_start_rxtx(dev);
  3739. nv_enable_irq(dev);
  3740. }
  3741. return 0;
  3742. }
  3743. #define FORCEDETH_REGS_VER 1
  3744. static int nv_get_regs_len(struct net_device *dev)
  3745. {
  3746. struct fe_priv *np = netdev_priv(dev);
  3747. return np->register_size;
  3748. }
  3749. static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
  3750. {
  3751. struct fe_priv *np = netdev_priv(dev);
  3752. u8 __iomem *base = get_hwbase(dev);
  3753. u32 *rbuf = buf;
  3754. int i;
  3755. regs->version = FORCEDETH_REGS_VER;
  3756. spin_lock_irq(&np->lock);
  3757. for (i = 0; i <= np->register_size/sizeof(u32); i++)
  3758. rbuf[i] = readl(base + i*sizeof(u32));
  3759. spin_unlock_irq(&np->lock);
  3760. }
  3761. static int nv_nway_reset(struct net_device *dev)
  3762. {
  3763. struct fe_priv *np = netdev_priv(dev);
  3764. int ret;
  3765. if (np->autoneg) {
  3766. int bmcr;
  3767. netif_carrier_off(dev);
  3768. if (netif_running(dev)) {
  3769. nv_disable_irq(dev);
  3770. netif_tx_lock_bh(dev);
  3771. netif_addr_lock(dev);
  3772. spin_lock(&np->lock);
  3773. /* stop engines */
  3774. nv_stop_rxtx(dev);
  3775. spin_unlock(&np->lock);
  3776. netif_addr_unlock(dev);
  3777. netif_tx_unlock_bh(dev);
  3778. netdev_info(dev, "link down\n");
  3779. }
  3780. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3781. if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
  3782. bmcr |= BMCR_ANENABLE;
  3783. /* reset the phy in order for settings to stick*/
  3784. if (phy_reset(dev, bmcr)) {
  3785. netdev_info(dev, "phy reset failed\n");
  3786. return -EINVAL;
  3787. }
  3788. } else {
  3789. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3790. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3791. }
  3792. if (netif_running(dev)) {
  3793. nv_start_rxtx(dev);
  3794. nv_enable_irq(dev);
  3795. }
  3796. ret = 0;
  3797. } else {
  3798. ret = -EINVAL;
  3799. }
  3800. return ret;
  3801. }
  3802. static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3803. {
  3804. struct fe_priv *np = netdev_priv(dev);
  3805. ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3806. ring->rx_mini_max_pending = 0;
  3807. ring->rx_jumbo_max_pending = 0;
  3808. ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
  3809. ring->rx_pending = np->rx_ring_size;
  3810. ring->rx_mini_pending = 0;
  3811. ring->rx_jumbo_pending = 0;
  3812. ring->tx_pending = np->tx_ring_size;
  3813. }
  3814. static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
  3815. {
  3816. struct fe_priv *np = netdev_priv(dev);
  3817. u8 __iomem *base = get_hwbase(dev);
  3818. u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
  3819. dma_addr_t ring_addr;
  3820. if (ring->rx_pending < RX_RING_MIN ||
  3821. ring->tx_pending < TX_RING_MIN ||
  3822. ring->rx_mini_pending != 0 ||
  3823. ring->rx_jumbo_pending != 0 ||
  3824. (np->desc_ver == DESC_VER_1 &&
  3825. (ring->rx_pending > RING_MAX_DESC_VER_1 ||
  3826. ring->tx_pending > RING_MAX_DESC_VER_1)) ||
  3827. (np->desc_ver != DESC_VER_1 &&
  3828. (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
  3829. ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
  3830. return -EINVAL;
  3831. }
  3832. /* allocate new rings */
  3833. if (!nv_optimized(np)) {
  3834. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3835. sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3836. &ring_addr);
  3837. } else {
  3838. rxtx_ring = pci_alloc_consistent(np->pci_dev,
  3839. sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3840. &ring_addr);
  3841. }
  3842. rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
  3843. tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
  3844. if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
  3845. /* fall back to old rings */
  3846. if (!nv_optimized(np)) {
  3847. if (rxtx_ring)
  3848. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
  3849. rxtx_ring, ring_addr);
  3850. } else {
  3851. if (rxtx_ring)
  3852. pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
  3853. rxtx_ring, ring_addr);
  3854. }
  3855. kfree(rx_skbuff);
  3856. kfree(tx_skbuff);
  3857. goto exit;
  3858. }
  3859. if (netif_running(dev)) {
  3860. nv_disable_irq(dev);
  3861. nv_napi_disable(dev);
  3862. netif_tx_lock_bh(dev);
  3863. netif_addr_lock(dev);
  3864. spin_lock(&np->lock);
  3865. /* stop engines */
  3866. nv_stop_rxtx(dev);
  3867. nv_txrx_reset(dev);
  3868. /* drain queues */
  3869. nv_drain_rxtx(dev);
  3870. /* delete queues */
  3871. free_rings(dev);
  3872. }
  3873. /* set new values */
  3874. np->rx_ring_size = ring->rx_pending;
  3875. np->tx_ring_size = ring->tx_pending;
  3876. if (!nv_optimized(np)) {
  3877. np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
  3878. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  3879. } else {
  3880. np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
  3881. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  3882. }
  3883. np->rx_skb = (struct nv_skb_map *)rx_skbuff;
  3884. np->tx_skb = (struct nv_skb_map *)tx_skbuff;
  3885. np->ring_addr = ring_addr;
  3886. memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
  3887. memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
  3888. if (netif_running(dev)) {
  3889. /* reinit driver view of the queues */
  3890. set_bufsize(dev);
  3891. if (nv_init_ring(dev)) {
  3892. if (!np->in_shutdown)
  3893. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  3894. }
  3895. /* reinit nic view of the queues */
  3896. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  3897. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  3898. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  3899. base + NvRegRingSizes);
  3900. pci_push(base);
  3901. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  3902. pci_push(base);
  3903. /* restart engines */
  3904. nv_start_rxtx(dev);
  3905. spin_unlock(&np->lock);
  3906. netif_addr_unlock(dev);
  3907. netif_tx_unlock_bh(dev);
  3908. nv_napi_enable(dev);
  3909. nv_enable_irq(dev);
  3910. }
  3911. return 0;
  3912. exit:
  3913. return -ENOMEM;
  3914. }
  3915. static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  3916. {
  3917. struct fe_priv *np = netdev_priv(dev);
  3918. pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
  3919. pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
  3920. pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
  3921. }
  3922. static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
  3923. {
  3924. struct fe_priv *np = netdev_priv(dev);
  3925. int adv, bmcr;
  3926. if ((!np->autoneg && np->duplex == 0) ||
  3927. (np->autoneg && !pause->autoneg && np->duplex == 0)) {
  3928. netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
  3929. return -EINVAL;
  3930. }
  3931. if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
  3932. netdev_info(dev, "hardware does not support tx pause frames\n");
  3933. return -EINVAL;
  3934. }
  3935. netif_carrier_off(dev);
  3936. if (netif_running(dev)) {
  3937. nv_disable_irq(dev);
  3938. netif_tx_lock_bh(dev);
  3939. netif_addr_lock(dev);
  3940. spin_lock(&np->lock);
  3941. /* stop engines */
  3942. nv_stop_rxtx(dev);
  3943. spin_unlock(&np->lock);
  3944. netif_addr_unlock(dev);
  3945. netif_tx_unlock_bh(dev);
  3946. }
  3947. np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
  3948. if (pause->rx_pause)
  3949. np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
  3950. if (pause->tx_pause)
  3951. np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
  3952. if (np->autoneg && pause->autoneg) {
  3953. np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
  3954. adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
  3955. adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
  3956. if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
  3957. adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  3958. if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
  3959. adv |= ADVERTISE_PAUSE_ASYM;
  3960. mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
  3961. if (netif_running(dev))
  3962. netdev_info(dev, "link down\n");
  3963. bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  3964. bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
  3965. mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
  3966. } else {
  3967. np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
  3968. if (pause->rx_pause)
  3969. np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
  3970. if (pause->tx_pause)
  3971. np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
  3972. if (!netif_running(dev))
  3973. nv_update_linkspeed(dev);
  3974. else
  3975. nv_update_pause(dev, np->pause_flags);
  3976. }
  3977. if (netif_running(dev)) {
  3978. nv_start_rxtx(dev);
  3979. nv_enable_irq(dev);
  3980. }
  3981. return 0;
  3982. }
  3983. static u32 nv_fix_features(struct net_device *dev, u32 features)
  3984. {
  3985. /* vlan is dependent on rx checksum offload */
  3986. if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
  3987. features |= NETIF_F_RXCSUM;
  3988. return features;
  3989. }
  3990. static void nv_vlan_mode(struct net_device *dev, u32 features)
  3991. {
  3992. struct fe_priv *np = get_nvpriv(dev);
  3993. spin_lock_irq(&np->lock);
  3994. if (features & NETIF_F_HW_VLAN_RX)
  3995. np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
  3996. else
  3997. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
  3998. if (features & NETIF_F_HW_VLAN_TX)
  3999. np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
  4000. else
  4001. np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
  4002. writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4003. spin_unlock_irq(&np->lock);
  4004. }
  4005. static int nv_set_features(struct net_device *dev, u32 features)
  4006. {
  4007. struct fe_priv *np = netdev_priv(dev);
  4008. u8 __iomem *base = get_hwbase(dev);
  4009. u32 changed = dev->features ^ features;
  4010. if (changed & NETIF_F_RXCSUM) {
  4011. spin_lock_irq(&np->lock);
  4012. if (features & NETIF_F_RXCSUM)
  4013. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  4014. else
  4015. np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
  4016. if (netif_running(dev))
  4017. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  4018. spin_unlock_irq(&np->lock);
  4019. }
  4020. if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
  4021. nv_vlan_mode(dev, features);
  4022. return 0;
  4023. }
  4024. static int nv_get_sset_count(struct net_device *dev, int sset)
  4025. {
  4026. struct fe_priv *np = netdev_priv(dev);
  4027. switch (sset) {
  4028. case ETH_SS_TEST:
  4029. if (np->driver_data & DEV_HAS_TEST_EXTENDED)
  4030. return NV_TEST_COUNT_EXTENDED;
  4031. else
  4032. return NV_TEST_COUNT_BASE;
  4033. case ETH_SS_STATS:
  4034. if (np->driver_data & DEV_HAS_STATISTICS_V3)
  4035. return NV_DEV_STATISTICS_V3_COUNT;
  4036. else if (np->driver_data & DEV_HAS_STATISTICS_V2)
  4037. return NV_DEV_STATISTICS_V2_COUNT;
  4038. else if (np->driver_data & DEV_HAS_STATISTICS_V1)
  4039. return NV_DEV_STATISTICS_V1_COUNT;
  4040. else
  4041. return 0;
  4042. default:
  4043. return -EOPNOTSUPP;
  4044. }
  4045. }
  4046. static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
  4047. {
  4048. struct fe_priv *np = netdev_priv(dev);
  4049. /* update stats */
  4050. nv_do_stats_poll((unsigned long)dev);
  4051. memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
  4052. }
  4053. static int nv_link_test(struct net_device *dev)
  4054. {
  4055. struct fe_priv *np = netdev_priv(dev);
  4056. int mii_status;
  4057. mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4058. mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4059. /* check phy link status */
  4060. if (!(mii_status & BMSR_LSTATUS))
  4061. return 0;
  4062. else
  4063. return 1;
  4064. }
  4065. static int nv_register_test(struct net_device *dev)
  4066. {
  4067. u8 __iomem *base = get_hwbase(dev);
  4068. int i = 0;
  4069. u32 orig_read, new_read;
  4070. do {
  4071. orig_read = readl(base + nv_registers_test[i].reg);
  4072. /* xor with mask to toggle bits */
  4073. orig_read ^= nv_registers_test[i].mask;
  4074. writel(orig_read, base + nv_registers_test[i].reg);
  4075. new_read = readl(base + nv_registers_test[i].reg);
  4076. if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
  4077. return 0;
  4078. /* restore original value */
  4079. orig_read ^= nv_registers_test[i].mask;
  4080. writel(orig_read, base + nv_registers_test[i].reg);
  4081. } while (nv_registers_test[++i].reg != 0);
  4082. return 1;
  4083. }
  4084. static int nv_interrupt_test(struct net_device *dev)
  4085. {
  4086. struct fe_priv *np = netdev_priv(dev);
  4087. u8 __iomem *base = get_hwbase(dev);
  4088. int ret = 1;
  4089. int testcnt;
  4090. u32 save_msi_flags, save_poll_interval = 0;
  4091. if (netif_running(dev)) {
  4092. /* free current irq */
  4093. nv_free_irq(dev);
  4094. save_poll_interval = readl(base+NvRegPollingInterval);
  4095. }
  4096. /* flag to test interrupt handler */
  4097. np->intr_test = 0;
  4098. /* setup test irq */
  4099. save_msi_flags = np->msi_flags;
  4100. np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
  4101. np->msi_flags |= 0x001; /* setup 1 vector */
  4102. if (nv_request_irq(dev, 1))
  4103. return 0;
  4104. /* setup timer interrupt */
  4105. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4106. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4107. nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  4108. /* wait for at least one interrupt */
  4109. msleep(100);
  4110. spin_lock_irq(&np->lock);
  4111. /* flag should be set within ISR */
  4112. testcnt = np->intr_test;
  4113. if (!testcnt)
  4114. ret = 2;
  4115. nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
  4116. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  4117. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4118. else
  4119. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  4120. spin_unlock_irq(&np->lock);
  4121. nv_free_irq(dev);
  4122. np->msi_flags = save_msi_flags;
  4123. if (netif_running(dev)) {
  4124. writel(save_poll_interval, base + NvRegPollingInterval);
  4125. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4126. /* restore original irq */
  4127. if (nv_request_irq(dev, 0))
  4128. return 0;
  4129. }
  4130. return ret;
  4131. }
  4132. static int nv_loopback_test(struct net_device *dev)
  4133. {
  4134. struct fe_priv *np = netdev_priv(dev);
  4135. u8 __iomem *base = get_hwbase(dev);
  4136. struct sk_buff *tx_skb, *rx_skb;
  4137. dma_addr_t test_dma_addr;
  4138. u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
  4139. u32 flags;
  4140. int len, i, pkt_len;
  4141. u8 *pkt_data;
  4142. u32 filter_flags = 0;
  4143. u32 misc1_flags = 0;
  4144. int ret = 1;
  4145. if (netif_running(dev)) {
  4146. nv_disable_irq(dev);
  4147. filter_flags = readl(base + NvRegPacketFilterFlags);
  4148. misc1_flags = readl(base + NvRegMisc1);
  4149. } else {
  4150. nv_txrx_reset(dev);
  4151. }
  4152. /* reinit driver view of the rx queue */
  4153. set_bufsize(dev);
  4154. nv_init_ring(dev);
  4155. /* setup hardware for loopback */
  4156. writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
  4157. writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
  4158. /* reinit nic view of the rx queue */
  4159. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4160. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4161. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4162. base + NvRegRingSizes);
  4163. pci_push(base);
  4164. /* restart rx engine */
  4165. nv_start_rxtx(dev);
  4166. /* setup packet for tx */
  4167. pkt_len = ETH_DATA_LEN;
  4168. tx_skb = dev_alloc_skb(pkt_len);
  4169. if (!tx_skb) {
  4170. netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
  4171. ret = 0;
  4172. goto out;
  4173. }
  4174. test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
  4175. skb_tailroom(tx_skb),
  4176. PCI_DMA_FROMDEVICE);
  4177. pkt_data = skb_put(tx_skb, pkt_len);
  4178. for (i = 0; i < pkt_len; i++)
  4179. pkt_data[i] = (u8)(i & 0xff);
  4180. if (!nv_optimized(np)) {
  4181. np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
  4182. np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  4183. } else {
  4184. np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
  4185. np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
  4186. np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
  4187. }
  4188. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4189. pci_push(get_hwbase(dev));
  4190. msleep(500);
  4191. /* check for rx of the packet */
  4192. if (!nv_optimized(np)) {
  4193. flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
  4194. len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
  4195. } else {
  4196. flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
  4197. len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
  4198. }
  4199. if (flags & NV_RX_AVAIL) {
  4200. ret = 0;
  4201. } else if (np->desc_ver == DESC_VER_1) {
  4202. if (flags & NV_RX_ERROR)
  4203. ret = 0;
  4204. } else {
  4205. if (flags & NV_RX2_ERROR)
  4206. ret = 0;
  4207. }
  4208. if (ret) {
  4209. if (len != pkt_len) {
  4210. ret = 0;
  4211. } else {
  4212. rx_skb = np->rx_skb[0].skb;
  4213. for (i = 0; i < pkt_len; i++) {
  4214. if (rx_skb->data[i] != (u8)(i & 0xff)) {
  4215. ret = 0;
  4216. break;
  4217. }
  4218. }
  4219. }
  4220. }
  4221. pci_unmap_single(np->pci_dev, test_dma_addr,
  4222. (skb_end_pointer(tx_skb) - tx_skb->data),
  4223. PCI_DMA_TODEVICE);
  4224. dev_kfree_skb_any(tx_skb);
  4225. out:
  4226. /* stop engines */
  4227. nv_stop_rxtx(dev);
  4228. nv_txrx_reset(dev);
  4229. /* drain rx queue */
  4230. nv_drain_rxtx(dev);
  4231. if (netif_running(dev)) {
  4232. writel(misc1_flags, base + NvRegMisc1);
  4233. writel(filter_flags, base + NvRegPacketFilterFlags);
  4234. nv_enable_irq(dev);
  4235. }
  4236. return ret;
  4237. }
  4238. static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
  4239. {
  4240. struct fe_priv *np = netdev_priv(dev);
  4241. u8 __iomem *base = get_hwbase(dev);
  4242. int result;
  4243. memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
  4244. if (!nv_link_test(dev)) {
  4245. test->flags |= ETH_TEST_FL_FAILED;
  4246. buffer[0] = 1;
  4247. }
  4248. if (test->flags & ETH_TEST_FL_OFFLINE) {
  4249. if (netif_running(dev)) {
  4250. netif_stop_queue(dev);
  4251. nv_napi_disable(dev);
  4252. netif_tx_lock_bh(dev);
  4253. netif_addr_lock(dev);
  4254. spin_lock_irq(&np->lock);
  4255. nv_disable_hw_interrupts(dev, np->irqmask);
  4256. if (!(np->msi_flags & NV_MSI_X_ENABLED))
  4257. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4258. else
  4259. writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
  4260. /* stop engines */
  4261. nv_stop_rxtx(dev);
  4262. nv_txrx_reset(dev);
  4263. /* drain rx queue */
  4264. nv_drain_rxtx(dev);
  4265. spin_unlock_irq(&np->lock);
  4266. netif_addr_unlock(dev);
  4267. netif_tx_unlock_bh(dev);
  4268. }
  4269. if (!nv_register_test(dev)) {
  4270. test->flags |= ETH_TEST_FL_FAILED;
  4271. buffer[1] = 1;
  4272. }
  4273. result = nv_interrupt_test(dev);
  4274. if (result != 1) {
  4275. test->flags |= ETH_TEST_FL_FAILED;
  4276. buffer[2] = 1;
  4277. }
  4278. if (result == 0) {
  4279. /* bail out */
  4280. return;
  4281. }
  4282. if (!nv_loopback_test(dev)) {
  4283. test->flags |= ETH_TEST_FL_FAILED;
  4284. buffer[3] = 1;
  4285. }
  4286. if (netif_running(dev)) {
  4287. /* reinit driver view of the rx queue */
  4288. set_bufsize(dev);
  4289. if (nv_init_ring(dev)) {
  4290. if (!np->in_shutdown)
  4291. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4292. }
  4293. /* reinit nic view of the rx queue */
  4294. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4295. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4296. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4297. base + NvRegRingSizes);
  4298. pci_push(base);
  4299. writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
  4300. pci_push(base);
  4301. /* restart rx engine */
  4302. nv_start_rxtx(dev);
  4303. netif_start_queue(dev);
  4304. nv_napi_enable(dev);
  4305. nv_enable_hw_interrupts(dev, np->irqmask);
  4306. }
  4307. }
  4308. }
  4309. static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
  4310. {
  4311. switch (stringset) {
  4312. case ETH_SS_STATS:
  4313. memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
  4314. break;
  4315. case ETH_SS_TEST:
  4316. memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
  4317. break;
  4318. }
  4319. }
  4320. static const struct ethtool_ops ops = {
  4321. .get_drvinfo = nv_get_drvinfo,
  4322. .get_link = ethtool_op_get_link,
  4323. .get_wol = nv_get_wol,
  4324. .set_wol = nv_set_wol,
  4325. .get_settings = nv_get_settings,
  4326. .set_settings = nv_set_settings,
  4327. .get_regs_len = nv_get_regs_len,
  4328. .get_regs = nv_get_regs,
  4329. .nway_reset = nv_nway_reset,
  4330. .get_ringparam = nv_get_ringparam,
  4331. .set_ringparam = nv_set_ringparam,
  4332. .get_pauseparam = nv_get_pauseparam,
  4333. .set_pauseparam = nv_set_pauseparam,
  4334. .get_strings = nv_get_strings,
  4335. .get_ethtool_stats = nv_get_ethtool_stats,
  4336. .get_sset_count = nv_get_sset_count,
  4337. .self_test = nv_self_test,
  4338. };
  4339. /* The mgmt unit and driver use a semaphore to access the phy during init */
  4340. static int nv_mgmt_acquire_sema(struct net_device *dev)
  4341. {
  4342. struct fe_priv *np = netdev_priv(dev);
  4343. u8 __iomem *base = get_hwbase(dev);
  4344. int i;
  4345. u32 tx_ctrl, mgmt_sema;
  4346. for (i = 0; i < 10; i++) {
  4347. mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
  4348. if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
  4349. break;
  4350. msleep(500);
  4351. }
  4352. if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
  4353. return 0;
  4354. for (i = 0; i < 2; i++) {
  4355. tx_ctrl = readl(base + NvRegTransmitterControl);
  4356. tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
  4357. writel(tx_ctrl, base + NvRegTransmitterControl);
  4358. /* verify that semaphore was acquired */
  4359. tx_ctrl = readl(base + NvRegTransmitterControl);
  4360. if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
  4361. ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
  4362. np->mgmt_sema = 1;
  4363. return 1;
  4364. } else
  4365. udelay(50);
  4366. }
  4367. return 0;
  4368. }
  4369. static void nv_mgmt_release_sema(struct net_device *dev)
  4370. {
  4371. struct fe_priv *np = netdev_priv(dev);
  4372. u8 __iomem *base = get_hwbase(dev);
  4373. u32 tx_ctrl;
  4374. if (np->driver_data & DEV_HAS_MGMT_UNIT) {
  4375. if (np->mgmt_sema) {
  4376. tx_ctrl = readl(base + NvRegTransmitterControl);
  4377. tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
  4378. writel(tx_ctrl, base + NvRegTransmitterControl);
  4379. }
  4380. }
  4381. }
  4382. static int nv_mgmt_get_version(struct net_device *dev)
  4383. {
  4384. struct fe_priv *np = netdev_priv(dev);
  4385. u8 __iomem *base = get_hwbase(dev);
  4386. u32 data_ready = readl(base + NvRegTransmitterControl);
  4387. u32 data_ready2 = 0;
  4388. unsigned long start;
  4389. int ready = 0;
  4390. writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
  4391. writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
  4392. start = jiffies;
  4393. while (time_before(jiffies, start + 5*HZ)) {
  4394. data_ready2 = readl(base + NvRegTransmitterControl);
  4395. if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
  4396. ready = 1;
  4397. break;
  4398. }
  4399. schedule_timeout_uninterruptible(1);
  4400. }
  4401. if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
  4402. return 0;
  4403. np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
  4404. return 1;
  4405. }
  4406. static int nv_open(struct net_device *dev)
  4407. {
  4408. struct fe_priv *np = netdev_priv(dev);
  4409. u8 __iomem *base = get_hwbase(dev);
  4410. int ret = 1;
  4411. int oom, i;
  4412. u32 low;
  4413. /* power up phy */
  4414. mii_rw(dev, np->phyaddr, MII_BMCR,
  4415. mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
  4416. nv_txrx_gate(dev, false);
  4417. /* erase previous misconfiguration */
  4418. if (np->driver_data & DEV_HAS_POWER_CNTRL)
  4419. nv_mac_reset(dev);
  4420. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4421. writel(0, base + NvRegMulticastAddrB);
  4422. writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
  4423. writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
  4424. writel(0, base + NvRegPacketFilterFlags);
  4425. writel(0, base + NvRegTransmitterControl);
  4426. writel(0, base + NvRegReceiverControl);
  4427. writel(0, base + NvRegAdapterControl);
  4428. if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
  4429. writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
  4430. /* initialize descriptor rings */
  4431. set_bufsize(dev);
  4432. oom = nv_init_ring(dev);
  4433. writel(0, base + NvRegLinkSpeed);
  4434. writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4435. nv_txrx_reset(dev);
  4436. writel(0, base + NvRegUnknownSetupReg6);
  4437. np->in_shutdown = 0;
  4438. /* give hw rings */
  4439. setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
  4440. writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
  4441. base + NvRegRingSizes);
  4442. writel(np->linkspeed, base + NvRegLinkSpeed);
  4443. if (np->desc_ver == DESC_VER_1)
  4444. writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
  4445. else
  4446. writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
  4447. writel(np->txrxctl_bits, base + NvRegTxRxControl);
  4448. writel(np->vlanctl_bits, base + NvRegVlanControl);
  4449. pci_push(base);
  4450. writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
  4451. if (reg_delay(dev, NvRegUnknownSetupReg5,
  4452. NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
  4453. NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
  4454. netdev_info(dev,
  4455. "%s: SetupReg5, Bit 31 remained off\n", __func__);
  4456. writel(0, base + NvRegMIIMask);
  4457. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4458. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4459. writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
  4460. writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
  4461. writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
  4462. writel(np->rx_buf_sz, base + NvRegOffloadConfig);
  4463. writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
  4464. get_random_bytes(&low, sizeof(low));
  4465. low &= NVREG_SLOTTIME_MASK;
  4466. if (np->desc_ver == DESC_VER_1) {
  4467. writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
  4468. } else {
  4469. if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
  4470. /* setup legacy backoff */
  4471. writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
  4472. } else {
  4473. writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
  4474. nv_gear_backoff_reseed(dev);
  4475. }
  4476. }
  4477. writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
  4478. writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
  4479. if (poll_interval == -1) {
  4480. if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
  4481. writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
  4482. else
  4483. writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
  4484. } else
  4485. writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
  4486. writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
  4487. writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
  4488. base + NvRegAdapterControl);
  4489. writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
  4490. writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
  4491. if (np->wolenabled)
  4492. writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
  4493. i = readl(base + NvRegPowerState);
  4494. if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
  4495. writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
  4496. pci_push(base);
  4497. udelay(10);
  4498. writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
  4499. nv_disable_hw_interrupts(dev, np->irqmask);
  4500. pci_push(base);
  4501. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4502. writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
  4503. pci_push(base);
  4504. if (nv_request_irq(dev, 0))
  4505. goto out_drain;
  4506. /* ask for interrupts */
  4507. nv_enable_hw_interrupts(dev, np->irqmask);
  4508. spin_lock_irq(&np->lock);
  4509. writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
  4510. writel(0, base + NvRegMulticastAddrB);
  4511. writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
  4512. writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
  4513. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4514. /* One manual link speed update: Interrupts are enabled, future link
  4515. * speed changes cause interrupts and are handled by nv_link_irq().
  4516. */
  4517. {
  4518. u32 miistat;
  4519. miistat = readl(base + NvRegMIIStatus);
  4520. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4521. }
  4522. /* set linkspeed to invalid value, thus force nv_update_linkspeed
  4523. * to init hw */
  4524. np->linkspeed = 0;
  4525. ret = nv_update_linkspeed(dev);
  4526. nv_start_rxtx(dev);
  4527. netif_start_queue(dev);
  4528. nv_napi_enable(dev);
  4529. if (ret) {
  4530. netif_carrier_on(dev);
  4531. } else {
  4532. netdev_info(dev, "no link during initialization\n");
  4533. netif_carrier_off(dev);
  4534. }
  4535. if (oom)
  4536. mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
  4537. /* start statistics timer */
  4538. if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
  4539. mod_timer(&np->stats_poll,
  4540. round_jiffies(jiffies + STATS_INTERVAL));
  4541. spin_unlock_irq(&np->lock);
  4542. return 0;
  4543. out_drain:
  4544. nv_drain_rxtx(dev);
  4545. return ret;
  4546. }
  4547. static int nv_close(struct net_device *dev)
  4548. {
  4549. struct fe_priv *np = netdev_priv(dev);
  4550. u8 __iomem *base;
  4551. spin_lock_irq(&np->lock);
  4552. np->in_shutdown = 1;
  4553. spin_unlock_irq(&np->lock);
  4554. nv_napi_disable(dev);
  4555. synchronize_irq(np->pci_dev->irq);
  4556. del_timer_sync(&np->oom_kick);
  4557. del_timer_sync(&np->nic_poll);
  4558. del_timer_sync(&np->stats_poll);
  4559. netif_stop_queue(dev);
  4560. spin_lock_irq(&np->lock);
  4561. nv_stop_rxtx(dev);
  4562. nv_txrx_reset(dev);
  4563. /* disable interrupts on the nic or we will lock up */
  4564. base = get_hwbase(dev);
  4565. nv_disable_hw_interrupts(dev, np->irqmask);
  4566. pci_push(base);
  4567. spin_unlock_irq(&np->lock);
  4568. nv_free_irq(dev);
  4569. nv_drain_rxtx(dev);
  4570. if (np->wolenabled || !phy_power_down) {
  4571. nv_txrx_gate(dev, false);
  4572. writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
  4573. nv_start_rx(dev);
  4574. } else {
  4575. /* power down phy */
  4576. mii_rw(dev, np->phyaddr, MII_BMCR,
  4577. mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
  4578. nv_txrx_gate(dev, true);
  4579. }
  4580. /* FIXME: power down nic */
  4581. return 0;
  4582. }
  4583. static const struct net_device_ops nv_netdev_ops = {
  4584. .ndo_open = nv_open,
  4585. .ndo_stop = nv_close,
  4586. .ndo_get_stats = nv_get_stats,
  4587. .ndo_start_xmit = nv_start_xmit,
  4588. .ndo_tx_timeout = nv_tx_timeout,
  4589. .ndo_change_mtu = nv_change_mtu,
  4590. .ndo_fix_features = nv_fix_features,
  4591. .ndo_set_features = nv_set_features,
  4592. .ndo_validate_addr = eth_validate_addr,
  4593. .ndo_set_mac_address = nv_set_mac_address,
  4594. .ndo_set_rx_mode = nv_set_multicast,
  4595. #ifdef CONFIG_NET_POLL_CONTROLLER
  4596. .ndo_poll_controller = nv_poll_controller,
  4597. #endif
  4598. };
  4599. static const struct net_device_ops nv_netdev_ops_optimized = {
  4600. .ndo_open = nv_open,
  4601. .ndo_stop = nv_close,
  4602. .ndo_get_stats = nv_get_stats,
  4603. .ndo_start_xmit = nv_start_xmit_optimized,
  4604. .ndo_tx_timeout = nv_tx_timeout,
  4605. .ndo_change_mtu = nv_change_mtu,
  4606. .ndo_fix_features = nv_fix_features,
  4607. .ndo_set_features = nv_set_features,
  4608. .ndo_validate_addr = eth_validate_addr,
  4609. .ndo_set_mac_address = nv_set_mac_address,
  4610. .ndo_set_rx_mode = nv_set_multicast,
  4611. #ifdef CONFIG_NET_POLL_CONTROLLER
  4612. .ndo_poll_controller = nv_poll_controller,
  4613. #endif
  4614. };
  4615. static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
  4616. {
  4617. struct net_device *dev;
  4618. struct fe_priv *np;
  4619. unsigned long addr;
  4620. u8 __iomem *base;
  4621. int err, i;
  4622. u32 powerstate, txreg;
  4623. u32 phystate_orig = 0, phystate;
  4624. int phyinitialized = 0;
  4625. static int printed_version;
  4626. if (!printed_version++)
  4627. pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
  4628. FORCEDETH_VERSION);
  4629. dev = alloc_etherdev(sizeof(struct fe_priv));
  4630. err = -ENOMEM;
  4631. if (!dev)
  4632. goto out;
  4633. np = netdev_priv(dev);
  4634. np->dev = dev;
  4635. np->pci_dev = pci_dev;
  4636. spin_lock_init(&np->lock);
  4637. SET_NETDEV_DEV(dev, &pci_dev->dev);
  4638. init_timer(&np->oom_kick);
  4639. np->oom_kick.data = (unsigned long) dev;
  4640. np->oom_kick.function = nv_do_rx_refill; /* timer handler */
  4641. init_timer(&np->nic_poll);
  4642. np->nic_poll.data = (unsigned long) dev;
  4643. np->nic_poll.function = nv_do_nic_poll; /* timer handler */
  4644. init_timer(&np->stats_poll);
  4645. np->stats_poll.data = (unsigned long) dev;
  4646. np->stats_poll.function = nv_do_stats_poll; /* timer handler */
  4647. err = pci_enable_device(pci_dev);
  4648. if (err)
  4649. goto out_free;
  4650. pci_set_master(pci_dev);
  4651. err = pci_request_regions(pci_dev, DRV_NAME);
  4652. if (err < 0)
  4653. goto out_disable;
  4654. if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
  4655. np->register_size = NV_PCI_REGSZ_VER3;
  4656. else if (id->driver_data & DEV_HAS_STATISTICS_V1)
  4657. np->register_size = NV_PCI_REGSZ_VER2;
  4658. else
  4659. np->register_size = NV_PCI_REGSZ_VER1;
  4660. err = -EINVAL;
  4661. addr = 0;
  4662. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  4663. if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
  4664. pci_resource_len(pci_dev, i) >= np->register_size) {
  4665. addr = pci_resource_start(pci_dev, i);
  4666. break;
  4667. }
  4668. }
  4669. if (i == DEVICE_COUNT_RESOURCE) {
  4670. dev_info(&pci_dev->dev, "Couldn't find register window\n");
  4671. goto out_relreg;
  4672. }
  4673. /* copy of driver data */
  4674. np->driver_data = id->driver_data;
  4675. /* copy of device id */
  4676. np->device_id = id->device;
  4677. /* handle different descriptor versions */
  4678. if (id->driver_data & DEV_HAS_HIGH_DMA) {
  4679. /* packet format 3: supports 40-bit addressing */
  4680. np->desc_ver = DESC_VER_3;
  4681. np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
  4682. if (dma_64bit) {
  4683. if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
  4684. dev_info(&pci_dev->dev,
  4685. "64-bit DMA failed, using 32-bit addressing\n");
  4686. else
  4687. dev->features |= NETIF_F_HIGHDMA;
  4688. if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
  4689. dev_info(&pci_dev->dev,
  4690. "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
  4691. }
  4692. }
  4693. } else if (id->driver_data & DEV_HAS_LARGEDESC) {
  4694. /* packet format 2: supports jumbo frames */
  4695. np->desc_ver = DESC_VER_2;
  4696. np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
  4697. } else {
  4698. /* original packet format */
  4699. np->desc_ver = DESC_VER_1;
  4700. np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
  4701. }
  4702. np->pkt_limit = NV_PKTLIMIT_1;
  4703. if (id->driver_data & DEV_HAS_LARGEDESC)
  4704. np->pkt_limit = NV_PKTLIMIT_2;
  4705. if (id->driver_data & DEV_HAS_CHECKSUM) {
  4706. np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
  4707. dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
  4708. NETIF_F_TSO | NETIF_F_RXCSUM;
  4709. }
  4710. np->vlanctl_bits = 0;
  4711. if (id->driver_data & DEV_HAS_VLAN) {
  4712. np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
  4713. dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
  4714. }
  4715. dev->features |= dev->hw_features;
  4716. np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
  4717. if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
  4718. (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
  4719. (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
  4720. np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
  4721. }
  4722. err = -ENOMEM;
  4723. np->base = ioremap(addr, np->register_size);
  4724. if (!np->base)
  4725. goto out_relreg;
  4726. dev->base_addr = (unsigned long)np->base;
  4727. dev->irq = pci_dev->irq;
  4728. np->rx_ring_size = RX_RING_DEFAULT;
  4729. np->tx_ring_size = TX_RING_DEFAULT;
  4730. if (!nv_optimized(np)) {
  4731. np->rx_ring.orig = pci_alloc_consistent(pci_dev,
  4732. sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
  4733. &np->ring_addr);
  4734. if (!np->rx_ring.orig)
  4735. goto out_unmap;
  4736. np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
  4737. } else {
  4738. np->rx_ring.ex = pci_alloc_consistent(pci_dev,
  4739. sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
  4740. &np->ring_addr);
  4741. if (!np->rx_ring.ex)
  4742. goto out_unmap;
  4743. np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
  4744. }
  4745. np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
  4746. np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
  4747. if (!np->rx_skb || !np->tx_skb)
  4748. goto out_freering;
  4749. if (!nv_optimized(np))
  4750. dev->netdev_ops = &nv_netdev_ops;
  4751. else
  4752. dev->netdev_ops = &nv_netdev_ops_optimized;
  4753. netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
  4754. SET_ETHTOOL_OPS(dev, &ops);
  4755. dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
  4756. pci_set_drvdata(pci_dev, dev);
  4757. /* read the mac address */
  4758. base = get_hwbase(dev);
  4759. np->orig_mac[0] = readl(base + NvRegMacAddrA);
  4760. np->orig_mac[1] = readl(base + NvRegMacAddrB);
  4761. /* check the workaround bit for correct mac address order */
  4762. txreg = readl(base + NvRegTransmitPoll);
  4763. if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
  4764. /* mac address is already in correct order */
  4765. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4766. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4767. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4768. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4769. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4770. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4771. } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
  4772. /* mac address is already in correct order */
  4773. dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
  4774. dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
  4775. dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
  4776. dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
  4777. dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
  4778. dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
  4779. /*
  4780. * Set orig mac address back to the reversed version.
  4781. * This flag will be cleared during low power transition.
  4782. * Therefore, we should always put back the reversed address.
  4783. */
  4784. np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
  4785. (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
  4786. np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
  4787. } else {
  4788. /* need to reverse mac address to correct order */
  4789. dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
  4790. dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
  4791. dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
  4792. dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
  4793. dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
  4794. dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
  4795. writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
  4796. dev_dbg(&pci_dev->dev,
  4797. "%s: set workaround bit for reversed mac addr\n",
  4798. __func__);
  4799. }
  4800. memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  4801. if (!is_valid_ether_addr(dev->perm_addr)) {
  4802. /*
  4803. * Bad mac address. At least one bios sets the mac address
  4804. * to 01:23:45:67:89:ab
  4805. */
  4806. dev_err(&pci_dev->dev,
  4807. "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
  4808. dev->dev_addr);
  4809. random_ether_addr(dev->dev_addr);
  4810. dev_err(&pci_dev->dev,
  4811. "Using random MAC address: %pM\n", dev->dev_addr);
  4812. }
  4813. /* set mac address */
  4814. nv_copy_mac_to_hw(dev);
  4815. /* disable WOL */
  4816. writel(0, base + NvRegWakeUpFlags);
  4817. np->wolenabled = 0;
  4818. device_set_wakeup_enable(&pci_dev->dev, false);
  4819. if (id->driver_data & DEV_HAS_POWER_CNTRL) {
  4820. /* take phy and nic out of low power mode */
  4821. powerstate = readl(base + NvRegPowerState2);
  4822. powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
  4823. if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
  4824. pci_dev->revision >= 0xA3)
  4825. powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
  4826. writel(powerstate, base + NvRegPowerState2);
  4827. }
  4828. if (np->desc_ver == DESC_VER_1)
  4829. np->tx_flags = NV_TX_VALID;
  4830. else
  4831. np->tx_flags = NV_TX2_VALID;
  4832. np->msi_flags = 0;
  4833. if ((id->driver_data & DEV_HAS_MSI) && msi)
  4834. np->msi_flags |= NV_MSI_CAPABLE;
  4835. if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
  4836. /* msix has had reported issues when modifying irqmask
  4837. as in the case of napi, therefore, disable for now
  4838. */
  4839. #if 0
  4840. np->msi_flags |= NV_MSI_X_CAPABLE;
  4841. #endif
  4842. }
  4843. if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
  4844. np->irqmask = NVREG_IRQMASK_CPU;
  4845. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  4846. np->msi_flags |= 0x0001;
  4847. } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
  4848. !(id->driver_data & DEV_NEED_TIMERIRQ)) {
  4849. /* start off in throughput mode */
  4850. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  4851. /* remove support for msix mode */
  4852. np->msi_flags &= ~NV_MSI_X_CAPABLE;
  4853. } else {
  4854. optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
  4855. np->irqmask = NVREG_IRQMASK_THROUGHPUT;
  4856. if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
  4857. np->msi_flags |= 0x0003;
  4858. }
  4859. if (id->driver_data & DEV_NEED_TIMERIRQ)
  4860. np->irqmask |= NVREG_IRQ_TIMER;
  4861. if (id->driver_data & DEV_NEED_LINKTIMER) {
  4862. np->need_linktimer = 1;
  4863. np->link_timeout = jiffies + LINK_TIMEOUT;
  4864. } else {
  4865. np->need_linktimer = 0;
  4866. }
  4867. /* Limit the number of tx's outstanding for hw bug */
  4868. if (id->driver_data & DEV_NEED_TX_LIMIT) {
  4869. np->tx_limit = 1;
  4870. if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
  4871. pci_dev->revision >= 0xA2)
  4872. np->tx_limit = 0;
  4873. }
  4874. /* clear phy state and temporarily halt phy interrupts */
  4875. writel(0, base + NvRegMIIMask);
  4876. phystate = readl(base + NvRegAdapterControl);
  4877. if (phystate & NVREG_ADAPTCTL_RUNNING) {
  4878. phystate_orig = 1;
  4879. phystate &= ~NVREG_ADAPTCTL_RUNNING;
  4880. writel(phystate, base + NvRegAdapterControl);
  4881. }
  4882. writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
  4883. if (id->driver_data & DEV_HAS_MGMT_UNIT) {
  4884. /* management unit running on the mac? */
  4885. if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
  4886. (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
  4887. nv_mgmt_acquire_sema(dev) &&
  4888. nv_mgmt_get_version(dev)) {
  4889. np->mac_in_use = 1;
  4890. if (np->mgmt_version > 0)
  4891. np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
  4892. /* management unit setup the phy already? */
  4893. if (np->mac_in_use &&
  4894. ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
  4895. NVREG_XMITCTL_SYNC_PHY_INIT)) {
  4896. /* phy is inited by mgmt unit */
  4897. phyinitialized = 1;
  4898. } else {
  4899. /* we need to init the phy */
  4900. }
  4901. }
  4902. }
  4903. /* find a suitable phy */
  4904. for (i = 1; i <= 32; i++) {
  4905. int id1, id2;
  4906. int phyaddr = i & 0x1F;
  4907. spin_lock_irq(&np->lock);
  4908. id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
  4909. spin_unlock_irq(&np->lock);
  4910. if (id1 < 0 || id1 == 0xffff)
  4911. continue;
  4912. spin_lock_irq(&np->lock);
  4913. id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
  4914. spin_unlock_irq(&np->lock);
  4915. if (id2 < 0 || id2 == 0xffff)
  4916. continue;
  4917. np->phy_model = id2 & PHYID2_MODEL_MASK;
  4918. id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
  4919. id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
  4920. np->phyaddr = phyaddr;
  4921. np->phy_oui = id1 | id2;
  4922. /* Realtek hardcoded phy id1 to all zero's on certain phys */
  4923. if (np->phy_oui == PHY_OUI_REALTEK2)
  4924. np->phy_oui = PHY_OUI_REALTEK;
  4925. /* Setup phy revision for Realtek */
  4926. if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
  4927. np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
  4928. break;
  4929. }
  4930. if (i == 33) {
  4931. dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
  4932. goto out_error;
  4933. }
  4934. if (!phyinitialized) {
  4935. /* reset it */
  4936. phy_init(dev);
  4937. } else {
  4938. /* see if it is a gigabit phy */
  4939. u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
  4940. if (mii_status & PHY_GIGABIT)
  4941. np->gigabit = PHY_GIGABIT;
  4942. }
  4943. /* set default link speed settings */
  4944. np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
  4945. np->duplex = 0;
  4946. np->autoneg = 1;
  4947. err = register_netdev(dev);
  4948. if (err) {
  4949. dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
  4950. goto out_error;
  4951. }
  4952. if (id->driver_data & DEV_HAS_VLAN)
  4953. nv_vlan_mode(dev, dev->features);
  4954. netif_carrier_off(dev);
  4955. dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
  4956. dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
  4957. dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
  4958. dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
  4959. dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
  4960. "csum " : "",
  4961. dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
  4962. "vlan " : "",
  4963. id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
  4964. id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
  4965. id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
  4966. np->gigabit == PHY_GIGABIT ? "gbit " : "",
  4967. np->need_linktimer ? "lnktim " : "",
  4968. np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
  4969. np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
  4970. np->desc_ver);
  4971. return 0;
  4972. out_error:
  4973. if (phystate_orig)
  4974. writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
  4975. pci_set_drvdata(pci_dev, NULL);
  4976. out_freering:
  4977. free_rings(dev);
  4978. out_unmap:
  4979. iounmap(get_hwbase(dev));
  4980. out_relreg:
  4981. pci_release_regions(pci_dev);
  4982. out_disable:
  4983. pci_disable_device(pci_dev);
  4984. out_free:
  4985. free_netdev(dev);
  4986. out:
  4987. return err;
  4988. }
  4989. static void nv_restore_phy(struct net_device *dev)
  4990. {
  4991. struct fe_priv *np = netdev_priv(dev);
  4992. u16 phy_reserved, mii_control;
  4993. if (np->phy_oui == PHY_OUI_REALTEK &&
  4994. np->phy_model == PHY_MODEL_REALTEK_8201 &&
  4995. phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
  4996. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
  4997. phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
  4998. phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
  4999. phy_reserved |= PHY_REALTEK_INIT8;
  5000. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
  5001. mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
  5002. /* restart auto negotiation */
  5003. mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
  5004. mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
  5005. mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
  5006. }
  5007. }
  5008. static void nv_restore_mac_addr(struct pci_dev *pci_dev)
  5009. {
  5010. struct net_device *dev = pci_get_drvdata(pci_dev);
  5011. struct fe_priv *np = netdev_priv(dev);
  5012. u8 __iomem *base = get_hwbase(dev);
  5013. /* special op: write back the misordered MAC address - otherwise
  5014. * the next nv_probe would see a wrong address.
  5015. */
  5016. writel(np->orig_mac[0], base + NvRegMacAddrA);
  5017. writel(np->orig_mac[1], base + NvRegMacAddrB);
  5018. writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
  5019. base + NvRegTransmitPoll);
  5020. }
  5021. static void __devexit nv_remove(struct pci_dev *pci_dev)
  5022. {
  5023. struct net_device *dev = pci_get_drvdata(pci_dev);
  5024. unregister_netdev(dev);
  5025. nv_restore_mac_addr(pci_dev);
  5026. /* restore any phy related changes */
  5027. nv_restore_phy(dev);
  5028. nv_mgmt_release_sema(dev);
  5029. /* free all structures */
  5030. free_rings(dev);
  5031. iounmap(get_hwbase(dev));
  5032. pci_release_regions(pci_dev);
  5033. pci_disable_device(pci_dev);
  5034. free_netdev(dev);
  5035. pci_set_drvdata(pci_dev, NULL);
  5036. }
  5037. #ifdef CONFIG_PM_SLEEP
  5038. static int nv_suspend(struct device *device)
  5039. {
  5040. struct pci_dev *pdev = to_pci_dev(device);
  5041. struct net_device *dev = pci_get_drvdata(pdev);
  5042. struct fe_priv *np = netdev_priv(dev);
  5043. u8 __iomem *base = get_hwbase(dev);
  5044. int i;
  5045. if (netif_running(dev)) {
  5046. /* Gross. */
  5047. nv_close(dev);
  5048. }
  5049. netif_device_detach(dev);
  5050. /* save non-pci configuration space */
  5051. for (i = 0; i <= np->register_size/sizeof(u32); i++)
  5052. np->saved_config_space[i] = readl(base + i*sizeof(u32));
  5053. return 0;
  5054. }
  5055. static int nv_resume(struct device *device)
  5056. {
  5057. struct pci_dev *pdev = to_pci_dev(device);
  5058. struct net_device *dev = pci_get_drvdata(pdev);
  5059. struct fe_priv *np = netdev_priv(dev);
  5060. u8 __iomem *base = get_hwbase(dev);
  5061. int i, rc = 0;
  5062. /* restore non-pci configuration space */
  5063. for (i = 0; i <= np->register_size/sizeof(u32); i++)
  5064. writel(np->saved_config_space[i], base+i*sizeof(u32));
  5065. if (np->driver_data & DEV_NEED_MSI_FIX)
  5066. pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
  5067. /* restore phy state, including autoneg */
  5068. phy_init(dev);
  5069. netif_device_attach(dev);
  5070. if (netif_running(dev)) {
  5071. rc = nv_open(dev);
  5072. nv_set_multicast(dev);
  5073. }
  5074. return rc;
  5075. }
  5076. static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
  5077. #define NV_PM_OPS (&nv_pm_ops)
  5078. #else
  5079. #define NV_PM_OPS NULL
  5080. #endif /* CONFIG_PM_SLEEP */
  5081. #ifdef CONFIG_PM
  5082. static void nv_shutdown(struct pci_dev *pdev)
  5083. {
  5084. struct net_device *dev = pci_get_drvdata(pdev);
  5085. struct fe_priv *np = netdev_priv(dev);
  5086. if (netif_running(dev))
  5087. nv_close(dev);
  5088. /*
  5089. * Restore the MAC so a kernel started by kexec won't get confused.
  5090. * If we really go for poweroff, we must not restore the MAC,
  5091. * otherwise the MAC for WOL will be reversed at least on some boards.
  5092. */
  5093. if (system_state != SYSTEM_POWER_OFF)
  5094. nv_restore_mac_addr(pdev);
  5095. pci_disable_device(pdev);
  5096. /*
  5097. * Apparently it is not possible to reinitialise from D3 hot,
  5098. * only put the device into D3 if we really go for poweroff.
  5099. */
  5100. if (system_state == SYSTEM_POWER_OFF) {
  5101. pci_wake_from_d3(pdev, np->wolenabled);
  5102. pci_set_power_state(pdev, PCI_D3hot);
  5103. }
  5104. }
  5105. #else
  5106. #define nv_shutdown NULL
  5107. #endif /* CONFIG_PM */
  5108. static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
  5109. { /* nForce Ethernet Controller */
  5110. PCI_DEVICE(0x10DE, 0x01C3),
  5111. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5112. },
  5113. { /* nForce2 Ethernet Controller */
  5114. PCI_DEVICE(0x10DE, 0x0066),
  5115. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5116. },
  5117. { /* nForce3 Ethernet Controller */
  5118. PCI_DEVICE(0x10DE, 0x00D6),
  5119. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
  5120. },
  5121. { /* nForce3 Ethernet Controller */
  5122. PCI_DEVICE(0x10DE, 0x0086),
  5123. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5124. },
  5125. { /* nForce3 Ethernet Controller */
  5126. PCI_DEVICE(0x10DE, 0x008C),
  5127. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5128. },
  5129. { /* nForce3 Ethernet Controller */
  5130. PCI_DEVICE(0x10DE, 0x00E6),
  5131. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5132. },
  5133. { /* nForce3 Ethernet Controller */
  5134. PCI_DEVICE(0x10DE, 0x00DF),
  5135. .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
  5136. },
  5137. { /* CK804 Ethernet Controller */
  5138. PCI_DEVICE(0x10DE, 0x0056),
  5139. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5140. },
  5141. { /* CK804 Ethernet Controller */
  5142. PCI_DEVICE(0x10DE, 0x0057),
  5143. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5144. },
  5145. { /* MCP04 Ethernet Controller */
  5146. PCI_DEVICE(0x10DE, 0x0037),
  5147. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5148. },
  5149. { /* MCP04 Ethernet Controller */
  5150. PCI_DEVICE(0x10DE, 0x0038),
  5151. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
  5152. },
  5153. { /* MCP51 Ethernet Controller */
  5154. PCI_DEVICE(0x10DE, 0x0268),
  5155. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
  5156. },
  5157. { /* MCP51 Ethernet Controller */
  5158. PCI_DEVICE(0x10DE, 0x0269),
  5159. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
  5160. },
  5161. { /* MCP55 Ethernet Controller */
  5162. PCI_DEVICE(0x10DE, 0x0372),
  5163. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
  5164. },
  5165. { /* MCP55 Ethernet Controller */
  5166. PCI_DEVICE(0x10DE, 0x0373),
  5167. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
  5168. },
  5169. { /* MCP61 Ethernet Controller */
  5170. PCI_DEVICE(0x10DE, 0x03E5),
  5171. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5172. },
  5173. { /* MCP61 Ethernet Controller */
  5174. PCI_DEVICE(0x10DE, 0x03E6),
  5175. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5176. },
  5177. { /* MCP61 Ethernet Controller */
  5178. PCI_DEVICE(0x10DE, 0x03EE),
  5179. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5180. },
  5181. { /* MCP61 Ethernet Controller */
  5182. PCI_DEVICE(0x10DE, 0x03EF),
  5183. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
  5184. },
  5185. { /* MCP65 Ethernet Controller */
  5186. PCI_DEVICE(0x10DE, 0x0450),
  5187. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5188. },
  5189. { /* MCP65 Ethernet Controller */
  5190. PCI_DEVICE(0x10DE, 0x0451),
  5191. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5192. },
  5193. { /* MCP65 Ethernet Controller */
  5194. PCI_DEVICE(0x10DE, 0x0452),
  5195. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5196. },
  5197. { /* MCP65 Ethernet Controller */
  5198. PCI_DEVICE(0x10DE, 0x0453),
  5199. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5200. },
  5201. { /* MCP67 Ethernet Controller */
  5202. PCI_DEVICE(0x10DE, 0x054C),
  5203. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5204. },
  5205. { /* MCP67 Ethernet Controller */
  5206. PCI_DEVICE(0x10DE, 0x054D),
  5207. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5208. },
  5209. { /* MCP67 Ethernet Controller */
  5210. PCI_DEVICE(0x10DE, 0x054E),
  5211. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5212. },
  5213. { /* MCP67 Ethernet Controller */
  5214. PCI_DEVICE(0x10DE, 0x054F),
  5215. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5216. },
  5217. { /* MCP73 Ethernet Controller */
  5218. PCI_DEVICE(0x10DE, 0x07DC),
  5219. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5220. },
  5221. { /* MCP73 Ethernet Controller */
  5222. PCI_DEVICE(0x10DE, 0x07DD),
  5223. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5224. },
  5225. { /* MCP73 Ethernet Controller */
  5226. PCI_DEVICE(0x10DE, 0x07DE),
  5227. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5228. },
  5229. { /* MCP73 Ethernet Controller */
  5230. PCI_DEVICE(0x10DE, 0x07DF),
  5231. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
  5232. },
  5233. { /* MCP77 Ethernet Controller */
  5234. PCI_DEVICE(0x10DE, 0x0760),
  5235. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5236. },
  5237. { /* MCP77 Ethernet Controller */
  5238. PCI_DEVICE(0x10DE, 0x0761),
  5239. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5240. },
  5241. { /* MCP77 Ethernet Controller */
  5242. PCI_DEVICE(0x10DE, 0x0762),
  5243. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5244. },
  5245. { /* MCP77 Ethernet Controller */
  5246. PCI_DEVICE(0x10DE, 0x0763),
  5247. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5248. },
  5249. { /* MCP79 Ethernet Controller */
  5250. PCI_DEVICE(0x10DE, 0x0AB0),
  5251. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5252. },
  5253. { /* MCP79 Ethernet Controller */
  5254. PCI_DEVICE(0x10DE, 0x0AB1),
  5255. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5256. },
  5257. { /* MCP79 Ethernet Controller */
  5258. PCI_DEVICE(0x10DE, 0x0AB2),
  5259. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5260. },
  5261. { /* MCP79 Ethernet Controller */
  5262. PCI_DEVICE(0x10DE, 0x0AB3),
  5263. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
  5264. },
  5265. { /* MCP89 Ethernet Controller */
  5266. PCI_DEVICE(0x10DE, 0x0D7D),
  5267. .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
  5268. },
  5269. {0,},
  5270. };
  5271. static struct pci_driver driver = {
  5272. .name = DRV_NAME,
  5273. .id_table = pci_tbl,
  5274. .probe = nv_probe,
  5275. .remove = __devexit_p(nv_remove),
  5276. .shutdown = nv_shutdown,
  5277. .driver.pm = NV_PM_OPS,
  5278. };
  5279. static int __init init_nic(void)
  5280. {
  5281. return pci_register_driver(&driver);
  5282. }
  5283. static void __exit exit_nic(void)
  5284. {
  5285. pci_unregister_driver(&driver);
  5286. }
  5287. module_param(max_interrupt_work, int, 0);
  5288. MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
  5289. module_param(optimization_mode, int, 0);
  5290. MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
  5291. module_param(poll_interval, int, 0);
  5292. MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
  5293. module_param(msi, int, 0);
  5294. MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
  5295. module_param(msix, int, 0);
  5296. MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
  5297. module_param(dma_64bit, int, 0);
  5298. MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
  5299. module_param(phy_cross, int, 0);
  5300. MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
  5301. module_param(phy_power_down, int, 0);
  5302. MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
  5303. MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
  5304. MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
  5305. MODULE_LICENSE("GPL");
  5306. MODULE_DEVICE_TABLE(pci, pci_tbl);
  5307. module_init(init_nic);
  5308. module_exit(exit_nic);