intel_hdmi.c 28 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042
  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2009 Intel Corporation
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Jesse Barnes <jesse.barnes@intel.com>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include "drmP.h"
  32. #include "drm.h"
  33. #include "drm_crtc.h"
  34. #include "drm_edid.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. static void
  39. assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  40. {
  41. struct drm_device *dev = intel_hdmi->base.base.dev;
  42. struct drm_i915_private *dev_priv = dev->dev_private;
  43. uint32_t enabled_bits;
  44. enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  45. WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
  46. "HDMI port enabled, expecting disabled\n");
  47. }
  48. struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  49. {
  50. return container_of(encoder, struct intel_hdmi, base.base);
  51. }
  52. static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  53. {
  54. return container_of(intel_attached_encoder(connector),
  55. struct intel_hdmi, base);
  56. }
  57. void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  58. {
  59. uint8_t *data = (uint8_t *)frame;
  60. uint8_t sum = 0;
  61. unsigned i;
  62. frame->checksum = 0;
  63. frame->ecc = 0;
  64. for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  65. sum += data[i];
  66. frame->checksum = 0x100 - sum;
  67. }
  68. static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  69. {
  70. switch (frame->type) {
  71. case DIP_TYPE_AVI:
  72. return VIDEO_DIP_SELECT_AVI;
  73. case DIP_TYPE_SPD:
  74. return VIDEO_DIP_SELECT_SPD;
  75. default:
  76. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  77. return 0;
  78. }
  79. }
  80. static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  81. {
  82. switch (frame->type) {
  83. case DIP_TYPE_AVI:
  84. return VIDEO_DIP_ENABLE_AVI;
  85. case DIP_TYPE_SPD:
  86. return VIDEO_DIP_ENABLE_SPD;
  87. default:
  88. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  89. return 0;
  90. }
  91. }
  92. static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
  93. {
  94. switch (frame->type) {
  95. case DIP_TYPE_AVI:
  96. return VIDEO_DIP_ENABLE_AVI_HSW;
  97. case DIP_TYPE_SPD:
  98. return VIDEO_DIP_ENABLE_SPD_HSW;
  99. default:
  100. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  101. return 0;
  102. }
  103. }
  104. static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
  105. {
  106. switch (frame->type) {
  107. case DIP_TYPE_AVI:
  108. return HSW_TVIDEO_DIP_AVI_DATA(pipe);
  109. case DIP_TYPE_SPD:
  110. return HSW_TVIDEO_DIP_SPD_DATA(pipe);
  111. default:
  112. DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  113. return 0;
  114. }
  115. }
  116. static void g4x_write_infoframe(struct drm_encoder *encoder,
  117. struct dip_infoframe *frame)
  118. {
  119. uint32_t *data = (uint32_t *)frame;
  120. struct drm_device *dev = encoder->dev;
  121. struct drm_i915_private *dev_priv = dev->dev_private;
  122. u32 val = I915_READ(VIDEO_DIP_CTL);
  123. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  124. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  125. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  126. val |= g4x_infoframe_index(frame);
  127. val &= ~g4x_infoframe_enable(frame);
  128. I915_WRITE(VIDEO_DIP_CTL, val);
  129. mmiowb();
  130. for (i = 0; i < len; i += 4) {
  131. I915_WRITE(VIDEO_DIP_DATA, *data);
  132. data++;
  133. }
  134. mmiowb();
  135. val |= g4x_infoframe_enable(frame);
  136. val &= ~VIDEO_DIP_FREQ_MASK;
  137. val |= VIDEO_DIP_FREQ_VSYNC;
  138. I915_WRITE(VIDEO_DIP_CTL, val);
  139. POSTING_READ(VIDEO_DIP_CTL);
  140. }
  141. static void ibx_write_infoframe(struct drm_encoder *encoder,
  142. struct dip_infoframe *frame)
  143. {
  144. uint32_t *data = (uint32_t *)frame;
  145. struct drm_device *dev = encoder->dev;
  146. struct drm_i915_private *dev_priv = dev->dev_private;
  147. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  148. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  149. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  150. u32 val = I915_READ(reg);
  151. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  152. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  153. val |= g4x_infoframe_index(frame);
  154. val &= ~g4x_infoframe_enable(frame);
  155. I915_WRITE(reg, val);
  156. mmiowb();
  157. for (i = 0; i < len; i += 4) {
  158. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  159. data++;
  160. }
  161. mmiowb();
  162. val |= g4x_infoframe_enable(frame);
  163. val &= ~VIDEO_DIP_FREQ_MASK;
  164. val |= VIDEO_DIP_FREQ_VSYNC;
  165. I915_WRITE(reg, val);
  166. POSTING_READ(reg);
  167. }
  168. static void cpt_write_infoframe(struct drm_encoder *encoder,
  169. struct dip_infoframe *frame)
  170. {
  171. uint32_t *data = (uint32_t *)frame;
  172. struct drm_device *dev = encoder->dev;
  173. struct drm_i915_private *dev_priv = dev->dev_private;
  174. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  175. int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  176. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  177. u32 val = I915_READ(reg);
  178. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  179. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  180. val |= g4x_infoframe_index(frame);
  181. /* The DIP control register spec says that we need to update the AVI
  182. * infoframe without clearing its enable bit */
  183. if (frame->type != DIP_TYPE_AVI)
  184. val &= ~g4x_infoframe_enable(frame);
  185. I915_WRITE(reg, val);
  186. mmiowb();
  187. for (i = 0; i < len; i += 4) {
  188. I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  189. data++;
  190. }
  191. mmiowb();
  192. val |= g4x_infoframe_enable(frame);
  193. val &= ~VIDEO_DIP_FREQ_MASK;
  194. val |= VIDEO_DIP_FREQ_VSYNC;
  195. I915_WRITE(reg, val);
  196. POSTING_READ(reg);
  197. }
  198. static void vlv_write_infoframe(struct drm_encoder *encoder,
  199. struct dip_infoframe *frame)
  200. {
  201. uint32_t *data = (uint32_t *)frame;
  202. struct drm_device *dev = encoder->dev;
  203. struct drm_i915_private *dev_priv = dev->dev_private;
  204. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  205. int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  206. unsigned i, len = DIP_HEADER_SIZE + frame->len;
  207. u32 val = I915_READ(reg);
  208. WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
  209. val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
  210. val |= g4x_infoframe_index(frame);
  211. val &= ~g4x_infoframe_enable(frame);
  212. I915_WRITE(reg, val);
  213. mmiowb();
  214. for (i = 0; i < len; i += 4) {
  215. I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
  216. data++;
  217. }
  218. mmiowb();
  219. val |= g4x_infoframe_enable(frame);
  220. val &= ~VIDEO_DIP_FREQ_MASK;
  221. val |= VIDEO_DIP_FREQ_VSYNC;
  222. I915_WRITE(reg, val);
  223. POSTING_READ(reg);
  224. }
  225. static void hsw_write_infoframe(struct drm_encoder *encoder,
  226. struct dip_infoframe *frame)
  227. {
  228. uint32_t *data = (uint32_t *)frame;
  229. struct drm_device *dev = encoder->dev;
  230. struct drm_i915_private *dev_priv = dev->dev_private;
  231. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  232. u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  233. u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
  234. unsigned int i, len = DIP_HEADER_SIZE + frame->len;
  235. u32 val = I915_READ(ctl_reg);
  236. if (data_reg == 0)
  237. return;
  238. val &= ~hsw_infoframe_enable(frame);
  239. I915_WRITE(ctl_reg, val);
  240. mmiowb();
  241. for (i = 0; i < len; i += 4) {
  242. I915_WRITE(data_reg + i, *data);
  243. data++;
  244. }
  245. mmiowb();
  246. val |= hsw_infoframe_enable(frame);
  247. I915_WRITE(ctl_reg, val);
  248. POSTING_READ(ctl_reg);
  249. }
  250. static void intel_set_infoframe(struct drm_encoder *encoder,
  251. struct dip_infoframe *frame)
  252. {
  253. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  254. intel_dip_infoframe_csum(frame);
  255. intel_hdmi->write_infoframe(encoder, frame);
  256. }
  257. static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
  258. struct drm_display_mode *adjusted_mode)
  259. {
  260. struct dip_infoframe avi_if = {
  261. .type = DIP_TYPE_AVI,
  262. .ver = DIP_VERSION_AVI,
  263. .len = DIP_LEN_AVI,
  264. };
  265. if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  266. avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
  267. intel_set_infoframe(encoder, &avi_if);
  268. }
  269. static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
  270. {
  271. struct dip_infoframe spd_if;
  272. memset(&spd_if, 0, sizeof(spd_if));
  273. spd_if.type = DIP_TYPE_SPD;
  274. spd_if.ver = DIP_VERSION_SPD;
  275. spd_if.len = DIP_LEN_SPD;
  276. strcpy(spd_if.body.spd.vn, "Intel");
  277. strcpy(spd_if.body.spd.pd, "Integrated gfx");
  278. spd_if.body.spd.sdi = DIP_SPD_PC;
  279. intel_set_infoframe(encoder, &spd_if);
  280. }
  281. static void g4x_set_infoframes(struct drm_encoder *encoder,
  282. struct drm_display_mode *adjusted_mode)
  283. {
  284. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  285. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  286. u32 reg = VIDEO_DIP_CTL;
  287. u32 val = I915_READ(reg);
  288. u32 port;
  289. assert_hdmi_port_disabled(intel_hdmi);
  290. /* If the registers were not initialized yet, they might be zeroes,
  291. * which means we're selecting the AVI DIP and we're setting its
  292. * frequency to once. This seems to really confuse the HW and make
  293. * things stop working (the register spec says the AVI always needs to
  294. * be sent every VSync). So here we avoid writing to the register more
  295. * than we need and also explicitly select the AVI DIP and explicitly
  296. * set its frequency to every VSync. Avoiding to write it twice seems to
  297. * be enough to solve the problem, but being defensive shouldn't hurt us
  298. * either. */
  299. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  300. if (!intel_hdmi->has_hdmi_sink) {
  301. if (!(val & VIDEO_DIP_ENABLE))
  302. return;
  303. val &= ~VIDEO_DIP_ENABLE;
  304. I915_WRITE(reg, val);
  305. POSTING_READ(reg);
  306. return;
  307. }
  308. switch (intel_hdmi->sdvox_reg) {
  309. case SDVOB:
  310. port = VIDEO_DIP_PORT_B;
  311. break;
  312. case SDVOC:
  313. port = VIDEO_DIP_PORT_C;
  314. break;
  315. default:
  316. return;
  317. }
  318. if (port != (val & VIDEO_DIP_PORT_MASK)) {
  319. if (val & VIDEO_DIP_ENABLE) {
  320. val &= ~VIDEO_DIP_ENABLE;
  321. I915_WRITE(reg, val);
  322. POSTING_READ(reg);
  323. }
  324. val &= ~VIDEO_DIP_PORT_MASK;
  325. val |= port;
  326. }
  327. val |= VIDEO_DIP_ENABLE;
  328. val &= ~VIDEO_DIP_ENABLE_VENDOR;
  329. I915_WRITE(reg, val);
  330. POSTING_READ(reg);
  331. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  332. intel_hdmi_set_spd_infoframe(encoder);
  333. }
  334. static void ibx_set_infoframes(struct drm_encoder *encoder,
  335. struct drm_display_mode *adjusted_mode)
  336. {
  337. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  338. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  339. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  340. u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  341. u32 val = I915_READ(reg);
  342. u32 port;
  343. assert_hdmi_port_disabled(intel_hdmi);
  344. /* See the big comment in g4x_set_infoframes() */
  345. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  346. if (!intel_hdmi->has_hdmi_sink) {
  347. if (!(val & VIDEO_DIP_ENABLE))
  348. return;
  349. val &= ~VIDEO_DIP_ENABLE;
  350. I915_WRITE(reg, val);
  351. POSTING_READ(reg);
  352. return;
  353. }
  354. switch (intel_hdmi->sdvox_reg) {
  355. case HDMIB:
  356. port = VIDEO_DIP_PORT_B;
  357. break;
  358. case HDMIC:
  359. port = VIDEO_DIP_PORT_C;
  360. break;
  361. case HDMID:
  362. port = VIDEO_DIP_PORT_D;
  363. break;
  364. default:
  365. return;
  366. }
  367. if (port != (val & VIDEO_DIP_PORT_MASK)) {
  368. if (val & VIDEO_DIP_ENABLE) {
  369. val &= ~VIDEO_DIP_ENABLE;
  370. I915_WRITE(reg, val);
  371. POSTING_READ(reg);
  372. }
  373. val &= ~VIDEO_DIP_PORT_MASK;
  374. val |= port;
  375. }
  376. val |= VIDEO_DIP_ENABLE;
  377. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  378. VIDEO_DIP_ENABLE_GCP);
  379. I915_WRITE(reg, val);
  380. POSTING_READ(reg);
  381. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  382. intel_hdmi_set_spd_infoframe(encoder);
  383. }
  384. static void cpt_set_infoframes(struct drm_encoder *encoder,
  385. struct drm_display_mode *adjusted_mode)
  386. {
  387. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  388. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  389. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  390. u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
  391. u32 val = I915_READ(reg);
  392. assert_hdmi_port_disabled(intel_hdmi);
  393. /* See the big comment in g4x_set_infoframes() */
  394. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  395. if (!intel_hdmi->has_hdmi_sink) {
  396. if (!(val & VIDEO_DIP_ENABLE))
  397. return;
  398. val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
  399. I915_WRITE(reg, val);
  400. POSTING_READ(reg);
  401. return;
  402. }
  403. /* Set both together, unset both together: see the spec. */
  404. val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
  405. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  406. VIDEO_DIP_ENABLE_GCP);
  407. I915_WRITE(reg, val);
  408. POSTING_READ(reg);
  409. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  410. intel_hdmi_set_spd_infoframe(encoder);
  411. }
  412. static void vlv_set_infoframes(struct drm_encoder *encoder,
  413. struct drm_display_mode *adjusted_mode)
  414. {
  415. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  416. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  417. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  418. u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
  419. u32 val = I915_READ(reg);
  420. assert_hdmi_port_disabled(intel_hdmi);
  421. /* See the big comment in g4x_set_infoframes() */
  422. val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
  423. if (!intel_hdmi->has_hdmi_sink) {
  424. if (!(val & VIDEO_DIP_ENABLE))
  425. return;
  426. val &= ~VIDEO_DIP_ENABLE;
  427. I915_WRITE(reg, val);
  428. POSTING_READ(reg);
  429. return;
  430. }
  431. val |= VIDEO_DIP_ENABLE;
  432. val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
  433. VIDEO_DIP_ENABLE_GCP);
  434. I915_WRITE(reg, val);
  435. POSTING_READ(reg);
  436. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  437. intel_hdmi_set_spd_infoframe(encoder);
  438. }
  439. static void hsw_set_infoframes(struct drm_encoder *encoder,
  440. struct drm_display_mode *adjusted_mode)
  441. {
  442. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  443. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  444. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  445. u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
  446. u32 val = I915_READ(reg);
  447. assert_hdmi_port_disabled(intel_hdmi);
  448. if (!intel_hdmi->has_hdmi_sink) {
  449. I915_WRITE(reg, 0);
  450. POSTING_READ(reg);
  451. return;
  452. }
  453. val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
  454. VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
  455. I915_WRITE(reg, val);
  456. POSTING_READ(reg);
  457. intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
  458. intel_hdmi_set_spd_infoframe(encoder);
  459. }
  460. static void intel_hdmi_mode_set(struct drm_encoder *encoder,
  461. struct drm_display_mode *mode,
  462. struct drm_display_mode *adjusted_mode)
  463. {
  464. struct drm_device *dev = encoder->dev;
  465. struct drm_i915_private *dev_priv = dev->dev_private;
  466. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
  467. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
  468. u32 sdvox;
  469. sdvox = SDVO_ENCODING_HDMI;
  470. if (!HAS_PCH_SPLIT(dev))
  471. sdvox |= intel_hdmi->color_range;
  472. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  473. sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
  474. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  475. sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
  476. if (intel_crtc->bpp > 24)
  477. sdvox |= COLOR_FORMAT_12bpc;
  478. else
  479. sdvox |= COLOR_FORMAT_8bpc;
  480. /* Required on CPT */
  481. if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
  482. sdvox |= HDMI_MODE_SELECT;
  483. if (intel_hdmi->has_audio) {
  484. DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
  485. pipe_name(intel_crtc->pipe));
  486. sdvox |= SDVO_AUDIO_ENABLE;
  487. sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
  488. intel_write_eld(encoder, adjusted_mode);
  489. }
  490. if (HAS_PCH_CPT(dev))
  491. sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
  492. else if (intel_crtc->pipe == PIPE_B)
  493. sdvox |= SDVO_PIPE_B_SELECT;
  494. I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
  495. POSTING_READ(intel_hdmi->sdvox_reg);
  496. intel_hdmi->set_infoframes(encoder, adjusted_mode);
  497. }
  498. static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
  499. enum pipe *pipe)
  500. {
  501. struct drm_device *dev = encoder->base.dev;
  502. struct drm_i915_private *dev_priv = dev->dev_private;
  503. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  504. u32 tmp;
  505. tmp = I915_READ(intel_hdmi->sdvox_reg);
  506. if (!(tmp & SDVO_ENABLE))
  507. return false;
  508. if (HAS_PCH_CPT(dev))
  509. *pipe = PORT_TO_PIPE_CPT(tmp);
  510. else
  511. *pipe = PORT_TO_PIPE(tmp);
  512. return true;
  513. }
  514. static void intel_enable_hdmi(struct intel_encoder *encoder)
  515. {
  516. struct drm_device *dev = encoder->base.dev;
  517. struct drm_i915_private *dev_priv = dev->dev_private;
  518. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  519. u32 temp;
  520. u32 enable_bits = SDVO_ENABLE;
  521. if (intel_hdmi->has_audio)
  522. enable_bits |= SDVO_AUDIO_ENABLE;
  523. temp = I915_READ(intel_hdmi->sdvox_reg);
  524. /* HW workaround for IBX, we need to move the port to transcoder A
  525. * before disabling it. */
  526. if (HAS_PCH_IBX(dev)) {
  527. struct drm_crtc *crtc = encoder->base.crtc;
  528. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  529. /* Restore the transcoder select bit. */
  530. if (pipe == PIPE_B)
  531. enable_bits |= SDVO_PIPE_B_SELECT;
  532. }
  533. /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  534. * we do this anyway which shows more stable in testing.
  535. */
  536. if (HAS_PCH_SPLIT(dev)) {
  537. I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  538. POSTING_READ(intel_hdmi->sdvox_reg);
  539. }
  540. temp |= enable_bits;
  541. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  542. POSTING_READ(intel_hdmi->sdvox_reg);
  543. /* HW workaround, need to write this twice for issue that may result
  544. * in first write getting masked.
  545. */
  546. if (HAS_PCH_SPLIT(dev)) {
  547. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  548. POSTING_READ(intel_hdmi->sdvox_reg);
  549. }
  550. }
  551. static void intel_disable_hdmi(struct intel_encoder *encoder)
  552. {
  553. struct drm_device *dev = encoder->base.dev;
  554. struct drm_i915_private *dev_priv = dev->dev_private;
  555. struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
  556. u32 temp;
  557. u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
  558. temp = I915_READ(intel_hdmi->sdvox_reg);
  559. /* HW workaround for IBX, we need to move the port to transcoder A
  560. * before disabling it. */
  561. if (HAS_PCH_IBX(dev)) {
  562. struct drm_crtc *crtc = encoder->base.crtc;
  563. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  564. if (temp & SDVO_PIPE_B_SELECT) {
  565. temp &= ~SDVO_PIPE_B_SELECT;
  566. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  567. POSTING_READ(intel_hdmi->sdvox_reg);
  568. /* Again we need to write this twice. */
  569. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  570. POSTING_READ(intel_hdmi->sdvox_reg);
  571. /* Transcoder selection bits only update
  572. * effectively on vblank. */
  573. if (crtc)
  574. intel_wait_for_vblank(dev, pipe);
  575. else
  576. msleep(50);
  577. }
  578. }
  579. /* HW workaround, need to toggle enable bit off and on for 12bpc, but
  580. * we do this anyway which shows more stable in testing.
  581. */
  582. if (HAS_PCH_SPLIT(dev)) {
  583. I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
  584. POSTING_READ(intel_hdmi->sdvox_reg);
  585. }
  586. temp &= ~enable_bits;
  587. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  588. POSTING_READ(intel_hdmi->sdvox_reg);
  589. /* HW workaround, need to write this twice for issue that may result
  590. * in first write getting masked.
  591. */
  592. if (HAS_PCH_SPLIT(dev)) {
  593. I915_WRITE(intel_hdmi->sdvox_reg, temp);
  594. POSTING_READ(intel_hdmi->sdvox_reg);
  595. }
  596. }
  597. static int intel_hdmi_mode_valid(struct drm_connector *connector,
  598. struct drm_display_mode *mode)
  599. {
  600. if (mode->clock > 165000)
  601. return MODE_CLOCK_HIGH;
  602. if (mode->clock < 20000)
  603. return MODE_CLOCK_LOW;
  604. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  605. return MODE_NO_DBLESCAN;
  606. return MODE_OK;
  607. }
  608. static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
  609. const struct drm_display_mode *mode,
  610. struct drm_display_mode *adjusted_mode)
  611. {
  612. return true;
  613. }
  614. static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
  615. {
  616. struct drm_device *dev = intel_hdmi->base.base.dev;
  617. struct drm_i915_private *dev_priv = dev->dev_private;
  618. uint32_t bit;
  619. switch (intel_hdmi->sdvox_reg) {
  620. case SDVOB:
  621. bit = HDMIB_HOTPLUG_LIVE_STATUS;
  622. break;
  623. case SDVOC:
  624. bit = HDMIC_HOTPLUG_LIVE_STATUS;
  625. break;
  626. default:
  627. bit = 0;
  628. break;
  629. }
  630. return I915_READ(PORT_HOTPLUG_STAT) & bit;
  631. }
  632. static enum drm_connector_status
  633. intel_hdmi_detect(struct drm_connector *connector, bool force)
  634. {
  635. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  636. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  637. struct edid *edid;
  638. enum drm_connector_status status = connector_status_disconnected;
  639. if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
  640. return status;
  641. intel_hdmi->has_hdmi_sink = false;
  642. intel_hdmi->has_audio = false;
  643. edid = drm_get_edid(connector,
  644. intel_gmbus_get_adapter(dev_priv,
  645. intel_hdmi->ddc_bus));
  646. if (edid) {
  647. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  648. status = connector_status_connected;
  649. if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
  650. intel_hdmi->has_hdmi_sink =
  651. drm_detect_hdmi_monitor(edid);
  652. intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
  653. }
  654. kfree(edid);
  655. }
  656. if (status == connector_status_connected) {
  657. if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
  658. intel_hdmi->has_audio =
  659. (intel_hdmi->force_audio == HDMI_AUDIO_ON);
  660. }
  661. return status;
  662. }
  663. static int intel_hdmi_get_modes(struct drm_connector *connector)
  664. {
  665. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  666. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  667. /* We should parse the EDID data and find out if it's an HDMI sink so
  668. * we can send audio to it.
  669. */
  670. return intel_ddc_get_modes(connector,
  671. intel_gmbus_get_adapter(dev_priv,
  672. intel_hdmi->ddc_bus));
  673. }
  674. static bool
  675. intel_hdmi_detect_audio(struct drm_connector *connector)
  676. {
  677. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  678. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  679. struct edid *edid;
  680. bool has_audio = false;
  681. edid = drm_get_edid(connector,
  682. intel_gmbus_get_adapter(dev_priv,
  683. intel_hdmi->ddc_bus));
  684. if (edid) {
  685. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  686. has_audio = drm_detect_monitor_audio(edid);
  687. kfree(edid);
  688. }
  689. return has_audio;
  690. }
  691. static int
  692. intel_hdmi_set_property(struct drm_connector *connector,
  693. struct drm_property *property,
  694. uint64_t val)
  695. {
  696. struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
  697. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  698. int ret;
  699. ret = drm_connector_property_set_value(connector, property, val);
  700. if (ret)
  701. return ret;
  702. if (property == dev_priv->force_audio_property) {
  703. enum hdmi_force_audio i = val;
  704. bool has_audio;
  705. if (i == intel_hdmi->force_audio)
  706. return 0;
  707. intel_hdmi->force_audio = i;
  708. if (i == HDMI_AUDIO_AUTO)
  709. has_audio = intel_hdmi_detect_audio(connector);
  710. else
  711. has_audio = (i == HDMI_AUDIO_ON);
  712. if (i == HDMI_AUDIO_OFF_DVI)
  713. intel_hdmi->has_hdmi_sink = 0;
  714. intel_hdmi->has_audio = has_audio;
  715. goto done;
  716. }
  717. if (property == dev_priv->broadcast_rgb_property) {
  718. if (val == !!intel_hdmi->color_range)
  719. return 0;
  720. intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  721. goto done;
  722. }
  723. return -EINVAL;
  724. done:
  725. if (intel_hdmi->base.base.crtc) {
  726. struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
  727. intel_set_mode(crtc, &crtc->mode,
  728. crtc->x, crtc->y, crtc->fb);
  729. }
  730. return 0;
  731. }
  732. static void intel_hdmi_destroy(struct drm_connector *connector)
  733. {
  734. drm_sysfs_connector_remove(connector);
  735. drm_connector_cleanup(connector);
  736. kfree(connector);
  737. }
  738. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = {
  739. .mode_fixup = intel_hdmi_mode_fixup,
  740. .mode_set = intel_ddi_mode_set,
  741. .disable = intel_encoder_noop,
  742. };
  743. static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
  744. .mode_fixup = intel_hdmi_mode_fixup,
  745. .mode_set = intel_hdmi_mode_set,
  746. .disable = intel_encoder_noop,
  747. };
  748. static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
  749. .dpms = intel_connector_dpms,
  750. .detect = intel_hdmi_detect,
  751. .fill_modes = drm_helper_probe_single_connector_modes,
  752. .set_property = intel_hdmi_set_property,
  753. .destroy = intel_hdmi_destroy,
  754. };
  755. static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
  756. .get_modes = intel_hdmi_get_modes,
  757. .mode_valid = intel_hdmi_mode_valid,
  758. .best_encoder = intel_best_encoder,
  759. };
  760. static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
  761. .destroy = intel_encoder_destroy,
  762. };
  763. static void
  764. intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
  765. {
  766. intel_attach_force_audio_property(connector);
  767. intel_attach_broadcast_rgb_property(connector);
  768. }
  769. void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
  770. {
  771. struct drm_i915_private *dev_priv = dev->dev_private;
  772. struct drm_connector *connector;
  773. struct intel_encoder *intel_encoder;
  774. struct intel_connector *intel_connector;
  775. struct intel_hdmi *intel_hdmi;
  776. intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
  777. if (!intel_hdmi)
  778. return;
  779. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  780. if (!intel_connector) {
  781. kfree(intel_hdmi);
  782. return;
  783. }
  784. intel_encoder = &intel_hdmi->base;
  785. drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
  786. DRM_MODE_ENCODER_TMDS);
  787. connector = &intel_connector->base;
  788. drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
  789. DRM_MODE_CONNECTOR_HDMIA);
  790. drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
  791. intel_encoder->type = INTEL_OUTPUT_HDMI;
  792. connector->polled = DRM_CONNECTOR_POLL_HPD;
  793. connector->interlace_allowed = 1;
  794. connector->doublescan_allowed = 0;
  795. intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  796. intel_encoder->cloneable = false;
  797. intel_hdmi->ddi_port = port;
  798. switch (port) {
  799. case PORT_B:
  800. intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
  801. dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
  802. break;
  803. case PORT_C:
  804. intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
  805. dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
  806. break;
  807. case PORT_D:
  808. intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
  809. dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
  810. break;
  811. case PORT_A:
  812. /* Internal port only for eDP. */
  813. default:
  814. BUG();
  815. }
  816. intel_hdmi->sdvox_reg = sdvox_reg;
  817. if (!HAS_PCH_SPLIT(dev)) {
  818. intel_hdmi->write_infoframe = g4x_write_infoframe;
  819. intel_hdmi->set_infoframes = g4x_set_infoframes;
  820. } else if (IS_VALLEYVIEW(dev)) {
  821. intel_hdmi->write_infoframe = vlv_write_infoframe;
  822. intel_hdmi->set_infoframes = vlv_set_infoframes;
  823. } else if (IS_HASWELL(dev)) {
  824. intel_hdmi->write_infoframe = hsw_write_infoframe;
  825. intel_hdmi->set_infoframes = hsw_set_infoframes;
  826. } else if (HAS_PCH_IBX(dev)) {
  827. intel_hdmi->write_infoframe = ibx_write_infoframe;
  828. intel_hdmi->set_infoframes = ibx_set_infoframes;
  829. } else {
  830. intel_hdmi->write_infoframe = cpt_write_infoframe;
  831. intel_hdmi->set_infoframes = cpt_set_infoframes;
  832. }
  833. if (IS_HASWELL(dev)) {
  834. intel_encoder->enable = intel_enable_ddi;
  835. intel_encoder->disable = intel_disable_ddi;
  836. intel_encoder->get_hw_state = intel_ddi_get_hw_state;
  837. drm_encoder_helper_add(&intel_encoder->base,
  838. &intel_hdmi_helper_funcs_hsw);
  839. } else {
  840. intel_encoder->enable = intel_enable_hdmi;
  841. intel_encoder->disable = intel_disable_hdmi;
  842. intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
  843. drm_encoder_helper_add(&intel_encoder->base,
  844. &intel_hdmi_helper_funcs);
  845. }
  846. intel_connector->get_hw_state = intel_connector_get_hw_state;
  847. intel_hdmi_add_properties(intel_hdmi, connector);
  848. intel_connector_attach_encoder(intel_connector, intel_encoder);
  849. drm_sysfs_connector_add(connector);
  850. /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
  851. * 0xd. Failure to do so will result in spurious interrupts being
  852. * generated on the port when a cable is not attached.
  853. */
  854. if (IS_G4X(dev) && !IS_GM45(dev)) {
  855. u32 temp = I915_READ(PEG_BAND_GAP_DATA);
  856. I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
  857. }
  858. }